JP2014072200A - Photoelectric conversion device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a photoelectric conversion device with an i-type amorphous silicon carbide semiconductor layer that has excellent photoelectric conversion characteristics.SOLUTION: A photoelectric conversion device includes a stack of a first conductive layer, a first photoelectric conversion layer, and a second conductive layer in that order. The first photoelectric conversion layer has a p-type silicon-based semiconductor layer, an i-type amorphous silicon carbide semiconductor layer, an interface control layer, and an n-type silicon-based semiconductor layer that are sequentially stacked from the first conductive layer side to the second conductive layer side. The interface control layer contains silicon atoms, carbon atoms, and oxygen atoms.

Description

  The present invention relates to a photoelectric conversion device, and more particularly to a technology for improving the efficiency of a photoelectric conversion device. The present invention also relates to a method for manufacturing a photoelectric conversion device.

  2. Description of the Related Art In recent years, attention has been focused on solar cells, which are representative of renewable energy, due to power energy sources and global warming issues. The most widespread among solar cells are those using bulk crystals such as single crystal silicon and polycrystalline silicon, but bulk crystal solar cells use a silicon substrate with a thickness of several hundred μm. Therefore, it is difficult to reduce the cost significantly. In contrast, thin-film silicon solar cells are easy to increase in area and have a merit that the material cost is low and the cost can be reduced because the film thickness is as thin as about 1/100 that of bulk crystal solar cells. . However, thin-film silicon solar cells have lower power generation efficiency than crystalline solar cells, and improvement of photoelectric conversion characteristics is an important issue.

  The photoelectric conversion layer of the thin-film silicon-based solar cell uses an amorphous silicon solar cell using a hydrogenated amorphous silicon-based semiconductor for the light absorption layer, and a hydrogenated microcrystalline silicon-based semiconductor for the light absorption layer. Broadly divided into microcrystalline silicon solar cells. Also, in recent years, a stacked thin film silicon solar cell in which both of these are used to take advantage of the difference in band gap and spectral sensitivity characteristics has attracted particular attention in recent years. In order to increase the efficiency of a stacked thin film silicon solar cell, it is of course necessary to increase the efficiency of both the amorphous silicon layer and the microcrystalline silicon layer.

  In addition, in order to increase the open circuit voltage of amorphous silicon solar cells, thin film solar cells in which the i layer is an amorphous silicon carbide layer have been developed. In Japanese Patent Application Laid-Open No. 8-111080 (Patent Document 1), the i layer is an amorphous silicon carbide layer, and the p layer is a microcrystalline silicon layer. It is described that the open-circuit voltage is improved by adjusting the amount of hydrogen.

Japanese Patent Application Laid-Open No. 8-111080

  However, even with the photoelectric conversion element having an i layer composed of an amorphous silicon carbide layer described in Patent Document 1, the open-circuit voltage is not sufficiently improved, and further improvement in characteristics has been desired.

  An object of the present invention is to provide a photoelectric conversion device having excellent photoelectric conversion characteristics in a photoelectric conversion device having an i-type amorphous silicon carbide semiconductor layer, and a method for manufacturing the photoelectric conversion device.

  The inventor has provided a specific layer between an i-type amorphous silicon carbide semiconductor layer and an n-type semiconductor layer in a photoelectric conversion device having an i-type amorphous silicon carbide semiconductor layer and having a pin junction, The inventors have found that the short circuit current density and the open circuit voltage can be improved, and have completed the present invention. The present invention includes the following.

[1] A photoelectric conversion device in which a first conductive layer, a first photoelectric conversion layer, and a second conductive layer are laminated in this order,
The first photoelectric conversion layer is sequentially stacked from the first conductive layer side to the second conductive layer side, a p-type silicon-based semiconductor layer, an i-type amorphous silicon carbide semiconductor layer, an interface control layer, an n-type silicon-based semiconductor layer,
The interface control layer is a photoelectric conversion device including silicon atoms, carbon atoms, and oxygen atoms.

[2] The photoelectric conversion device according to [1], wherein the interface control layer has an oxygen concentration of 1 × 10 ²⁰ (atoms / cm ³ ) or more and 1 × 10 ²² (atoms / cm ³ ) or less.

  [3] The photoelectric conversion device according to [1] or [2], wherein the interface control layer has a maximum value of oxygen concentration in a layer thickness direction.

[4] The carbon concentration in the interface control layer is 1 × 10 ²⁰ (atoms / cm ³ ) or more and 2 × 10 ²¹ (atoms / cm ³ ) or less, according to any one of [1] to [3] Photoelectric conversion device.

  [5] The photoelectric conversion device according to any one of [1] to [4], wherein the interface control layer has a thickness of 100 nm or less.

[6] The photoelectric conversion device according to any one of [1] to [5], wherein the carbon concentration of the i-type amorphous silicon carbide semiconductor layer is 1 × 10 ²² (atoms / cm ³ ) or less.

  [7] The oxygen concentration of the interface control layer is higher than the oxygen concentration of the i-type amorphous silicon carbide semiconductor layer, and the carbon concentration of the interface control layer is higher than the carbon concentration of the i-type amorphous silicon carbide semiconductor layer. The photoelectric conversion device according to any one of [1] to [6].

  [8] The photoelectric conversion device according to any one of [1] to [7], wherein the interface control layer has no crystalline silicon peak observed by Raman scattering measurement.

[9] In the first photoelectric conversion layer, the band gap Es of the interface control layer and the band gap Ei of the i-type amorphous silicon carbide semiconductor layer are expressed by the following formula:
Ei−0.05 [eV] ≦ Es ≦ Ei + 0.20 [eV]
The photoelectric conversion device according to any one of [1] to [8], which satisfies a relationship represented by:

  [10] The photoelectric conversion device according to any one of [1] to [9], further including a second photoelectric conversion layer between the first conductive layer and the second conductive layer.

  [11] A translucent insulating substrate is provided, and the first conductive layer, the first photoelectric conversion layer, and the second conductive layer are stacked in this order on the translucent insulating substrate. [10] The photoelectric conversion device according to any one of [10].

  [12] A non-translucent insulating substrate is provided, and the second conductive layer, the first photoelectric conversion layer, and the first conductive layer are laminated in this order on the non-translucent insulating substrate [1] ] The photoelectric conversion apparatus in any one of [10].

[13] A method for manufacturing the photoelectric conversion device according to [1],
A method for manufacturing a photoelectric conversion device, comprising a step of supplying a gas containing silicon atoms, carbon atoms, and oxygen atoms to form the interface control layer.

  [14] The method for manufacturing a photoelectric conversion device according to [13], wherein the gas includes carbon dioxide.

  According to the present invention, a photoelectric conversion device with an improved open circuit voltage can be provided.

It is sectional drawing which shows schematically the structure of the photoelectric conversion apparatus of 1st Embodiment. It is sectional drawing which shows typically a part of structure of the plasma CVD apparatus used by 1st and 2nd embodiment. It is sectional drawing which shows schematically the structure of the photoelectric conversion apparatus of 2nd Embodiment. It is a figure which shows the relationship of the distance of the layer thickness direction in the photoelectric conversion apparatus of Example 1, and atomic concentration. It is a figure which shows the relationship of the distance of the layer thickness direction and atomic concentration in the photoelectric conversion apparatus of Example 2. FIG.

  The photoelectric conversion device of the present invention is formed by laminating a first conductive layer, a first photoelectric conversion layer, and a second conductive layer in this order. The first photoelectric conversion layer is sequentially stacked from the first conductive layer side to the second conductive layer side, the p-type silicon-based semiconductor layer, the i-type amorphous silicon carbide semiconductor layer, the silicon atom, the carbon It has an interface control layer containing atoms and oxygen atoms, and an n-type silicon-based semiconductor layer. Hereinafter, the photoelectric conversion device of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
(Configuration of photoelectric conversion device)
FIG. 1 is a cross-sectional view schematically showing the configuration of the photoelectric conversion apparatus according to the first embodiment. As shown in FIG. 1, in the photoelectric conversion device 100 according to the first embodiment, a first conductive layer 12, a first photoelectric conversion layer 10, and a second conductive layer 17 are stacked in this order on a substrate 11. It becomes. The photoelectric conversion device 100 is a super straight type in which light is incident from the substrate 11 side. In the photoelectric conversion device 100, the substrate 11 side is referred to as a light incident side, and the second conductive layer 17 side is referred to as a back side.

  The substrate 11 is a translucent insulating substrate made of a translucent material. The substrate 11 is preferably made of, for example, a resin such as glass or polyimide, and has heat resistance and translucency in the semiconductor layer formation step by the plasma CVD method.

The first conductive layer 12 is made of a light transmissive material. The first conductive layer 12 can be made of, for example, SnO ₂ , indium tin oxide (ITO), or the like. The thickness and shape of the substrate 11 and the first conductive layer 12 are not particularly limited.

The 2nd conductive layer 17 consists of the transparent conductive film 17a and the metal film 17b which were laminated | stacked in order from the side close | similar to the 1st photoelectric converting layer 10. FIG. The transparent conductive film 17a can be made of, for example, SnO ₂ , ITO, ZnO or the like. The metal film 17b can be made of, for example, silver, aluminum, titanium, palladium, or the like. The second conductive layer 17 may be configured only by the metal film 17b.

  The first photoelectric conversion layer 10 includes a p-type silicon-based semiconductor layer 13, an i-type amorphous silicon carbide semiconductor layer 14, an interface control layer 15 including silicon atoms, carbon atoms, and oxygen atoms, and an n-type silicon-based semiconductor. The layers 16 are sequentially stacked and have a p-i-n junction structure from the substrate 11 side.

  In the photoelectric conversion device 100, by having the interface control layer 15 containing oxygen and carbon, a high open circuit voltage can be obtained. This is because the interface control layer 15 containing oxygen and carbon has a deeper energy level Ev at the upper end of the valence band and an energy level Ec at the lower end of the conduction band than the i-type amorphous silicon carbide semiconductor layer. Therefore, it is considered that the diffusion of holes to the n layer side is reduced, the reverse saturation current is improved, and the open-circuit voltage is improved.

  The band gap Es of the interface control layer 15 and the band gap Ei of the i-type amorphous silicon carbide semiconductor layer 14 preferably satisfy the following relationship.

Ei−0.05 [eV] ≦ Es ≦ Ei + 0.20 [eV]
In the case of Es <Ei−0.05 [eV], it may be difficult for the interface control layer 15 to take the deep energy level Ev at the upper end of the valence band than the i-type silicon-based semiconductor layer 14. In the case of Es> Ei + 0.20 [eV], too much oxygen and carbon are added to deteriorate the film quality of the interface control layer 15, so that the short-circuit current density and the open-circuit voltage, which are the effects of the present invention, are improved. It can be difficult.

  The layer thickness of the interface control layer 15 is preferably 100 nm or less. When the layer thickness of the interface control layer 15 exceeds 100 nm, the series resistance component of the interface control layer 15 increases and the fill factor deteriorates. The layer thickness of the interface control layer 15 is preferably 5 nm or more.

In the interface control layer 15, the oxygen concentration is preferably 1 × 10 ²⁰ (atoms / cm ³ ) or more and 1 × 10 ²² (atoms / cm ³ ) or less. When the oxygen concentration is less than 1 × 10 ²⁰ (atoms / cm ³ ), the energy level Ev at the upper end of the valence band is not sufficiently deep, and it is difficult to obtain the effect of improving the open-circuit voltage. In addition, when the oxygen concentration exceeds 1 × 10 ²² (atoms / cm ³ ), the series resistance component of the interface control layer 15 increases, and the curve factor deteriorates. The carbon concentration of the interface control layer 15 is preferably 1 × 10 ²⁰ (atoms / cm ³ ) or more and 2 × 10 ²¹ (atoms / cm ³ ) or less. When the carbon concentration exceeds 2 × 10 ²¹ (atoms / cm ³ ), the series resistance component of the interface control layer 15 increases, and the curve factor deteriorates. In the interface control layer 15, the oxygen concentration in the layer thickness direction does not need to be constant, and preferably has a maximum oxygen concentration in the film thickness direction of the interface control layer 15.

  The interface control layer 15 is preferably a semiconductor layer made of an amorphous silicon-based semiconductor, and therefore it is preferable that no crystalline silicon peak is observed by Raman scattering measurement. The interface control layer 15 is preferably i-type.

  The p-type silicon-based semiconductor layer 13 is preferably made of an amorphous silicon-based semiconductor, and the layer thickness is preferably 5 nm or more and 50 nm or less. When the layer thickness of the p-type silicon-based semiconductor layer 13 is less than 5 nm, the first conductive layer 12 may partially contact the i-type amorphous silicon carbide semiconductor layer 14 and a normal semiconductor pin junction is formed. This is because the characteristics as a photoelectric conversion device may be remarkably deteriorated. On the other hand, when the thickness of the p-type silicon-based semiconductor layer 13 exceeds 50 nm, the light absorption amount of the p-type silicon-based semiconductor layer 13 becomes excessive, and the amount of light reaching the i-type amorphous silicon carbide semiconductor layer 14 decreases. For this reason, the short-circuit current as the photoelectric conversion layer device may decrease.

  The i-type amorphous silicon carbide semiconductor layer 14 is preferably made of an amorphous silicon-based semiconductor, and the layer thickness is preferably 50 nm or more and 1000 nm or less.

The carbon concentration of the i-type amorphous silicon carbide semiconductor layer 14 is preferably 1 × 10 ²² (atoms / cm ³ ) or less. Further, the oxygen concentration of the interface control layer 15 is higher than the oxygen concentration of the i-type amorphous silicon carbide semiconductor layer 14, and the carbon concentration of the interface control layer 15 is higher than the carbon concentration of the i-type amorphous silicon carbide semiconductor layer 14. Preferably it is low. Due to such a configuration, when the interface control layer 15 and the i-type amorphous silicon carbide semiconductor layer 14 are compared, the interface control layer 15 has a valence band even if the band gap is comparable. The energy level Ev at the upper end of the semiconductor layer and the energy level Ec at the lower end of the conduction band are easily taken to have a deep level, the diffusion of holes to the n-layer side is reduced, the reverse saturation current is improved, and the open circuit voltage This is thought to be due to the improvement.

  The n-type silicon-based semiconductor layer 16 is preferably made of an amorphous silicon-based semiconductor, and the layer thickness is preferably 5 nm or more and 50 nm or less.

(Plasma CVD equipment)
FIG. 2 is a cross-sectional view schematically showing a part of the configuration of a plasma CVD apparatus used for manufacturing the photoelectric conversion apparatus of the present embodiment. The plasma CVD apparatus shown in FIG. 2 is a so-called capacitively coupled plasma CVD apparatus, in which the cathode electrode 3 in the reaction chamber 4 and the high-frequency power source 6 are connected via a matching circuit 5 to fix the cathode electrode 3 and the substrate 11. The plasma is generated in the region between the anode electrode 2 and the anode electrode 2. The substrate 11 is preheated to a desired temperature by the heater 1 before film formation. Note that the plasma CVD apparatus used in this embodiment is a multi-chamber plasma CVD apparatus, and a plurality of reaction chambers are provided, for example, in a straight line.

(Manufacturing method of photoelectric conversion device)
In the manufacturing method of the present embodiment, the following steps are performed using the plasma CVD apparatus shown in FIG. First, the p-type silicon-based semiconductor layer 13 is formed on the substrate 11 provided with the first conductive layer 12. The reaction chamber 4 is evacuated to 1 × 10 ⁻⁶ Torr, and the temperature of the substrate 11 is controlled to 250 ° C. or lower. Then, a mixed gas is introduced into the reaction chamber 4 by a flow rate controller (not shown), and the pressure in the reaction chamber 4 is kept constant by a conduction valve (not shown) provided in the exhaust system.

The pressure in the reaction chamber 4 is, for example, not less than 0.1 Torr and not more than 1 Torr. As the mixed gas introduced into the reaction chamber 4, for example, a mixed gas containing silane gas, methane gas, hydrogen gas, and diborane gas is used. After the mixed gas is introduced and the pressure in the reaction chamber 4 is stabilized, AC power of 10 MHz to 150 MHz is supplied to the cathode electrode 3 to generate plasma between the cathode electrode 3 and the anode electrode 2. A p-type silicon-based semiconductor layer 13 is formed by the generation of this plasma. The power density per unit area of the cathode electrode 3, for example, to 0.02 W / cm ² or more 0.5 W / cm ² or less.

Next, the i-type amorphous silicon carbide semiconductor layer 14 is formed. The pressure in the reaction chamber 4 is, for example, not less than 0.1 Torr and not more than 1 Torr. As the mixed gas introduced into the reaction chamber 4, for example, a mixed gas containing silane gas, hydrogen gas, and methane gas is used. After the mixed gas is introduced and the pressure in the reaction chamber 4 is stabilized, AC power of 10 MHz to 150 MHz is supplied to the cathode electrode 3 to generate plasma between the cathode electrode 3 and the anode electrode 2. The i-type amorphous silicon carbide semiconductor layer 14 is formed by the generation of this plasma. The power density per unit area of the cathode electrode 3, for example, to 0.02 W / cm ² or more 0.5 W / cm ² or less.

Next, the interface control layer 15 is formed. The pressure in the reaction chamber 4 is, for example, not less than 0.1 Torr and not more than 1 Torr. As the mixed gas introduced into the reaction chamber 4, for example, a mixed gas containing silane gas, hydrogen gas, and carbon dioxide gas is used. Carbon dioxide gas is used as a source of carbon and oxygen atoms. In addition to carbon dioxide gas, oxygen gas, dinitrogen monoxide gas, or the like can be used as the oxygen atom supply source, and methane, ethane, ethylene, propane, propylene, acetylene, or the like can be used as the carbon atom supply source. Carbon dioxide gas is preferably used because it is an inert gas, is easy to handle, and can supply carbon atoms and oxygen atoms simultaneously. Moreover, the concentration of oxygen atoms and carbon atoms contained in the interface control layer can be controlled separately by supplying carbon dioxide gas and methane gas simultaneously and adjusting the respective supply amounts. After the mixed gas is introduced and the pressure in the reaction chamber 4 is stabilized, AC power of 10 MHz to 150 MHz is supplied to the cathode electrode 3 to generate plasma between the cathode electrode 3 and the anode electrode 2. The interface control layer 15 is formed by the generation of this plasma. The power density per unit area of the cathode electrode 3, for example, to 0.02 W / cm ² or more 0.5 W / cm ² or less. When increasing the oxygen concentration of the interface control layer 15, the supply amount of carbon dioxide gas per unit time is continuously increased.

Next, the n-type silicon-based semiconductor layer 16 is formed. The pressure in the reaction chamber 4 is, for example, not less than 0.1 Torr and not more than 1 Torr. As the mixed gas introduced into the reaction chamber 4, for example, a mixed gas containing silane gas, hydrogen gas, and phosphine gas is used. After the mixed gas is introduced and the pressure in the reaction chamber 4 is stabilized, AC power of 10 MHz to 150 MHz is supplied to the cathode electrode 3 to generate plasma between the cathode electrode 3 and the anode electrode 2. The n-type silicon semiconductor layer 16 is formed by the generation of this plasma. The power density per unit area of the cathode electrode 3, for example, to 0.02 W / cm ² or more 0.5 W / cm ² or less. As described above, the photoelectric conversion layer 10 is formed.

  Next, the second conductive layer 17 is formed on the photoelectric conversion layer 10. The second conductive layer 17 includes a transparent conductive film 17a and a metal film 17b, which are sequentially formed by a method such as CVD, sputtering, or vapor deposition.

(Modification)
The photoelectric conversion device 100 according to the first embodiment has a superstrate type configuration, but can also be applied to a substrate type configuration. In the substrate type configuration, the substrate 11 formed on the first conductive layer 12 side in the super straight type photoelectric conversion device 100 shown in FIG. 1 is connected to the n-type silicon-based semiconductor layer 16 side of the second conductive layer 17. A non-translucent insulating substrate is used as the substrate 11. The configurations of the first conductive layer 12 and the second conductive layer 17 can be selected as appropriate, but the first conductive layer 12 on the light incident side has a grid shape that does not uniformly cover the p-type silicon-based semiconductor layer 13. Configure. Also in the substrate type photoelectric conversion device, by providing the interface control layer 15, the effect of the present invention can be obtained as in the case of the super straight type photoelectric conversion device.

[Second Embodiment]
(Configuration of photoelectric conversion device)
FIG. 3 is a cross-sectional view schematically showing the configuration of the photoelectric conversion apparatus according to the second embodiment. The photoelectric conversion device 200 of the second embodiment shown in FIG. 3 is different from the photoelectric conversion device 100 shown in FIG. 1 in that the n-type silicon-based semiconductor layer 16 of the first photoelectric conversion layer 10 has two layers. The point which has the 2nd photoelectric converting layer 20 differs. In the photoelectric conversion device 200, the same components as those of the photoelectric conversion device 100 are denoted by the same reference numerals and description thereof is omitted.

  As illustrated in FIG. 3, the photoelectric conversion device 200 includes a second photoelectric conversion layer 20 between the second conductive layer 17 and the first photoelectric conversion layer 10. The second photoelectric conversion layer 20 is a p-type silicon-based semiconductor composed of a microcrystalline silicon-based semiconductor in order from the first conductive layer 12 side so that the direction of the pin junction is the same as that of the first photoelectric conversion layer 10. A semiconductor layer 21, an i-type silicon-based semiconductor layer 22 made of a microcrystalline silicon-based semiconductor, and an n-type silicon-based semiconductor layer 23 are stacked. The n-type silicon-based semiconductor layer 23 is formed by laminating an n-type amorphous silicon layer 23a and an n-type microcrystalline silicon layer 23b in this order from the i-type silicon-based semiconductor layer 22 side. In addition, an n-type silicon-based semiconductor layer 16 is provided between the interface control layer 15 and the p-type silicon-based semiconductor layer 21, and the n-type silicon-based semiconductor layer 16 includes an n-type amorphous silicon layer 16 a and an n-type microscopic semiconductor layer 16. A crystalline silicon layer 16b is laminated.

  In the photoelectric conversion device 200, the substrate 11 side is referred to as a light incident side, and the second conductive layer 17 side is referred to as a back side. In addition, the term “microcrystal” in this specification includes a portion that partially contains an amorphous state.

  In the photoelectric conversion device 200, light enters from the substrate 11 side. Since the first photoelectric conversion layer 10 is located on the light incident side from the second photoelectric conversion layer 20, only the light transmitted through the first photoelectric conversion layer 10 is incident on the second photoelectric conversion layer 20. Since the first photoelectric conversion layer 10 and the second photoelectric conversion layer 20 can be configured to receive different regions by dividing the region of the incident light spectrum, a stacked structure having a plurality of such photoelectric conversion layers. In, light can be used effectively and a high open circuit voltage can be obtained. In order to enhance such an effect, the band gap of the first photoelectric conversion layer 10 on the light incident side is preferably configured to be larger than the band gap of the second photoelectric conversion layer 20. In this case, short wavelength light of incident light is mainly absorbed by the first photoelectric conversion layer 10, and long wavelength light is mainly absorbed by the second photoelectric conversion layer 20, and light in each wavelength region is effectively used. Can do.

  An intermediate layer may be formed between the first photoelectric conversion layer 10 and the second photoelectric conversion layer 20. In this case, the intermediate layer is preferably a transparent conductive film. By providing the intermediate layer, a part of the light incident on the intermediate layer from the first photoelectric conversion layer 10 is reflected by the intermediate layer, and the remaining light is transmitted through the intermediate layer to the second photoelectric conversion layer 20. Since the light enters, the amount of light incident on each photoelectric conversion layer can be controlled. As a result, the photocurrent values of the photoelectric conversion layers 10 and 20 are equalized, and the photogenerated carriers generated in the photoelectric conversion layers 10 and 20 can contribute to the short-circuit current of the stacked photoelectric conversion device without waste. As a result, the short-circuit current of the photoelectric conversion device can be increased as a result, and the photoelectric conversion efficiency can be improved. Further, when the light absorption layer of the first photoelectric conversion layer 10 is made of an amorphous silicon-based semiconductor, light degradation occurs, but the first photoelectric conversion layer 10 is reflected by reflecting a part of incident light by the intermediate layer. Therefore, the influence of light deterioration can be reduced, and stable photoelectric conversion efficiency can be obtained.

(Modification)
In the present embodiment, a photoelectric conversion device in which two photoelectric conversion layers are stacked is shown, but a photoelectric conversion device in which three or more photoelectric conversion layers are stacked may be used. Further, in the present embodiment, the super straight type photoelectric conversion device has been described. However, the present embodiment can also be applied to a substrate type photoelectric conversion device, as in the first embodiment.

[Photoelectric conversion module]
The photoelectric conversion device of the present invention can be used as a component of the photoelectric conversion module. For example, the photoelectric conversion module can be configured by sealing the photoelectric conversion device with a sealing resin.

  EXAMPLES Hereinafter, although an Example is given and this invention is demonstrated in detail, this invention is not limited to these.

[Example 1, Comparative Example 1]
(Configuration of photoelectric conversion device)
As Example 1, a photoelectric conversion device having the same configuration as the photoelectric conversion device 100 of the first embodiment shown in FIG. The thickness of the i-type amorphous silicon carbide semiconductor layer 14 of Example 1 was 200 nm, and the thickness of the interface control layer 15 was 50 nm. Further, as Comparative Example 1, a photoelectric conversion device different from Example 1 was manufactured only in that the film thickness of the i-type amorphous silicon carbide semiconductor layer 14 was 250 nm and the interface control layer was not formed. Since the interface control layer of Example 1 is i-type, the total film thickness of the i-type layer is the same at 250 nm in Example 1 and 250 nm in Comparative Example 1.

(Manufacture of photoelectric conversion devices)
A multi-chamber plasma CVD apparatus is used on a glass substrate 11 (Asahi-VU substrate manufactured by Asahi Glass Co., Ltd.) having a SnO ₂ film as the first conductive layer 12 according to the manufacturing method of the first embodiment. A first photoelectric conversion layer 10 was formed.

First, the p-type silicon-based semiconductor layer 13 was formed as follows. The inside of the first reaction chamber 4 was evacuated to 1 × 10 ⁻⁶ Torr, and the temperature of the substrate 11 was set to 200 ° C. The mixed gas was introduced into the reaction chamber 4 by a flow rate controller, and the pressure in the reaction chamber 4 was kept constant by a conduction valve provided in the exhaust system. The pressure in the reaction chamber 4 was 0.22 Torr. Silane gas, hydrogen gas, methane gas, and diborane gas were used as the mixed gas. After the mixed gas was introduced and the pressure in the reaction chamber 4 was stabilized, 27.12 MHz AC power was supplied to the cathode electrode 3 to generate plasma between the cathode electrode 3 and the anode electrode 2. The plasma was intermittent plasma. The power density per unit area of the cathode electrode 3 was 0.22 W / cm ² . The thickness of the formed p-type silicon-based semiconductor layer 13 was 8 nm.

Next, the i-type amorphous silicon carbide semiconductor layer 14 was formed as follows. The pressure in the second reaction chamber 4 was 0.20 Torr. Silane gas, methane gas, and hydrogen gas were used as the mixed gas. The supply amount of methane gas per unit time relative to the supply amount of silane gas per unit time was set to 50% by volume. After the mixed gas was introduced and the pressure in the reaction chamber 4 was stabilized, 27.12 MHz AC power was supplied to the cathode electrode 3 to generate plasma between the cathode electrode 3 and the anode electrode 2. The plasma was intermittent plasma. The power density per unit area of the cathode electrode 3 was 0.05 W / cm ² . The i-type amorphous silicon carbide semiconductor layer 14 thus formed had a thickness of 200 nm. The band gap Eg was 1.93 eV. The band gap Eg was calculated from single layer transmission / reflection measurements using a tautu plot.

Next, the interface control layer 15 was formed as follows. The i-type amorphous silicon carbide semiconductor layer 14 and the interface control layer 15 were continuously formed in the same reaction chamber. The pressure in the second reaction chamber 4 was 0.20 Torr. 27.12 MHz AC power was applied to the cathode electrode 3 to generate plasma between the cathode electrode 3 and the anode electrode 2. The plasma was intermittent plasma, and the power density per unit area of the cathode electrode 3 was 0.50 W / cm ² . As a mixed gas, a mixed gas containing silane gas, methane gas, hydrogen gas, and carbon dioxide gas was used. Initially, a gas consisting only of silane gas, hydrogen gas, and methane gas was used as a mixed gas, and carbon dioxide gas was not supplied. The supply volume of methane gas per unit time was 50% of the supply volume of silane gas per unit time. Subsequently, the ratio of the supply volume per unit time of carbon dioxide gas to the supply volume of silane gas per unit time is continuously increased, and the supply volume per unit time of carbon dioxide gas is equal to the supply volume per unit time of silane gas. Increased to 50%. At the same time, for the methane gas, the ratio of the supply volume per unit time of the methane gas to the supply volume per unit time of the silane gas was continuously reduced, and the supply amount was set to 0 to form the interface control layer 15. The band gap Eg (minimum band gap Eg) on the light incident side was 1.93 eV, and the band gap Eg (maximum band gap Eg) on the second conductive layer 17 side was 1.93 eV. The thickness of the formed interface control layer 15 was 50 nm.

Next, the n-type silicon-based semiconductor layer 16 was formed as follows. The pressure in the third reaction chamber 4 was 0.22 Torr. A mixed gas containing silane gas and phosphine gas was used as the mixed gas. After introducing the mixed gas and stabilizing the pressure in the reaction chamber 4, AC power of 13.56 MHz was supplied to the cathode electrode 3 to generate plasma between the cathode electrode 3 and the anode electrode 2. The power density per unit area of the cathode electrode 3 was 0.05 W / cm ² . The layer thickness of the formed n-type silicon-based semiconductor layer 16 was 20 nm.

  Next, the second conductive layer 17 was formed as follows. The second conductive layer 17 was composed of a transparent conductive film 17a and a metal film 17b, which were sequentially formed. A 80 nm ZnO film was formed as the transparent conductive film 17a by magnetron sputtering, and a 120 nm silver layer was stacked as the metal film 17b by magnetron sputtering. In this manner, the super straight type photoelectric conversion device 100 of Example 1 was manufactured.

  As the photoelectric conversion device of Comparative Example 1, a photoelectric conversion device different from that of Example 1 was produced only in that the i-type amorphous silicon carbide semiconductor layer 14 had a thickness of 250 nm and no interface control layer was formed.

(Measurement of oxygen concentration and carbon concentration)
About the photoelectric conversion apparatus of Example 1, after etching the 2nd conductive layer 17 with a chemical | medical solution, the oxygen concentration and carbon concentration of the layer thickness direction were measured by secondary ion mass spectrometry (SIMS). FIG. 4 shows the measurement results of Example 1. In FIG. 4, the horizontal axis represents the distance (depth) in the layer thickness direction, and the vertical axis represents the atomic concentration. In this measurement, the acceleration voltage of the primary ion beam was 5.0 kV, and the detection area was 36 × 36 μm ² . The primary ion beam was incident from the back side (second conductive layer 17 side) of the n-type silicon-based semiconductor layer 16. In FIG. 4, the depth of 0 nm is the position where the n-type silicon-based semiconductor layer 16 is in contact with the second conductive layer 17, and the depth value is the layer thickness from the position of the depth of 0 nm toward the substrate 11 side. The distance in the direction is expressed, and the larger the depth value, the closer to the substrate 11 (light incident side).

  As can be seen from FIG. 4, in Example 1, in the region close to the second conductive layer 17 side (back side), the oxygen concentration tends to increase as it progresses in the direction of the second conductive layer 17 side (back side). Show. This is understood to be due to the indentation of oxygen from the surface oxide film on the back surface side. Further, the surface of the Asahi-VU substrate manufactured by Asahi Glass Co., Ltd. used as the substrate 11 on the side where the first conductive layer 12 is provided has a texture structure, and its roughness is about 50 to 200 nm. . Even when the first photoelectric conversion layer 10 is formed on the substrate 11, it is understood that the roughness of 50 to 200 nm still remains on the surface. Therefore, since the detection region in the SIMS measurement includes a plurality of texture particles, it is understood that the peak shown in FIG. 4 is measured as a broader signal than actual.

In FIG. 4, the oxygen concentration has a local maximum at a depth of about 26 nm (interface control layer 15). In Example 1 shown in FIG. 4, since the n-type silicon-based semiconductor layer 16 is formed with a thickness of 20 nm and the interface control layer 15 is formed with a thickness of 50 nm, the vicinity of the depth of 26 nm corresponds to the position of the interface control layer 15. Yes. Therefore, in Example 1, it can be considered that the part where the oxygen concentration has the maximum value is included in the interface control layer 15. The maximum value of the oxygen concentration in the interface control layer 15 was 4.0 × 10 ²¹ (atoms / cm ³ ). The carbon concentration at that time was 6.4 × 10 ²⁰ (atoms / cm ³ ).

(Measurement of energy level)
The energy levels of the i-type amorphous silicon carbide semiconductor layer 14 and the interface control layer 15 of Example 1 were calculated using the following method. Note that all energy levels have a vacuum level of 0 eV. The energy level Ev at the upper end of the valence band was measured using an atmospheric photoelectron spectrometer (trade name: AC-3, manufactured by Riken Keiki Co., Ltd.). Further, the energy level Ec at the lower end of the conduction band was calculated from the energy level Ev at the upper end of the valence band and the band gap Eg obtained from the Tautz plot. The Fermi level Ef was measured using a Fermi level measuring device (trade name: FAC-2, manufactured by Riken Keiki Co., Ltd.).

  Table 1 shows energy levels of the i-type amorphous silicon carbide semiconductor layer and the interface control layer of the photoelectric conversion device of Example 1 near the light incident side surface and near the back surface side.

  As can be seen from Table 1, the energy level Ev at the top of the valence band and the energy level Ec at the bottom of the conduction band in the interface control layer are deeper in the vicinity of the back surface side than in the vicinity of the light incident surface. It was.

(Evaluation of electrical characteristics)
The electrical characteristics of Example 1 and Comparative Example 1 were measured. The measurement conditions were a spectral distribution AM1.5, irradiation with a light intensity of 100 mW / cm ² , and a measurement temperature of 25 ° C. Table 2 shows the measurement results.

  As shown in Table 2, in Example 1 in which the interface control layer 15 was formed, both the short-circuit current density and the open-circuit voltage were improved as compared with Comparative Example 1 having no interface control layer. That is, it can be seen that the short circuit current and the open circuit voltage are both improved by the interface control layer 15 containing oxygen and carbon.

  This is because the interface control layer has the same Fermi level Ef and the same band gap Eg as the i-type amorphous silicon carbide semiconductor layer, but the energy level at the lower end of the conduction band. Since the energy level Ev at the top of Ec and the valence band is relatively deep, the diffusion of holes to the n-type silicon-based semiconductor layer side is reduced and the reverse saturation current is improved, improving the characteristics It is thought that.

[Example 2, Comparative Example 2]
(Configuration of photoelectric conversion device)
As Example 2, a photoelectric conversion device having the same configuration as that of the photoelectric conversion device 100 of the first embodiment shown in FIG. 1 was produced. The film thickness of the i-type amorphous silicon carbide semiconductor layer 14 of Example 2 was 320 nm, and the film thickness of the interface control layer 15 was 50 nm. Further, as Comparative Example 2, a photoelectric conversion device different from Example 2 was manufactured only in that the thickness of the i-type amorphous silicon carbide semiconductor layer 14 was 370 nm and the interface control layer was not formed. Since the interface control layer of Example 2 is i-type, the total film thickness of the i-type layer is 370 nm in Example 2 and 370 nm in Comparative Example 2.

(Manufacture of photoelectric conversion devices)
A multi-chamber plasma CVD apparatus is used on a glass substrate 11 (Asahi-VU substrate manufactured by Asahi Glass Co., Ltd.) having a SnO ₂ film as the first conductive layer 12 according to the manufacturing method of the first embodiment. A first photoelectric conversion layer 10 was formed.

First, the p-type silicon-based semiconductor layer 13 was formed as follows. The inside of the first reaction chamber 4 was evacuated to 1 × 10 ⁻⁶ Torr, and the temperature of the substrate 11 was set to 200 ° C. The mixed gas was introduced into the reaction chamber 4 by a flow rate controller, and the pressure in the reaction chamber 4 was kept constant by a conduction valve provided in the exhaust system. The pressure in the reaction chamber 4 was 0.22 Torr. Silane gas, hydrogen gas, methane gas, and diborane gas were used as the mixed gas. After the mixed gas was introduced and the pressure in the reaction chamber 4 was stabilized, 27.12 MHz AC power was supplied to the cathode electrode 3 to generate plasma between the cathode electrode 3 and the anode electrode 2. The plasma was intermittent plasma. The power density per unit area of the cathode electrode 3 was 0.22 W / cm ² . The thickness of the formed p-type silicon-based semiconductor layer 13 was 8 nm.

Next, the i-type amorphous silicon carbide semiconductor layer 14 was formed as follows. The pressure in the second reaction chamber 4 was 0.20 Torr. Silane gas, methane gas, and hydrogen gas were used as the mixed gas. The supply amount per unit time of methane gas with respect to the supply amount per unit time of silane gas was set to 59% by volume. After the mixed gas was introduced and the pressure in the reaction chamber 4 was stabilized, 27.12 MHz AC power was supplied to the cathode electrode 3 to generate plasma between the cathode electrode 3 and the anode electrode 2. The plasma was intermittent plasma. The power density per unit area of the cathode electrode 3 was 0.05 W / cm ² . The thickness of the formed i-type amorphous silicon carbide semiconductor layer 14 was 320 nm. The band gap Eg was 1.95 eV. The band gap Eg was calculated from single layer transmission / reflection measurements using a tautu plot.

Next, the interface control layer 15 was formed as follows. The i-type amorphous silicon carbide semiconductor layer 14 and the interface control layer 15 were continuously formed in the same reaction chamber. The pressure in the second reaction chamber 4 was 0.20 Torr. 27.12 MHz AC power was applied to the cathode electrode 3 to generate plasma between the cathode electrode 3 and the anode electrode 2. The plasma was intermittent plasma, and the power density per unit area of the cathode electrode 3 was 0.50 W / cm ² . As a mixed gas, a mixed gas containing silane gas, methane gas, hydrogen gas, and carbon dioxide gas was used. Initially, a gas consisting only of silane gas, hydrogen gas, and methane gas was used as a mixed gas, and carbon dioxide gas was not supplied. The supply volume per unit time of methane gas was 59% of the supply volume per unit time of silane gas. Subsequently, the ratio of the supply volume per unit time of carbon dioxide gas to the supply volume of silane gas per unit time is continuously increased, and the supply volume per unit time of carbon dioxide gas is equal to the supply volume per unit time of silane gas. Increased to 67%. At the same time, for the methane gas, the ratio of the supply volume per unit time of the methane gas to the supply volume per unit time of the silane gas was continuously reduced, and the supply amount was set to 0 to form the interface control layer 15. An interface control layer 15 was formed. By forming in this way, a graded structure having the smallest band gap on the light incident side and the largest band gap on the back surface side (second conductive layer 17 side) was formed. The band gap Eg (minimum band gap Eg) on the light incident side was 1.95 eV, and the band gap Eg (maximum band gap Eg) on the second conductive layer 17 side was 1.99 eV. The thickness of the formed interface control layer 15 was 50 nm.

Next, the n-type silicon-based semiconductor layer 16 was formed as follows. The pressure in the third reaction chamber 4 was 0.22 Torr. A mixed gas containing silane gas and phosphine gas was used as the mixed gas. After introducing the mixed gas and stabilizing the pressure in the reaction chamber 4, AC power of 13.56 MHz was supplied to the cathode electrode 3 to generate plasma between the cathode electrode 3 and the anode electrode 2. The power density per unit area of the cathode electrode 3 was 0.05 W / cm ² . The layer thickness of the formed n-type silicon-based semiconductor layer 16 was 20 nm.

  Next, the second conductive layer 17 was formed as follows. The second conductive layer 17 was composed of a transparent conductive film 17a and a metal film 17b, which were sequentially formed. A 80 nm ZnO film was formed as the transparent conductive film 17a by magnetron sputtering, and a 120 nm silver layer was stacked as the metal film 17b by magnetron sputtering. In this manner, a super straight type photoelectric conversion device 100 of Example 2 was produced.

  As a photoelectric conversion device of Comparative Example 2, a photoelectric conversion device different from that of Example 2 was produced only in that the i-type amorphous silicon carbide semiconductor layer 14 had a thickness of 370 nm and no interface control layer was formed.

(Measurement of oxygen concentration and carbon concentration)
About the photoelectric conversion apparatus of Example 2, after etching the 2nd conductive layer 17 with a chemical | medical solution, the oxygen concentration and carbon concentration of the layer thickness direction were measured by secondary ion mass spectrometry (SIMS). FIG. 5 shows the measurement results of Example 2. In FIG. 5, the horizontal axis represents the distance (depth) in the layer thickness direction, and the vertical axis represents the atomic concentration. In this measurement, the acceleration voltage of the primary ion beam was 5.0 kV, and the detection area was 36 × 36 μm ² . The primary ion beam was incident from the back side (second conductive layer 17 side) of the n-type silicon-based semiconductor layer 16. In FIG. 4, the depth of 0 nm is the position where the n-type silicon-based semiconductor layer 16 is in contact with the second conductive layer 17, and the depth value is the layer thickness from the position of the depth of 0 nm toward the substrate 11 side. The distance in the direction is expressed, and the larger the depth value, the closer to the substrate 11 (light incident side).

  As can be seen from FIG. 5, in Example 2, in the region close to the second conductive layer 17 side (back side), the oxygen concentration tends to increase as it proceeds in the direction of the second conductive layer 17 side (back side). Show. This is understood to be due to the indentation of oxygen from the surface oxide film on the back surface side. Further, the surface of the Asahi-VU substrate manufactured by Asahi Glass Co., Ltd. used as the substrate 11 on the side where the first conductive layer 12 is provided has a texture structure, and its roughness is about 50 to 200 nm. . Even when the first photoelectric conversion layer 10 is formed on the substrate 11, it is understood that the roughness of 50 to 200 nm still remains on the surface. Therefore, since the detection region in the SIMS measurement includes a plurality of texture particles, it is understood that the peak shown in FIG. 5 is measured as a broader signal than actual.

In FIG. 5, the oxygen concentration has a local maximum at a depth of about 33 nm (interface control layer 15). In Example 2 shown in FIG. 5, since the n-type silicon-based semiconductor layer 16 is formed with a thickness of 20 nm and the interface control layer 15 is formed with a thickness of 50 nm, the vicinity of the depth of 33 nm corresponds to the position of the interface control layer 15. Yes. Therefore, in Example 2, it can be considered that the part where the oxygen concentration has the maximum value is included in the interface control layer 15. The maximum value of the oxygen concentration in the interface control layer 15 was 4.3 × 10 ²¹ (atoms / cm ³ ). The carbon concentration at that time was 4.3 × 10 ²⁰ (atoms / cm ³ ).

(Measurement of energy level)
The energy levels of the i-type amorphous silicon carbide semiconductor layer 14 and the interface control layer 15 of Example 2 were calculated using the following method. Note that all energy levels have a vacuum level of 0 eV. The energy level Ev at the upper end of the valence band was measured using an atmospheric photoelectron spectrometer (trade name: AC-3, manufactured by Riken Keiki Co., Ltd.). Further, the energy level Ec at the lower end of the conduction band was calculated from the energy level Ev at the upper end of the valence band and the band gap Eg obtained from the Tautz plot. The Fermi level Ef was measured using a Fermi level measuring device (trade name: FAC-2, manufactured by Riken Keiki Co., Ltd.).

  Table 3 shows energy levels of the i-type amorphous silicon carbide semiconductor layer and the interface control layer of the photoelectric conversion device of Example 2 near the light incident surface and near the back surface.

  As can be seen from Table 3, the energy level Ev at the top of the valence band and the energy level Ec at the bottom of the conduction band in the interface control layer are deeper in the vicinity of the back surface side than in the vicinity of the light incident surface. It was.

(Evaluation of electrical characteristics)
The electrical characteristics of Example 2 and Comparative Example 2 were measured. The measurement conditions were a spectral distribution AM1.5, irradiation with a light intensity of 100 mW / cm ² , and a measurement temperature of 25 ° C. Table 4 shows the measurement results.

  As shown in Table 2, in Example 2 in which the interface control layer 15 was formed, the open-circuit voltage was improved as compared with Comparative Example 2 having no interface control layer. That is, it can be seen that the open circuit voltage is improved by the interface control layer 15 containing oxygen and carbon.

  This is because the interface control layer has the same Fermi level Ef and a slightly larger band gap Eg than the i-type amorphous silicon carbide semiconductor layer, but the lower end of the conduction band. Since the energy level Ec and the energy level Ev at the upper end of the valence band are relatively deep, the diffusion of holes to the n-type silicon-based semiconductor layer side is reduced and the reverse saturation current is improved. It is thought that the characteristics were improved.

  DESCRIPTION OF SYMBOLS 1 Heater, 2 Anode electrode, 3 Cathode electrode, 4 Reaction chamber, 5 Matching circuit, 6 High frequency power supply, 10 1st photoelectric converting layer, 11 board | substrate, 12 1st conductive layer, 13 p-type silicon type semiconductor layer, 14 i type Amorphous silicon carbide semiconductor layer, 15 interface control layer, 16 n-type silicon-based semiconductor layer, 16a n-type amorphous silicon layer, 16b n-type microcrystalline silicon layer, 17 second conductive layer, 17a transparent conductive film, 17b Metal film, 20 second photoelectric conversion layer, 21 p-type silicon-based semiconductor layer, 22 i-type silicon-based semiconductor layer, 23 n-type silicon-based semiconductor layer, 23a n-type amorphous silicon-based semiconductor layer, 23b n-type microcrystal Silicon-based semiconductor layer, 100, 200 photoelectric conversion device.

Claims (5)

A photoelectric conversion device in which a first conductive layer, a first photoelectric conversion layer, and a second conductive layer are laminated in this order,
The first photoelectric conversion layer includes a p-type silicon-based semiconductor layer, an i-type amorphous silicon carbide semiconductor layer, and an interface control, which are sequentially stacked from the first conductive layer side to the second conductive layer side. A layer and an n-type silicon-based semiconductor layer,
The said interface control layer is a photoelectric conversion apparatus containing a silicon atom, a carbon atom, and an oxygen atom. 2. The photoelectric conversion device according to claim 1, wherein an oxygen concentration of the interface control layer is 1 × 10 ²⁰ (atoms / cm ³ ) or more and 1 × 10 ²² (atoms / cm ³ ) or less.   The photoelectric conversion device according to claim 1, wherein the interface control layer has a maximum value of oxygen concentration in a layer thickness direction. The photoelectric conversion device according to claim 1, wherein a carbon concentration of the interface control layer is 1 × 10 ²⁰ (atoms / cm ³ ) or more and 2 × 10 ²¹ (atoms / cm ³ ) or less. It is a manufacturing method of the photoelectric conversion device according to claim 1,
A method for manufacturing a photoelectric conversion device, comprising a step of supplying a gas containing silicon atoms, carbon atoms, and oxygen atoms to form the interface control layer.

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