JP2014053835A - Saturated amplification circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent DC offset cancellation from becoming incomplete by measuring a signal level of a saturated amplifier of each stage and comprehensively controlling a gain of the saturated amplifier of each stage on the basis of the result.SOLUTION: A saturated amplification circuit includes: saturated amplifiers (intermediate stages) 104a, 104b, 104c connected in series; a memory for storing upper limit signal levels that are upper limit values of signal level of signals which, when amplified, have an amplification range within a linear amplification range, in association with the saturated amplifiers (intermediate stages) 104a, 104b, 104c; a power measurement circuit 109 for measuring the signal level of a signal input into at least any one of the saturated amplifiers (intermediate stages) 104a, 104b, 104c, and outputting the measured signal level as a measurement signal level; and a control signal generation circuit 108 for controlling gains of the saturated amplifiers (intermediate stages) 104a, 104b, 104c on the basis of the measurement signal level output from the power measurement circuit 109 and the upper limit signal levels stored in the memory.

Description

  The present invention relates to a saturation amplifier circuit including a DC offset cancel circuit that cancels a DC offset.

  In an analog circuit, a DC offset is generated due to variations in elements constituting the circuit, which causes deterioration of characteristics. Among them, the saturation amplifier has a very high gain in order to amplify a minute signal to a desired signal level. For this reason, the DC offset is also amplified at a high gain at the same time, and the characteristic deterioration appears remarkably. In order to avoid such characteristic deterioration due to DC offset, a method of adding a DC offset cancel circuit has been conventionally used.

  However, in a saturated amplifier having a high gain, when a signal of a certain level or more is input, the output is saturated, and the gain is relatively lowered with respect to the input signal. Due to the relative gain reduction, the DC offset cancellation does not function normally, and characteristic deterioration occurs.

The following techniques are disclosed as techniques for suppressing such deterioration of characteristics.
Patent Document 1 discloses a technique for distributing a correction voltage to each stage.
Patent Document 2 discloses a technique for controlling the gain of the entire amplification stage.
Patent Document 3 discloses a technique for adjusting a feedback amount with an external gain control voltage.
In Patent Document 4, the second correction unit is corrected based on the input to the second amplifier after controlling the amplification gain of the first amplifier to be maximum, and then the corrected first gain is corrected. A technique is disclosed in which the correction of the first correction unit is performed based on the two amplified signals and the adjustment is performed in order from the side closer to the output.

JP 2005-278153 A JP 2011-250136 A JP 2004-072361 A JP 2012-039363 A

  Patent Document 1 discloses a technique for distributing a correction voltage to each stage. However, since correction is performed by directly applying the correction voltage to a signal line, there is a problem that the operation becomes complicated.

  Patent Document 2 discloses gain control of the entire amplification stage, but there is a problem that individual gain control with high accuracy cannot be performed because of gain control of the entire amplification stage.

  Patent Document 3 has a problem that the amount of feedback is adjusted by an external gain control voltage, and the signal level cannot be measured to generate a control signal internally.

  In Patent Document 4, the second correction unit is corrected based on the input to the second amplifier after controlling the amplification gain of the first amplifier to be maximum, and then the corrected first gain is corrected. The correction of the first correction unit is performed based on the second amplified signal, and there is a problem that collective control cannot be performed and the operation becomes complicated.

  An object of the present invention is to measure the signal level of each stage saturation amplifier and collectively control the gain of each stage saturation amplifier based on the result to prevent incomplete DC offset cancellation.

A saturation amplification circuit according to the present invention includes a plurality of saturation amplifiers connected in series, and the amplification range after amplification when each saturation amplifier of the plurality of saturation amplifiers is input to each saturation amplifier. A memory for associating and storing an upper limit signal level, which is an upper limit value of the signal level of the signal falling within the range, and a signal level of a signal input to at least one of the plurality of saturation amplifiers, and measuring the measured signal level A power measurement circuit that outputs a signal as a measurement signal level;
A control circuit for controlling the gain of each saturation amplifier based on the measurement signal level output from the power measurement circuit and the upper limit signal level corresponding to each saturation amplifier stored in the memory. Features.

  According to the saturation amplifier circuit of the present invention, the adjustment of the gain of the saturation amplifier can be individually controlled and collectively controlled by the operation of the components configured therein.

1 is a circuit configuration diagram of a saturation amplifier circuit 100 according to Embodiment 1. FIG. 3 is an example of a circuit configuration diagram of a saturation amplifier circuit 101 according to Embodiment 2. FIG. 6 is another example of a circuit configuration diagram of the saturation amplifier circuit 101 according to the second embodiment. FIG. 5 is a circuit configuration diagram of a saturation amplifier circuit 102 according to a third embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the description of each embodiment, the directions such as “up”, “down”, “left”, “right”, “front”, “back”, “front”, “back” are However, it is not intended to limit the arrangement or orientation of devices, instruments, parts, or the like.

Embodiment 1 FIG.
FIG. 1 is a circuit configuration diagram of a saturation amplifier circuit 100 according to the present embodiment.

  In FIG. 1, a saturation amplification circuit 100 includes a saturation amplification unit 104, which is an intermediate stage, a saturation amplifier (output stage) 105, an LPF (low-pass filter), a feedback amplifier 106, a power measurement circuit 109, a control signal generation circuit 108, and an addition circuit. 110.

  The saturation amplification unit 104 includes saturation amplifiers (intermediate stages) 104a, 104b, and 104c connected in series. The input signal Pin applied to the saturation amplifier 104 is amplified by saturation amplifiers (intermediate stages) 104a, 104b, and 104c, further amplified by the saturation amplifier (output stage) 105, and output as an output signal Pout.

  The LPF feeds back only the DC offset component of the amplified output output from the saturation amplification unit 104 to the input side of the saturation amplification unit 104. This DC offset component is converted into a predetermined feedback signal via the feedback amplifier 106 and added to the input signal Pin by the adder circuit 110. Thereby, the DC offset component is removed from the input signal Pin. The saturation amplifier circuit 100 is a DC offset cancel circuit that cancels (removes) the DC offset in this way.

  Saturation amplifiers (intermediate stages) 104a to 104c and feedback amplifier 106 are saturated amplifiers each capable of setting gains in several stages by applying the control signal generated by control signal generation circuit 108. It does not matter whether the saturation amplifier 105 has a gain setting function.

  The power measurement circuit 109 measures the signal level of a signal input to at least one of the plurality of saturation amplifiers (intermediate stages) 104a, 104b, and 104c, and uses a signal corresponding to the measured signal level as a measurement signal level. Output. The power measurement circuit 108 outputs a measurement signal level corresponding one-to-one with the signal level of the measurement point input.

  As shown in FIG. 1, in this embodiment, the input side (Sa) of the saturation amplifier (intermediate stage) 104a, the input side (Sb) of the saturation amplifier (intermediate stage) 104b, and the input of the saturation amplifier (intermediate stage) 104c. Three points on the side (Sc) are measurement points. The signal level on the input side of the saturation amplifier (intermediate stage) 104a is the measurement signal level La, the signal level on the input side of the saturation amplifier (intermediate stage) 104b is the measurement signal level Lb, and the input side of the saturation amplifier (intermediate stage) 104c. This signal level is defined as a measurement signal level Lc. The measurement signal levels La, Lb, and Lc are signals indicating the signal levels on the input side of the saturation amplifiers (intermediate stages) 104a, 104b, and 104c.

  The control signal generation circuit 108 receives the measurement signal levels La, Lb, and Lc of the measurement points Sa, Sb, and Sc sent from the power measurement circuit 109, and saturates the saturation amplifiers (intermediate stages) 104a, 104b, and 104c.・ Determine non-saturation. The control signal generation circuit 108 generates a control signal to be applied to each of the saturated amplifiers (intermediate stages) 104a, 104b, and 104c based on the determination result.

  Next, a description will be given of a decrease in the DC offset cancel capability in the presupposed DC offset cancel circuit. Here, a saturation amplification circuit 100 in the case where the power measurement circuit 109 and the control signal generation circuit 108 are not provided is assumed as the DC offset cancellation circuit.

The input signal of the saturation amplification unit 104 is defined as Pin_offset of the DC offset component, and the DC offset component Pout_offset of the output signal of the saturation amplification unit 104. Further, the gain of the saturation amplifiers (intermediate stages) 104a, 104b, and 104c as a whole is A, and the gain of the feedback amplifier 106 is G. At this time, the transfer function of the DC component is expressed by Equation 1 below.
Pout_offset = − (A / (1 + AG)) Pin_offset (Equation 1)

  When a signal of a certain level or higher is input to the DC offset cancel circuit (saturation amplifier circuit 100 when there is no power measurement circuit 109 and control signal generation circuit 108), saturation amplifiers (intermediate stages) 104a and 104b of the saturation amplifier 104. , 104c, the output is saturated, and the gain A is relatively lowered with respect to the input signal. When the gain A is relatively lowered with respect to the input signal, the value of the DC offset (Pout_offset) to be fed back becomes small as shown in the above equation 1. That is, when the amplification range is saturated (when the gain A is relatively lowered) compared to the operation when the amplification range is a linear region (when the gain A is not relatively lowered). Decreases the DC offset canceling ability.

  In the saturation amplifier circuit 100 (a circuit including the power measurement circuit 109 and the control signal generation circuit 108) according to the present embodiment, the gain of each of the saturation amplifiers (saturation amplifiers (intermediate stages) 104a, 104b, and 104c) depends on the input level. And control is performed so as not to saturate until the input of the final stage (saturation amplifier (output stage) 105).

  Next, the operation of the saturation amplifier circuit 100 according to the present embodiment will be described.

  The power measurement circuit 109 measures the measurement signal levels La, Lb, and Lc at the measurement points Sa, Sb, and Sc. The power measurement circuit 109 generates a DC signal having a level corresponding to the measured measurement signal level and sends it to the control signal generation circuit 108. The power measurement circuit 109 generates and outputs a DC signal having a level corresponding to the measurement signal level for each measurement point.

  The control signal generation circuit 108 has a threshold value generated inside. The threshold generated inside is, for example, the signal level of a signal in which the amplification range after amplification falls within the linear amplification range when input to itself for each of the saturation amplifiers (intermediate stages) 104a, 104b, and 104c. The upper limit signal level, which is the upper limit value, is stored in a memory or the like in association with it. The memory may be provided inside the control signal generation circuit 108 or may be provided outside the control signal generation circuit 108. Assume that upper limit signal levels Ma, Mb, and Mc are associated with saturation amplifiers (intermediate stages) 104a, 104b, and 104c, respectively.

  The threshold values (upper limit signal levels Ma, Mb, Mc) may be design values stored in advance in the memory. Alternatively, the outputs of the saturation amplifiers (intermediate stages) 104a, 104b, and 104c that can be confirmed from the measurement results of the saturation amplifiers (intermediate stages) 104a, 104b, and 104c alone are saturated with the threshold values (upper limit signal levels Ma, Mb, and Mc). A DC signal level corresponding to the input level may be set.

  Based on the measurement signal level output from the power measurement circuit 109 and the upper limit signal level (threshold value) corresponding to each saturation amplifier stored in the memory, the control signal generation circuit 108 (control circuit) The gain of each saturation amplifier is controlled so as not to saturate.

  For example, the control signal generation circuit 108 compares the measurement signal level of each saturation amplifier output from the power measurement circuit 108 with the upper limit signal level corresponding to each saturation amplifier stored in the memory, and If the measured signal level is higher than the upper limit signal level corresponding to each saturation amplifier, a control signal is generated to lower the gain of each saturation amplifier so that each saturation amplifier does not saturate, and the generated control signal is output to each saturation amplifier. To do. The control signal generation circuit 108 sends control signals to all the saturation amplifiers to be controlled at once.

  The control signal generation circuit 108 compares each signal (measurement signal level) generated by the power measurement circuit 109 with a threshold value generated internally, so that each stage amplifier (saturation amplifier (intermediate stage) 104a, 104b, 104c). Generate a control signal to The gain setting of each stage (saturation amplifier (intermediate stage) 104a, 104b, 104c) is determined according to the measured signal, and the control signal is sent to all the saturation amplifiers to be controlled.

  If the input level at the measurement point is large and the output of the intermediate stage saturates, the control signal generation circuit 108 can select one of the saturation amplifiers (intermediate stages) 104a to 104c and the feedback amplifier 106 according to the input signal level. Alternatively, automatic adjustment is performed by applying a control signal for reducing the gain to the control terminal for all of them.

  In this way, saturation in the intermediate stage is prevented by automatically controlling the gain in the loop according to the input level. By preventing saturation at the intermediate stage, offset cancellation functions normally in a desired range.

  As described above, the saturation amplification circuit 100 according to the present embodiment measures the signal level between the input and the stage by the power measurement circuit 109 connected to the input unit and the output of each stage saturation amplifier, and is proportional to the input signal. The control signal generation circuit 108 generates a control signal based on the comparison between the measurement result and the internally generated threshold value, and each stage (saturation amplifier (intermediate stage) 104a, 104b, 104c) is a DC offset cancel circuit characterized by automatically adjusting the gains individually.

  In the saturation amplifier circuit 100 according to the present embodiment, the control signal generation circuit 108 generates a control signal to each stage amplifier based on the signal level between the stages measured by the power measurement circuit 109. When a signal with a large signal level is input, the gain of each stage amplifier is controlled to decrease so as not to saturate at the intermediate stage, and the signal between stages is always kept within the linear amplification range. Even if it exists, a normal offset cancel operation is made possible. As a result, it is possible to prevent characteristic deterioration due to DC offset.

  According to the saturation amplifier circuit 100 according to the present embodiment, in a saturated amplifier connected in multiple stages, the gain is relatively lowered due to saturation in the intermediate amplifier, and the DC offset cancellation by the DC feedback system becomes incomplete. Improve.

  According to the saturation amplifier circuit 100 according to the present embodiment, the signal level between stages is measured for saturated amplifiers connected in multiple stages, and the gain of each stage amplifier is controlled not to be saturated at the intermediate stage based on the result. However, it is possible to prevent characteristic deterioration by being within the linear amplification range.

  According to the saturation amplifier circuit 100 according to the present embodiment, by adjusting so that the DC offset cancellation does not normally function due to output saturation in the intermediate stage, the adjustment is performed so that it functions normally. Thus, it is possible to perform normal amplification while suppressing the influence of the DC offset.

Embodiment 2. FIG.
FIG. 2 is an example of a circuit configuration diagram of the saturation amplifier circuit 101 according to the present embodiment. FIG. 3 is another example of a circuit configuration diagram of the saturation amplifier circuit 101 according to the present embodiment.

  Differences between the saturation amplifier circuit 100 and the saturation amplifier circuit 101 according to the first embodiment will be described with reference to FIGS. 2 and 3. 2 and 3, the same functional components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

  2 is different from FIG. 1 in that the saturation amplification circuit 101 is provided with the measurement point Sd only on the input side of the saturation amplification unit 104 (input side of the addition circuit 110).

  The power measurement circuit 109 measures the input level at the measurement point Sd and outputs the measurement signal level Ld to the control signal generation circuit 108.

  The control signal generation circuit 108 is based on the measurement signal level Ld of the measurement point Sd input from the power measurement circuit 109, so that the saturation amplifiers (intermediate stages) 104a, 104b, and 104c are not saturated. A control signal for adjusting the gain of each of 104a, 104b, and 104c is generated. The control signal generation circuit 108 transmits the control signals of the generated saturation amplifiers (intermediate stages) 104a, 104b, and 104c all at once.

  For example, the control signal generation circuit 108 stores the characteristics (gains) of the saturation amplifiers (intermediate stages) 104a, 104b, and 104c and the feedback amplifier 106. The control signal generation circuit 108 calculates the input levels of the saturation amplifiers (intermediate stages) 104a, 104b, and 104c from the input measurement signal level Ld of the measurement point Sd and the respective characteristics (gains). The input levels Ka, Kb, Calculated as Kc. Then, the control signal generation circuit 108 includes threshold values (upper limit signal levels Ma, Mb, Mc) of the saturation amplifiers (intermediate stages) 104a, 104b, 104c stored in the memory, and calculated calculated signal levels Ka, Kb, Compare with Kc. Based on the comparison result, the control signal generation circuit 108 generates control signals corresponding to the saturation amplifiers (intermediate stages) 104a, 104b, and 104c so that the saturation amplifiers (intermediate stages) 104a, 104b, and 104c are not saturated. . Then, the control signal generation circuit 108 collectively transmits control signals corresponding to the saturation amplifiers (intermediate stages) 104a, 104b, and 104c to the saturation amplifiers (intermediate stages) 104a, 104b, and 104c, respectively.

  As shown in FIG. 3, the saturation amplifier circuit 101 may provide the measurement point Sd between the saturation amplifier (intermediate stage) 104b and the saturation amplifier (intermediate stage) 104c. Alternatively, the measurement point Sd may be provided between the saturation amplifier (intermediate stage) 104b and the saturation amplifier (intermediate stage) 104c. Alternatively, two measurement points are provided between the saturation amplifier (intermediate stage) 104a and the saturation amplifier (intermediate stage) 104b, and between the saturation amplifier (intermediate stage) 104b and the saturation amplifier (intermediate stage) 104c. Also good. Any number of measurement points may be arranged as long as the control signal generation circuit 108 can adjust the respective gains of the saturation amplifiers (intermediate stages) 104a to 104c.

Embodiment 3 FIG.
FIG. 4 is a circuit configuration diagram of the saturation amplifier circuit 102 according to the present embodiment. In FIG. 4, differences from FIG. 1 will be described. The same functional components as those in FIG.

  As shown in FIG. 4, in the saturation amplifier circuit 102, the power measurement circuit 109 is a peak hold circuit 111. The operation in the configuration of the saturation amplifier circuit 102 will be described with reference to FIG.

  In the configuration of the saturation amplifier circuit 102, the peak level circuit 111 is used to measure the voltage at the signal level at each measurement point. About the position of a measurement point, as demonstrated in Embodiment 1-2, it can provide in Sa, Sb, Sc, Sd (refer FIGS. 1-3) and other positions.

  The peak hold circuit 111 detects and holds the maximum value or the minimum value of the signal amplitude at the measurement point, and sends it to the control signal generation circuit 108 as a measurement signal level. The operation when the control signal generation circuit 108 receives the measurement signal level is the same as that described in the first and second embodiments.

  Since the saturation amplification circuit 102 according to the present embodiment includes the power measurement circuit that performs the signal level measurement of the measurement point using the operation of holding the maximum value or the minimum value of the input signal amplitude of the peak hold circuit 111, A circuit can be easily configured using an existing circuit.

  As mentioned above, although embodiment of this invention was described, you may implement in combination of 2 or more among these embodiment. Alternatively, one of these embodiments may be partially implemented. Alternatively, two or more of these embodiments may be partially combined. In addition, this invention is not limited to these embodiment, A various change is possible as needed.

  100, 101, 102 Saturation amplification circuit, 104 Saturation amplification unit, 104a, 104b, 104c Saturation amplifier (intermediate stage), 105 Saturation amplifier (output stage), 106 Feedback amplifier, 108 Control signal generation circuit, 109 Power measurement circuit, 110 Adder circuit, 111 peak hold circuit, Ma, Mb, Mc upper limit signal level, La, Lb, Lc measurement signal level, Pin input signal, Pout output signal, Sa, Sb, Sc, Sd measurement point.

Claims (3)

A plurality of saturation amplifiers connected in series;
For each saturation amplifier of the plurality of saturation amplifiers, an upper limit signal level that is an upper limit value of the signal level of the signal within which the amplification range after amplification falls within the linear amplification range when input to each saturation amplifier is stored in association with each other. Memory,
A power measurement circuit for measuring a signal level of a signal input to at least one of the plurality of saturation amplifiers and outputting the measured signal level as a measurement signal level;
A control circuit for controlling the gain of each saturation amplifier based on the measurement signal level output from the power measurement circuit and the upper limit signal level corresponding to each saturation amplifier stored in the memory. A featured saturation amplifier circuit. The power measurement circuit includes:
Measuring a signal level of a signal input to each saturation amplifier of the plurality of saturation amplifiers, and outputting the measurement signal level of each saturation amplifier;
The control circuit includes:
The measurement signal level of each saturation amplifier output from the power measurement circuit is compared with the upper limit signal level corresponding to each saturation amplifier stored in the memory. 2. The control signal according to claim 1, wherein when the upper limit signal level corresponding to a saturation amplifier is higher than the upper limit signal level, a control signal for reducing a gain of each saturation amplifier is generated, and the generated control signal is output to each saturation amplifier. Saturation amplifier circuit. The power measurement circuit includes:
The saturation amplifier circuit according to claim 1, wherein the saturation amplifier circuit is a peak hold circuit.

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