JP2014053761A - Data spreading circuit and frequency measurement circuit - Google Patents

Abstract

Noise of a digital filter circuit connected to a subsequent stage is suppressed.
When the input data IN changes by a minute value from the same continuous data, the data distribution circuit distributes the change amount to a plurality of times and outputs it to the subsequent stage while sequentially adding it to the continuous data. For example, when the input data IN changes by −1 LSB from “8” to “7”, the 16 times input data IN × 16 changes by −16 LSB from “128” to “112”. At this time, the data distribution circuit does not output “112” once as the distributed input data IN ′, but outputs “124” four times with a predetermined distribution interval.
[Selection] Figure 7

Description

  Of the various inventions disclosed in this specification, the first invention relates to a data distribution circuit, and the second invention relates to a frequency measurement circuit.

  Patent document 1 can be mentioned as an example of the prior art relevant to the noise suppression technique of a digital filter circuit.

  Moreover, Patent Documents 2 to 5 can be cited as examples of conventional techniques related to the frequency measurement circuit.

JP 2000-299622 A JP-A-6-326629 JP 2003-143006 A JP 2012-5022 A JP 2009-250807 A

  In Patent Document 1, by providing a gain adjustment circuit before and after the digital filter circuit, limit cycle oscillation that occurs when minute data is input is suppressed. However, before and after the digital filter circuit, the gain adjustment timing corresponding to the processing of the same data is different, so that data change at the gain adjustment timing is a problem.

  In Patent Document 2, a differential frequency fout between an input frequency f1 and a reference frequency f2 is generated using a D flip-flop. However, this conventional method has a problem that the measurement accuracy does not increase (noise is generated) because the differential frequency fout is low, and it is difficult to apply to an application that requires high detection accuracy of the differential frequency. .

  In Patent Document 3, a beat waveform signal having a difference frequency between an input signal (for example, a PLL [phase locked loop] output signal) and a reference clock signal is generated, and a divided clock signal and a beat waveform obtained by dividing the reference clock signal by N. The difference frequency between the input signal and the reference clock signal is measured by comparing the signal. However, even in this conventional method, as in Patent Document 2, the output frequency of the beat waveform signal (the difference frequency between the input signal and the reference clock signal) is lowered, and there is a problem that the measurement accuracy does not increase.

  In Patent Document 4, in order to detect a phase difference between two input signals with high accuracy, a delay circuit is inserted into one input signal, and edge detection is performed to detect a phase difference. However, this conventional method is only for detecting the phase difference between two input signals and not for measuring the difference frequency.

  Patent Document 5 discloses a configuration in which when measuring the frequency of an input signal using a counter and a low-pass filter, the frequency measurement accuracy is improved by counting the number of pulses of the input signal while switching a plurality of counters. However, in this conventional method, since the input signal is only one system, if the cutoff frequency of the low-pass filter cannot be lowered in order to increase the response speed, even if a plurality of counters are used, the low-pass filter There was a problem that noise was generated in the output signal.

Of the various inventions disclosed in this specification, the first invention suppresses the noise of the digital filter circuit connected to the subsequent stage in view of the above-described problems found by the inventors of the present application. An object of the present invention is to provide a data distribution circuit that can perform the above-described processing.
<Second purpose>
Of the various inventions disclosed in this specification, the second invention measures the frequency of the input signal with high accuracy in view of the above-mentioned problems found by the inventors of the present application. An object of the present invention is to provide a frequency measurement circuit capable of performing

<First invention>
Of the various inventions disclosed in this specification, the data distribution circuit according to the first invention, when digital input data changes by a minute value from the same continuous data, changes the amount of change multiple times. The data is output to the subsequent stage while being sequentially added to the continuous data (first-first configuration).

  The data distribution circuit having the above configuration 1-1 includes a continuous data holding unit that holds the continuous data, a minute change detection unit that detects minute changes in the input data, and the number of continuous times of the continuous data. A continuous number detection unit to detect, a control unit that controls data distribution processing based on each detection result of the minute change detection unit and the continuous number detection unit, and the input data and the continuous in accordance with an instruction from the control unit A selector that selectively outputs one of the data, a multiplier that multiplies the output of the selector, a data distribution processor that outputs a variance value in accordance with an instruction from the controller, and an output of the multiplier It is preferable to have a configuration (1-2 configuration) having an addition unit that adds a dispersion value and outputs the added value to the subsequent stage.

In the data distribution circuit having the above-described configuration 1-2, the multiplication unit may have a configuration (configuration 1-3) that multiplies the output of the selector unit by 2 ^m (where m is a natural number).

  Further, in the data distribution circuit having the above-described configuration 1-3, the control unit detects that a continuous change of the continuous data is equal to or greater than a predetermined value and a minute change in the input data is detected. Configuration in which the data distribution processing unit is in an operating state when the input data matches the held continuous data and the data distribution processing unit is in a stopped state (configuration 1-4) It is good to.

  In the data distribution circuit having the above-described configuration 1-3 or 1-4, the data distribution processing unit determines the size of the distribution value and the number of distributions in accordance with the number of continuous data. (Structure 1-5) may be used.

  Further, in the data distribution circuit having the above configuration 1-5, the data distribution processing unit determines the distribution interval of the distribution values according to the number of consecutive continuous data (configuration 1-6) It is good to.

  In the data distribution circuit having any one of the first to third to first-6 configurations, a plurality of the data distribution processing units are provided, and when one data distribution processing unit is in an operating state, When a minute change in input data is detected, another data distribution processing unit may be configured to operate in parallel (first to seventh configurations).

  In the data distribution circuit having any one of the first to first to seventh configurations, the minute value may be ± 1LSB (first to eighth configuration).

  According to a first aspect of the present invention, there is provided a data processing circuit comprising: a data distribution circuit having any one of the first to first-8 configurations; and a digital filter circuit provided at a subsequent stage of the data distribution circuit. It is set as the structure (1-9th structure) to have.

  According to a first aspect of the present invention, there is provided a frequency measurement circuit comprising: an input data generation circuit for generating input data according to the frequency of an input signal; and a data distribution comprising any one of the above-described first to first-8 configurations. The configuration includes a circuit and a digital filter circuit provided in a subsequent stage of the data distribution circuit (first to tenth configurations).

  In the frequency measurement circuit having the above configuration 1-10, the input data generation circuit generates input data according to the difference frequency between the first input signal and the second input signal (first 1-11). Configuration).

  According to a first aspect of the present invention, there is provided an electronic apparatus including: a frequency measurement circuit having the above configuration 1-11; and a processing apparatus that performs processing according to a measurement result of the frequency measurement circuit (first 1 12 configurations).

  An electronic apparatus according to a first aspect of the present invention includes a sensor that generates a sensor signal, an AD converter that AD-converts the sensor signal to generate input data, and any one of the first to first-8. A data distribution circuit having a configuration; a digital filter circuit provided at a subsequent stage of the data distribution circuit; and a processing device that performs processing according to output data of the digital filter circuit (configuration 1-13) ).

  In the electronic apparatus having the above-described configuration 1-13, the sensor may be a microphone, and the processing device may be a recording device (configuration 1-14).

<Second invention>
Of the various inventions disclosed in this specification, the frequency measurement circuit according to the second invention includes a plurality of differential signal generators, and one of the first input signal and the second input signal is the plurality of A delay unit that delays the differential signal generation unit so that the differential signal generation unit is input at different phases, and according to a differential frequency between the first input signal and the second input signal from a plurality of differential signals. It is set as the structure (2-1 structure) which produces | generates an output signal.

In the frequency measurement circuit having the above-described configuration 2-1 described above, the differential signal generation unit may be configured to have 2 ^m (where m is a natural number) (configuration 2-2).

  In addition, the frequency measuring circuit having the above configuration 2-1 or 2-2 generates an output signal by adding an adder that takes the sum of the plurality of difference signals and filtering the output of the adder. It is good to make it the structure (2-3 structure) which has a filter part to perform.

  The frequency measurement circuit having the above configuration 2-1 or 2-2 is configured to select and output the plurality of differential signals cyclically, and to perform output processing by filtering the output of the selector unit. It is preferable to have a configuration (a second to fourth configuration) including a filter unit that generates a signal.

  Further, in the frequency measurement circuit having any one of the above configurations 2-1 to 2-4, each of the plurality of differential signal generation units receives the first input signal as a clock signal and outputs the second input. A configuration including a D flip-flop in which a signal is input as a data signal, and a counter unit that counts the number of output pulses of the D flip-flop and outputs a count value for each gate period determined by a gate signal (second 2-5) (Configuration).

  Further, in the frequency measurement circuit having any one of the above configurations 2-1 to 2-5, the delay unit includes at least one of a buffer, an inverter, and a D flip-flop. Configuration).

  According to a second aspect of the present invention, there is provided a frequency measuring circuit comprising: a plurality of counter units that count the number of pulses of an input signal for each gate period determined by a gate signal and output a count value; and the input signal includes the plurality of counter units. And a delay unit that gives a delay so that the signals are input in different phases, and generates an output signal corresponding to the frequency of the input signal from a plurality of count values (second to seventh configuration) It is said that.

In the frequency measurement circuit having the above-described configuration 2-7, the counter section may be configured to have 2 ^m (where m is a natural number) (configuration 2-8).

  The frequency measuring circuit having the above-described configuration 2-7 or 2-8 generates an output signal by adding an adder for summing up the plurality of count values and filtering the output of the adder And a filter section (second 9th configuration).

  Further, the frequency measuring circuit having the above-described configuration 2-7 or 2-8, a selector unit for cyclically selecting and outputting the plurality of count values, and filtering the output of the selector unit to output the output And a filter section for generating a signal (configuration 2-10).

  An electronic apparatus according to a second aspect of the present invention includes a frequency measurement circuit having any one of the above configurations 2-1 to 2-10, a processing device that performs processing according to a measurement result of the frequency measurement circuit, It is set as the structure (2-11th structure).

  With the data distribution circuit according to the first invention, it is possible to suppress noise in the digital filter circuit connected to the subsequent stage.

  Further, with the frequency measurement circuit according to the second invention, it is possible to measure the frequency of the input signal with high accuracy.

Block diagram showing one configuration example of digital filter circuit Timing chart showing a first operation example of the digital filter circuit 100 Timing chart showing a second operation example of the digital filter circuit 100 Timing chart for explaining the mechanism of noise generation at the time of minute change of input data Block diagram showing one configuration example of a data processing circuit The block diagram which shows one structural example of the data distribution part 210 Timing chart showing an example of data distribution processing The block diagram which shows the example of 1 structure of the data distribution process part 218-x Timing chart showing an example of distributed value output processing The figure which shows an example of a data distribution processing table Diagram showing an example of distributed interval control Block diagram showing application example to differential frequency measurement circuit Correlation diagram between frequency f2 and standard deviation σ The block diagram which shows the 1st structural example (remote control) of an electronic device. External view showing a first configuration example (remote control) of an electronic device Block diagram showing a second configuration example (sensing device) of an electronic device The block diagram which shows the 3rd structural example (audio equipment) of an electronic device. Block diagram showing a first configuration example of a differential frequency measurement circuit Correlation diagram of difference frequency (f1-f2) and standard deviation σ The figure which shows the 1st example of a metastable countermeasure The figure which shows the 2nd example of a metastable countermeasure Block diagram showing a second configuration example of the differential frequency measurement circuit Block diagram showing a third configuration example of the differential frequency measurement circuit Block diagram showing a fourth configuration example of the differential frequency measurement circuit Block diagram showing a fifth configuration example of the differential frequency measurement circuit Block diagram showing a sixth configuration example of the differential frequency measurement circuit Block diagram showing an example of application to a frequency measurement circuit

<Digital filter circuit>
FIG. 1 is a block diagram illustrating a configuration example of a digital filter circuit. The digital filter circuit 100 of this configuration example is an IIR [infinite impulse response] filter circuit (cut-off frequency: 1.1 × fs) that operates in synchronization with the clock signal CLK (frequency: fs). , An adder 102, a delay unit 103, and a multiplier 104.

The multiplication unit 101 generates (m + n) -bit multiplication data S1 by multiplying the m-bit input data IN by 2 ⁿ times (n-bit left shift).

  The adder 102 adds (m + n) -bit multiplication data S1 and (m + n) -bit feedback data S3 to generate (m + n + 1) -bit addition data S2.

  The delay unit 103 generates (m + n + 1) -bit output data OUT by delaying the (m + n + 1) -bit added data S2 by one cycle (= 1 / fs) of the clock signal CLK.

  The multiplier 104 generates (m + n) -bit feedback data S3 by multiplying the (m + n + 1) -bit output data OUT by 1/2 (1-bit right shift). However, the decimal part of the feedback data S3 is rounded down.

  FIG. 2 is a timing chart showing a first operation example (m = 5, n = 0) of the digital filter circuit 100. The clock signal CLK, input data IN, multiplication data S1, addition data S2, Output data OUT and feedback data S3 are depicted.

In the initial state, OUT = [0] and S3 = [0] (= OUT [0] / 2). Further, the n = 0, the gain multiplier 101 is 1 times (2 ⁰ times), a S1 = IN. Therefore, if IN = [7], S1 = [7] and S2 = [7] (= S1 [7] + S3 [0]).

  When a pulse rises in the clock signal CLK, the immediately preceding addition data S2 is delayed and output as output data OUT in synchronization with the rising edge. Therefore, OUT = [7], and S3 = [3] (= OUT [7] / 2). At this time, if IN = [8], S1 = [8] and S2 = [11] (= S1 [8] + S3 [3]).

  When the next pulse rises in the clock signal CLK, the immediately preceding addition data S2 is delayed and output as output data OUT in synchronization with the rising edge. Accordingly, OUT = [11], and S3 = [5] (= OUT [11] / 2). At this time, if IN = [6], S1 = [6] and S2 = [11] (= S1 [6] + S3 [5]).

  Thereafter, the same operation as described above is repeated each time a pulse rises in the clock signal CLK. As a result, for example, when the average value of the input data IN is [7], the average value of the output data OUT approaches [14] (= IN × 2).

  FIG. 3 is a timing chart showing a second operation example (m = 5, n = 4) of the digital filter circuit 100. The clock signal CLK, input data IN, multiplication data S1, addition data S2, Output data OUT and feedback data S3 are depicted.

As before, in the initial state, OUT = [0] and S3 = [0] (= OUT [0] / 2). Further, in the n = 4, the gain multiplier 101 is 16 times (2 ^4x), and S1 = IN × 16. Therefore, if IN = [7], S1 = [112] and S2 = [112] (= S1 [112] + S3 [0]).

  When a pulse rises in the clock signal CLK, the immediately preceding addition data S2 is delayed and output as output data OUT in synchronization with the rising edge. Accordingly, OUT = [112], and S3 = [56] (= OUT [112] / 2). At this time, if IN = [8], S1 = [128] and S2 = [184] (= S1 [128] + S3 [56]).

  When the next pulse rises in the clock signal CLK, the immediately preceding addition data S2 is delayed and output as output data OUT in synchronization with the rising edge. Accordingly, OUT = [184], and S3 = [92] (= OUT [184] / 2). At this time, if IN = [6], S1 = [96] and S2 = [188] (= S1 [96] + S3 [92]).

  Thereafter, the same operation as described above is repeated each time a pulse rises in the clock signal CLK. As a result, for example, when the average value of the input data IN is [7], the average value of the output data OUT approaches [224] (= IN × 16 × 2).

  As described above, when the number of bits of the output data OUT is increased with respect to the number of bits of the input data IN, the rounding error (truncation after the decimal point) generated in the multiplication unit 104 is reduced, so that the filter accuracy of the digital filter circuit 100 is improved. Can do. However, it has been found that increasing the number of bits of the output data OUT with respect to the number of bits of the input data IN increases the noise when the input data IN changes slightly.

  FIG. 4 is a timing chart for explaining the noise generation mechanism when the input data IN is slightly changed. The clock signal CLK, the input data IN, and the output data OUT are depicted in order from the top.

  In the example of this figure, the average value of the input data IN is slightly smaller than “8”, and after the input data IN is maintained at “8” over a plurality of cycles of the clock signal CLK, it is “7” for one cycle. The state of changing to is repeated. As described above, when the input data IN changes to a minute value from the same continuous data, the input data IN is changed by ± 1 LSB, and the output data OUT is about several tens LSB to 100 LSB (16-bit output). Change), which causes large noise (20LSBrms or more).

  In particular, when the cut-off frequency fc of the digital filter circuit 100 cannot be set low in order to increase the input / output response speed of the data processing circuit in which the digital filter circuit 100 is incorporated, fluctuations in the output data OUT may be caused by the digital filter. The circuit 100 is not smoothed and appears as noise.

<Data processing circuit>
FIG. 5 is a block diagram illustrating a configuration example of a data processing circuit that can solve the above-described problem. The data processing circuit 200 of this configuration example includes a data distribution unit 210 and a digital filter unit 220.

  The data distribution unit 210 operates in response to the input of the clock signal CLK. When the x-bit (for example, 5 bits) input data IN changes from the same continuous data by a minute value (± 1LSB), the amount of change is calculated. The distributed input data IN ′ of y bits (for example, 10 bits) is generated while being distributed to a plurality of times and sequentially added to continuous data, and this is output to the digital filter unit 220 at the subsequent stage.

  The digital filter unit 220 operates in response to the input of the clock signal CLK, and performs a predetermined filtering process on the distributed input data IN ′ to generate z-bit (for example, 16 bits) output data OUT. As the digital filter unit 220, for example, the digital filter circuit 100 of FIG. 1 can be used.

<Data distribution unit>
FIG. 6 is a block diagram illustrating a configuration example of the data distribution unit 210. The data distribution unit 210 of this configuration example includes a continuous data holding unit 211, a minute change detection unit 212, a continuous number detection unit 213, a control unit 214, a selector unit 215, an OR gate unit 216, and a multiplication unit 217. And a data distribution processing unit 218-x (x = 1, 2, 3 in the example of FIG. 6) and addition units 219a to 219c.

  The continuous data holding unit 211 is a processing block that monitors the 5-bit input data IN and holds continuous data (= input data IN of the same value that is continuously input) and matches the input delay register 211a. A determination unit 211b and a continuous data register 211c are included.

  The input delay register 211a newly holds the input data IN as a 5-bit register value in_dly for each pulse of the clock signal CLK, while holding the register value in_dly (corresponding to the input data IN of the previous cycle). Is output.

  The match determination unit 211b determines whether or not the input data IN and the register value in_dly match.

  The continuous data register 211c holds the input data IN as a 5-bit register value main_data (corresponding to continuous data) when the input data IN and the register value in_dly match.

  The minute change detection unit 212 monitors the input data IN and outputs a register value in_near indicating whether or not a minute change has occurred and a register value pnm indicating the positive / negative polarity of the minute change. Note that the register value in_near is “1: true value (with minute change)” when the input data IN matches (in_dly + 1) or (in_dly−1), and “0” when neither of them matches. : False value (no minute change) ”. The register value pnm is “1: true value (positive polarity)” when the input data IN matches (in_dly + 1), and “0: false value (negative polarity)” when the input data IN does not match. All you need is enough.

  The continuous number detection unit 213 monitors the determination result of the coincidence determination unit 211b and detects the continuous number of continuous data (how many times the input data IN and the register value in_dly have been determined to be consistent). The detection result is held as a 10-bit register value (cnt_same).

  The control unit 214 performs activation control of the data distribution processing unit 218-x based on the detection results of the minute change detection unit 212 and the continuous frequency detection unit 213. More specifically, the control unit 214 detects that a continuous change of the continuous data is greater than or equal to a predetermined value (for example, cnt_same ≧ 16), a minute change in the input data IN is detected (in_near = 1), and the register value in_dly. When the register value main_data (corresponding to the continuous data) matches (corresponding to the input data IN in the previous cycle) and the data distribution processing unit 218-x is in the stopped state (ax = 0), the stopped state The load signal LDx is generated so that the data distribution processing unit 218-x is appropriately operated.

  When the data distribution processing unit 218-x is all in a stopped state (a1 = a2 = a3 = 0) when a minute change of the input data IN occurs, the control unit 214 sets a pulse on the load signal LD1. The data distribution processing unit 218-1 is put into an operating state.

  On the other hand, when a slight change occurs in the input data IN, the data distribution processing unit 218-1 is already in an operating state (a1 = 1), and both the data distribution processing units 218-1 and 218-3 are in a stopped state ( When a2 = a3 = 0), the control unit 214 raises a pulse to the load signal LD2 to set the data distribution processing unit 218-2 in an operating state.

  Further, when the minute change of the input data IN occurs, the data distribution processing units 218-1 and 218-2 are already in the operating state (a1 = a2 = 1), and only the data distribution processing unit 218-3 is stopped. In the state (a3 = 0), the control unit 214 raises a pulse to the load signal LD3 to place the data distribution processing unit 218-3 in an operating state.

  In this way, the control unit 214 individually monitors whether the data distribution processing unit 218-x is in the operating state or the stopped state, and the input data when one data distribution processing unit is in the operating state. When a small change in IN is detected, another data distribution processing unit that has been in a stopped state is set in an operating state in parallel.

  When the data distribution processing unit 218-x is all in the operating state (a1 = a2 = a3 = 1) when the minute change of the input data IN occurs, the control unit 214 determines which of the load signals LD1 to LD3. Also don't launch a pulse. As a result, a pulse does not rise in the selection signal MUX, and the selector 215 is maintained in a state in which the input data IN is output through.

  The selector unit 215 selects and outputs the input data IN when the selection signal MUX is at a low level, and selectively outputs the register value main_data (corresponding to continuous data) when the selection signal MUX is at a high level. That is, every time the data distribution processing unit 218-x is activated in accordance with the load signal LDx, the selector unit 215 switches from a state in which the input data IN is output through to a state in which the register value main_data is output.

  The OR gate unit 216 generates a selection signal MUX by performing an OR operation on the load signals LD1 to LD3. Accordingly, the selection signal MUX is at a high level when at least one of the load signals LD1 to LD3 is at a high level, and is at a low level when all of the load signals LD1 to LD3 are at a low level.

Multiplication unit 217 (in this configuration example, 16 times (= 2 ^4-fold)) gain multiple 5-bit output of the selector unit 215 performs nine bits output by. However, the gain of the multiplication unit 217 is not limited to the above, and an arbitrary gain (5 times, 7.5 times, etc.) can be set. For example, when the gain of the multiplication unit 217 is set to 16 times, a minute change (± 16 LSB) occurring in the 16-times input data IN × 16 may be distributed and output in ± 1 LSB × 16 times. When the gain of 217 is set to 5 times, a minute change (± 5 LSB) that occurs in the input data IN × 5 that is 5 times may be dispersed and output in ± 1 LSB × 5 times. Note that when the gain of the multiplication unit 217 is set to a fractional multiple (for example, 7.5 times), the circuit becomes slightly complicated, but each time a slight change of the input signal IN occurs, the number of dispersion is changed. can do. More specifically, a minute change (± 7.5LSB) generated in 7.5 times the input data IN × 7.5 is output after being dispersed in ± 1LSB × 7 times, and then again the same minute change (± 7). .5LSB) occurs, it may be dispersed and output in ± 1LSB × 8 times.

  The data distribution processing unit 218-x outputs a 5-bit distribution value dx according to the load signal LDx input from the control unit 214. At this time, the data distribution processing unit 218-x determines the size of the distributed value dx, the number of distributions, and the distribution interval in accordance with the number of consecutive continuous data (cnt_same). The configuration and operation of the data distribution processing unit 218-x will be described in detail later.

  The adders 219a to 219c add the variance value dx to the 9-bit output of the multiplier 217 to generate 10-bit distributed input data IN ', and output this to the subsequent stage.

  FIG. 7 is a timing chart showing an example of data distribution processing. From the top, a clock signal CLK, input data IN, 16 times input data IN × 16, distributed input data IN ′, and output data OUT are depicted. ing. In the example of this figure, like the previous FIG. 4, the average value of the input data IN is slightly smaller than “8”, and the input data IN is maintained at “8” over a plurality of cycles of the clock signal CLK. Thereafter, the state of changing to “7” for one period is repeated.

  Here, when the input data IN changes by a minute value from the same continuous data, the data distribution unit 210 distributes the change amount to a plurality of times and outputs it to the subsequent stage while sequentially adding it to the continuous data. For example, when the input data IN changes by −1 LSB from “8” to “7”, the 16 times input data IN × 16 changes by −16 LSB from “128” to “112”. At this time, the data distribution unit 210 does not output “112” once as the distributed input data IN ′, but outputs “124” four times while leaving a predetermined distribution interval.

  That is, when the data distribution unit 210 detects that a small change of −1LSB has occurred in the input data IN, the data distribution unit 210 divides the amount of change (−16LSB) generated in the input data IN × 16 by 16 times into four times. A value dx (= −4LSB) is generated, and this is sequentially added to 16 times continuous data “128”, and output to the subsequent stage as distributed input data IN ′.

  By performing such data distribution processing, the output data OUT of the digital filter unit 220 provided in the subsequent stage is stabilized. Therefore, the noise amount of the output data OUT can be reduced without unnecessarily lowering the cut-off frequency fc of the digital filter unit 220, so that the input / output response speed of the data processing circuit 200 can be increased.

  FIG. 8 is a block diagram illustrating a configuration example of the data distribution processing unit 218-x. The data distribution processing unit 218-x of this configuration example includes registers 218a to 218e.

  The register 218a stores a 3-bit register value “shift”. The register value shft is a register value that determines the size of the variance value dx. The variance value dx is generated by right-shifting the amount of change (−16 LSB) occurring in the 16-times input data IN × 16 by a shift amount corresponding to the register value shift. For example, when the register value shift is “2”, the variance value dx is a value obtained by shifting -16LSB to the right by 2 bits, that is, -4LSB (= -16LSB / 4).

  The register 218b stores a 7-bit register value DCNT_MAX. The register value DCNT_MAX is a register value that determines an initial value of the register value dcnt_a (corresponding to the dispersion interval of the dispersion value dx). The greater the register value DCNT_MAX, the longer the dispersion interval of the dispersion value dx.

  The register 218c stores a 7-bit register value dcnt_a. The register value dcnt_a is a count value of a down counter that is decremented by one for each pulse of the clock signal CLK. The register value dcnt_a is reset to an initial value determined by the register value DCNT_MAX every time the register value dcnt_b is decremented.

  The register 218d stores a 5-bit register value dcnt_b. The register value dcnt_b is a count value of a down counter that is decremented by 1 at a timing when the register value dcnt_a becomes 0. Note that the initial value of the register value dcnt_b corresponds to the number of distributions of the distribution value dx.

  The register 218e stores a 1-bit register value pnm. The register value pnm is a register value indicating the positive / negative polarity of the minute change generated in the input data IN, and is input from the minute change detection unit 212.

  FIG. 9 is a timing chart showing an example of the distributed value output processing. In order from the top, the clock signal CLK, the load input load (corresponding to the load signal LDx), the register value shift, the register value DCNT_MAX, the register value dcnt_b, the register A value dcnt_a, a register value pnm, an active output active (corresponding to the active signal ax), and a distributed output diff_out (corresponding to the distributed value dx) are depicted.

  When a pulse rises in the load input load, the register value shift, the register value DCNT_MAX, and the register value dcnt_b are set according to the number of times of continuous data (cut_same), and the sign of the minute change that occurs in the input data IN The register value pnm is set according to the polarity.

  In the example of FIG. 9, since the register value shift is 2 and the register value pnm is 0 (negative polarity), the dispersion value dx is a value obtained by shifting -16LSB to the right by 2 bits, that is, -4LSB (= −16LSB / 4).

  Thereafter, the register value dcnt_a is decremented by one for each pulse of the clock signal CLK. Every time the register value dcnt_a becomes 1, -4LSB is output as the variance value dx. At the remaining timing, 0 is output as the variance value dx.

  At the timing when the register value dcnt_a becomes 0, the register value dcnt_b is decremented by 1, and the register value dcnt_a is reset to the initial value (= DCNT_MAX). Note that the reset operation of the register value dcnt_a (and the output process of the distributed value dx) is repeated until the register value dcnt_b becomes zero.

  In the example of FIG. 9, since the register value DCNT_MAX is 6 and the initial value of the register value dcnt_b is 4, the output process of the distributed value dx is performed once every 6 pulses of the clock signal CLK, for a total of 4 times. Will be implemented.

  Thus, the magnitude of the variance value dx (−4 LSB) and the number of outputs (4 times) are equal to the amount of change (−16 LSB) to be dispersed and the total amount of variance values dx (−4 LSB × 4 times). Is set to be

  The active output active is set to the high level (ax = 1) from when the pulse rises to the load input load until the register value dcnt_b becomes 0. Thereby, the control unit 214 can determine whether the data distribution processing unit 218-x is in an operating state or a stopped state.

  FIG. 10 is a diagram illustrating an example of the data distribution processing table. This data distribution processing table shows the correlation between the continuous count cnt_same, the register value dcnt_b, the register value shift, and the distributed output diff_out, and is implemented in the data distribution processing unit 218-x.

  For example, when cnt_name = 16 CLK, dcnt_b = 2 and shift = 1 are set, and diff_out = ± 8LSB. In other words, the change amount of ± 16 LSB is dispersed and output in ± 8 LSB × 2 times.

  When cnt_name = 32CLK, dcnt_b = 4 and shift = 2 are set, and diff_out = ± 4LSB. In other words, the change amount of ± 16 LSB is dispersed and output in ± 4 LSB × 4 times.

  When cnt_same = 64 CLK, dcnt_b = 8 and shift = 3 are set, and diff_out = ± 2LSB. In other words, the change amount of ± 16 LSB is dispersed and output in ± 2 LSB × 8 times.

  When cnt_same = 128 CLK, dcnt_b = 16 and shift = 4 are set, and diff_out = ± 1LSB. In other words, the change amount of ± 16 LSB is dispersed and output in ± 1 LSB × 16 times.

  As described above, the data distribution processing unit 218-x decreases the distribution value dx and increases the number of distributions as the number of consecutive continuous data (cnt_same) increases. With such a configuration, it is possible to appropriately suppress fluctuations in the output data OUT.

  FIG. 11 is a diagram illustrating an example of distributed interval control. The data distribution processing unit 218-x sets the distribution interval (register value DCNT_MAX) of the distributed value dx longer in proportion to the continuous number of continuous data (cnt_same) without changing the number of distributions of the distributed value dx. It also has.

  For example, when cnt_same = 16CLK and cnt_same = 24CLK are compared, the number of times of dispersion does not change by two, but the time interval of dispersion is extended from Ta to Tb. With such a configuration, the variance dx can be evenly distributed during the continuous data input period, so that fluctuations in the output data OUT can be appropriately suppressed. In addition, when cnt_name = 16CLK and cnt_name = 32CLK are compared, the number of dispersion increases from 2 to 4, so that the dispersion interval is Ta.

  If minute changes in the input data IN appear at regular intervals, it may be sufficient to provide one data distribution processing unit 218-x. On the other hand, in the case where minute changes in the input data IN appear irregularly, in view of the fact that the next minute change may occur while one data distribution processing unit 218-x is performing data distribution processing, the data distribution It is desirable to provide a plurality of processing units 218-x.

<Application example to differential frequency measurement circuit>
FIG. 12 is a block diagram showing an application example to the differential frequency measurement circuit. The differential frequency measurement circuit 300 of this application example includes counter units 310 and 320, a subtraction unit 330, a data distribution unit 340, and a low-pass filter unit 350.

  The counter unit 310 counts the number of pulses of the input signal IN1 (frequency: f1) and outputs a count value D1 for each gate period Tg (= 1 / fg) determined by the gate signal Sg (frequency: fg).

  The counter unit 320 counts the number of pulses of the input signal IN2 (frequency: f2) for each gate period Tg and outputs a count value D2.

  The subtractor 330 generates a difference count value by subtracting the count value D2 from the count value D1, and outputs this as input data IN.

  The counter units 310 and 320 and the subtracting unit 330 function as an input data generation circuit that generates input data IN corresponding to the difference frequency between the input signals IN1 and IN2. When a single input signal is a frequency measurement target, only one counter unit needs to be provided as an input data generation circuit.

  When the input data IN changes by a minute value (± 1 LSB) from the same continuous data, the data distribution unit 340 generates the distributed input data IN ′ by distributing the change amount to a plurality of times and sequentially adding the continuous data to the continuous data. Then, this is output to the low-pass filter section 340 at the subsequent stage. Note that the configuration and operation of the data distribution unit 340 are the same as those of the data distribution unit 210 described above, and a duplicate description is omitted.

  The low-pass filter unit 350 is a digital filter circuit that performs low-pass filter processing (cut-off frequency: fc) on a series of distributed input data IN ′ obtained every gate period Tg to generate output data OUT. As the low-pass filter unit 350, for example, the digital filter circuit 100 of FIG. 1 can be used.

  In the frequency measuring circuit 300 configured as described above, the counter units 310 and 320 are counter units (so-called short gate time counter units) that count the number of pulses of the input signals IN1 and IN2 in a relatively short gate period Tg (1 s or less). ) Is used. A series of count values D1 and D2 output for each gate period Tg from the counter units 310 and 320 adopting such a method behave as a kind of pulse train, and each of the count values D1 and D2 corresponds to the frequency change of the input signals IN1 and IN2. The frequency (roughness) changes.

  Information regarding the difference frequency between the input signals IN1 and IN2 exists in the low frequency component of the frequency spectrum of the input data IN (and thus the distributed input data IN ') that behaves as a pulse train. Therefore, the low-pass filter unit 350 is used to extract low-frequency components from the dispersion input data IN ′ (remove harmonic components due to quantization errors), thereby obtaining information on the difference frequency between the input signals IN1 and IN2. It can be extracted (demodulated) and output as output data OUT.

  FIG. 13 is a correlation diagram between the frequency f2 of the input signal IN2 and the standard deviation σ of the output data OUT (16 bits: −32768 to +32767). The solid line in the figure shows the behavior of the input data IN with the data distribution process, and the broken line in the figure shows the behavior of the input data IN without the data distribution process. Note that the degree of fluctuation (noise amount) of the output data OUT can be evaluated using the standard deviation σ as an index.

  In FIG. 13, the frequency f1 of the input signal IN1 is fixed at 160 kHz, and the output signal OUT is measured 10 times every about 300 ms at each frequency while sweeping the frequency f2 of the input signal IN2 near 160 kHz. The result of calculating the standard deviation σ based on the measurement results of 10 times is depicted.

  As a result, the noise of the output data OUT increased at a specific frequency without the data distribution processing of the input data IN (broken line). More specifically, when the frequency f2 is set to 160 kHz, the standard deviation σ is 5 LSBrms or less, whereas when the frequency f2 is set to 160.02 kHz, the standard deviation σ increases to 25 LSBrms. It was.

  As described above, when the average value of the input data IN is slightly smaller than an integer (for example, “8”), the noise increase occurring at a specific frequency causes the input data IN to become a clock signal as shown in FIG. This is due to the fact that after being maintained at “8” over a plurality of cycles of CLK, the state of minute change to “7” for one cycle is repeated.

  On the other hand, it was confirmed that the standard deviation σ decreased to almost 8LSBrms even when the frequency f2 was set to 160.02 kHz when the input data IN was distributed (solid line). Therefore, the frequency measurement circuit 300 of this application example can accurately measure the difference frequency between the input signals IN1 and IN2.

<Application examples to electronic devices>
14 and 15 are a block diagram and an external view showing a first configuration example (remote control) of an electronic device on which the frequency measurement circuit is mounted, respectively. The remote controller 400 of this configuration example includes MEMS [micro electro mechanical systems] motion sensors 410 and 420, a differential frequency measurement IC 430, and a microcomputer 440 therein.

  The MEMS motion sensors 410 and 420 respectively generate input signals IN1 and IN2 having different output characteristics (sensitivity) and changing frequencies according to the movement (pressing state) of a button provided on the remote controller 400. For example, when a button is pressed, the MEMS motion sensor 410 changes the frequency of the input signal IN1 relatively slowly with respect to the button movement, while the MEMS motion sensor 420 changes with respect to the button movement. The frequency of the input signal IN2 is changed relatively steeply. As a result, the difference frequency between the input signals IN1 and IN2 changes according to the movement of the button.

  The differential frequency measurement IC 430 is a monolithic semiconductor device that is formed by integrating the previous frequency measurement circuit 300 and generates output data OUT corresponding to the differential frequency of the input signals IN1 and IN2. Note that the frequency measurement circuit 300 may not be realized as a semiconductor device, but may be assembled using commercially available discrete components.

  The microcomputer 440 performs an arithmetic process according to the output data OUT, and not only digitally detects whether or not the button is pressed, but also detects how much the button is pressed in an analog manner. .

  In the case of the remote controller 400 of this configuration example, for example, the first process is performed when the button is pressed down strongly, while the second process is performed when the button is pressed down weakly. Therefore, it is possible to achieve both multi-functionality and miniaturization of the remote control 400.

  FIG. 16 is a block diagram illustrating a second configuration example (sensing device) of the electronic device. The electronic device 500 of the second configuration example includes a sensor 510, an AD converter 520, a data distribution circuit 530, a digital filter circuit 540, and a microcomputer 550.

  The sensor 510 generates an analog sensor signal Da. As the sensor 510, any sensor such as an optical sensor, a temperature sensor, or a motion sensor may be used.

  The AD converter 520 performs AD conversion on the analog sensor signal Da to generate digital input data IN.

  When the input data IN changes by a minute value from the same continuous data, the data distribution circuit 530 generates the distributed input data IN ′ while distributing the change amount to a plurality of times and sequentially adding to the continuous data. The data is output to the subsequent digital filter circuit 540. Note that the configuration and operation of the data distribution circuit 530 are the same as those of the data distribution unit 210 described above, and thus redundant description is omitted.

  The digital filter circuit 540 performs predetermined filter processing on the distributed input data IN ′ to generate output data OUT. As the digital filter circuit 540, for example, the digital filter circuit 100 in FIG. 1 can be used.

  The microcomputer 550 is a processing device that performs processing according to the output data OUT. The processing device is not limited to the microcomputer 550, and a DSP [digital signal processor], an FPGA [field-programmable gate array], or a personal computer can also be used.

  As described above, the data distribution circuit 530 can be applied not only to the remote controller but also to various sensing devices.

  FIG. 17 is a block diagram illustrating a third configuration example (audio device) of the electronic device. The electronic apparatus 500 of this configuration example has substantially the same configuration as that of the second configuration example, and includes a microphone 560 instead of the sensor 510 and a recording device 570 instead of the microcomputer 550. Thus, the data distribution circuit 530 can be applied to audio equipment.

<Differential frequency measurement circuit>
FIG. 18 is a block diagram illustrating a first configuration example of the differential frequency measurement circuit. The differential frequency measurement circuit 600 of this configuration example is a circuit that generates an output signal OUT corresponding to the differential frequency (f1-f2) between the input signal IN1 (frequency: f1) and the input signal IN2 (frequency: f2 <f1). Yes, a differential signal generator 610-X (where X = 1, 2,..., X), an adder 620, a low-pass filter 630, and a delay unit 640-Y (where Y = 1, 2,..., Y) (= X-1)).

The difference signal generation unit 610-X is a circuit block that generates n-bit difference data BX corresponding to the difference frequency (f1-f2) between the input signals IN1 and IN2, and includes a D flip-flop 611-X and a counter unit 612. -X. Note that it is desirable to provide 2 ^m differential signal generation units 610-X (where m is a natural number). With such a configuration, the total data C generated by the adder 620 becomes (n + m) bits, so that the design of the differential frequency measurement circuit 600 is facilitated.

  The D flip-flop 611-X is a sequential circuit in which the input signal IN1 is input as a clock signal and the input signal IN2 is input as a data signal.

  The counter unit 612-X counts the number of pulses of the output signal AX generated by the D flip-flop 611-X every gate period (= 1 / fg) determined by the gate signal Sg (frequency: fg), and the count The value is output as n-bit difference data BX.

  The adder 620 generates the sum data C of (n + m) bits by taking the sum of the difference data BX.

  The low-pass filter unit 630 is a digital filter circuit that performs low-pass filter processing on the sum data C and generates an output signal OUT.

  The delay unit 640-Y provides a delay so that the input signal IN1 is input to the plurality of differential signal generation units 610-X with different phases. In the example of FIG. 18, the input signal IN1 is input to the differential signal generation unit 610-1 without delay. Further, the differential signal generation unit 610-2 receives a delayed input signal IN1d1 obtained by delaying the input signal IN1 by the delay unit 640-1 once. Further, the differential signal generation unit 610-x receives a delay signal IN1dy obtained by delaying the input signal IN1 Y times by the delay units 640-1 to y.

  As the delay unit 640-Y, a buffer (or a delay buffer) can be used. The buffer is formed by connecting an even number of inverters in series. A buffer having a large delay amount is called a delay buffer. The delay buffer is formed by increasing the number of inverters or inserting a resistor and a capacitor between the two inverters to provide a delay.

When 2 ^m differential signal generation units 610-X are provided, the delay amount for each delay unit 640-Y is set to T1 / 2 ^m with respect to the cycle T1 (= 1 / f1) of the input signal IN1. It is desirable to set.

In this way, by inputting the input signal IN1 with different phases to the plurality of differential signal generation units 610-X, the noise of the output signal OUT is reduced without unnecessarily reducing the cutoff frequency of the low-pass filter unit 630. It becomes possible to suppress. For example, when 2 ^m differential signal generation units 610-X are provided, the number of bits of the output signal OUT increases by m bits, so that the noise of the output signal OUT becomes 1/2 ^m .

  FIG. 19 is a correlation diagram between the difference frequency (f1−f2) between the input signals IN1 and IN2 and the standard deviation σ of the output signal OUT. The solid line in the figure shows the behavior when the input signal IN1 is input to the plurality of differential signal generation units 610-X with different phases, and the broken line in the figure shows only one differential signal generation unit 610. The behavior when provided (conventional behavior) is shown.

  As is clear from the comparison between the solid line and the broken line in the figure, the standard deviation σ of the output signal OUT is significantly reduced by inputting the input signal IN1 with different phases to the plurality of differential signal generation units 610-X. It was confirmed. Therefore, the frequency measurement circuit 600 of this configuration example can accurately measure the difference frequency between the input signals IN1 and IN2.

  18 illustrates a configuration in which the differential signal generation unit 610-X includes a single D flip-flop 611-X. However, since the input signals IN1 and IN2 are input asynchronously to each other, Table measures are required.

  FIG. 20 is a diagram illustrating a first example of measures against metastable. The D flip-flop 611-X of this configuration example includes D flip-flops 611a and 611b. An input signal IN1 (or delayed input signal IN1dY) is input as a clock signal to the D flip-flop 611a, and an input signal IN2 is input as a data signal. On the other hand, the input signal IN1 (or the delayed input signal IN1dY) is input to the D flip-flop 611b as a clock signal, and the output signal of the D flip-flop 611a is input as a data signal.

  FIG. 21 is a diagram illustrating a second example of a countermeasure against metastable. The D flip-flop 611-X of this configuration example includes D flip-flops 611a and 611b, and an inverter 611c. An input signal IN1 (or delayed input signal IN1dY) is input as a clock signal to the D flip-flop 611a, and an input signal IN2 is input as a data signal. On the other hand, a logically inverted signal of the input signal IN1 (or delayed input signal IN1dY) is input to the D flip-flop 611b as a clock signal, and an output signal of the D flip-flop 611a is input as a data signal.

  FIG. 22 is a block diagram illustrating a second configuration example of the differential frequency measurement circuit. The differential frequency measurement circuit 600 of this configuration example has a configuration in which two differential signal generation units 610-X (X = 1, 2) are provided. In this configuration example, it is desirable to set the delay amount of the delay unit 640 to T1 / 2 with respect to the cycle T1 of the input signal IN1, and thus a simple inverter can be used as the delay unit 640.

FIG. 23 is a block diagram illustrating a third configuration example of the differential frequency measurement circuit. The differential frequency measurement circuit 600 of this configuration example has a configuration in which four differential signal generation units 610-X (where X = 1, 2, 3, 4) are provided. In this configuration example, for example, when f1 = 100 kHz (T1 = 10 μs), the delay amount for each delay unit 640-Y (Y = 1, 2, 3) is 2.5 μs (= 10 μs / 2 ² ). It becomes. Therefore, if the delay unit 640-Y is formed only by a general inverter (delay amount: 1 ns or less), a large number of elements are required, and the circuit scale of the delay unit 640-Y is increased.

  Therefore, the differential frequency measurement circuit 600 of the third configuration example has a configuration in which the delay unit 640-Y is formed using a D flip-flop that delays the input signal IN1 in synchronization with the clock signal CLK having the frequency fs (for example, 10 MHz). It is said that. With this configuration, the circuit scale of the delay unit 640-Y can be prevented from being unnecessarily increased.

  FIG. 24 is a block diagram illustrating a fourth configuration example of the differential frequency measurement circuit. The differential frequency measurement circuit 600 of this configuration example has the same configuration as that of the third configuration example (FIG. 23). The delay unit 640-1 is formed of a D flip-flop, while the delay units 640-2 and 640-3 are configured. Both have the feature that they are formed by inverters. In the delay unit 640-2, the delay input signal IN1d2 is generated by applying an inverter delay to the input signal IN1. Further, in the delay unit 640-3, the delay input signal IN1d3 is generated by applying an inverter delay to the delay input signal IN1d1 generated by the delay unit 640-1. With this configuration, the circuit scale of the delay unit 640-Y can be further reduced.

  FIG. 25 is a block diagram illustrating a fifth configuration example of the differential frequency measurement circuit. The differential frequency measurement circuit 600 of this configuration has the same configuration as that of the first configuration example (FIG. 18), and is configured to delay the input signal IN2 instead of the input signal IN1. In this way, by adopting a configuration in which the input signal IN2 is input to the plurality of differential signal generation units 610-X with different phases, the noise of the output signal OUT is reduced and the input signal OUT is reduced as in the first configuration example. It becomes possible to accurately measure the difference frequency between IN1 and IN2.

  FIG. 26 is a block diagram illustrating a sixth configuration example of the differential frequency measurement circuit. The differential frequency measurement circuit 600 of this configuration example has the same configuration as that of the third configuration example (FIG. 23), and has a configuration in which a selector unit 650 is provided instead of the addition unit 620 and a frequency division unit 660 is added separately. ing.

  The selector unit 650 cyclically selects and outputs the four systems of difference signals B1 to B4 according to the 2-bit selection signal MUX2. For example, the selector unit 650 selects and outputs the difference signal B1 when the selection signal MUX2 is “11”, selects and outputs the difference signal B2 when the selection signal MUX2 is “10”, and the selection signal MUX2 is “ The differential signal B3 is selected and output when it is "01", and the differential signal B4 is selectively output when the selection signal MUX2 is "00".

  The frequency dividing unit 660 generates a 10 kHz upper bit signal BITa and a 20 kHz lower bit signal BITb from the 10 MHz clock signal CLK, and outputs them to the selector unit 650 as a 2-bit selection signal MUX2, while the upper bit signal BITa. Is output as a gate signal Sg to the differential signal generation unit 610-X.

  With this configuration, the number of samples of the selection output signal C output from the low-pass filter unit 630 can be increased, so that the differential frequency between the input signals IN1 and IN2 can be measured with high accuracy.

  Further, noise can be further reduced by inserting the above-described data distribution unit 210 (FIG. 6) between the addition unit 620 or the selector unit 650 and the low-pass filter unit 630.

  Note that the differential frequency measurement circuit 600 described above can be incorporated into various electronic devices in the same manner as the differential frequency measurement circuit 300 described above.

<Application example to frequency measurement circuit>
FIG. 27 is a block diagram showing an application example to the frequency measurement circuit. The frequency measurement circuit 700 of this configuration example has a configuration in which the differential frequency measurement circuit 600 of the first configuration example (FIG. 18) is changed to a single input format, and instead of the difference signal generation unit 610-X, a counter unit 710-X. The basic configuration is the same as that of the first configuration example except that (where X = 1, 2,..., X) is provided.

  The counter unit 710-X counts the number of pulses of the input signal IN (or delayed input signal INdY) for each gate period determined by the gate signal Sg, and outputs a count value BX.

  In this way, by inputting the input signal IN to the counter units 710-X with different phases, the frequency of the input signal IN can be measured with high accuracy.

<Other variations>
The various technical features disclosed in the present specification can be variously modified within the scope of the technical creation in addition to the above-described embodiment. That is, the above-described embodiment is to be considered in all respects as illustrative and not restrictive, and the technical scope of the present invention is indicated not by the description of the above-described embodiment but by the scope of the claims. It should be understood that all modifications that fall within the meaning and range equivalent to the terms of the claims are included.

  Among various inventions disclosed in this specification, a data distribution circuit according to a first invention includes, for example, a signal processing unit of a sensor, an audio device, and an image processing device (digital still camera, digital video camera). , DVD playback device) and the like.

  Of the various inventions disclosed in this specification, the frequency measurement circuit according to the second invention is used for, for example, a switch determination circuit of a remote control, a PLL circuit, and a high frequency circuit (wireless communication circuit). Is possible.

DESCRIPTION OF SYMBOLS 100 Digital filter circuit 101 Multiplication part 102 Addition part 103 Delay part 104 Multiplication part 200 Data processing circuit 210 Data distribution part 211 Continuous data holding part 211a Input delay register 211b Match determination part 211c Continuous data register 212 Minute change detection part 213 Continuous frequency detection Unit 214 control unit 215 selector unit 216 OR gate unit 217 multiplication unit 218 data distribution processing unit 218a to 218e register 219a to 219c addition unit 220 digital filter unit 300 differential frequency measurement circuit 310, 320 counter unit (short gate time counter unit)
330 Subtraction unit 340 Data distribution unit 350 Low-pass filter unit 400 Electronic device (remote control)
410, 420 MEMS motion sensor 430 Differential frequency measurement IC
440 Microcomputer 500 Electronic equipment (sensing equipment, audio equipment, etc.)
510 sensors (light, temperature, motion, etc.)
520 AD converter 530 Data distribution circuit 540 Digital filter circuit 550 Microcomputer 560 Microphone 570 Recording device 600 Differential frequency measurement circuit 610 Differential signal generation unit 611 D flip-flop 611a, 611b D flip-flop 611c Inverter 612 Counter unit 620 Addition unit 630 Low-pass filter unit 640 delay unit (D flip-flop, inverter, etc.)
650 Selector unit 660 Divider unit 700 Frequency measurement circuit 710 Counter unit 720 Adder unit 730 Low-pass filter unit 740 Delay unit

Claims (25)

  A data distribution circuit characterized in that when digital input data changes by a minute value from the same continuous data, the amount of change is distributed to a plurality of times and sequentially added to the continuous data and output to the subsequent stage. A continuous data holding unit for holding the continuous data;
A minute change detection unit for detecting minute changes in the input data;
A continuous number detection unit for detecting the continuous number of the continuous data;
A control unit for controlling data distribution processing based on each detection result of the minute change detection unit and the continuous number of times detection unit;
A selector unit that selectively outputs one of the input data and the continuous data in accordance with an instruction from the control unit;
A multiplier for multiplying the output of the selector by a gain;
A data distribution processing unit that outputs a distributed value in accordance with an instruction from the control unit;
An adder that adds the variance to the output of the multiplier and outputs it to the subsequent stage;
The data distribution circuit according to claim 1, comprising: 3. The data distribution circuit according to claim 2, wherein the multiplication unit multiplies the output of the selector unit by 2 ^m (where m is a natural number).   The control unit has a continuous count of the continuous data equal to or greater than a predetermined value, a minute change in the input data is detected, the input data in the previous period and the held continuous data match, and 4. The data distribution circuit according to claim 3, wherein when the data distribution processing unit is in a stopped state, the data distribution processing unit is set in an operating state.   5. The data distribution circuit according to claim 3, wherein the data distribution processing unit determines the size of the distribution value and the number of distributions according to the number of continuous times of the continuous data.   The data distribution circuit according to claim 5, wherein the data distribution processing unit determines a distribution interval of the distribution values according to the number of continuous times of the continuous data.   A plurality of data distribution processing units are provided, and when a small change in the input data is detected when one data distribution processing unit is in an operating state, another data distribution processing unit is connected in parallel. The data distribution circuit according to claim 3, wherein the data distribution circuit is in an operating state.   The data distribution circuit according to claim 1, wherein the minute value is ± 1 LSB. A data distribution circuit according to any one of claims 1 to 8,
A digital filter circuit provided at a subsequent stage of the data distribution circuit;
A data processing circuit comprising: An input data generation circuit for generating input data according to the frequency of the input signal;
A data distribution circuit according to any one of claims 1 to 8,
A digital filter circuit provided at a subsequent stage of the data distribution circuit;
A frequency measurement circuit comprising:   The frequency measurement circuit according to claim 10, wherein the input data generation circuit generates input data corresponding to a difference frequency between the first input signal and the second input signal. A frequency measurement circuit according to claim 11;
A processing device for performing processing according to the measurement result of the frequency measurement circuit;
An electronic device comprising: A sensor that generates a sensor signal;
An AD converter that AD converts the sensor signal to generate input data;
A data distribution circuit according to any one of claims 1 to 8,
A digital filter circuit provided at a subsequent stage of the data distribution circuit;
A processing device for performing processing according to output data of the digital filter circuit;
An electronic device comprising:   The electronic apparatus according to claim 13, wherein the sensor is a microphone, and the processing device is a recording device. A plurality of differential signal generators;
A delay unit that gives a delay so that one of the first input signal and the second input signal is input to each of the plurality of differential signal generation units with a different phase;
Have
An output signal corresponding to a difference frequency between the first input signal and the second input signal is generated from a plurality of difference signals. The frequency measurement circuit according to claim 15, wherein 2 ^m differential signal generation units (where m is a natural number) are provided. An adder for summing the plurality of difference signals;
A filter unit that performs filtering on the output of the adder unit to generate the output signal;
The frequency measurement circuit according to claim 15 or 16, characterized by comprising: A selector unit that cyclically selects and outputs the plurality of difference signals;
A filter unit that filters the output of the selector unit to generate the output signal;
The frequency measurement circuit according to claim 15 or 16, characterized by comprising: Each of the plurality of differential signal generators is
A D flip-flop in which the first input signal is input as a clock signal and the second input signal is input as a data signal;
A counter unit that counts the number of output pulses of the D flip-flop for each gate period determined by a gate signal and outputs a count value;
The frequency measurement circuit according to claim 15, further comprising:   The frequency measurement circuit according to claim 15, wherein the delay unit includes at least one of a buffer, an inverter, and a D flip-flop. A plurality of counter units for counting the number of pulses of the input signal for each gate period determined by the gate signal and outputting a count value;
A delay unit that gives a delay so that the input signal is input to each of the plurality of counter units at different phases;
Have
An output signal corresponding to the frequency of the input signal is generated from a plurality of count values. The frequency measurement circuit according to claim 21, wherein the counter unit is provided with 2 ^m pieces (where m is a natural number). An adder for summing the plurality of count values;
A filter unit that performs filtering on the output of the adder unit to generate the output signal;
The frequency measurement circuit according to claim 21, wherein the frequency measurement circuit has. A selector unit that cyclically selects and outputs the plurality of count values;
A filter unit that filters the output of the selector unit to generate the output signal;
The frequency measurement circuit according to claim 21, wherein the frequency measurement circuit has. A frequency measurement circuit according to any one of claims 15 to 24;
A processing device for performing processing according to the measurement result of the frequency measurement circuit;
An electronic device comprising:

Images