JP2014016382A - Solid state image pickup device, electronic equipment and method for pixel read-out - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a suitable line sensor by an AF sensor.SOLUTION: A solid state image pickup device includes a plurality of line sensors having a plurality of pixels aligned in one line including an amplifier for amplifying a signal corresponding to electric charge accumulated in a photoelectric converter and a signal line for reading signals of respective pixels in the line sensors. The plurality of line sensors are arranged discretely and the signal lines are wired converged along a region where a circuit block including the line sensors is arranged. This technology, for example, can be applied to an AF sensor.

Description

  The present technology relates to a solid-state imaging device, an electronic device, and a pixel reading method, and more particularly, to a solid-state imaging device, an electronic device, and a pixel reading method that can provide a line sensor suitable for an AF sensor.

  In recent years, in digital single-lens reflex cameras, a phase difference detection method applying the principle of triangulation is used to realize an autofocus (AF) function for automatically focusing.

  The phase difference detection method obtains two subject images by dividing the light incident on the imaging lens into two by a separator lens, calculates the amount of focus shift from the image interval, and takes the photographing lens so that it is in focus This is a method for controlling the driving of the.

  An imaging apparatus that provides an AF function using such a phase difference detection method is configured by disposing a plurality of line sensors in which pixels that perform photoelectric conversion are arranged in a line in a discrete manner in accordance with a focus point. An AF sensor is used.

  As an AF sensor, for example, an AF solid-state imaging device has been proposed in which two output circuits are arranged adjacent to each other so as to correspond to two line sensors, thereby speeding up reading (for example, a patent) Reference 1).

JP 2006-285013 A

  Conventionally, a CCD (Charge Coupled Device) has been used as a line sensor constituting an AF sensor. The CCD transfers the signal charge generated in the unit pixel by incident light to the output circuit by the charge transfer function without amplifying the signal charge.

  An amplifier called an FD (Floating Diffusion) amplifier is used for the output circuit. In general, the FD amplifier is provided for each line sensor, and sequentially amplifies and outputs signal charges (pixel signals) transferred by the CCD.

  For this reason, in the AF sensor using a CCD, even if signals are simultaneously read out for two line sensors used in pairs, disturbances that occur in the process of holding, transferring, and amplifying signals in analog, etc. As a result, the signal quality deteriorates. That is, with an AF sensor using a CCD, it has been difficult to maintain noise resistance and pixel signal identity (simultaneity) of a pair of line sensors.

  In an AF sensor using a CCD, pixel signals are transferred and amplified sequentially, but the processing speed is determined by the CCD transfer speed and the frequency characteristics of the FD amplifier, and it is not easy to increase the processing speed. There wasn't.

  As a result, the accuracy of the AF operation in the AF sensor using the CCD is lowered, and the followability of the AF function with respect to a subject moving at high speed is reduced.

  The present technology has been made in view of such a situation, and makes it possible to provide a suitable line sensor by using an AF sensor.

  A solid-state imaging device according to one aspect of the present technology includes a plurality of line sensors in which a plurality of pixels including an amplifier that amplifies a signal corresponding to a charge accumulated in a photoelectric conversion element are arranged in a line, and each of the line sensors A plurality of the line sensors are discretely arranged, and the signal lines are converged along a region where a circuit block including the line sensor is arranged. Wired.

  An interval between the signal lines that are converged and wired can be narrower than an interval between the pixels arranged in the line sensor.

  The solid-state imaging device further includes a parallel A / D converter capable of performing A / D conversion on the signals of the pixels of the plurality of line sensors in parallel, and the signal line includes each of the plurality of line sensors. A pixel and the A / D converter can be connected.

  The A / D converter can A / D convert the signals of the pixels of all the line sensors in parallel.

  A plurality of the line sensors are selectively operated, and the signal lines share a wiring on the A / D converter side for each corresponding pixel among the plurality of line sensors, and a plurality of the line sensors are shared. Each pixel of the sensor and the A / D converter can be connected, and the A / D converter can A / D convert the signal of each pixel of the selected line sensor in parallel.

  In the solid-state imaging device, a switch for turning on / off the connection between each pixel and the A / D converter for each line sensor is provided in a wiring portion of the signal line that is not supplied with the pixel of another line sensor. The A / D converter can perform A / D conversion in parallel on the signals of the pixels of the line sensor corresponding to the signal line on which the switch is turned on.

  The solid-state imaging device may further include a line memory that holds the digital signal output from the A / D converter.

  The solid-state imaging device may further include a signal processing circuit that performs predetermined signal processing on the digital signal output from the A / D converter.

  A shield line connected to a power supply potential or a ground potential can be further wired near a region where the signal lines are converged and wired.

  When at least some of the plurality of line sensors are arranged adjacent to each other in parallel, the signal line for reading the signal of each pixel of one of the line sensors is wired across the other line sensor. You can make it.

  In the plurality of line sensors, one of the line sensors is paired with the other of the line sensors, and each of the paired line sensors has pixel rows arranged in a row in a predetermined direction. Can be arranged as follows.

  The line sensor can be a complementary metal-oxide semiconductor (CMOS) image sensor.

  An electronic apparatus according to an aspect of the present technology includes a plurality of line sensors in which a plurality of pixels including an amplifier that amplifies a signal corresponding to a charge accumulated in a photoelectric conversion element are arranged in a line, and each pixel of the line sensor A plurality of the line sensors are discretely arranged, and the signal lines are converged and wired along a region where the circuit block including the line sensor is arranged. A solid-state imaging device.

  A pixel readout method according to one aspect of the present technology includes a plurality of line sensors in which a plurality of pixels including an amplifier that amplifies a signal corresponding to a charge accumulated in a photoelectric conversion element are arranged in a line, and each of the line sensors. A signal line for reading out a pixel signal, a parallel A / D converter capable of performing A / D conversion on the signal of each pixel of the plurality of line sensors in parallel, and the signal line on the line sensor side, Each line sensor includes a switch for turning on / off connection between each pixel and the A / D converter, the plurality of line sensors are discretely arranged, and the signal line includes a circuit block including the line sensor. Are arranged and converged along a region where the plurality of line sensors are arranged, and for each corresponding pixel among the plurality of line sensors, the wiring on the A / D converter side is shared, and each pixel of the plurality of line sensors is shared. And the A / D converter A pixel readout method of a solid-state imaging device, the solid-state imaging device, comprising the steps of A / D conversion signals of the pixels of the line sensors corresponding to the signal line in which the switch is turned on in parallel.

  In one aspect of the present technology, a plurality of line sensors are discretely arranged, and signal lines are converged and wired along a region where a circuit block including the line sensors is arranged.

  According to one aspect of the present technology, it is possible to provide a line sensor that is more suitable for the AF sensor.

It is a figure which shows the structural example of the conventional AF sensor. It is a figure which shows the structural example of 1st Embodiment of the solid-state imaging device to which this technique is applied. It is the schematic which shows the structure of a unit pixel. It is a figure which shows the specific structural example of a unit pixel. It is a figure which shows the structural example of 2nd Embodiment of the solid-state imaging device to which this technique is applied. It is a figure which shows the structural example of 3rd Embodiment of the solid-state imaging device to which this technique is applied. It is a figure which shows the structural example of 4th Embodiment of the solid-state imaging device to which this technique is applied. It is a figure explaining the example of reading of a line sensor. It is a figure explaining other examples of reading of a line sensor. It is a figure which shows the structural example of 5th Embodiment of the solid-state imaging device to which this technique is applied. It is a figure which shows the structural example of a switch. It is a figure explaining the example of reading of a line sensor. It is a figure which shows the structural example of 6th Embodiment of the solid-state imaging device to which this technique is applied. It is a figure which shows the structural example of 7th Embodiment of the solid-state imaging device to which this technique is applied. It is a figure which shows the structural example of one Embodiment of the electronic device to which this technique is applied.

  First, prior to describing embodiments of the present technology, a conventional configuration will be described.

[Example of conventional AF sensor configuration]
FIG. 1 is a diagram showing a configuration example of a conventional AF (Auto Focus) sensor using a CCD.

  The AF sensor shown in FIG. 1 includes four line sensors 11, an output changeover switch 12, and an output circuit 13.

  In the AF sensor of FIG. 1, two line sensors 11 arranged in the horizontal direction form a pair, and two line sensors 11 arranged in the vertical direction form a pair.

  In each line sensor 11, unit pixels 21 made of photodiodes that are photoelectric conversion elements are arranged in a line (in a line), and each unit pixel 21 converts incident light into a signal charge, and a CCD shift register. 22 to output. The CCD shift register 22 sequentially transfers signal charges output from each unit pixel 21 to an FD (Floating Diffusion) amplifier 23. The FD amplifier 23 is provided for each line sensor 11, sequentially amplifies signal charges (pixel signals) transferred from the CCD shift register 22, and outputs them to the output changeover switch 12.

  The output changeover switch 12 selects the output from each line sensor 11 in a predetermined order and supplies it to the output circuit 13.

  The output circuit 13 is configured to include at least a CDS (Correlated Double Sampling) circuit, and performs correlated double sampling. Thereby, the noise component contained in the output from each unit pixel 21 is removed.

  In the AF sensor, the simultaneity of the pixel signals between the paired line sensors is important. However, in the configuration shown in FIG. 1, when the pixel signals are read from the two line sensors 11 forming the pair, The noise component superimposed due to disturbance during the transfer by the shift register 22 differs between the paired line sensors 11 and is therefore not removed by the CDS circuit. That is, in the AF sensor of FIG. 1, the pixel signal simultaneity between the paired line sensors could not be maintained.

  On the other hand, Patent Document 1 discloses that two output circuits are arranged adjacent to each other corresponding to two line sensors and pixel signals are read out in parallel from the two line sensors. As a result, the AF speed has been increased, but the pixel signal from the line sensor is sequentially transferred by a vertical shift register composed of a CCD, so the AF processing speed is the CCD transfer speed or This was determined by the operating speed of the output circuit, which hindered further increases in AF processing speed.

  In addition, an AF sensor using a CCD requires a power supply voltage exceeding 10 V for its operation, and also requires a plurality of power supplies for a plurality of peripheral circuits, resulting in an increase in power consumption. . Furthermore, an AF sensor using a CCD requires a dedicated process for its manufacture, or requires a combination of a plurality of peripheral circuits to be operated, resulting in a very complicated system.

As described above, in the conventional AF sensor, it is difficult to ensure the noise resistance and simultaneity of the pixel signal of the line sensor and to increase the reading speed. The following two points are mentioned as the cause.
1. 1. The pixel signals of all the pixels in the line sensor cannot be read out simultaneously. Signal readout is performed with analog signals with low noise resistance

  Therefore, in the following, the configuration of the AF sensor that eliminates the above-described two points, and ensures the noise resistance and simultaneity of the pixel signals of the line sensor and speeds up reading will be described.

[First embodiment of solid-state imaging device to which the present technology is applied]
FIG. 2 is a diagram illustrating a configuration example of the first embodiment of the solid-state imaging device to which the present technology is applied.

  The solid-state imaging device 31 of FIG. 2 includes five line sensors 41, a pixel driving unit 42, a pixel signal line 43, a column ADC (Analog Digital Converter) 44, and a line memory 45.

  Each line sensor 41 is discretely arranged on the chip constituting the solid-state imaging device 31, that is, distributed in a certain regularity, and includes the same number of unit pixels 51. In the line sensor 41, a predetermined number of unit pixels 51 are arranged in a line. The line sensor 41 is configured as a CMOS image sensor (Complementary Metal Oxide Semiconductor).

  Here, the configuration of the unit pixel 51 will be described with reference to FIGS. 3 and 4. FIG. 3 is a schematic diagram illustrating a configuration of the unit pixel 51, and FIG. 4 is a diagram illustrating a configuration example of the unit pixel 51.

  First, as shown in FIG. 3, the unit pixel 51 includes at least a photoelectric conversion element 61, an amplifier 65, and a switch 66. In the unit pixel 51, the photoelectric conversion element 61 accumulates signal charges according to the amount of incident light, and the amplifier 65 amplifies pixel signals according to the signal charges. The switch 66 outputs an amplified pixel signal in accordance with the drive signal from the pixel drive unit 42.

  The unit pixel 51 shown in FIG. 4 includes a photodiode (PD) 61, a transfer gate 62, a floating diffusion (FD) 63, a reset transistor 64, an amplification transistor 65, and a selection transistor 66. The photodiode 61, the amplification transistor 65, and the selection transistor 66 in FIG. 4 correspond to the photoelectric conversion element 61, the amplifier 65, and the switch 66 in FIG.

  The anode of the photodiode 61 is grounded, and the cathode of the photodiode 61 is connected to the source of the transfer gate 62. The drain of the transfer gate 62 is connected to the drain of the reset transistor 64 and the gate of the amplification transistor 65, respectively, and this connection point constitutes the FD 63.

  The source of the reset transistor 64 is connected to a predetermined power source, and the source of the amplification transistor 65 is also connected to a predetermined power source. The drain of the amplification transistor 65 is connected to the source of the selection transistor 66, and the drain of the selection transistor 66 is connected to the pixel signal line 43.

  The gate of the transfer gate 62, the gate of the reset transistor 64, and the gate of the selection transistor 66 are connected to the pixel drive unit 42 via a control line (not shown), and a pulse as a drive signal is supplied thereto. .

  The photodiode 61 photoelectrically converts incident light, and generates and accumulates charges corresponding to the amount of light.

  The transfer gate 62 turns on / off the transfer of charges from the photodiode 61 to the FD 63 in accordance with the drive signal TRG supplied from the pixel drive unit 42. For example, when an H (High) level drive signal TRG is supplied to the transfer gate 62, the charge accumulated in the photodiode 61 is transferred to the FD 63 and an L (Low) level drive signal TRG is supplied. Then, the charge transfer is stopped. Note that the charge photoelectrically converted by the photodiode 61 is stored in the photodiode 61 while the transfer gate 62 stops transferring the charge to the FD 63.

  The FD 63 accumulates the charge transferred from the photodiode 61 via the transfer gate 62 and converts it into a voltage. Note that the FD 63 functions as a charge holding unit that holds charges accumulated in the photodiode 61 during the exposure period.

  The reset transistor 64 turns on / off the discharge of the charge accumulated in the FD 63 according to the drive signal RST supplied from the pixel drive unit 42. For example, when the H level drive signal RST is supplied, the reset transistor 64 clamps the FD 63 to the power supply voltage and discharges (resets) the electric charge accumulated in the FD 63. The reset transistor 64 causes the FD 63 to be in an electrically floating state when an L level drive signal RST is supplied.

  The amplification transistor 65 amplifies a voltage corresponding to the electric charge accumulated in the FD 63. The voltage (voltage signal) amplified by the amplification transistor 65 is output to the pixel signal line 43 via the selection transistor 66.

  The selection transistor 66 turns on / off the output of the voltage signal from the amplification transistor 65 to the pixel signal line 43 in accordance with the drive signal SEL supplied from the pixel drive unit 42. For example, the selection transistor 66 outputs a voltage signal to the pixel signal line 43 when an H level drive signal SEL is supplied, and stops outputting the voltage signal when an L level drive signal SEL is supplied.

  As described above, the unit pixel 51 is driven in accordance with the drive signal TRG, the drive signal RST, and the drive signal SEL supplied from the pixel drive unit 42.

  The unit pixel 51 is not limited to the configuration shown in FIG.

  Hereinafter, the unit pixel 51 is also simply referred to as a pixel 51.

  Returning to the description of FIG. 2, the pixel driving unit 42 drives the pixel 51 by supplying a driving signal to each pixel 51 of the line sensor 41.

  The pixel signal line 43 is a signal line for reading the signal of each pixel 51 of each line sensor 41 and connects each pixel 51 and the column ADC 44.

  As shown in FIG. 2, the pixel signal lines 43 are converged and wired along a circuit block including the line sensor 41, that is, a region where the line sensor 41, the column ADC 44, and the line memory 45 are arranged. Yes. The interval (pitch) between the pixel signal lines 43 arranged in a concentrated manner is narrower than the interval (pitch) between the pixels 51 arranged in the line sensor 41.

  The column ADC 44 is a column parallel type column AD converter, and performs a CDS process on the signal of each pixel 51 of each line sensor 41 in parallel and performs an AD conversion to convert the pixel signal into a digital signal as a line memory. 45 (output).

  The line memory 45 holds the digital signal supplied from the column ADC 44, and appropriately outputs the held digital signal as necessary.

  According to the above configuration, the line sensor uses a CMOS image sensor having an amplifier for each pixel, and the pixel output is AD-converted in parallel in the column ADC. The pixel signals of these pixels can be read out simultaneously, and the signal readout is performed with a digital signal having high noise resistance. As a result, it is possible to secure the noise resistance and simultaneity of the pixel signals of the line sensor and eliminate the cause that hinders the speeding up of reading, and to provide a solid-state imaging device more suitable for the AF sensor. It becomes possible.

  In the configuration of FIG. 2, the pixel signal line 43 for each pixel 51 of the line sensor 41 increases according to the number of pixels 51 in the line sensor 41 and the number of line sensors 41 on the chip. Further, since the line sensor 41 is discretely arranged on the chip, there is a great restriction on the location where other circuit blocks (column ADC 44, line memory 45, etc.) are arranged.

  Therefore, in the above, the pixel signal lines 43 for the respective pixels 51 are converged and wired along the region where the line sensor 41 and other circuit blocks are arranged, so that the column ADC 44, the line memory 45, etc. All the pixels 51 and the column ADC 44 can be connected while securing an area for arranging the circuit blocks, and the chip size can be reduced.

  In addition, the conventional AF sensor using a CCD requires a high power supply voltage for its operation. However, according to the configuration of FIG. 2, the CMOS is used so that it can be operated with a low power supply voltage. As a result, power consumption can be reduced.

  Further, according to the configuration of FIG. 2, since reading can be performed in parallel with respect to all the line sensors 41, the AF sensor can focus on more focus points with high accuracy. It becomes.

  By the way, as shown in FIG. 2, when the pixel signal lines 43 are wired with a sufficiently narrow interval, the longer the distance between the pixel signal lines 43, the more the pixel signal is affected by crosstalk due to the parasitic capacitance between the pixel signal lines 43. It becomes easy to receive. Further, when the pixel signal lines 43 are wired in a wide range on the chip, it is conceivable that the signal lines of the column ADC 44 and other circuit blocks are parallel or crossed.

  In such a case, in the wiring layout, in the vicinity of the pixel signal lines 43, specifically, between the pixel signal lines 43 or above or below the wiring layer where the pixel signal lines 43 are wired, A shield line connected to the power supply potential or the ground potential may be wired. As a result, the influence of crosstalk on the pixel signal due to the parasitic capacitance between the pixel signal lines 43 can be suppressed.

  In addition, by wiring a shield line in the vicinity of the pixel signal line 43, a parasitic capacitance between each pixel signal line 43 and the shield line is generated. On the other hand, the pixel signal is set so that the parasitic capacitance has an appropriate capacitance value in consideration of the distance at which the pixel signal line 43 is wired and the settling time (settling time) required for the pixel signal line 43. The distance between the line 43 and the shield line and the driving capability of the amplifier provided in each pixel 51 may be adjusted.

[Second Embodiment of Solid-State Imaging Device to which Present Technology is Applied]
FIG. 5 is a diagram illustrating a configuration example of the second embodiment of the solid-state imaging device to which the present technology is applied.

  The solid-state imaging device 31 </ b> A of FIG. 5 includes six line sensors 41, a pixel driving unit 42, a pixel signal line 43, a column ADC 44, and a line memory 45. 5, parts having the same functions as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  In the solid-state imaging device 31A of FIG. 5, two line sensors 41 are arranged adjacent to each other in parallel. Furthermore, in the solid-state imaging device 31A of FIG. 5, of the two line sensors 41 arranged adjacently in parallel, each pixel 51 of one line sensor 41 (the line sensor 41 far from the column ADC 44). The pixel signal line 43 for reading a signal is wired across the other line sensor 41 (the line sensor 41 closer to the column ADC 44).

  According to the above configuration, the same operation and effect as the solid-state imaging device 31 of FIG. 2 can be obtained, and the wiring area can be increased even when the line sensors 41 are arranged adjacently in parallel. Therefore, the chip size can be reduced.

[Third embodiment of a solid-state imaging device to which the present technology is applied]
FIG. 6 is a diagram illustrating a configuration example of the third embodiment of the solid-state imaging device to which the present technology is applied.

  The solid-state imaging device 31B of FIG. 6 includes eight line sensors 41-1 to 41-8, pixel driving units 42-1 to 42-3, pixel signal lines 43-1 and 43-2, and column ADCs 44-1 and 44-. 2 and line memories 45-1 and 45-2. 6, parts having the same functions as those in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted as appropriate. In FIG. 6, branch numbers are assigned to the reference numerals of the respective parts for convenience, and description will be made by appropriately adding branch numbers.

  In the solid-state imaging device 31B of FIG. 6, the line sensors 41-1, 41-3, 41-5, and 41-7 are respectively paired with the line sensors 41-2, 41-4, 41-6, and 41-8. ). The paired line sensors 41 are arranged discretely and symmetrically, specifically, so that the pixel columns of the pixels 51 are arranged in a line in the horizontal direction or the vertical direction around the pixel driving unit 42. Has been.

  Here, one of the paired line sensors 41 (line sensors 41-1, 41-3, 41-5, and 41-7) is the main line sensor 41, and the other (line sensors 41-2, 41-). 4, 41-6, 41-8) are referred to as sub-row line sensors 41, the signals of the pixels 51 of the main-row line sensors 41 are transmitted to the column ADC 44-1 via the pixel signal lines 43-1. The signal of each pixel 51 of the sub-line line sensor 41 is output to the column ADC 44-2 via the pixel signal line 43-2.

  The digital signal output from the column ADC 44-1 is supplied to the line memory 45-1, and the digital signal output from the column ADC 44-2 is supplied to the line memory 45-2.

  Also in the solid-state imaging device 31B of FIG. 6, the pixel signal line 43 (43-1, 43-2) includes a circuit block including the line sensor 41, that is, the line sensor 41, the column ADC 44, and the line memory 45. Concentrated and wired along the area. The interval (pitch) between the pixel signal lines 43 arranged in a concentrated manner is narrower than the interval (pitch) between the pixels 51 arranged in the line sensor 41.

  In the solid-state imaging device 31B of FIG. 6, the column ADCs 44-1 and 44-2 can be operated simultaneously by a timing control signal from a control unit (not shown). Thereby, it is possible to AD convert the signals of the pixels 51 of all the line sensors 41 in parallel while ensuring simultaneity.

  Also in the above configuration, the same operation and effect as the solid-state imaging device 31 of FIG.

[Fourth embodiment of solid-state imaging device to which the present technology is applied]
FIG. 7 is a diagram illustrating a configuration example of the fourth embodiment of the solid-state imaging device to which the present technology is applied.

  The solid-state imaging device 31C of FIG. 7 includes 16 line sensors 41-1A, 41-1B,..., 41-8A, 41-8B, pixel driving units 42-1 to 42-3, and a pixel signal line 43-1. 43-2, column ADCs 44-1, 44-2, and line memories 45-1, 45-2. In FIG. 7, parts corresponding to those in FIG. 6 are denoted by the same reference numerals, and description thereof is omitted as appropriate.

  In the solid-state imaging device 31C of FIG. 7, the line sensors 41-1A, 41-1B, 41-3A, 41-3B, 41-5A, 41-5B, 41-7A, and 41-7B are line sensors 41-2A. , 41-2B, 41-4A, 41-4B, 41-6A, 41-6B, 41-8A, and 41-8B, respectively. The paired line sensors 41 are arranged discretely and symmetrically, specifically, so that the pixel columns of the pixels 51 are arranged in a line in the horizontal direction or the vertical direction around the pixel driving unit 42. Has been.

  In the solid-state imaging device 31C of FIG. 7, a set of line sensors that are locally adjacent to each other is referred to as a line sensor group. Specifically, the line sensors 41-1A and 41-1B are referred to as a line sensor group 71-1 and the line sensors 41-2A and 41-2B are referred to as a line sensor group 71-2. The same applies to the other line sensors 41.

  Again, one of the paired line sensors 41 (line sensors 41-1A, 41-1B, 41-3A, 41-3B, 41-5A, 41-5B, 41-7A, 41-7B) is mainly used. The line sensor 41 in the row and the other (line sensors 41-2A, 41-2B, 41-4A, 41-4B, 41-6A, 41-6B, 41-8A, 41-8B) are connected to the line sensor 41 in the subrow. As a result, the signal of each pixel 51 of the line sensor 41 in the main column is output to the column ADC 44-1 via the pixel signal line 43-1, and the signal of each pixel 51 of the line sensor 41 in the sub column is The signal is output to the column ADC 44-2 via the pixel signal line 43-2.

  Also in the solid-state imaging device 31C of FIG. 7, the signal of each pixel 51 of one line sensor 41 (the line sensor 41 far from the column ADC 44) is read out of the two line sensors 41 constituting the line sensor group. The pixel signal line 43 for this purpose is wired across the other line sensor 41 (the line sensor 41 closer to the column ADC 44).

  The digital signal output from the column ADC 44-1 is supplied to the line memory 45-1, and the digital signal output from the column ADC 44-2 is supplied to the line memory 45-2.

  Furthermore, in the solid-state imaging device 31C of FIG. 7, the paired main row line sensors 41 and sub row line sensors 41 are selectively operated. In other words, in the solid-state imaging device 31C of FIG. 7, only one pair of line sensors 41 out of eight pairs is selected and outputs a pixel signal.

  Further, in the solid-state imaging device 31C of FIG. 7, the pixel signal lines 43 (43-1, 43-2) are converged and wired along the region where the circuit block including the line sensor 41 is disposed. In addition, the column ADCs 44-1 and 44-2 are shared, and the line sensor 41 of the main column and the line sensor 41 of the sub column and the column ADCs 44-1 and 44-2 are respectively connected.

  Therefore, the column ADCs 44-1 and 44-2 receive only the signals corresponding to the number of pixels included in each pixel 51 of the selected main row line sensor 41 and sub row line sensor 41, that is, one line sensor 41. It is sufficient to perform AD conversion in parallel. As a result, the number of columns of the column ADC 44 is greatly reduced, and the column ADC 44 can be downsized.

  FIG. 8 shows an example of reading by the line sensor 41 in the solid-state imaging device 31C of FIG.

  In FIG. 8, the line sensor 41 is selected in the order of a pair of line sensor groups 71 and 72, a pair of line sensor groups 73 and 74, a pair of line sensor groups 75 and 76, and a pair of line sensor groups 77 and 78. In this example, reading (AD conversion) is performed. The selected pair of line sensors 41 is one pair in each line sensor group. Here, it is assumed that the accumulation times of all the line sensors 41 are set to be the same.

  In the example of FIG. 8, since the column ADC 44 performs AD conversion by pipeline processing, accumulation of the line sensor 41 in each line sensor group is sequentially started according to the time required for AD conversion.

  When the accumulation times of all the line sensors 41 are the same, reading can be performed in the shortest time by the operation sequence shown in FIG.

  When the accumulation times of the line sensors 41 are set to different times, as shown in FIG. 9, reading is performed by changing the order and timing so that the AD conversion timing does not overlap. You may make it perform.

  Note that in the solid-state imaging device 31C of FIG.

  Further, in the solid-state imaging device 31C in FIG. 7, which line sensor group pair is selected and which pair is selected in the line sensor group is determined in which area in the screen is focused. Determined by.

  According to the above configuration, by sharing a part of the wiring of the pixel signal line 43, the wiring area can be reduced, and the chip size can be reduced.

  Further, in the configuration of FIG. 7, the pixels 51 of all the line sensors 41 are not read in parallel, but the pixels 51 of the selected pair of line sensors 41 are sequentially read in parallel. The number of columns of −1 and 44-2 can be reduced to the number of pixels included in one line sensor 41, respectively. As a result, the column ADC 44 can be downsized, the chip size can be further reduced, and the power consumption can be reduced.

  In the configuration of FIG. 7, the reading of the selected pair of line sensors 41 is sequentially performed, but the time required for reading (AD conversion) by the column ADC 44 is about several μsec to tens of μsec per time. Therefore, it does not significantly impair simultaneity and high speed.

  In addition, since the reading of the selected pair of line sensors 41 is sequentially performed, the AD conversion gain can be changed for each read pair. Thereby, for example, the sensitivity can be increased by increasing the gain of the line sensor near the outer periphery of the chip where the amount of incident light is optically reduced.

  In the solid-state imaging device 31C of FIG. 7, each line sensor group is composed of two line sensors, but may be composed of three or more line sensors.

  Further, in the solid-state imaging device 31C of FIG. 7, each line sensor 41 is arranged as a line sensor group, but the line sensor 41 may be arranged alone.

  By the way, in the solid-state imaging device 31C of FIG. 7, when the number of line sensors increases or when the line sensors are arranged at positions separated from each other, the parasitic capacitance and parasitic resistance of the pixel signal line 43 increase, and the pixel signal It takes time to settle the pixel signal transmitted through the line 43. In order to improve the settling, it is necessary to increase the current, resulting in an increase in power consumption.

  Therefore, in the following, a configuration for suppressing an increase in power consumption due to the settling described above will be described.

[Fifth embodiment of solid-state imaging device to which the present technology is applied]
FIG. 10 is a diagram illustrating a configuration example of the fifth embodiment of the solid-state imaging device to which the present technology is applied.

  A solid-state imaging device 31D in FIG. 10 includes switches SW_1, SW_2, SW_5, SW_6, SW_7, and SW_8 in addition to the same configuration as the solid-state imaging device 31C in FIG. In the following description, the switches SW_1, SW_2, SW_5, SW_6, SW_7, and SW_8 are simply referred to as switches SW when not distinguished from each other.

  The switch SW_1 is connected to the other line sensor group among the wirings of the pixel signal line 43-1 that connects each pixel 51 of the line sensor group 71 (line sensors 41-1A and 41-1B) and the column ADC 44-1. It is provided in a wiring portion that is not shared with the pixel. The switch SW_1 turns on / off the connection between each pixel 51 of the line sensor group 71 and the column ADC 44-1.

  The switch SW_2 is another line sensor in the wiring of the pixel signal line 43-2 that connects each pixel 51 of the line sensor group 72 (line sensors 41-2A, 41-2B) and the column ADC 44-2. It is provided in a wiring portion that is not shared with a group of pixels. The switch SW_2 turns on / off the connection between each pixel 51 of the line sensor group 72 and the column ADC 44-2.

  Similarly, the switch SW_5 is provided for the line sensor group 75, the switch SW_6 is provided for the line sensor group 76, the switch SW_7 is provided for the line sensor group 77, and the switch SW_8 is provided for the line sensor group 78. It has been. Note that the switch SW is not provided for the line sensor groups 73 and 74.

  FIG. 11 is a diagram illustrating a configuration example of the switch SW.

  The switch SW includes transistors 81 and 82 and a NOT gate 83. When a control signal from a control unit (not shown) is input to the NOT gate 83 (becomes H level), the transistors 81 and 82 operate as a switch, and p-q is conducted.

  The configuration of the switch SW is not limited to the configuration shown in FIG.

  FIG. 12 shows an example of reading by the line sensor 41 in the solid-state imaging device 31D of FIG.

  Here, reading (AD conversion) is performed in the same operation sequence as in FIG.

  In the example of FIG. 12, when the control signals of the switches SW_1 and SW_2 become H level, the switches SW_1 and SW_2 are turned on, and the column ADCs 44-1 and 44-2 read out the pair of line sensor groups 71 and 72. (AD conversion) is performed.

  Further, when the control signals of the switches SW_5 and SW_6 become H level, the switches SW_5 and SW_6 are turned on, and the column ADCs 44-1 and 44-2 read out the pair of line sensor groups 75 and 76 (AD conversion). Is done.

  Further, when the control signals of the switches SW_7 and SW_8 become H level, the switches SW_7 and SW_8 are turned on, and the column ADCs 44-1 and 44-2 read out a pair of line sensor groups 77 and 78 (AD conversion). Is done.

  Further, the switch SW for the line sensor groups 73 and 74 is not provided, but the drive signal SEL from the pixel drive unit 42 is supplied to each pixel 51 of the pair of line sensor groups 73 and 74, A pair of line sensor groups 73 and 74 is read (AD conversion) by the column ADCs 44-1 and 44-2.

  In addition, in the solid-state imaging device 31D of FIG. 10, the switches SW_3 and SW_4 for the line sensor groups 73 and 74 are provided, respectively, so that reading (AD conversion) of the pair of line sensor groups 73 and 74 is performed. Good.

  According to the above configuration, only the line sensor 41 to be read is electrically connected to the column ADC 44, and the other line sensors 41 are electrically disconnected from the column ADC 44. As a result, the influence of the parasitic capacitance and parasitic resistance of the pixel signal line 43 is reduced to a negligible level, and as a result, an increase in power consumption for improving settling in the pixel signal line can be suppressed.

[Sixth embodiment of a solid-state imaging device to which the present technology is applied]
FIG. 13 is a diagram illustrating a configuration example of the sixth embodiment of the solid-state imaging device to which the present technology is applied.

  A solid-state imaging device 31E in FIG. 13 has the same configuration as that of the solid-state imaging device 31B in FIG. 6, and a digital memory and signal processing circuits 91-1, 91- 2 is provided.

  The digital memory and signal processing circuits 91-1 and 91-2 receive part or all of the output data (pixel signals) of each line sensor 41 supplied as digital output signals from the line memories 45-1 and 45-2. save. Further, the digital memory and signal processing circuits 91-1 and 91-2 perform predetermined signal processing on the stored output data of each line sensor 41 at a predetermined timing.

  In a conventional AF sensor using a CCD, all readout processing is performed in analog, so the microcontroller mounted on the set performs AD conversion of the readout signal and performs predetermined signal processing. . For this reason, the number of mounted parts on the set increases and the design of the control sequence is complicated.

  On the other hand, according to the above configuration, since the digital memory and the signal processing circuits 91-1 and 91-2 can be integrated on the same chip as the line sensor 41 and the like, a very simple system can be realized. Can be provided.

  Further, since the digital memory and the signal processing circuits 91-1 and 91-2 can perform predetermined signal processing on the output data of each line sensor 41 at a predetermined timing, the output of each line sensor 41 is output. Data can be arbitrarily read without time constraints, and calculation processing such as peak detection in AF can be realized on a single chip.

[Seventh embodiment of a solid-state imaging device to which the present technology is applied]
FIG. 14 is a diagram illustrating a configuration example of the seventh embodiment of the solid-state imaging device to which the present technology is applied.

  The solid-state imaging device 31F in FIG. 14 has the same configuration as the solid-state imaging device 31D in FIG. 10, and in addition to a digital memory and signal processing circuits 91-1 and 91- in a vacant area on the chip of the solid-state imaging device 31D in FIG. 2 is provided.

  Also in the above configuration, since the digital memory and the signal processing circuits 91-1 and 91-2 can be integrated on the same chip as the line sensor 41 and the like, a very simple system can be provided.

  In the embodiment of the solid-state imaging device to which the present technology is applied as described above, the line sensor group is a single line sensor unit in a configuration in which a shield line is wired near the pixel signal line 43 or the line sensor group is provided. Of course, it can be replaced with.

  Further, in the solid-state imaging device 31B of FIG. 6, the solid-state imaging device 31C of FIG. 7, and the like, the arrangement of the discrete line sensors 41 is such that the pixel columns of the pixels 51 are arranged in a row in the horizontal direction or the vertical direction. However, the present invention is not limited to this, and the pixel rows may be arranged in, for example, an oblique line.

[Embodiment of an electronic device to which the present technology is applied]
The solid-state imaging device of the present technology is an image capturing unit (photoelectric conversion unit) such as an imaging device such as a digital still camera or a video camera, a portable terminal device having an imaging function, a copying machine using the solid-state imaging device for an image reading unit The present invention is applicable to all electronic devices that use solid-state imaging devices. The solid-state imaging device may have a form formed as a single chip, or may have a modular form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together.

  FIG. 15 is a block diagram illustrating a configuration example of an embodiment of an imaging apparatus as an electronic apparatus to which the present technology is applied.

  The imaging apparatus 200 in FIG. 15 includes an optical unit 201 including a lens group such as an imaging lens, a solid-state imaging device 202 that images a subject, a DSP circuit 203 that is a camera signal processing circuit, and the line sensor 41 described above. A plurality of solid-state imaging devices 204 are provided. The imaging apparatus 200 also includes a frame memory 205, a display unit 206, a recording unit 207, an operation unit 208, and a power supply unit 209. The DSP circuit 203, the solid-state imaging device 204, the frame memory 205, the display unit 206, the recording unit 207, the operation unit 208, and the power supply unit 209 are connected to each other via the bus line 210.

  The optical unit 201 captures incident light (image light) from a subject and forms an image on the imaging surface of the solid-state imaging device 202, and is connected to the line sensor 41 paired with the solid-state imaging device 204 via a separator lens. Image.

  The solid-state imaging device 202 converts the amount of incident light imaged on the imaging surface by the optical unit 201 into an electrical signal for each pixel and outputs the electrical signal as a pixel signal.

  The solid-state imaging device 204 calculates the amount of defocusing of the imaging lens in the optical unit 201 based on the subject image formed on the line sensor 41 paired by the optical unit 201, and shoots so as to be in focus. A control signal for driving the lens is output. As the solid-state imaging element 204, a solid-state imaging device such as the solid-state imaging device 31 according to the above-described embodiment can be used.

  The display unit 206 includes, for example, a panel type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays a moving image or a still image captured by the solid-state image sensor 202. The recording unit 207 records a moving image or a still image captured by the solid-state imaging device 202 on a recording medium such as a video tape or a DVD (Digital Versatile Disk).

  The operation unit 208 issues operation commands for various functions of the imaging apparatus 200 under the operation of the user. The power supply unit 209 appropriately supplies various power sources serving as operation power sources for the DSP circuit 203, the frame memory 205, the display unit 206, the recording unit 207, and the operation unit 208 to these supply targets.

  As described above, by using the solid-state imaging device 31 that is more suitable for the AF sensor and realizes a reduction in chip size as the solid-state imaging device 204, a highly accurate AF function is provided and the imaging device 200 is small. Can be achieved.

  The embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present technology.

Furthermore, this technique can take the following structures.
(1)
A plurality of line sensors in which a plurality of pixels including an amplifier for amplifying a signal corresponding to the charge accumulated in the photoelectric conversion element are arranged in a line;
A signal line for reading a signal of each pixel of the line sensor,
The plurality of line sensors are arranged discretely,
The signal line is converged and wired along a region where a circuit block including the line sensor is arranged. Solid-state imaging device.
(2)
The solid-state imaging device according to (2), wherein an interval between the signal lines that are converged and wired is narrower than an interval between the pixels that are arranged in the line sensor.
(3)
A parallel A / D converter capable of A / D converting the signals of the pixels of the plurality of line sensors in parallel;
The solid-state imaging device according to (1) or (2), wherein the signal line connects each pixel of the plurality of line sensors and the A / D converter.
(4)
The solid-state imaging device according to (3), wherein the A / D converter performs A / D conversion in parallel on signals of pixels of all the line sensors.
(5)
Each of the plurality of line sensors selectively operates,
The signal line connects each pixel of the plurality of line sensors and the A / D converter by sharing the wiring on the A / D converter side for each corresponding pixel between the plurality of line sensors. And
The solid-state imaging device according to (3), wherein the A / D converter performs A / D conversion in parallel on a signal of each pixel of the selected line sensor.
(6)
In the signal line, a wiring portion that does not supply the pixel of another line sensor includes a switch for turning on / off the connection between each pixel and the A / D converter for each line sensor,
The solid-state imaging device according to (5), wherein the A / D converter performs A / D conversion in parallel on a signal of each pixel of the line sensor corresponding to the signal line on which the switch is turned on.
(7)
The solid-state imaging device according to any one of (3) to (6), further including a line memory that holds a digital signal output by the A / D converter.
(8)
The solid-state imaging device according to any one of (3) to (7), further including a signal processing circuit that performs predetermined signal processing on the digital signal output by the A / D converter.
(9)
The solid-state imaging device according to any one of (1) to (8), wherein a shield line connected to a power supply potential or a ground potential is further wired near a region where the signal lines are converged and wired.
(10)
When at least some of the plurality of line sensors are arranged adjacent to each other in parallel, the signal line for reading the signal of each pixel of one of the line sensors is wired across the other line sensor. The solid-state imaging device according to any one of (1) to (9).
(11)
In the plurality of line sensors, one of the line sensors is paired with the other of the line sensors,
The solid-state imaging device according to any one of (1) to (10), wherein the pair of line sensors are arranged such that pixel rows arranged in a pair are arranged in a row in a predetermined direction.
(12)
The solid-state imaging device according to any one of (1) to (12), wherein the line sensor is a complementary metal-oxide semiconductor (CMOS) image sensor.
(13)
A plurality of line sensors in which a plurality of pixels including an amplifier for amplifying a signal corresponding to the charge accumulated in the photoelectric conversion element are arranged in a line;
A signal line for reading a signal of each pixel of the line sensor,
The plurality of line sensors are arranged discretely,
An electronic apparatus comprising: a solid-state imaging device in which the signal line is converged and wired along a region where a circuit block including the line sensor is disposed.
(14)
A plurality of line sensors in which a plurality of pixels including an amplifier for amplifying a signal corresponding to the charge accumulated in the photoelectric conversion element are arranged in a line;
A signal line for reading a signal of each pixel of the line sensor;
A parallel A / D converter capable of performing A / D conversion on the signals of the pixels of the plurality of line sensors in parallel, and each pixel and the A / D for each line sensor on the line sensor side of the signal line It has a switch to turn on / off the connection with the converter,
The plurality of line sensors are arranged discretely,
The signal line is converged and wired along a region where the circuit block including the line sensor is disposed, and the wiring on the A / D converter side is provided for each corresponding pixel between the plurality of line sensors. In the pixel readout method of the solid-state imaging device that shares and connects each pixel of the plurality of line sensors and the A / D converter,
The solid-state imaging device is
A pixel readout method including a step of performing A / D conversion in parallel on a signal of each pixel of the line sensor corresponding to the signal line on which the switch is turned on.

  31 solid-state imaging device, 41 line sensor, 42 pixel drive unit, 43 pixel signal line, 44 column ADC, 45 line memory, 51 unit pixel

Claims (14)

A plurality of line sensors in which a plurality of pixels including an amplifier for amplifying a signal corresponding to the charge accumulated in the photoelectric conversion element are arranged in a line;
A signal line for reading a signal of each pixel of the line sensor,
The plurality of line sensors are arranged discretely,
The signal line is converged and wired along a region where a circuit block including the line sensor is arranged. Solid-state imaging device. The solid-state imaging device according to claim 1, wherein an interval between the signal lines that are converged and wired is narrower than an interval between the pixels that are arranged in the line sensor. A parallel A / D converter capable of A / D converting the signals of the pixels of the plurality of line sensors in parallel;
The solid-state imaging device according to claim 1, wherein the signal line connects each pixel of the plurality of line sensors and the A / D converter. The solid-state imaging device according to claim 3, wherein the A / D converter performs A / D conversion in parallel on signals of pixels of all the line sensors. Each of the plurality of line sensors selectively operates,
The signal line connects each pixel of the plurality of line sensors and the A / D converter by sharing the wiring on the A / D converter side for each corresponding pixel between the plurality of line sensors. And
The solid-state imaging device according to claim 3, wherein the A / D converter performs A / D conversion in parallel on a signal of each pixel of the selected line sensor. In the signal line, a wiring portion that does not supply the pixel of another line sensor includes a switch for turning on / off the connection between each pixel and the A / D converter for each line sensor,
The solid-state imaging device according to claim 5, wherein the A / D converter performs A / D conversion in parallel on a signal of each pixel of the line sensor corresponding to the signal line on which the switch is turned on. The solid-state imaging device according to claim 3, further comprising a line memory that holds a digital signal output by the A / D converter. The solid-state imaging device according to claim 3, further comprising a signal processing circuit that performs predetermined signal processing on the digital signal output by the A / D converter. The solid-state imaging device according to claim 1, further comprising a shield line connected to a power supply potential or a ground potential in a vicinity of a region where the signal lines are converged and wired. When at least some of the plurality of line sensors are arranged adjacent to each other in parallel, the signal line for reading the signal of each pixel of one of the line sensors is wired across the other line sensor. The solid-state imaging device according to claim 1. In the plurality of line sensors, one of the line sensors is paired with the other of the line sensors,
The solid-state imaging device according to claim 1, wherein the paired line sensors are arranged such that pixel columns arranged in a line are arranged in a line in a predetermined direction. The solid-state imaging device according to claim 1, wherein the line sensor is a complementary metal-oxide semiconductor (CMOS) image sensor. A plurality of line sensors in which a plurality of pixels including an amplifier for amplifying a signal corresponding to the charge accumulated in the photoelectric conversion element are arranged in a line;
A signal line for reading a signal of each pixel of the line sensor,
The plurality of line sensors are arranged discretely,
An electronic apparatus comprising: a solid-state imaging device in which the signal line is converged and wired along a region where a circuit block including the line sensor is disposed. A plurality of line sensors in which a plurality of pixels including an amplifier for amplifying a signal corresponding to the charge accumulated in the photoelectric conversion element are arranged in a line;
A signal line for reading a signal of each pixel of the line sensor;
A parallel A / D converter capable of performing A / D conversion on the signals of the pixels of the plurality of line sensors in parallel, and each pixel and the A / D for each line sensor on the line sensor side of the signal line It has a switch to turn on / off the connection with the converter,
The plurality of line sensors are arranged discretely,
The signal line is converged and wired along a region where the circuit block including the line sensor is disposed, and the wiring on the A / D converter side is provided for each corresponding pixel between the plurality of line sensors. In the pixel readout method of the solid-state imaging device that shares and connects each pixel of the plurality of line sensors and the A / D converter,
The solid-state imaging device is
A pixel readout method including a step of performing A / D conversion in parallel on a signal of each pixel of the line sensor corresponding to the signal line on which the switch is turned on.

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