JP2013254548A - Semiconductor device - Google Patents

Abstract

The standby current of a semiconductor device with a built-in memory module continues to increase with the miniaturization of transistors. To reduce the standby current, measures that reflect changes in the manufacturing conditions and usage environment of the semiconductor device are taken. is necessary.
A first transistor (PU_L), a second transistor (PD_L), a third transistor (PU_R), and a fourth transistor connected between a first power supply node (arvdd) and a second power supply node (arvss). In the memory cell (MC) having PD_R), the values of the first power supply voltage and the second power supply voltage respectively supplied to the first power supply node and the second power supply node are shifted according to the set standby mode. .
[Selection] Figure 4

Description

  The present invention relates to a semiconductor device, for example, a semiconductor device incorporating a memory module.

  Along with miniaturization of a transistor mounted on a semiconductor device, a leakage current of the transistor continues to increase in a state where a power supply voltage is supplied but the transistor is not operating (hereinafter referred to as a standby mode). This increase in leakage current causes a decrease in battery driving time of mobile devices, restrictions on speeding up due to heat generation, and the like. Note that in this specification, a state in which a transistor is operating is referred to as a normal operation mode.

  When a semiconductor device incorporates an SRAM (Static Random Access Memory), various methods for reducing leakage current caused by the SRAM have been disclosed. In Japanese Patent Laid-Open No. 2006-164314 (Patent Document 1), among the selected memory mats, memory cells that are not subjected to data read or write operations are supplied to the memory cells that are performing those operations. A configuration for supplying a voltage lower than the voltage to be disclosed is disclosed. As a result, the leakage current of the memory cell in the selected memory mat is reduced.

  Japanese Patent Laying-Open No. 2004-206745 (Patent Document 2) discloses a configuration in which a positive voltage is applied between a source and a back gate of a transistor constituting a memory cell to reduce a subthreshold leakage current by a substrate bias effect. Japanese Patent Laying-Open No. 2005-302071 (Patent Document 3) discloses that in a semiconductor system having a plurality of memory systems having different threshold voltages, the gate-source voltage that determines the off-leak current of each memory cell has an absolute value that is greater than or equal to a predetermined value. A configuration for setting a negative voltage is disclosed.

JP 2006-164314 A JP 2004-206745 A JP 2005-302071 A

  Subthreshold leakage current increases with the miniaturization of transistors. This subthreshold leakage current also increases due to the short channel effect, and halo ion implantation is introduced to suppress this short channel effect. However, this ion implantation increases the substrate leakage current due to GIDL (Gate Induced Drain Leakage) and junction leakage. Therefore, in order to suppress the leakage current of the memory cell, a countermeasure that comprehensively considers the subthreshold leakage current and the substrate leakage current is required. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to an embodiment, a memory cell array including a plurality of memory cells connected to the first power supply wiring and the second power supply wiring, and the first standby mode and the second standby mode are selectively selected for the memory cell array, respectively. A memory cell having a first conductivity type first transistor having a source connected to the first power supply line, a drain connected to the first data node, and a gate connected to the second data node, A second transistor of a second conductivity type having a source connected to the second power supply line, a drain connected to the first data node, and a gate connected to the second data node, a source connected to the first power supply line, and a drain connected to the second data node In addition, a third transistor of the first conductivity type whose gate is connected to the first data node and a source of the third transistor are connected to the second power supply wiring. Has a second transistor of the second conductivity type having a gate connected to the first data node and a first standby mode set by the mode setting circuit when the first standby mode is set by the mode setting circuit. When the first power supply voltage is supplied, the second power supply voltage is supplied to the second power supply wiring, and the second standby mode is set by the mode setting circuit, the third power supply voltage is supplied to the first power supply wiring, A fourth power supply voltage is supplied to the power supply wiring, the third power supply voltage has a voltage value between the first power supply voltage and the second power supply voltage, and the second power supply voltage is between the third power supply voltage and the fourth power supply voltage. This is a semiconductor device having the following voltage value.

  According to the one embodiment, it is possible to provide a semiconductor device having a leakage current reduction function that reflects variations in manufacturing conditions and usage environments of the semiconductor device.

1 is a configuration diagram of a semiconductor device according to a first embodiment. 1 is a specific configuration diagram of a semiconductor device according to a first embodiment; 1 is a configuration diagram of a memory cell array included in a semiconductor device according to a first embodiment. 3 is a circuit diagram of a memory cell included in the semiconductor device according to the first embodiment. FIG. 4 is a specific circuit diagram of a cell power supply voltage control circuit provided in the semiconductor device according to the first embodiment. FIG. 6 is a diagram illustrating an operation mode of a memory module included in the semiconductor device according to the first embodiment. FIG. 1 is a configuration diagram of a leak monitor circuit included in a semiconductor device according to a first embodiment. FIG. 10 is a configuration diagram of a leak monitor circuit included in a semiconductor device according to Modification 1 of Embodiment 1. FIG. 6 is a configuration diagram of a leak monitor circuit included in a semiconductor device according to Modification 2 of Embodiment 1. FIG. 5 is a circuit diagram of a comparator applicable to the semiconductor device according to the first embodiment and its modification. It is a circuit diagram of the other comparator applicable to the semiconductor device which concerns on Embodiment 1 and its modification. FIG. 11 is a configuration diagram of a leak monitor circuit when another comparator is applied to the semiconductor device according to the second modification of the first embodiment. FIG. 10 is a timing diagram for explaining the operation of the leak monitor circuit when another comparator is applied to the semiconductor device according to the second modification of the first embodiment. FIG. 11 is a circuit diagram of Modification 1 of another comparator applicable to the semiconductor device according to the first embodiment and its modification. FIG. 10 is a circuit diagram of Modification 2 of another comparator applicable to the semiconductor device according to the first embodiment and its modification. FIG. 10 is a circuit diagram of Modification 3 of another comparator applicable to the semiconductor device according to the first embodiment and its modification. FIG. 10 is a configuration diagram of a leak monitor circuit in a case where the first modification of another comparator is applied to the semiconductor device according to the second modification of the first embodiment. FIG. 10 is a timing diagram for explaining the operation of the leak monitor circuit when the modification 1 of the other comparator is applied to the semiconductor device according to the modification 2 of the first embodiment. It is a circuit diagram of a ring oscillator applicable to another comparator and its modification. It is a circuit diagram of the timer applicable to another comparator and its modification. FIG. 6 is a circuit diagram of a leak monitor circuit provided in the semiconductor device according to the second embodiment. FIG. 6 is a circuit diagram of a leak monitor circuit included in a semiconductor device according to a third embodiment. FIG. 6 is a circuit diagram of a comparator provided in a semiconductor device according to a third embodiment. FIG. 10 is a circuit diagram of a leak monitor circuit included in a semiconductor device according to a fourth embodiment. FIG. 6 is a circuit diagram of a memory cell provided in a semiconductor device according to a fourth embodiment. FIG. 10 is a configuration diagram of a semiconductor device according to a fifth embodiment. FIG. 10 is a circuit diagram of a cell power supply voltage control circuit provided in a semiconductor device according to a fifth embodiment. FIG. 10 is a circuit diagram of a leak monitor circuit included in a semiconductor device according to a fifth embodiment. FIG. 10 is a circuit diagram of a leak monitor circuit included in a semiconductor device according to a sixth embodiment. FIG. 10 is a configuration diagram of a semiconductor device according to a seventh embodiment. FIG. 10 is a circuit diagram of a leak monitor circuit included in a semiconductor device according to a seventh embodiment. FIG. 10 illustrates an operation mode of a memory module included in a semiconductor device according to a seventh embodiment. FIG. 5 is a leakage current characteristic diagram of a MOS transistor newly found by the inventors of the present application. FIG. 10 is a circuit diagram of a comparator provided in a semiconductor device according to a fifth embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In the description of the embodiment, reference to the number, amount, and the like is not necessarily limited to the number, amount, and the like unless otherwise specified. In the drawings of the embodiments, the same reference numerals and reference numerals represent the same or corresponding parts. Further, in the description of the embodiments, the overlapping description may not be repeated for the portions with the same reference numerals and the like.

<Embodiment 1>
A configuration of the semiconductor device LSI according to the first embodiment will be described with reference to FIG.

  The semiconductor device LSI is a high-function SOC for mobile phones and digital home appliances, for example, and includes a central processing unit CPU1, a central processing unit CPU2, a specific function circuit block IP1, a specific function circuit block IP2, and a standby mode setting circuit RS_CTL. . The specific functional circuit block is, for example, a functional block that performs image processing and music playback.

  The central processing unit CPU1 has a memory module RAM_MOD1, a leak monitor circuit LEAK_MON1, and a monitor control circuit MON_CTL1. The central processing unit CPU2 includes a memory module RAM_MOD2, a leak monitor circuit LEAK_MON2, and a monitor control circuit MON_CTL2. The specific function circuit block IP1 includes a memory module RAM_MOD3, a leak monitor circuit LEAK_MON3, and a monitor control circuit MON_CTL3. The specific function circuit block IP2 includes a memory module RAM_MOD4, a leak monitor circuit LEAK_MON4, and a monitor control circuit MON_CTL4.

  The central processing unit CPU1 further includes logic circuits (not shown) such as various arithmetic circuits that operate in response to the supply of the power supply voltage vdd1. The central processing unit CPU2, the specific function circuit block IP1, and the specific function circuit block IP2 also have logic circuits (not shown) such as various arithmetic circuits that operate in response to the supply of the power supply voltages vdd2, vdd3, and vdd4. . The semiconductor device LSI including the central processing unit CPU1, the central processing unit CPU2, the specific function circuit block IP1, and the specific function circuit block IP2 is composed of a single semiconductor chip.

  The central processing unit CPU1, the central processing unit CPU2, the specific function circuit block IP1, and the specific function circuit block IP2 are supplied with the power supply voltage vdd1, the power supply voltage vdd2, the power supply voltage vdd3, and the power supply voltage vdd4, respectively. The power supply voltages vdd1, vdd2, vdd3, and vdd4 are supplied from a regulator circuit REG_POWER provided separately from the semiconductor device LSI.

  The standby mode setting circuit RS_CTL outputs a control signal rsj and a control signal ram_rs_cntj for setting the operation mode of each memory module RAM_MODj (j = 1, 2, 3, 4). Further, the standby mode setting circuit RS_CTL outputs a monitor enable signal mon_enj that activates the monitor control circuit MON_CTLj, and receives the monitor signal result_monj output from the leak monitor circuit LEAK_MONj. Each memory module RAM_MODj is configured by an SRAM. Unless otherwise specified, the same symbol is used for the signal name and its signal wiring. The same applies to the name of the power supply wiring and its power supply voltage. The transistor means a MOS (Metal-Oxide-Semiconductor) type transistor.

  The standby mode setting circuit RS_CTL outputs each control signal vddj_cnt to the regulator circuit REG_POWER based on the monitor signal result_monj. The regulator circuit REG_POWER controls the power supply voltage vddj based on the control signal vddj_cnt. For example, the value of the power supply voltage vdd1 supplied to the central processing unit CPU1 is controlled based on the control signal vdd1_cnt.

A specific configuration of the semiconductor device LSI according to the first embodiment will be described with reference to FIG.
The memory module RAM_MODj includes a memory cell array CELL_ARRAY, a peripheral circuit PERI, and a cell power supply voltage control circuit ARVSS_CTL1. The peripheral circuit PERI has a row decoder, a word driver, a column decoder, a column selection switch, a sense amplifier, a write driver, and other control circuits necessary for writing and reading data to and from the memory cell array CELL_ARRAY. A power supply voltage vddj is applied to the memory cell array CELL_ARRAY and the peripheral circuit PERI.

  The cell power supply voltage control circuit ARVSS_CTL1 is connected to the power supply wiring vss and the cell power supply wiring arvssc, and controls the voltage value of the cell power supply wiring arvssc in response to the control signal nstb_mode. The power supply wiring Icvss that supplies the power supply voltage to the peripheral circuit PERI is connected to the power supply wiring vss via the n-type transistor NSW_PERI. A signal obtained by inverting the logic level of the control signal rsj by the inverter INV is applied to the gate of the n-type transistor NSW_PERI.

  The OR circuit OR outputs an OR processing signal between the output of the inverter INV and the control signal ram_rs_cntj as the control signal nstb_mode. When the control signal rsj is at the low level, the control signal nstb_mode is set to the high level regardless of the logic level of the control signal ram_rs_cntj. When the control signal rsj is at a high level, the control signal nstb_mode logic level is in phase with the logic level of the control signal ram_rs_cntj.

  The control signal rsj is output from the standby mode setting circuit RS_CTL, and sets the memory module RAM_MODj to either the normal operation mode or the standby mode. As a result, the supply of the power supply voltage vss to the peripheral circuit PERI is controlled by the control signal rsj, and the voltage of the cell power supply wiring arvssc that supplies the power supply voltage to the memory cell array CELL_ARRAY is controlled by the control signal rsj and the control signal ram_rs_cntj. A power supply voltage vddj is supplied to the peripheral circuit PERI and the memory cell array CELL_ARRAY. The memory cell array CELL_ARRAY is connected to the cell power supply wiring vssbc to which the power supply voltage vss is applied.

  As will be described later, the leak monitor circuit LEAK_MONj has a monitor cell array ARY1 and a monitor cell array ARY2 set in different standby modes. Based on the control signal output from the monitor control circuit MON_CTLj in response to the monitor enable signal mon_enj, the leak monitor circuit LEAK_MONj uses the comparison result of the leak current values of the monitor cell arrays ARY1 and ARY2 as the monitor signal result_monj, and the standby mode setting circuit Output to RS_CTL.

  The standby mode setting circuit RS_CTL outputs a control signal ram_rs_cntj to the memory module RAM_MODj based on the monitor signal result_monj, and controls the voltages of the power supply wiring lcvss and the cell power supply wiring arvssc. Further, based on the control signal vddj_cnt output from the standby mode setting circuit RS_CTL, the regulator circuit REG_POWER controls the power supply voltage vddj supplied to the semiconductor device LSI.

  A configuration of the memory cell array CELL_ARRAY included in the semiconductor device LSI according to the first embodiment will be described with reference to FIG.

  In the following description, the configuration of the memory cell array CELL_ARRAY included in the central processing unit CPU1 (j = 1 in FIG. 2) is shown as an example. Other configurations (j = 2 to 4 in FIG. 2) also have similar configurations in which the number of memory cells is appropriately set.

  The memory cell array CELL_ARRAY includes n pieces in the direction of the word line wl [p] (p = 0 to m−1) and m pieces in the direction of the bit line pair bt [q] / bb [q] (q = 0 to n−1). It has SRAM type memory cells MC arranged in an array. The back gate node vddb and the power supply node arvdd of each memory cell MC are connected to the power supply wiring vdd1. The back gate node vssb and the power supply node arvss of each memory cell MC are connected to the cell power supply line vssbc and the cell power supply line arvssc, respectively. In each memory cell MC, word line node wl is connected to word line wl [p], and bit line node bt and bit line node bb are connected to bit line bt and bit line bb, respectively.

  A circuit diagram of the memory cell MC provided in the semiconductor device LSI according to the first embodiment will be described with reference to FIG.

  The memory cell MC has a data holding circuit DH including a p-type transistor PU_L, a p-type transistor PU_R, an n-type transistor PD_L, and an n-type transistor PD_R. The drains of p-type transistor PU_L and n-type transistor PD_L are connected to data node Nd_R, and the gates of p-type transistor PU_R and n-type transistor PD_R are connected to data node Nd_L. Each drain of p-type transistor PU_R and n-type transistor PD_R is connected to data node Nd_R, and each drain of p-type transistor PU_L and n-type transistor PD_L is connected to data node Nd_L.

  Each source of p-type transistors PU_L and PU_R is connected to power supply node arvdd, and the back gates of both transistors are connected to back gate node vdb. The sources of n-type transistor PD_L and n-type transistor PD_R are connected to power supply node arvss, and the back gates of both transistors are connected to back gate node vssb.

  The data holding circuit DH is a latch circuit including an inverter composed of a p-type transistor PU_L and an n-type transistor PD_L and an inverter composed of a p-type transistor PU_R and an n-type transistor PD_R. By lowering the voltage of the power supply node arvdd with respect to the voltage of the back gate node vddb, it becomes possible to apply a back bias to a pair of p-type transistors including the p-type transistors PU_L and PU_R. Similarly, by raising the voltage of the power supply node arvss with respect to the voltage of the back gate node vssb, it becomes possible to apply a back bias to a pair of n-type transistors including the n-type transistors PD_L and PD_R.

  The memory cell MC further includes an n-type transistor PG_L having one of the source / drain connected to the data node Nd_L of the data holding circuit DH and the other of the source / drain connected to the bit line node bt, and the data holding circuit DH One source / drain is connected to the data node Nd_R, and an n-type transistor PG_R is connected to the bit line node bb. Each gate of n-type transistor PG_L and n-type transistor PG_R is connected to word line node wl, and the back gates of both transistors are connected to back gate node vssb. Note that the source and drain of the n-type transistor PG_L and the n-type transistor PG_R change depending on the magnitude of the applied voltage, and hence will be referred to as source / drain.

  With reference to FIG. 33, the leakage current characteristic of the MOS transistor newly found by the present inventors will be described.

  FIG. 33 is a graph for explaining the characteristics of the subthreshold leakage current and the substrate leakage of the MOS transistor newly found by the inventors of the present application when designing the most advanced manufacturing process. The horizontal axis represents the temperature of the semiconductor substrate on which the MOS transistor is formed, and the vertical axis represents the leak current value generated in the MOS transistor, which is an arbitrary scale.

  The graph LK1 shows the characteristics of the subthreshold leakage current when the threshold voltage of the MOS transistor is higher than the threshold voltage assumed in the manufacturing process design (high Vth). The graph LK2 shows the characteristics of the subthreshold leakage current when the threshold voltage of the MOS transistor is lower than the threshold voltage assumed in the manufacturing process design (low Vth). A graph LK3 shows the characteristics of the substrate leakage current flowing from the drain to the semiconductor substrate.

  The subthreshold leakage current increases exponentially as the temperature rises, while the temperature dependence of the substrate leakage current is hardly seen. On the other hand, with respect to threshold voltage fluctuations due to manufacturing process variations, the subthreshold leakage current increases as the threshold voltage decreases, while the substrate leakage current hardly changes. For this reason, it has been found that as the temperature rises, the sub-threshold leakage current becomes dominant in the leakage current of the MOS transistor from the substrate leakage current. In the case of a low Vth MOS transistor and a high Vth MOS transistor, the dominant leakage currents alternate at temperatures temp1 and temp, respectively.

  Although the subthreshold leakage current of the n-type MOS transistor can be effectively reduced by applying a back bias that raises the source voltage with respect to the back gate voltage, there is no effect in reducing the substrate leakage current. On the other hand, the substrate leakage current can be reduced by lowering the drain voltage of the MOS transistor. Therefore, if the subthreshold leakage current of the MOS transistor is larger than the substrate leakage current, a back bias is applied, and if the substrate leakage current is larger than the subthreshold leakage current, reducing the drain voltage is effective in reducing the leakage current of the MOS transistor. Is. That is, it is necessary to compare the subthreshold leakage current and the substrate leakage current and apply a back bias or reduce the drain voltage based on the comparison result.

  With reference to FIG. 5, a specific circuit of the cell power supply voltage control circuit ARVSS_CTL1 provided in the semiconductor device LSI according to the first embodiment will be described.

  FIG. 5A is a circuit diagram of a cell power supply voltage control circuit ARVSS_CTL1A which is a first specific example of the cell power supply voltage control circuit ARVSS_CTL1. The node Ncn1a is connected to the drains of the n-type transistor NSW_ARY, the n-type transistor NDIOD, and the n-type transistor NRESI, and the node Ncn2a is connected to the sources of these transistors. The n-type transistor NSW_ARY operates as a power switch whose conduction state is controlled based on the logic level of the control signal nstb_mode applied to its gate. N-type transistor NDIOD operates as a MOS diode whose gate and drain are both connected to node Ncn1a. The n-type transistor NRESI operates as a resistor having a predetermined impedance when a power supply voltage vddm set to a predetermined voltage value is applied to its gate.

  When the control signal nstb_mode is at a high level, the n-type transistor NSW_ARY is in a conductive state (a state where the power switch is closed), and the node Ncn1a and the node Ncn2a have the same voltage. That is, the power supply voltage vss is applied to the cell power supply wiring arvssc. When the control signal nstb_mode is at a low level, the n-type transistor NSW_ARY is in a non-conducting state (a state where the power switch is opened), and the voltage of the cell power supply wiring arvssc rises from the power supply voltage vss. The increased voltage is determined by the current flowing through the cell power supply line arvssc, the diode-connected n-type transistor NDIOD, and the n-type transistor NRESI operating as a resistor. Note that the n-type transistor NRESI may be omitted as necessary.

  FIG. 5B is a circuit diagram of a cell power supply voltage control circuit ARVSS_CTL1B which is a second specific example of the cell power supply voltage control circuit ARVSS_CTL1. Node Ncn1b is connected to the drains of n-type transistor NSWD and n-type transistor NRESI, and node Ncn2b is connected to the sources of these transistors. The n-type transistor NRESI operates as a resistor when the power supply voltage vddm is applied to its gate. The drain and source of the n-type transistor NDG are connected between the drain and gate of the n-type transistor NSWD, respectively, and the conduction state is controlled by the control signal nstb_mode. A power supply voltage vddm is applied to the source of the p-type transistor PD, and its drain is connected to the gate of the n-type transistor NSWD. The control signal nstb_mode is connected to the gate of the p-type transistor PD.

  When the control signal nstb_mode is at a low level, the n-type transistor NDG is turned off and the p-type transistor PD is turned on. As a result, the n-type transistor NSWD becomes conductive, and the power supply voltage vss is applied to the cell power supply wiring arvssc. When the control signal nstb_mode is at a high level, the p-type transistor PD is in a non-conductive state, but the n-type transistor NDG is in a conductive state, and the voltage of the cell power supply wiring arvssc rises from the power supply voltage vss. The increased voltage is determined by the current flowing through the cell power supply line arvssc, the diode-connected n-type transistor NSWD, and the n-type transistor NRESI operating as a resistor. Note that the n-type transistor NRESI may be omitted as necessary.

  With reference to FIG. 6, an operation mode of the memory module RAM_MOD1 included in the semiconductor device LSI according to the first embodiment will be described.

  The operation mode of the memory module RAM_MOD1 is set by a control signal rs1 and a control signal ram_rs_cnt1 (both correspond to j = 1 in FIG. 2) output from the standby mode setting circuit RS_CTL. When the control signal rs1 is set to low level (Low), the memory module RAM_MOD1 is set to the normal operation mode regardless of the value of the control signal ram_rs_cnt1. The power supply voltage vdd1 set to the power supply voltage vdd1norm and the power supply voltage vss are applied to the memory module RAM_MOD1 set to the normal operation mode.

  The power supply voltage vdd1norm and the voltage set for the power supply wiring lcvss are applied to the peripheral circuit PERI included in the memory module RAM_MOD1. Since the n-type transistor NSW_PERI is turned on by the control signal rs1, the voltage of the power supply wiring lcvss becomes the same voltage as the power supply voltage vss. A power supply voltage vdd1norm and a voltage controlled by the cell power supply voltage control circuit ARVSS_CTL1 are applied to the memory cell array CELL_ARRAY through the cell power supply wiring arvssc.

  A relationship between the cell power supply voltage control circuit ARVSS_CTL1 and the control signal ram_rs_cnt1 illustrated in FIG. 2 will be described. When the cell power supply voltage control circuit ARVSS_CTL1 is the cell power supply voltage control circuit ARVSS_CTL1A shown in FIG. 5A, the voltage between the node Ncn1a and the node Ncn2a is determined by the control signal nstb_mode. When the control signal rs1 is at the low level, the control signal nstb_mode is set to the high level regardless of the logic level of the control signal ram_rs_cnt1. As a result, the voltage at the node Ncn1a is the same as the power supply voltage vss, which is the voltage at the node Ncn2a. When the control signal rs1 is at a high level, the voltage of the node Ncn1a is controlled by the control signal ram_rs_cnt1.

  When the cell power supply voltage control circuit ARVSS_CTL1 is the cell power supply voltage control circuit ARVSS_CTL1B shown in FIG. 5B, the OR circuit OR that generates the control signal nstb_mode in FIG. 2 is replaced with a NOR circuit, thereby the cell power supply voltage control circuit ARVSS_CTL1B. And the control signal ram_rs_cnt1 are the same as the relationship between the cell power supply voltage control circuit ARVSS_CTL1A and the control signal ram_rs_cnt1.

  A voltage applied to each node (see FIGS. 3 and 4) of memory cell MC in the normal operation mode will be described. A power supply voltage vdd1norm set as a value of the power supply voltage vdd1 in the normal operation mode is applied to the power supply node arvdd and the back gate node vddb. The power supply voltage vdd1norm is, for example, 1.0V. A power supply voltage vss is applied to the power supply node arvss and the back gate node vssb. As a result, no back bias is applied to the pair of p-type transistors (PU_L, PU_R) and the pair of n-type transistors (PD_L, PD_R).

  The memory module RAM_MOD1 is set to the standby mode when the control signal rs1 is set to a high level. The memory module RAM_MOD1 set to the standby mode is further set to one of the two standby modes by the control signal ram_rs_cnt1. Each standby mode includes a standby mode 1 (hereinafter referred to as RS mode) when the control signal ram_rs_cnt1 is set to low level (Low), and a standby mode 2 (hereinafter referred to as LVRS) when set to high level (High). Mode, and description.).

  The power supply wiring lcvss for supplying the power supply voltage to the peripheral circuit PERI is in a floating state in which the power supply voltage vss is not applied in both the RS mode and the LVRS mode because the n-type transistor NSW_PERI is set in a non-conductive state by the control signal rs1. Generally, the power supply voltage rises to vdd1). The memory cell array CELL_ARRAY is supplied with the power supply voltage vdd1 and the voltage controlled by the cell power supply voltage control circuit ARVSS_CTL1 through the cell power supply wiring arvssc.

  A voltage applied to each node (see FIGS. 3 and 4) of the memory cell MC in the RS mode will be described. A power supply voltage vdd1norm set as a value of the power supply voltage vdd1 in the RS mode is applied to the power supply node arvdd and the back gate node vddb. As a result, in the pair of p-type transistors (PU_L / PU_R) included in the data holding circuit DH, the source and back gate are at the same voltage (power supply voltage vdd1norm), and no back bias is applied to both p-type transistors. Set to

  A voltage controlled by the cell power supply voltage control circuit ARVSS_CTL1 is applied to the power supply node arvss. In the RS mode, since the control signal ram_rs_cnt1 is set to a low level (the control signal nstb_mode is low level), the voltage of the cell power supply wiring arvssc becomes a value (vss + Δvss) obtained by adding a predetermined bias voltage Δvss to the power supply voltage vss. As a result, in the pair of n-type transistors (PD_L / PD_R) included in the data holding circuit DH, the source and back gate voltages are set to vss + Δvss and vss, respectively. A state in which a back bias of Δvss is applied is set. For example, the bias voltage Δvss is set to 0.2V.

  A voltage applied to each node of the memory cell MC in the LVRS mode will be described. A voltage set as the power supply voltage vdd1 in the LVRS mode, that is, a voltage (vdd1norm−Δvdd) obtained by lowering the power supply voltage vdd1norm by a predetermined bias voltage Δvdd is applied to the power supply node arvdd and the back gate node vddb. As a result, in the pair of p-type transistors included in the data holding circuit DH, the source and the back gate have the same voltage (vdd1norm−Δvdd), and both the p-type transistors are set to a state in which no back bias is applied. The bias voltage Δvdd is set to 0.2 V, for example.

  A voltage controlled by the cell power supply voltage control circuit ARVSS_CTL1 is applied to the power supply node arvss. In the LVRS mode, the control signal ram_rs_cnt1 is set to a high level (the control signal nstb_mode is at a high level), so that the voltage of the cell power supply wiring arvssc is the same as the power supply voltage vss. As a result, in the pair of n-type transistors included in the data holding circuit DH, the source and the back gate are set to the same voltage (vss), and the back bias is not applied.

  With reference to FIG. 4 and FIG. 6, the relationship between the RS mode and the LVRS mode and the leakage current of the memory cell MC will be described. In the following description, it is assumed that the data node Nd_R is set to the high level and the data node Nd_L is set to the low level in the data holding circuit DH of the memory cell MC set to the standby mode. In this case, the n-type transistor PD_R is non-conductive, the p-type transistor PU_R is conductive, the n-type transistor PD_L is conductive, and the p-type transistor PU_L is non-conductive. Further, in the standby mode, the word line node wl is set to the low level, the bit line node bt, and the bit line bb are set to the high level, and the n-type transistor PG_R and the n-type transistor PG_L are both non-conductive.

  In the RS mode, the source of the pair of n-type transistors (PD_L / PD_R) included in the data holding circuit DH is set to a voltage obtained by adding the bias voltage Δvss to the power supply voltage vss, and the back gate is set to the power supply voltage vss. A back bias having a bias voltage Δvss is applied to the n-type transistor. As a result, in the non-conducting n-type transistor PD_R, the threshold voltage increases and the subthreshold leakage current decreases.

  On the other hand, when the source voltage of the n-type transistor PD_L in the conductive state rises, the voltage of the data node Nd_L similarly rises. As a result, in the n-type transistor PG_L in the non-conductive state, the source voltage (source / drain voltage connected to the data node Nd_L) also increases the bias voltage Δvss, and the subthreshold leakage current decreases.

  In the LVRS mode, the source and back gate of the pair of p-type transistors (PU_L / PU_R) included in the data holding circuit DH are both set to a voltage obtained by lowering the power supply voltage vdd1norm by the bias voltage Δvdd. When the source voltage of the p-type transistor PU_R in the conducting state is lowered, the voltage of the data node Nd_R is similarly lowered. As a result, in the non-conducting n-type transistor PD_R, the drain voltage also decreases by the bias voltage Δvss, and the substrate leakage current decreases. Furthermore, since the power supply voltage vdd1 drops from the power supply voltage vdd1norm by the bias voltage Δvdd, the bit line node bt to which the power supply voltage vdd1 is applied and the n-type transistor PG_L to which the source / drain is connected and the power supply voltage vdd1 are applied. The substrate leakage current in the n-type transistor PG_R to which the bit line node bb and the source / drain are connected is also reduced. That is, by setting the memory cell MC to the RS mode and the LVRS mode, it is possible to reduce the leak current of the n-type transistor included in the memory cell MC.

  With reference to FIG. 7, the configuration of leak monitor circuit LEAK_MON1A provided in semiconductor device LSI according to the first embodiment will be described.

  The leak monitor circuit LEAK_MON1A includes a monitor cell array ARY1, a monitor cell array ARY2, a monitor voltage supply circuit ARVDD_SPLYA, a comparator COMP, and an array VSS generation circuit ARVSS_GEN1.

  The monitor cell array ARY1 includes a predetermined number of memory cells MC. Power supply node arvdd, back gate node vddb, bit line node bt, and bit line node bb of each memory cell MC are connected to cell power supply line arvdd1. The power supply node arvss of each memory cell MC is connected to the cell power supply line arvss1, and a predetermined voltage output from the array VSS generation circuit ARVSS_GEN1 is applied to the cell power supply line arvss1.

  The array VSS generation circuit ARVSS_GEN1 generates the bias voltage Δvss shown in FIG. 6, and applies a voltage obtained by adding the bias voltage Δvss to the power supply voltage vss to the cell power supply line arvss1. The back gate node vssb of each memory cell MC is connected to the cell power supply wiring vssb1, and the power supply voltage vss is applied.

  The monitor cell array ARY2 includes the same number of memory cells MC as the memory cells MC included in the monitor cell array ARY1. The power supply node arvdd, back gate node vddb, bit line node bt, and bit line node bb of each memory cell MC are connected to the cell power supply line arvdd2. The back gate node vssb of each memory cell MC is connected to the cell power supply wiring vssb2, and the power supply voltage vss is applied. The power supply node arvss of each memory cell MC is connected to the cell power supply wiring arvss2, and the power supply voltage vss is applied to the cell power supply wiring arvss2.

  A back bias is applied to the n-type transistor (PD_L / PD_R) of the data holding circuit DH included in the memory cell MC included in the monitor cell array ARY1 by the output voltage of the array VSS generation circuit ARVSS_GEN1. On the other hand, no back bias is applied to the n-type transistor of the data holding circuit DH included in the monitor cell array ARY2.

  The monitor voltage supply circuit ARVDD_SPLYA includes an amplifier AMP1. A reference voltage ref1 is applied to the inverting input terminal of the amplifier AMP1, and its normal input terminal is connected to the node Na11. The output of the amplifier AMP1 is connected to the gate of the p-type transistor ARVDD_PWS1. A power supply voltage vddm is applied to the source of the p-type transistor ARVDD_PWS1, and its drain is connected to the node Na11. Accordingly, the node Na11 is set to a voltage equal to the reference voltage ref1, and the reference voltage ref1 is set to vdd1norm that is the value of the power supply voltage vdd1 in the RS mode shown in FIG.

  The monitor voltage supply circuit ARVDD_SPLYA further includes an amplifier AMP2. A reference voltage ref2 is applied to the inverting input terminal of the amplifier AMP2, and its normal input terminal is connected to the node Na12. The output of the amplifier AMP2 is connected to the gate of the p-type transistor ARVDD_PWS2. A power supply voltage vddm is applied to the source of the p-type transistor ARVDD_PWS2, and its drain is connected to the node Na12. Therefore, the node Na12 is set to a voltage equal to the reference voltage ref2, and the reference voltage ref2 is set to vdd1norm−Δvdd which is the value of the power supply voltage vdd1 in the LVRS mode shown in FIG.

  The p-type transistors ARVDD_PWS1 and ARVDD_PWS2 of the monitor voltage supply circuit ARVDD_SPLYA are configured to have the same electrical characteristics. When the gate voltage of each transistor is the same, the same drain current flows. Therefore, the drain current can be increased or decreased by comparing the gate voltages of the transistors. Power supply voltage vddm is set to a power supply voltage necessary for correctly outputting reference voltages ref1 and ref2 to nodes Na11 and Na12 connected to the sources of p-type transistors ARVDD_PWS1 and ARVDD_PWS2, respectively.

  The monitor voltage supply circuit ARVDD_SPLYA outputs the power supply voltage vdd1norm to the cell power supply wiring arvdd1 of the monitor cell array ARY1 connected to the node Na11. At the same time, the monitor voltage supply circuit ARVDD_SPLYA outputs a voltage (vdd1norm−Δvdd) obtained by dropping the power supply voltage vdd1norm by the bias voltage Δvdd to the cell power supply wiring arvdd2 of the monitor cell array ARY2 connected to the node Na12. Further, the monitor voltage supply circuit ARVDD_SPLYA outputs the gate voltages of the p-type transistors ARVDD_PWS1 and ARVDD_PWS2 as the measurement output imageas1 and the measurement output imageas2, respectively.

  In the monitor cell array ARY1 in which the reference voltage ref1 (= vdd1norm) is supplied to the cell power supply wiring arvdd1, a voltage obtained by adding the bias voltage Δvss to the power supply voltage vss is applied to the power supply node arvss of each memory cell MC, and the back gate node vssb. Is supplied with a power supply voltage vss. Accordingly, each memory cell MC of the monitor cell array ARY1 is set to the same state as the RS mode of the memory module RAM_MOD1. At the same time, in the monitor cell array ARY2 to which the reference voltage ref2 (= vdd1norm−Δvdd) is supplied to the cell power supply wiring arvdd2, the power supply voltage vss is applied to the power supply node arvss and the back gate node vssb of each memory cell MC. Accordingly, each memory cell MC of the monitor cell array ARY2 is set to the same state as the LVRS mode of the memory module RAM_MOD1.

  The comparator COMP is a general voltage comparator, which compares the magnitudes of the measurement output imageas1 and the measurement output imageas2, and outputs the comparison result as a monitor signal result_mon1. The measurement output imageas1 is the gate voltage of the p-type transistor ARVDD_PWS1, and the gate voltage changes depending on the drain current. Similarly, the measurement output imageas2 is the gate voltage of the p-type transistor ARVDD_PWS2, and the gate voltage changes depending on the drain current. Each drain current is a leak current of the memory cell MC included in the monitor cell array ARY1 set in the RS mode and a leak current of the memory cell MC included in the monitor cell array ARY2 set in the LVRS mode.

  For example, assume that the voltage of the measurement output imageas1 is lower than the voltage of the measurement output imageas2, that is, the gate voltage of the p-type transistor ARVDD_PWS1 is lower than the gate voltage of the p-type transistor ARVDD_PWS2. In this case, the leak current flowing through the monitor cell array ARY1 is larger than the leak current flowing through the monitor cell array ARY2. Therefore, the leakage current can be reduced by setting the memory module RAM_MOD1 to the LVRS mode instead of the RS mode.

  A method of setting the memory module RAM_MOD1 to the RS mode and the LVRS mode by the regulator circuit REG_POWER and the standby mode setting circuit RS_CTL based on the monitor signal result_mon will be described with reference to FIG. 2, FIG. 4, and FIG.

  In the RS mode, each node of the memory cell MC shown in FIG. 4 is set as follows. That is, the power supply node arvss is set to a voltage obtained by adding the bias voltage Δvss to the power supply voltage vss, the back gate node vssb is set to the power supply voltage vss, and the power supply node arvdd and the back gate node vddb are set to the power supply voltage vdd1norm. When the memory module RAM_MOD1 is set to the RS mode based on the monitor signal result_mon, the standby mode setting circuit RS_CTL outputs the control signal vdd1_cnt to the regulator circuit REG_POWER and sets the power supply voltage vdd1 to the power supply voltage vdd1norm.

  Further, the standby mode setting circuit RS_CTL outputs the control signal nstb_mode set to the low level to the cell power supply voltage control circuit ARVSS_CTL1 based on the control signal rs1 and the control signal ram_rs_cnt1. When the cell power supply voltage control circuit ARVSS_CTL1 is the cell power supply voltage control circuit ARVSS_CTL1A shown in FIG. 5A, the voltage of the node Ncn1a increases with respect to the voltage of the node Ncn2a (power supply voltage vss). As a result, the voltage of the cell power supply wiring arvssc connected to the node Ncn1a, that is, the voltage of the power supply node arvss of the memory cell MC is set to a value obtained by increasing the power supply voltage vss by the bias voltage Δvss. On the other hand, the voltage of the back gate node vssb of the memory cell MC connected to the cell power supply wiring vssbc is set to the power supply voltage vss.

  In the LVRS mode, each node of the memory cell MC shown in FIG. 4 is set as follows. That is, the power supply node arvdd and the back gate node vddb are set to voltages obtained by lowering the power supply voltage vdd1norm by the bias voltage Δvdd, and the power supply node arvss and the back gate node vssb are set to the power supply voltage vss. When the memory module RAM_MOD1 is set to the LVRS mode based on the monitor signal result_mon, the standby mode setting circuit RS_CTL outputs the control signal vdd1_cnt to the regulator circuit REG_POWER so that the power supply voltage vdd1 is lowered to the bias voltage Δvss from the power supply voltage vdd1norm. Set.

  Further, the standby mode setting circuit RS_CTL outputs the control signal nstb_mode set to the high level to the cell power supply voltage control circuit ARVSS_CTL1A based on the control signal rs1 and the control signal ram_rs_cnt1, and the voltage of the node Ncn2a becomes the same voltage as the power supply voltage vss. Is set. As a result, the voltages of the power supply node arvss and the back gate node vssb are set to the power supply voltage vss.

  As described above, based on the monitor signal result_mon1, the regulator circuit REG_POWER and the standby mode setting circuit RS_CTL selectively set the memory module RAM_MOD1 to the RS mode or the LVRS mode. In the case where the cell power supply voltage control circuit ARVSS_CTL1 is the cell power supply voltage control circuit ARVSS_CTL1B shown in FIG. 5B, the OR circuit OR that generates the control signal nstb_mode in FIG. Is controlled in the same manner as described above.

The effect of the leak monitor circuit LEAK_MON1A according to the first embodiment will be described.
Of the leakage current components of the memory cell MC, the effective reduction method differs between the subthreshold leakage current and the substrate leakage current. In order to reduce the subthreshold leakage current, it is effective to apply a back bias to the n-type transistor constituting the memory cell MC. Further, in order to reduce the substrate leakage current, it is effective to reduce the drain voltage of the n-type transistor constituting the memory cell MC. The leak monitor circuit LEAK_MON1A includes a monitor cell array ARY1 in which the transistors constituting the memory cell MC are set in the RS mode and a monitor cell array ARY2 in which the transistor is set in the LVRS mode. It is possible to select a suitable leak reduction method, and to minimize the leak current in the memory module RAM_MOD1.

  With reference to FIG. 8, the configuration of leak monitor circuit LEAK_MON1B provided in the semiconductor device LSI according to Modification 1 of Embodiment 1 will be described.

  The leak monitor circuit LEAK_MON1B includes a monitor cell array ARY1, a monitor cell array ARY2, a monitor voltage supply circuit ARVDD_SPLYB, a comparator COMP, and an array VSS generation circuit ARVSS_GEN1.

  The functions of the array VSS generation circuit ARVSS_GEN1 are the same as those shown in FIG. Further, the configuration of the monitor cell array ARY1 and the power supply voltage applied to the power supply node arvdd of each memory cell MC are the same as the monitor cell array ARY1 in FIG.

  The monitor voltage supply circuit ARVDD_SPLYB is configured by the amplifier AMP1 by omitting the amplifier AMP2 of the monitor voltage supply circuit ARVDD_SPLYA. The power supply voltage vddm is applied to the sources of the p-type transistor ARVDD_PWS1 and the p-type transistor ARVDD_PWS2, and the output of the amplifier AMP1 is applied to each gate. The reference voltage ref1 is applied to the inverting input terminal of the amplifier AMP1, and the node Na21 connected to the drain of the p-type transistor ARVDD_PWS1 is connected to the normal input terminal. The drain of p-type transistor ARVDD_PWS2 is connected to node Na22. The reference voltage ref1 is set to the power supply voltage vdd1norm.

  The monitor voltage supply circuit ARVDD_SPLYB outputs the power supply voltage vdd1norm from the node Na21 and the node Na22 to the cell power supply wiring arvdd1 of the monitor cell array ARY1 and the cell power supply wiring arvdd2 of the monitor cell array ARY2. Further, the monitor voltage supply circuit ARVDD_SPLYB outputs the drain voltages of the p-type transistor ARVDD_PWS1 and the p-type transistor ARVDD_PWS2 as the measurement output imageas1 and the measurement output imageas2, respectively.

  In the monitor cell array ARY1, the reference voltage ref1 (= vdd1norm) is applied to the cell power supply line arvdd1. A voltage obtained by adding the bias voltage Δvss to the power supply voltage vss is applied to the power supply node arvss of each memory cell MC, and the power supply voltage vss is applied to the back gate node vssb. Accordingly, each memory cell MC of the monitor cell array ARY1 is set to the same state as the RS mode of the memory module RAM_MOD1.

  In the monitor cell array ARY2, the power supply node arvdd, the back gate node vddb, the bit line node bt, and the bit line node bb of the memory cell MC are connected to the cell power supply line arvdd2, and the power supply voltage vdd1norm of the node Na22 is applied. The power supply node arvss and the back gate node vssb of each memory cell MC are connected to the cell power supply line arvss2 and the cell power supply line vssb2, respectively. A voltage obtained by adding the bias voltage Δvss to the power supply voltage vss output from the array VSS generation circuit ARVSS_GEN1 is applied to the cell power supply wiring arvss2 and the cell power supply wiring vssb2.

  In the monitor cell array ARY2, the reference voltage vref1 is applied to the cell power supply line arvdd2. A voltage obtained by adding a bias voltage Δvss to the power supply voltage vss is applied to the power supply node arvss, the back gate node vssb, and the word line node wl of each memory cell MC. As a result, no back bias is applied to the n-type transistor of each memory cell MC in the monitor cell array ARY2, and the power supply voltage between the power supply node arvdd and the power supply node arvss of the data holding circuit DH becomes vdd1norm−bias voltage Δvss. Therefore, each memory cell MC of the monitor cell array ARY2 reproduces the same state as the LVRS mode of the memory module RAM_MOD1. A power supply that generates the reference voltage ref2 for the cell power supply wiring rvdd2 in FIG. 7 by setting the monitor cell array ARY2 to the LVRS mode in the state where the voltage of the cell power supply wiring arvdd2 and the voltage of the cell power supply wiring arvdd1 are set to be the same. The circuit and the operational amplifier for controlling the voltage of the cell power supply wiring arvdd2 become unnecessary, and the area and power can be reduced.

  The comparator COMP compares the magnitudes of the measurement output imageas1 and the measurement output imageas2, and outputs the comparison result as a monitor signal result_mon1. The measurement output imageas1 is the drain voltage of the p-type transistor ARVDD_PWS1, and the drain voltage changes depending on the drain current. Similarly, the measurement output imageas2 is the drain voltage of the p-type transistor ARVDD_PWS2, and the drain voltage changes depending on the drain current. Each drain current is a leak current of the memory cell MC included in the monitor cell array ARY1 set in the RS mode and a leak current of the memory cell MC included in the monitor cell array ARY2 set in the LVRS mode.

  For example, assume that the voltage of the measurement output imageas2 is lower than the voltage of the measurement output imageas1, that is, the drain voltage of the p-type transistor ARVDD_PWS2 is lower than the drain voltage of the p-type transistor ARVDD_PWS1. In this case, the leak current of the monitor cell array ARY2 is larger than the leak current of the monitor cell array ARY1. Therefore, the leak current can be reduced by setting the memory module RAM_MOD1 to the RS mode instead of the LVRS mode.

  The effect of the leak monitor circuit LEAK_MON1B according to the first modification of the first embodiment will be described.

  The leak monitor circuit LEAK_MON1B includes a monitor cell array ARY1 in which the transistors constituting the memory cell MC are set in the RS mode and a monitor cell array ARY2 in which the transistor is set in the LVRS mode, thereby comparing the leak currents in the standby mode 1 and the standby mode 2. And the leakage current in the memory module RAM_MOD1 can be minimized. Furthermore, by reducing the amplifier AMP2 and the generation circuit of the reference voltage ref2, it is possible to reduce the area and power consumption of the semiconductor device LSI as compared with the leak monitor circuit LEAK_MON1A according to the first embodiment.

  The amount of change in the drain voltage with respect to the change in the drain current of the p-type transistor ARVDD_PWS1 and the p-type transistor ARVDD_PWS2 is larger than the amount of change in the gate voltage. Therefore, the leak current can be measured with higher accuracy with respect to the leak monitor circuit LEAK_MON1A according to the modification of the first embodiment. Further, by reducing the measurement accuracy of the comparator COMP, it is possible to reduce the area and current consumption of the leak monitor circuit LEAK_MON1B.

  With reference to FIG. 9, the configuration of leak monitor circuit LEAK_MON1C provided in the semiconductor device LSI according to the second modification of the first embodiment will be described.

  The leak monitor circuit LEAK_MON1C includes a monitor cell array ARY1, a monitor cell array ARY2, a monitor voltage supply circuit ARVDD_SPLYC, a comparator COMP, and an array VSS generation circuit ARVSS_GEN1. The configurations of the monitor cell array ARY1, the monitor cell array ARY2, and the array VSS generation circuit ARVSS_GEN1 are the same as those given the same reference numerals in FIG. 8, and description thereof is omitted.

  The monitor voltage supply circuit ARVDD_SPLYC has a configuration in which the amplifier AMP1 of the monitor voltage supply circuit ARVDD_SPLYB is omitted and the conduction state of the p-type transistor ARVDD_PWS1 and the p-type transistor ARVDD_PWS2 is controlled by the control signal arvdd_en. The control signal arvdd_en is applied to the gates of the p-type transistor ARVDD_PWS1 and the p-type transistor ARVDD_PWS2, and the power supply voltage vdd1norm is applied to the source thereof. The drains of the p-type transistor ARVDD_PWS1 and the p-type transistor ARVDD_PWS2 are connected to the node Na31 and the node Na32, respectively, and supply the power supply voltage vdd1norm to the cell power supply wiring arvdd1 of the monitor cell array ARY1 and the cell power supply wiring arvdd2 of the monitor cell array ARY2. .

  Unlike the leak monitor circuit LEAK_MON1A of the first embodiment and the leak monitor circuit LEAK_MON1B of the first modification of the first embodiment, the monitor voltage supply circuit ARVDD_SPLYC is only in the period when the control signal arvdd_en is at the low level, and the monitor cell array ARY1 The power supply voltage vdd1norm is supplied to the cell array ARY2. When the control signal arvdd_en changes from the low level to the high level, the supply of the power supply voltage vdd1norm to the node Na31 and the node Na32 is cut off. Thereafter, the voltage at the node Na31 and the node Na32 decreases from the power supply voltage vdd1norm with the passage of time due to the leakage current of the memory cells in the monitor cell array ARY1 and the monitor cell array ARY2.

  The monitor voltage supply circuit ARVDD_SPLYC outputs the voltages of the node Na31 and the node Na32 to the comparator COMP as the measurement output imageas1 and the measurement output imageas2. A monitor cell array ARY1 set in the RS mode and a monitor cell array ARY2 set in the LVRS mode are connected to the node Na31 and the node Na32, respectively. In the monitor cell array ARY2, a voltage higher than the power supply voltage VSS by the bias voltage ΔVSS is applied to the node to which the power supply voltage VSS is set when the memory cell module RAM_MOD1 that is to be set in the standby mode is set in the LVRS mode, as in FIG. Has been.

  As a result, the standby state of the RS mode and the LVRS mode can be respectively reproduced in a state where the voltage of the cell power supply line arvdd1 and the voltage of the cell power supply line arvdd2 are the same. Since the voltages of the cell power supply line arvdd1 and the cell power supply line arvdd2 are the same, the magnitude of the voltage at both nodes after the supply of the power supply voltage vdd1norm to the nodes Na31 and Na32 corresponds to the magnitude of the leakage current. Therefore, by comparing the voltages at both nodes with the comparator COMP, it is possible to compare the leakage current of the monitor cell array ARY1 and the leakage current of the monitor cell array ARY2.

  The effect of the leak monitor circuit LEAK_MON1C according to the second modification of the first embodiment will be described.

  Leak monitor circuit LEAK_MON1C reduces leak amplifier circuit LEAK_MON1A according to the first embodiment and leak monitor circuit LEAK_MON1B according to the first modification of the first embodiment by reducing the amplifier and the reference voltage generation circuit applied to its input terminal. Thus, the area and power consumption of the semiconductor device LSI can be reduced.

  With reference to FIG. 10, a circuit of the comparator COMP1 applicable to the semiconductor device LSI according to the first embodiment and the modification thereof will be described.

  The comparator COMP1 includes an amplifier circuit AMP10, an amplifier circuit AMP20, and an inverter 11.

  The amplifier circuit AMP10 amplifies the difference between the measurement output imageas1 applied to the input terminal comp_in1 and the measurement output imageas2 applied to the input terminal comp_in2, and outputs an output comp_in1_drv and an output comp_in2_drv. An input terminal comp_in1 and an input terminal comp_in2 are connected to gates of the n-type transistor N11 and the n-type transistor N12, and sources are connected to the node Nac13. The drain and source of n-type transistor N13 are connected to node Nac13 and power supply wiring vss, respectively, and voltage highv is applied to the gate.

  The drains of p-type transistor P11 and p-type transistor P12 are connected to the drains of n-type transistors N11 and N12 at nodes Nac11 and Nac12, respectively. Power source voltage vddm is applied to the sources of p-type transistors P11 and P12, and the gate thereof is connected to node Nac11. An output comp_in1_drv and an output comp_in2_drv of the amplifier circuit AMP10 are output from the nodes Nac11 and Nac12, respectively. The amplifier circuit AMP10 amplifies the difference between the measurement output imageas1 and the measurement output imageas2, and outputs an output comp_in1_drv and an output comp_in2_drv. The magnitudes of the measurement outputs “images1” and “images2” are opposite to the magnitudes of the outputs “comp_in1_drv” and “output comp_in2_drv”.

  The amplifier circuit AMP20 outputs a monitor signal result_mon1 having a binary value from the output terminal comp_out based on the magnitude relationship between the output comp_in1_drv and the output comp_in2_drv of the amplifier circuit AMP10. When the output comp_in1_drv is smaller than the output comp_in2_drv, the monitor signal result_mon1 is at a high level, and when the output comp_in1_drv is greater than the output comp_in2_drv, the monitor signal result_mon1 is at a low level. That is, when the measurement output imageas1 is greater than the measurement output imageas2, the monitor signal result_mon1 is at a high level, and when the measurement output imageas1 is less than the measurement output imageas2, the monitor signal result_mon1 is at a low level.

  The amplifying circuit AMP20 includes an amplifying unit including an n-type transistor COMP_SW, an n-type transistor N23, an n-type transistor N24, a p-type transistor P23, and a p-type transistor P24, and p-type transistors P20, P21, and P22. And a precharge unit. The inputs of the output comp_in1_drv and the output comp_in2_drv to the amplifying unit are controlled by the n-type transistor N21 and the n-type transistor N22. The conduction state of the n-type transistors N21 and N22 is controlled by a signal compb obtained by inverting the control signal comp_en by the inverter INV11. The conduction state of the n-type transistor COMP_SW that activates the amplifying unit is controlled by a control signal comp_en.

  An operation of the comparator COMP1 will be described. Comparator COMP1 includes leak monitor circuit LEAK_MON1A according to Embodiment 1 shown in FIG. 7, leak monitor circuit LEAK_MON1B according to Modification 1 of Embodiment 1 shown in FIG. 8, and a modification of Embodiment 1 shown in FIG. The present invention can be applied to the comparator COMP of the leak monitor circuit LEAK_MON1C according to Example 2. The measurement output imageas1 input to the comparator COMP1 is generated based on the leakage current of the monitor cell array ARY1 set in the RS mode, and the measurement output imageas2 is based on the leakage current of the monitor cell array ARY1 set in the LVRS mode. Generated.

  The comparator COMP1 activated by the control signal comp_en for a predetermined time outputs a monitor signal result_mon1 based on the magnitude relationship between the measurement output images1 and the measurement outputs images2. As shown in FIG. 2, the standby mode setting circuit RS_CTL controls the cell power supply voltage control circuit ARVSS_CTL1 with the control signal ram_rs_cnt1 based on the logic level of the monitor signal result_mon1 to control the voltage of the cell power supply wiring arvss. Further, the standby mode setting circuit RS_CTL controls the regulator circuit REG_POWER with the control signal vdd1_cnt to control the value of the power supply voltage vdd1. Through these series of controls, the memory module RAM_MOD1 is set to either the RS mode or the LVRS mode in which the leakage current is further reduced.

The effect of the comparator COMP1 will be described.
The generation of the monitor signal result_mon1 by the comparator COMP1 is performed when the standby mode setting circuit RS_CTL sets the central processing unit CPU1 that operates in response to the supply of the power supply voltage vdd1 to the standby mode. Even when the central processing unit CPU2 or the like that operates in response to the supply of the power supply voltage vdd2 is set to the standby mode, control for minimizing the leakage current is performed. By this series of controls, even if the leakage current of the memory cell MC fluctuates due to variations in the transistor threshold voltage due to the manufacturing process of the semiconductor device LSI or due to temperature fluctuations of the semiconductor device LSI, the standby mode has a smaller leakage current. Can be set.

  With reference to FIG. 11, a circuit of another comparator COMP2 that can be applied to the semiconductor device LSI according to the first embodiment and the modification thereof will be described.

  The comparator COMP2 includes a ring oscillator ROS1, a ring oscillator ROS2, a counter CNT1, a counter CNT2, and a digital comparison circuit DIG_CMP.

  The ring oscillator ROS1 is activated by the control signal ros_en and outputs an output signal ros_out1 whose oscillation frequency changes based on the measurement output imageas1 applied to the input terminal comp_in1. Ring oscillator ROS1 includes inverter INV31 including p-type transistor P311, n-type transistor N312 and n-type transistor N311 connected in series. A power supply voltage vdd1norm is applied to the source of the p-type transistor P311 and its drain is connected to the drain of the n-type transistor N312. The drain of the n-type transistor N311 is connected to the source of the n-type transistor N312 and the power supply voltage vss is applied to the source. The gates of the p-type transistor P311 and the n-type transistor N312 are connected to the output of the NAND gate G11, and the gate of the n-type transistor N311 is connected to the input terminal comp_in1.

  The p-type transistor P311 and the n-type transistor N312 constitute a switching unit that inverts the logic level of the signal input in common to the gates of both transistors and outputs the inverted signal from the drains of both transistors connected in common. The n-type transistor N311 constitutes a current control unit that controls the current of the measurement switching unit based on the measurement output imageas1.

  The ring oscillator ROS1 is a ring oscillator in which an output of the final stage of the inverter INV31 connected in cascade with a predetermined number of stages is input to the NAND gate G11, and the output is returned to the inverter INV31 of the first stage to form an oscillation loop. The measured output imas1 applied to the gate of the n-type transistor N311 of the inverter INV31 changes the delay time of the inverter INV31, that is, the oscillation frequency of the output signal ros_out1 generated by the ring oscillator ROS1. When the control signal ros_en input to the NAND gate G11 is set to a high level, the ring oscillator ROS1 starts oscillating, and when it is set to a low level, the oscillation is stopped.

  The ring oscillator ROS2 has the same configuration as the ring oscillator ROS1 except for the following points. The gate of the n-type transistor N321 constituting the inverter INV32 is connected to the input terminal comp_in2, and the oscillation frequency of the output signal ros_out2 generated by the ring oscillator ROS2 changes at the measurement output imageas2.

  The counter CNT1 counts the number of oscillations of the output signal ros_out1 generated during a predetermined period, and is reset by a reset signal reset. The counter CNT2 also counts the number of oscillations of the output signal ros_out2 generated during the same predetermined period, and is reset by the reset signal reset.

  When the leak current of the monitor cell array ARY1 set to the RS mode increases, the voltage of the measurement output images1 decreases. When the leakage current of the monitor cell array ARY2 set to the LVRS mode increases, the voltage of the measurement output images2 decreases. Therefore, as the current of the monitor cell array ARY1 increases, the pulse period of the output signal ros_out1 becomes longer and the value (number of oscillations) of the counter CNT1 decreases. Similarly, as the current of the monitor cell array ARY2 increases, the pulse period of the output signal ros_out2 becomes longer, and the value (number of oscillations) of the counter CNT2 decreases.

  After being activated by the control signal dig_comp_en, the digital comparison circuit DIG_CMP compares the values of the counter CNT1 and the counter CNT2, and outputs the comparison result to the output terminal comp_out as a monitor signal result_mon1 having a binary logic level. For example, when the leak current of the monitor cell array ARY1 is smaller than the leak current of the monitor cell array ARY2, the value of the counter CNT1 is larger than the value of the counter CNT2. The digital comparison circuit DIG_CMP compares the value of the counter CNT1 with the value of the counter CNT2, and outputs the comparison result as a monitor signal result_mon1. Based on the logic level of the monitor signal result_mon1, the magnitude relationship between the leak currents in the monitor cell array ARY1 and the monitor cell array ARY2 is detected.

The effect of the comparator COMP2 will be described.
Since the comparator COMP1 shown in FIG. 10 is composed of an analog circuit, there are some problems. Since the comparator COMP1 is an analog circuit, it is vulnerable to noise, and as represented by the amplifier circuit AMP10, a direct current component exists and power consumption is large. Further, in order to suppress the influence of the random variation of the transistors, it is necessary to increase the size of the transistors constituting the comparator COMP1, which causes an increase in the area of the semiconductor device LSI. In addition to the power supply voltage vdd1norm of the digital circuit, a power supply circuit that generates the power supply voltage vddm is required, which causes power consumption and area increase.

  On the other hand, the comparator COMP2 includes a measurement output imageas1 that is an object of voltage comparison, a ring oscillator ROS1 whose number of oscillation frequencies is controlled by the measurement output imageas2, and a ring oscillator ROS2. With this configuration, even if the voltage difference between the measurement output imageas1 and the measurement output imageas2 is very small, it is possible to measure with high accuracy by extending the measurement period. Furthermore, since the comparator COMP2 is composed of a digital circuit, it can be operated with the same power supply voltage vdd1norm as other digital circuits, which is effective in reducing power consumption and area.

  With reference to FIG. 12, the configuration of leak monitor circuit LEAK_MON1 in the case where another comparator COMP2 is applied to the semiconductor device LSI according to the second modification of the first embodiment will be described.

  The leak monitor circuit LEAK_MON1 includes a monitor cell array ARY1, a monitor cell array ARY2, a monitor voltage supply circuit ARVDD_SPLYC, and a comparator COMP2. The specific configurations of the monitor cell array ARY1, the monitor cell array ARY2, and the monitor voltage supply circuit ARVDD_SPLYC are the same as those given the same reference numerals in FIG. 9, and the description thereof is omitted. Further, the specific configuration of the comparator COMP2 is as described in FIG.

  In response to the monitor enable signal mon_en1 output from the standby mode setting circuit RS_CTL, the monitor control circuit MON_CTL1 of the central processing unit CPU1 starts measuring the leak current by the leak monitor circuit LEAK_MON1. Based on the control signal arvdd_en, the monitor control circuit MON_CTL1 cuts off the supply of the power supply voltage vdd1norm to the monitor cell arrays ARY1 and ARY2 from the nodes Na31 and Na32 of the monitor voltage supply circuit ARVDD_SPLYC (see FIG. 9).

  When the supply of the power supply voltage vdd1norm is cut off, the voltage of the node Na31 (measurement output images1) and the voltage of the node Na32 (measurement output images2) start to drop according to the leak currents of the monitor cell array ARY1 and the monitor cell array ARY2. To do. The comparator COMP2 is activated for a predetermined period by the control signal ros_en. Over that period, the counter CNT1 and the counter CNT2 count the number of oscillations of the ring oscillator ROS1 to which the measurement output imageas1 is applied and the number of oscillations of the ring oscillator ROS2 to which the measurement output imageas2 is applied. The comparator COMP2 compares the values of the counter CNT1 and the counter CNT2, and outputs the monitor signal result_mon1 from the output terminal comp_out to the standby mode setting circuit RS_CTL.

  With reference to FIG. 13, an operation of leak monitor circuit LEAK_MON1 when another comparator COMP2 is applied to the semiconductor device LSI according to the second modification of the first embodiment will be described.

  FIG. 13 is a timing chart schematically showing changes in each signal shown in FIG. 12, and each signal changes between a reference low level (Low: vss) and a high level (High: vdd1norm). The horizontal axis of each signal has a common time axis described as time.

  At time t0, the standby mode setting circuit RS_CTL generates a pulse for the monitor enable signal mon_en1 at the low level. In response to the rise of the monitor enable signal mon_en1, the monitor control circuit MON_CTL1 maintains the control signal arvdd_en at a high level for a predetermined time, and the power supply voltage vdd1norm to the monitor cell array ARY1 and the monitor cell array ARY2 by the monitor voltage supply circuit ARVDD_SPLYC. Supply is shut off (see FIG. 9).

  The voltage of the cell power supply line arvdd1 (the voltage of the node Na31) of the monitor cell array ARY1 from which the supply of the power supply voltage vdd1norm is cut off starts to decrease due to a leak current flowing through the monitor cell array ARY1. Similarly, the voltage (node Na32) of the cell power supply wiring arvdd2 of the monitor cell array ARY2 from which the supply of the power supply voltage vdd1norm is cut off also starts to decrease due to the leak current flowing through the monitor cell array ARY2.

  At time t1, the monitor control circuit MON_CTL1 raises the control signal ros_en from the low level to the high level, and activates the ring oscillator ROS1 and the ring oscillator ROS2. The oscillation period of the activated ring oscillator ROS1 becomes longer as the voltage of the measurement output imageas1 decreases (output signal ros_out1), and the oscillation period of the ring oscillator ROS2 becomes longer as the voltage of the measurement output imageas2 decreases (output signal ros_out2) (FIG. 11). In FIG. 13, the voltage drop rate of the measurement output imageas1 is larger than the voltage drop rate of the measurement output imageas2, which indicates that the leak current of the monitor cell array ARY1 is larger than the leak current of the monitor cell array ARY2.

  At time t2, the monitor control circuit MON_CTL1 lowers the control signal ros_en from the high level to the low level, and stops the oscillation of the ring oscillator ROS1 and the ring oscillator ROS2. Over the period from time t1 to time t2, the counter CNT1 and the counter CNT2 count the number of oscillations of the output signal ros_out1 and the output signal ros_out2, respectively.

  At time t3, the digital comparison circuit DIG_CMP is activated by the control signal dig_comp_en, the values of the counter CNT1 and the counter CNT2 are compared, and the result is output to the standby mode setting circuit RS_CTL as the monitor signal result_mon1 (see FIG. 12). Based on the value of the monitor signal result_mon1, the standby mode setting circuit RS_CTL controls the cell power supply voltage control circuit ARVSS_CTL1 with the control signal ram_rs_cnt1 and the regulator circuit REG_POWER with the control signal vdd1_cnt. In the example of FIG. 13, the cell power supply voltage control circuit ARVSS_CTL1 and the regulator circuit REG_POWER are controlled so that the memory cell array CELL_ARRAY is set to the LVRS mode.

At time t4, the values of the counter CNT1 and the counter CNT2 are reset.
With reference to FIG. 14, a configuration of a comparator COMP21, which is a modification 1 of the other comparator COMP2, applicable to the semiconductor device LSI according to the first embodiment and the modification thereof will be described.

  The comparator COMP21 is configured to apply one measurement output imageas1 to the ring oscillator ROS1 and the ring oscillator ROS2, and to cumulatively count the number of oscillations of each ring oscillator by the counter CNT1. Similarly, the counter CNT2 cumulatively counts the number of oscillations of each ring oscillator corresponding to the other measurement output images2. The exact operation of the comparator COMP21 is described below. The comparator COMP21 can suppress the measurement error of the number of oscillations caused by random variations in the transistors constituting the ring oscillators ROS1 and ROS2 (characteristics of transistors having the same shape are randomly different in one semiconductor chip). It becomes.

  In FIG. 14 and FIG. 11, transistors and circuits with the same reference numerals have the same configuration and function. In FIG. 14, the measurement output imageas1 and the measurement output imageas2 are input to the selector IN_SEL1 and the selector IN_SEL2. The selector IN_SEL1 and the selector IN_SEL2 alternately select one of the measurement output imageas1 and the measurement output imageas2 based on the selection signal sele. When the selection signal sel is at the low level, the selector IN_SEL1 and the selector IN_SEL2 select and output the measurement output images1 and the measurement output images2, respectively. When the selection signal sel is at a high level, the measurement output output from each selector has a reverse relationship to the above.

  The output of the selector IN_SEL1 is applied to the gate of the n-type transistor N311 included in each of the plurality of inverters INV31 configuring the ring oscillator ROS1 through the signal wiring gin1. The output of the selector IN_SEL2 is applied to the gate of the n-type transistor N321 included in each of the plurality of inverters INV32 constituting the ring oscillator ROS2 through the signal wiring gin2.

  The output signal ros_out1 of the ring oscillator ROS1 and the output signal ros_out2 of the ring oscillator ROS2 are input to the selector OUT_SEL1 and the selector OUT_SEL2. When the selection signal sel is at a low level, the selector OUT_SEL1 and the selector OUT_SEL2 select and output the output signal ros_out1 and the output signal ros_out2, respectively. When the selection signal sel is at a high level, the selector OUT_SEL1 and the selector OUT_SEL2 select and output the output signal ros_out2 and the output signal ros_out1, respectively. The number of oscillations of the output signal cin11 of the selector OUT_SEL1 is counted by the counter CNT1, and the number of oscillations of the output signal cin12 of the selector OUT_SEL2 is counted by the counter CNT2. The counter CNT1 and the counter CNT2 are reset by a reset signal reset.

The operation of the comparator COMP21 will be described.
When the selection signal sel is set to the low level, the ring oscillator ROS1 and the ring oscillator ROS2 have the number of oscillations determined based on the measurement output images1 and the measurement output images2 over the period activated by the control signal ros_en. The output signal ros_out1 and the output signal ros_out2 are each output. The selector OUT_SEL1 and the selector OUT_SEL2 select and output the output signal ros_out1 and the output signal ros_out2. The counter CNT1 and the counter CNT2 count the number of oscillations of the output signal ros_out1 and the output signal ros_out2, and hold the values.

  When the selection signal sele is set from the low level to the high level, the ring oscillator ROS1 and the ring oscillator ROS2 are oscillated based on the measurement output images2 and the measurement output images1 over the period activated by the control signal ros_en. An output signal ros_out1 having a number and an output signal ros_out2 are output. The selector OUT_SEL1 and the selector OUT_SEL2 select and output the output signal ros_out2 and the output signal ros_out1. The counter CNT1 and the counter CNT2 continue counting by adding the number of oscillations of the output signal ros_out2 and the output signal ros_out1 to the number of counts when the selection signal sel is at the low level.

  After being activated by the control signal dig_comp_en, the digital comparison circuit DIG_CMP compares the values of the counter CNT1 and the counter CNT2, and outputs the comparison result to the output terminal comp_out as a monitor signal result_mon1 having a binary logic level.

The effect of the comparator COMP21 will be described.
As described above, the counter CNT1 holds a cumulative value of the number of oscillations of the ring oscillator ROS1 and the ring oscillator ROS2 to which the measurement output imageas1 is applied. On the other hand, the counter CNT2 holds the accumulated value of the number of oscillations of the ring oscillator ROS1 and the ring oscillator ROS2 to which the measurement output imageas2 is applied. That is, the comparator COMP21 does not fix the measurement output and the ring oscillator to which the measurement output is applied, but alternately applies one measurement output to the two ring oscillators, and sets the number of oscillations of each ring oscillator to one counter. It has the structure which accumulates by.

  The ring oscillator ROS1 and the ring oscillator ROS2 have the same configuration. However, when random variation occurs, a difference occurs in the threshold voltage and on-current of the transistors constituting each ring oscillator. In that case, even if measurement outputs having the same voltage value are input to each ring oscillator, the oscillation frequencies of the respective ring oscillators are different, resulting in a measurement output comparison error. Although the influence of random variation can be reduced by increasing the number of stages of the ring oscillator or increasing the size of the transistors constituting the ring oscillator, the area of the ring oscillator is increased.

  In the leak monitor circuit LEAK_MON1C shown in FIG. 9, when the comparator COMP2 shown in FIG. 11 is applied as the comparator COMP, the following problems may occur if the number of stages of the ring oscillator is increased. The leak monitor circuit LEAK_MON1C cuts off the power supply voltage vdd1norm supplied to the monitor cell arrays ARY1 and ARY2 by the monitor voltage supply circuit ARVDD_SPLYC, and outputs the subsequent voltages of the nodes Na31 and Na32 to the comparator COMP2 as measurement outputs imas1 and imas2.

  When the leak current of the monitor cell array is large, the voltage of the measurement output imageas1 or the measurement output imageas2 rapidly decreases to a level at which the ring oscillator does not operate, which causes a problem that the leakage current cannot be compared by the ring oscillator.

  According to the comparator COMP21 shown in FIG. 14, one measurement output imageas1 is alternately applied to the ring oscillator ROS1 and the ring oscillator ROS2, and the number of oscillations of each ring oscillator is cumulatively counted by the counter CNT1. Similarly, the counter CNT2 cumulatively counts the number of oscillations of each ring oscillator corresponding to the other measurement output images2. As a result, it is possible to eliminate measurement errors caused by random variations in the transistors constituting the ring oscillators ROS1 and ROS2.

  Furthermore, since the number of stages of the ring oscillator can be set within an appropriate range, even if the leakage monitor circuit measures the leakage current based on the change in the measurement output after the power supply voltage supplied to the monitor cell array is shut off, the ring oscillator Leakage current can be measured.

  With reference to FIG. 15, a configuration of a comparator COMP22, which is a modification 2 of the other comparator COMP2, applicable to the semiconductor device LSI according to the first embodiment and the modification thereof will be described.

  The comparator COMP22 is configured to alternately apply the measurement output imageas1 and the measurement output imageas2 to one ring oscillator ROS1, and count the number of oscillations of the ring oscillator ROS1 in each case by the counter CNT1 and the counter CNT2. The

  In FIG. 15 and FIG. 14, transistors and circuits having the same reference numerals have the same configuration and function. In FIG. 15, the selector IN_SEL1 selects and outputs the measurement output imageas1 when the selection signal sel is low level, and selects and outputs the measurement output imageas2 when the selection signal sele is high level. The output signal ros_out of the ring oscillator ROS1 is input to one of the gate G21 and the gate G22, and the selection signal sel is input to the other.

  Accordingly, when the selection signal sel is low level, the counter CNT1 counts the number of oscillations of the ring oscillator ROS1 when the measurement output image1 is applied. When the selection signal sel is high level, the counter CTN2 When applied, the number of oscillations of the ring oscillator ROS1 is counted. After being activated by the control signal dig_comp_en, the digital comparison circuit DIG_CMP compares the values of the counter CNT1 and the counter CNT2, and outputs the comparison result to the output terminal comp_out as a monitor signal result_mon1 having a binary logic level.

The effect of the comparator COMP22 will be described.
When the measurement time of the comparator COMP22 is sufficiently short compared to changes in the temperature and power supply voltage of the semiconductor device LSI, by applying the voltage of the measurement output images1 and 2 to the one ring oscillator ROS1 in a time division manner, It is possible to reduce the operating power and area.

  With reference to FIG. 16, a configuration of a comparator COMP23, which is a modification 3 of the other comparator COMP2, applicable to the semiconductor device LSI according to the first embodiment and the modification thereof will be described.

  In the central processing unit CPU1 that operates by receiving the supply of the power supply voltage vdd1, when the memory module RAM_MOD1 is set from the RS mode to the LVRS mode, the current of circuits other than the memory cell array CELL_ARRAY also decreases. For example, the data output latch circuit and the logic circuit included in the peripheral circuit PERI are in a state where the power supply voltage is applied even when the memory cell array CELL_ARRAY is set to the standby mode. The comparator COMP23 determines the standby mode of the memory module RAM_MOD1 in consideration of the current reduction effect of the circuit to which the power supply voltage is applied even in the standby mode.

  In FIG. 16 and FIG. 15, transistors and circuits having the same reference numerals have the same configuration and function. In FIG. 16, the counter CNT1 counts the number of oscillations of the ring oscillator ROS1 controlled by the measurement output imageas1. That is, the number of oscillations corresponding to the leak current of the monitor cell array ARY2 set to the RS mode is stored in the counter CNT1. The counter CNT2 counts the number of oscillations of the ring oscillator ROS1 controlled by the measurement output images2. That is, the number of oscillations corresponding to the leak current of the monitor cell array ARY2 set in the LVRS mode is stored in the counter CNT2.

  The signal logic_offset is used to change the power supply voltage applied to circuits other than the memory cell array CELL_ARRAY from the power supply voltage in the RS mode (vdd1norm) to the power supply voltage in the LVRS mode in the central processing unit CPU1 that operates by receiving the supply of the power supply voltage vdd1. This is the count number corresponding to the amount of current reduced when it is changed to (vdd1norm−Δvdd).

  The adder circuit ADDR outputs an added value of the output of the counter CNT1 and the signal logic_offset. The digital comparison circuit DIG_CMP compares the output of the adder circuit ADDR and the output of the counter CNT2, and outputs the result as a monitor signal result_mon1 to the output terminal comp_out.

The effect of the comparator COMP23 will be described.
When the memory cell array CELL_ARRAY of the central processing unit CPU1 is set to the LVRS mode by the comparator COMP23, the standby mode can be selected in consideration of a change in the amount of current flowing through a circuit other than the memory cell array CELL_ARRAY.

  With reference to FIG. 17, the configuration of leak monitor circuit LEAK_MON1 in the case where COMP21, which is Modification 1 of other comparator COMP2, is applied to the semiconductor device LSI according to Modification 2 of Embodiment 1 will be described.

  The leak monitor circuit LEAK_MON1 includes a monitor cell array ARY1, a monitor cell array ARY2, a monitor voltage supply circuit ARVDD_SPLYC, and a comparator COMP21. The specific configurations of the monitor cell array ARY1, the monitor cell array ARY2, and the monitor voltage supply circuit ARVDD_SPLYC are the same as those given the same reference numerals in FIG. 9, and the description thereof is omitted. Further, the specific configuration of the comparator COMP21 is as described in FIG.

  In response to the monitor enable signal mon_en1 output from the standby mode setting circuit RS_CTL, the monitor control circuit MON_CTL1 of the central processing unit CPU1 starts measuring the leak current by the leak monitor circuit LEAK_MON1. Based on the control signal arvdd_en, the monitor control circuit MON_CTL1 cuts off the supply of the power supply voltage vdd1norm to the monitor cell arrays ARY1 and ARY2 from the nodes Na31 and Na32 of the monitor voltage supply circuit ARVDD_SPLYC (see FIG. 9).

  When the supply of the power supply voltage vdd1norm is cut off, the voltage of the node Na31 (measurement output images1) and the voltage of the node Na32 (measurement output images2) start to fall according to the leak currents of the monitor cell array ARY1 and the monitor cell array ARY2. . For the first leak current measurement, the selection signal sel is set to the low level. With the control signal ros_en, the ring oscillator ROS1 and the ring oscillator ROS2 of the comparator COMP21 are activated for a predetermined period. Over that period, the counter CNT1 and the counter CNT2 count the number of oscillations of the ring oscillator ROS1 to which the measurement output imageas1 is applied and the number of oscillations of the ring oscillator ROS2 to which the measurement output imageas2 is applied.

  For the second leak current measurement, the selection signal sel is set to a high level. With the control signal ros_en, the ring oscillator ROS1 and the ring oscillator ROS2 of the comparator COMP21 are activated for a predetermined period. Over that period, the counter CNT1 and the counter CNT2 count the number of oscillations of the ring oscillator ROS2 to which the measurement output imageas1 is applied and the number of oscillations of the ring oscillator ROS1 to which the measurement output imageas2 is applied. The comparator COMP21 compares the values of the counter CNT1 and the counter CNT2, and outputs a monitor signal result_mon1 from the output terminal comp_out to the standby mode setting circuit RS_CTL.

  With reference to FIG. 18, the operation of the leak monitor circuit LEAK_MON1 when the COMP 21 which is the first modification of the other comparator COMP2 is applied to the semiconductor device LSI according to the second modification of the first embodiment will be described.

  FIG. 18 is a timing chart schematically showing changes in each signal shown in FIG. 17, and each signal changes between a reference low level (Low: vss) and a high level (High: vdd1norm). The horizontal axis of each signal has a common time axis described as time.

  The monitor control circuit MON_CTL1 sets the selection signal sel to the low level, and the first leak current is measured.

  At time t0, the standby mode setting circuit RS_CTL generates a pulse for the monitor enable signal mon_en1 at the low level. In response to the rise of the monitor enable signal mon_en1, the monitor control circuit MON_CTL1 maintains the control signal arvdd_en at a high level for a predetermined time, and supplies the power supply voltage vdd1norm to the monitor cell array ARY1 and the monitor cell array ARY2 by the monitor voltage supply circuit ARVDD_SPLYC. Is blocked (see FIG. 9).

  The voltage of the cell power supply line arvdd1 (the voltage of the node Na31) of the monitor cell array ARY1 from which the supply of the power supply voltage vdd1norm is cut off starts to decrease due to a leak current flowing through the monitor cell array ARY1. Similarly, the voltage (node Na32) of the cell power supply wiring arvdd2 of the monitor cell array ARY2 from which the supply of the power supply voltage vdd1norm is cut off also starts to decrease due to the leak current flowing through the monitor cell array ARY2.

  At time t1, the monitor control circuit MON_CTL1 raises the control signal ros_en from the low level to the high level, and activates the ring oscillator ROS1 and the ring oscillator ROS2. The measurement output imageas1 selected by the selector IN_SEL1 is applied to the ring oscillator ROS1, and the measurement output imageas2 selected by the selector IN_SEL2 is applied to the ring oscillator ROS2. The counter CNT1 counts the number of oscillations of the output of the ring oscillator ROS1 selected by the selector OUT_SEL1, and holds the result. The counter CNT2 counts the number of oscillations of the output of the ring oscillator ROS2 selected by the selector OUT_SEL2, and holds the result.

  At time t2, the monitor control circuit MON_CTL1 lowers the control signal ros_en from the high level to the low level, and ends the first leak current measurement.

  The monitor control circuit MON_CTL1 raises the selection signal sel from the low level to the high level, and the second leak current measurement is performed.

  At time t3, the standby mode setting circuit RS_CTL generates a pulse for the monitor enable signal mon_en1 at the low level. In response to the rise of the monitor enable signal mon_en1, the monitor control circuit MON_CTL1 maintains the control signal arvdd_en at a high level for a predetermined time, and supplies the power supply voltage vdd1norm to the monitor cell array ARY1 and the monitor cell array ARY2 by the monitor voltage supply circuit ARVDD_SPLYC. Shut off.

  The voltage of the cell power supply line arvdd1 (the voltage of the node Na31) of the monitor cell array ARY1 from which the supply of the power supply voltage vdd1norm is cut off starts to decrease due to a leak current flowing through the monitor cell array ARY1. Similarly, the voltage (node Na32) of the cell power supply wiring arvdd2 of the monitor cell array ARY2 from which the supply of the power supply voltage vdd1norm is cut off also starts to decrease due to the leak current flowing through the monitor cell array ARY2.

  At time t4, the monitor control circuit MON_CTL1 raises the control signal ros_en from the low level to the high level, and activates the ring oscillator ROS1 and the ring oscillator ROS2. The measurement output imageas2 selected by the selector IN_SEL1 is applied to the ring oscillator ROS1, and the measurement output imageas1 selected by the selector IN_SEL2 is applied to the ring oscillator ROS2. The counter CNT1 counts by adding the number of oscillations of the output of the ring oscillator ROS2 selected by the selector OUT_SEL1 to the count number of the first measurement result. The counter CNT2 counts by adding the number of oscillations of the output of the ring oscillator ROS2 selected by the selector OUT_SEL2 to the count number of the first measurement result.

  At time t6, the digital comparison circuit DIG_CMP is activated by the control signal dig_comp_en, the values of the counter CNT1 and the counter CNT2 are compared, and the result is output to the standby mode setting circuit RS_CTL as the monitor signal result_mon1. Based on the value of the monitor signal result_mon1, the standby mode setting circuit RS_CTL controls the cell power supply voltage control circuit ARVSS_CTL1 with the control signal ram_rs_cnt1, or the regulator circuit REG_POWER with the control signal vdd1_cnt.

At time t7, the values of the counter CNT1 and the counter CNT2 are reset.
Referring to FIG. 19, the configuration of ring oscillator ROS4 applicable to another comparator COMP2 and its modification will be described.

  The difference between the ring oscillator ROS4, the ring oscillator ROS1, and the ring oscillator ROS2 is that an n-type transistor Nfix to which the voltage fix_sig is applied to the gate is connected in parallel with the n-type transistor N41 of the inverter INV41. .

  The ring oscillator ROS4 is a ring oscillator in which the final stage output of the inverter INV41 connected in cascade with a predetermined number of stages is input to the NAND gate G41, and the output is returned to the first stage inverter INV41 to form an oscillation loop. The inverter INV41 includes a p-type transistor P41, n-type transistors N41, N42, and Nfix. A power supply voltage vdd1norm is applied to the source of the p-type transistor P41, and its drain is connected to the drain of the n-type transistor N42. The drain of the n-type transistor N41 is connected to the source of the n-type transistor N42, and the power supply voltage vss is applied to the source. The n-type transistor Nfix is connected in parallel with the n-type transistor N41, the voltage fix_sig is applied to the gate of the n-type transistor Nfix, and the signal comp_inx is applied to the gate of the n-type transistor N41. Here, the signal comp_inx is the measurement output imageas1 (x = 1) and the measurement output imageas2 (x = 2) indicated by the leak monitor circuit LEAK_MON1C.

  The voltage fix_sig is set so that the n-type transistor Nfix maintains a conductive state. As long as the n-type transistor Nfix is conductive, the ring oscillator ROS4 continues to oscillate even if the voltage of the measurement output imeasx applied to the gate of the n-type transistor N41 decreases. That is, the n-type transistor Nfix supplies a predetermined bias current to the switching unit composed of the p-type transistor P41 and the n-type transistor N42, and even if the current supply to the switching unit by the n-type transistor N41 decreases, The operation of the inverter INV41 is enabled.

The effect of the ring oscillator ROS4 will be described.
When the leak current of the monitor cell arrays ARY1 and ARY2 is measured by the leak monitor circuit LEAK_MON1C, the power supply voltage vdd1norm supplied by the monitor voltage supply circuit ARVDD_SPLYC is cut off, and the voltage fluctuation amount of the measurement output imageas1 and the measurement output image2 is changed to the ring oscillator ROS1. And the number of oscillations of the ring oscillator ROS2. When the leak current of the monitor cell array is very large, the input voltage to the ring oscillator becomes too low and the power supply voltage vss is not supplied to the inverter constituting the ring oscillator. As a result, there is a problem that the ring oscillator does not operate before a difference in the count of the number of oscillations of the ring oscillator occurs.

  The power supply voltage vss is applied to the inverter INV41 constituting the ring oscillator ROS4 by the n-type transistor Nfix, regardless of the value of the measurement output images1 and the measurement output images2. As a result, the ring oscillator ROS4 can continue to oscillate in response to changes in the voltages of the measurement output imageas1 and the measurement output imageas2.

  With reference to FIG. 20, the configuration of timer ROS_TIME applicable to another comparator COMP2 and its modification will be described.

  The timer ROS_TIME controls the activation period of the other comparator COMP2 and the ring oscillator ROS1 and the ring oscillator ROS2 included in the respective modifications. The timer ROS_TIME has a ring oscillator ROS_T and a counter CNT3, and the ring oscillator ROS_T has the same configuration as the ring oscillator ROS1 shown in FIG. The number of bits of the counter CNT3 and the counter CNT1 is set to be the same. The signal meas_start is applied to the NAND gate of the ring oscillator ROS_T, and the voltage tieh is applied to the inverter. The counter CNT3 counts the number of oscillations of the output signal time_ros_out output from the ring oscillator ROS_T, and outputs the result as a signal meas_time_cont. The value of the counter CNT3 is reset by a reset signal reset_meas_time.

  Using the comparator COMP2 of FIG. 11 as an example, a method for controlling the activation period of the ring oscillator ROS1 by the timer ROS_TIME will be described. When the control signal ros_en changes from the low level to the high level, the ring oscillator ROS1 is activated and starts oscillating at an oscillation frequency corresponding to the measurement output images1. When the signal meas_start changes from the low level to the high level in synchronization with the control signal ros_en, the ring oscillator ROS_T is activated and starts oscillating at an oscillation frequency corresponding to the value of the voltage tieh. The voltage tieh is always set to a constant value that is higher than the measurement output imageas1 and the measurement output imageas2.

  When the output signal meas_time_cont of the counter CNT3 reaches a predetermined value, for example, the maximum value that can be counted by the counter CNT3, the ring oscillator ROS1 is stopped (inactivated). Since the voltage tieh applied to the ring oscillator ROS_T is set to a voltage higher than the measurement output imageas1 and measurement output imageas2 applied to the ring oscillator ROS1, the value of the counter CNT3 is larger than the value of the counter CNT1. Therefore, the counter CNT1 of the comparator COMP2 can be prevented from overflowing by stopping (inactivating) the operation of the ring oscillator ROS1 when the value of the counter CNT3 reaches the maximum value that can be counted. .

The effect of the timer ROS_TIME will be described.
Since the oscillation frequency of the ring oscillator mounted on the semiconductor device LSI changes depending on the temperature, the manufacturing process, and the voltage condition, the measurement time of the number of oscillations of the ring oscillator is not uniform. If the measurement time is set unnecessarily long, the power consumption increases, and if the number of bits of the counter is increased to avoid overflow, the area increases. Conversely, if the measurement time is set shorter than necessary, the minimum potential difference that can be detected by the ring oscillator increases.

  The ring oscillator ROS_T included in the timer ROS_TIME is set to have the same structure as the ring oscillator ROS1 to which the measurement output imageas1 is applied, and the same power supply voltage vdd1norm is applied. Further, the oscillation frequency of the ring oscillator ROS_T is set to be higher than the oscillation frequency of the ring oscillator ROS1. Accordingly, by inactivating the ring oscillator ROS1 before the counter CNT3 that measures the number of oscillations of the ring oscillator ROS_T overflows, it is possible to appropriately set the measurement time of the measurement output images1 by the ring oscillator ROS1. .

<Embodiment 2>
With reference to FIG. 21, the configuration of leak monitor circuit LEAK_MON1_2 provided in the semiconductor device LSI according to the second embodiment will be described.

  The leak monitor circuit LEAK_MON1_2 sets one monitor cell array ARY3 to the RS mode and the LVRS mode, and outputs a monitor signal result_mon1 based on the comparison result of the leak current in each mode.

  The leak monitor circuit LEAK_MON1_2 includes a monitor cell array ARY3, a ring oscillator ROS1, a gate G21, a gate G22, a counter CNT1, a counter CNT2, a digital comparison circuit DIG_CMP, a p-type transistor ARVDD_PWS1, a selector SEL_PWS1, a selector SEL_PWS2, an inverter INV50, and an array VSS. A generation circuit ARVSS_GEN1;

  The monitor cell array ARY3 includes a predetermined number of memory cells MC. The power supply node arvdd, the back gate node vddb, the bit line node bt, and the bit line node bb of each memory cell MC are connected to the cell power supply line arvdd3. The power supply node arvss of each memory cell MC is connected to the cell power supply line arvss3, and a predetermined voltage output from the array VSS generation circuit ARVSS_GEN1 is applied to the cell power supply line arvss3.

  The array VSS generation circuit ARVSS_GEN1 generates the bias voltage Δvss shown in FIG. 6 and applies a voltage obtained by adding the bias voltage Δvss to the power supply voltage vss to the cell power supply wiring arvss3. The back gate node vssb and the word line node wl of each memory cell MC are connected to the cell power supply line vssb3, and the cell power supply line vssb3 is connected to one end of the selector SEL_PWS1 and the selector SEL_PWS2. The other ends of the selector SEL_PWS1 and the selector SEL_PWS2 are connected to the power supply wiring vss and the output of the array VSS generation circuit ARVSS_GEN1, respectively.

  The selector SEL_PWS1 and the selector SEL_PWS2 are exclusively set to a conductive state and a non-conductive state by a selection signal sel and a signal obtained by inverting the logic level of the selection signal sel by the inverter INV50. A power supply voltage vdd1norm is applied to the source of the p-type transistor ARVDD_PWS1, and its drain is connected to the cell power supply line arvdd3. Application / cutoff of the power supply voltage vdd1norm to the cell power supply wiring arvdd3 is controlled by a control signal arvdd_en applied to the gate of the p-type transistor ARVDD_PWS1.

  A method for measuring the leakage current of the monitor cell array ARY3 set to the RS mode will be described.

  When the selection signal sele is set to a low level, the selector SEL_PWS1 becomes conductive, and the power supply voltage vss is applied to the cell power supply wiring vssb3. On the other hand, a voltage obtained by adding a bias voltage Δvss to the power supply voltage vss output from the array VSS generation circuit ARVSS_GEN1 is applied to the cell power supply wiring arvss3. When the control signal arvdd_en is set to a low level in this state, the power supply voltage vdd1norm is applied to the cell power supply wiring arvdd3, and each memory cell MC of the monitor cell array ARY3 is set to the RS mode.

  When the control signal arvdd_en is set from the low level to the high level, the voltage of the cell power supply wiring arvdd3 starts to drop from the power supply voltage vdd1norm due to the leak current of the monitor cell array ARY3. When the control signal ros_en is changed from the low level to the high level at the same timing as this decrease, the activated ring oscillator ROS1 outputs the output signal ros_out having an oscillation frequency corresponding to the voltage of the cell power line arvdd3 that decreases to the counter CNT1. Output.

  The counter CNT1 counts the number of oscillations of the output signal ros_out of the ring oscillator ROS1. Since the selection signal sel is at the low level, the output of the ring oscillator ROS1 is input to the counter CNT1 as the output signal cin1 of the NAND circuit G21. After a predetermined time has elapsed since the control signal ros_en was changed from the low level to the high level, the control signal ros_en is set from the high level to the low level. As a result, the ring oscillator ROS1 is deactivated, and the leakage current measurement of the monitor cell array ARY3 set in the RS mode is completed.

  A method for measuring the leakage current of the monitor cell array ARY3 set in the LVRS mode will be described.

  When the selection signal sel is set to a high level, the selector SEL_PWS2 becomes conductive, and a bias voltage Δvss is applied to the cell power supply wiring vssb3 in addition to the power supply voltage vss output from the array VSS generation circuit ARVSS_GEN1, similarly to the cell power supply wiring arvss3. Applied voltage. When the control signal arvdd_en is set to a low level in this state, the power supply voltage vdd1norm is applied to the cell power supply wiring arvdd3, and each memory cell MC of the monitor cell array ARY3 is reproduced in the LVRS mode.

  When the control signal arvdd_en is set from the low level to the high level, the voltage of the cell power supply wiring arvdd3 starts to drop from the power supply voltage vdd1norm due to the leak current of the monitor cell array ARY3. When the control signal ros_en is changed from the low level to the high level at the same timing as this decrease, the activated ring oscillator ROS1 outputs the output signal ros_out having an oscillation frequency corresponding to the voltage of the decreasing cell power supply line arvdd3 to the counter CNT2. Output.

  The counter CNT2 counts the number of oscillations of the output signal ros_out from the ring oscillator ROS1. Since the selection signal sel is at a high level, the output of the ring oscillator ROS1 is input to the counter CNT2 as the output signal cin2 of the gate G22. After a predetermined time has elapsed since the control signal ros_en was changed from the low level to the high level, the control signal ros_en is set from the high level to the low level. As a result, the ring oscillator ROS1 is deactivated, and the leakage current measurement of the monitor cell array ARY3 set in the LVRS mode is completed.

  After completing the measurement of the leak current in the monitor cell array ARY3 in the RS mode and the LVRS mode, the digital comparison circuit DIG_CMP activated by the control signal dig_comp_en compares the values of the counter CNT1 and the counter CNT2, and outputs the comparison result to the output terminal comp_out. This is output as a monitor signal result_mon1 having a logic level of value.

The effect of the leak monitor circuit LEAK_MON1_2 will be described.
The leak monitor circuit LEAK_MON1_2 sets one monitor cell array ARY3 to the RS mode and the LVRS mode in a time division manner, and measures the leak current in each mode with one ring oscillator ROS1. Therefore, it is possible to reduce the power consumption and area caused by the monitor cell array and the ring oscillator. Also, by using the same memory cell array in a time-sharing manner, it is possible to reduce measurement errors due to leakage current variations in the monitor cell arrays ARY1 and ARY2 due to random variations.

<Embodiment 3>
With reference to FIG. 22, a configuration of leak monitor circuit LEAK_MON1_3 provided in the semiconductor device LSI according to the third embodiment will be described.

  In addition to the monitor cell array ARY1 (set to RS mode) and the monitor cell array ARY2 (set to LVRS mode), the leak monitor circuit LEAK_MON1_3 includes the monitor logic array LARY1 and the monitor logic array LARY2, and influences the leakage current of the logic circuit. The standby mode can be selected in consideration of the above.

  The configurations of the monitor cell array ARY1, the monitor cell array ARY2, the array VSS generation circuit ARVSS_GEN1, the p-type transistor ARVDD_PWS1, and the p-type transistor ARVDD_PWS2 are the same as those denoted by the same reference numerals in FIG. .

  The monitor logic array LARY1 and the monitor logic array LARY2 have the same configuration that simulates a logic circuit included in the central processing unit CPU1 that operates by receiving the supply of the power supply voltage vdd1. Although a plurality of inverters are shown in FIG. 22, a NAND circuit, a NOR circuit, or the like may be included in order to simulate a more actual circuit configuration. When there are a plurality of types of threshold voltages of the transistors constituting the logic circuit, the monitor logic array LARY1 and the monitor logic array LARY2 are configured to reflect the ratio of the number of transistors having each threshold voltage.

  When the memory module RAM_MOD1 of the central processing unit CPU1 is set to the RS mode, a power supply voltage obtained by adding the bias voltage Δvss to the power supply voltage vss is applied to the power supply node arvss of the memory cell MC in the memory cell array CELL_ARRAY. A power supply voltage vdd1norm is applied to arvdd. On the other hand, the power supply voltage vdd1norm and the power supply voltage vss are applied to the logic circuit included in the central processing unit CPU1. The bias voltage Δvss is not applied to the power supply voltage vss applied to the logic circuit. Accordingly, the power supply voltage vdd1norm and the power supply voltage vss are applied to the monitor logic array LARY1.

  When the memory module RAM_MOD1 of the central processing unit CPU1 is set to the LVRS mode, the power supply voltage vss is applied to the power supply node arvss of the memory cell MC in the memory cell array CELL_ARRAY, and the bias voltage Δvdd from the power supply voltage vdd1norm is applied to the power supply node arvdd. A lowered power supply voltage is applied. On the other hand, a power supply voltage that is lower than the power supply voltage vdd1norm by the bias voltage Δvdd and the power supply voltage vss are applied to the logic circuit included in the central processing unit CPU1.

  In the monitor cell array ARY2 of the leak monitor circuit LEAK_MON1_3 shown in FIG. 22, the power supply voltage avdd1norm is not applied to the power supply node arvdd and back gate node vddb of each memory cell MC, and the power supply voltage vdd1norm is not applied. Is applied. Instead, a power supply voltage obtained by adding a bias voltage Δvss to the power supply voltage vss is applied to the power supply node arvss and back gate node vssb of the memory cell MC, and the monitor cell array ARY2 is reproduced in the same state as in the LVRS mode. Similarly, a power supply voltage obtained by adding the bias voltage Δvss to the power supply voltage vss is applied to the monitor logic array LARY2 instead of applying a power supply voltage that is lower than the power supply voltage vdd1norm by the bias voltage Δvdd.

  The p-type transistor ARVDD_PWS1 and the p-type transistor ARVDD_PWS2, which respectively supply the power supply voltage vdd1norm to the monitor cell array ARY1 and the monitor logic array LARY1, and the monitor cell array ARY2 and the monitor logic array LARY2, are simultaneously turned off by the control signal arvdd_en. Subsequent measurement output images1 and measurement output images2 are compared by the comparator COMP, and the standby mode is selected in consideration of the influence of the leakage current of the logic circuit.

  With reference to FIG. 23, a configuration of a comparator COMP3 provided in the semiconductor device LSI according to the third embodiment will be described.

  The comparator COMP3 has the same configuration as the comparator COMP2 shown in FIG. The comparator COMP3 outputs a monitor signal result_mon1 based on the measurement output images1 of the monitor cell array ARY1 and the monitor logic array LARY1, and the measurement output images2 of the monitor cell array ARY2 and the monitor logic array LARY2.

  In FIG. 22, when the ratio of the logic circuit to the memory cell array CELL_ARRAY is reproduced, there is a concern that the circuit scale of the monitor logic array LARY1 and the monitor logic array LAR2 increases. Therefore, the leak current values of monitor logic array LARY1 and monitor logic array LARY2 are converted into count values of the number of oscillations by ring oscillator ROS1 and ring oscillator ROS2, respectively.

  The respective count values are appropriately adjusted to be several times or a fraction of each according to the circuit scale of the logic circuit, and set as the adjustment count values of the monitor logic array LARY1 and the monitor logic array LARY2. In addition, the count value for each memory cell corresponding to each leakage current value of the monitor cell array ARY1 and the monitor cell array ARY2 is obtained. The added value of the adjustment counter value of the monitor logic array LARY1 and the count value of the monitor cell array ARY1, and the adjustment count value of the monitor logic array LARY2 and the count value of the monitor cell array ARY2 are compared by the comparator COMP3 of FIG.

  As described above, the circuit scales of the monitor logic arrays LARY1 and LRAY2 are increased with respect to the monitor cell arrays ARY1 and ARY2 by adjusting the count values by the ring oscillators of the monitor logic arrays LAR1 and LARY2 according to the circuit scale of the logic circuits. Therefore, it becomes possible to compare the leak current reflecting the scale of the logic circuit. In the central processing unit CPU2 or the like having a different ratio of the logic circuit and the memory cell array CELL_ARRAY, the same monitor circuit can be used by appropriately setting the adjustment count values of the monitor logic arrays LARY1 and LARY2.

  When the count values by the ring oscillators of the monitor logic arrays LAR1 and LARY2 are adjusted by an arithmetic unit according to the circuit scale of the logic circuit, the arithmetic unit is required and the circuit scale increases. However, by adjusting the activation period (measurement period) of the ring oscillator ROS1 and the ring oscillator ROS2, the count value obtained from the leakage currents of the monitor logic array LARY1 and the monitor logic array LARY2 is changed to a value reflecting the circuit scale. The arithmetic circuit to adjust becomes unnecessary.

  In FIG. 22, the oscillation frequency of the ring oscillator is measured by changing the types of the memory cells MC of the monitor cell arrays ARY1 and ARY2 and the threshold voltage of the transistors, and the counter value of the number of oscillations of the ring oscillator in a predetermined period is weighted. . As a result, even when the type of the memory cell MC and the threshold voltage of the transistor are different, it is possible to use the leak monitor circuit having the same configuration, thereby reducing the development time and development cost of the semiconductor device.

<Embodiment 4>
With reference to FIG. 24, the configuration of leak monitor circuit LEAK_MON1_4 provided in the semiconductor device LSI according to the fourth embodiment will be described.

  The leak monitor circuit LEAK_MON1_4 includes a monitor cell array ARY4, a monitor cell write circuit ARY_WT, an array VSS generation circuit ARVSS_GEN1, and a p-type transistor ARVDD_PWS1.

  The monitor cell array ARY4 includes a predetermined number of memory cells MC2. The power supply node arvdd, the back gate node vddb, the bit line node bt, and the bit line node bb of each memory cell MC2 are connected to the cell power supply line arvdd4. The power supply node arvss_l of each memory cell MC2 is connected to the cell power supply line arvss_l4, the power supply node arvss_r of each memory cell MC2 is connected to the cell power supply line arvss_r4, the back gate node vssb of each memory cell MC2 and the word line node wl are The cell power supply wiring vssb4 is connected. A predetermined voltage output from the array VSS generation circuit ARVSS_GEN1 is applied to the cell power supply wiring vssb4. The array VSS generation circuit ARVSS_GEN1 generates the bias voltage Δvss shown in FIG. 6, and applies a voltage obtained by adding the bias voltage Δvss to the power supply voltage vss to the cell power supply wiring vssb4.

  A power supply voltage vdd1norm is applied to the source of the p-type transistor ARVDD_PWS1, and its drain is connected to the cell power supply line arvdd4. Application / cutoff of the power supply voltage vdd1norm to the cell power supply wiring arvdd4 is controlled by a control signal arvdd_en applied to the gate of the p-type transistor ARVDD_PWS1.

The configuration of the monitor cell write circuit ARY_WT will be described.
The monitor cell write circuit ARY_WT includes a gate G41, a gate G42, an n-type transistor N51, an n-type transistor N52, a p-type transistor P51, and a p-type transistor P52. The data setting signal set_data is applied to one end of the gate G41 and the gate G42, and the data selection signal sel_data is applied to the other end. A power supply voltage vdd1norm is applied to the source of the p-type transistor P51, and its drain is connected to the drain of the n-type transistor N51. The output voltage of the array VSS generation circuit ARVSS_GEN1 is applied to the source of the n-type transistor N51, and the output of the gate G41 is applied to the gates of the p-type transistor P51 and the n-type transistor N51.

  A power supply voltage vdd1norm is applied to the source of the p-type transistor P52, and its drain is connected to the drain of the n-type transistor N52. The output voltage of the array VSS generation circuit ARVSS_GEN1 is applied to the source of the n-type transistor N52, and the output of the gate G42 is applied to the gates of the p-type transistor P52 and the n-type transistor N52. The cell power supply line arvss_l4 and the cell power supply line arvss_r4 are connected to the drain of the n-type transistor N51 and the drain of the n-type transistor N52, respectively.

The operation of the monitor cell write circuit ARY_WT will be described.
When the data setting signal set_data is set to the high level, the monitor cell write circuit ARY_WT is set to the data write mode, and the outputs of the gate G41 and the gate G42 depend on the data selection signal sel_data. When the data selection signal sel_data is set to a high level, the gate G41 outputs a low level and outputs a gate G42 high level. The output level of the gate G41 is inverted by an inverter composed of a p-type transistor P51 and an n-type transistor N51, and the cell power supply line arvss_l4 is set to a high level (power supply voltage vdd1norm).

  The output level of the gate G42 is inverted by an inverter composed of a p-type transistor P52 and an n-type transistor N52, and the cell power supply line arvss_r4 is set to a low level (output voltage of the array VSS generation circuit ARVSS_GEN1). When the data selection signal sel_data is set to a low level, the cell power supply line arvss_l4 is set to a low level (output voltage of the array VSS generation circuit ARVSS_GEN1), and the cell power supply line arvss_r4 is set to a high level (power supply voltage vdd1norm).

  When the data setting signal set_data is set to a low level, the outputs of the gate G41 and the gate G42 both output a high level regardless of the value of the data selection signal sel_data. As a result, the voltages of the cell power supply wiring arvss_l4 and the cell power supply wiring arvss_r4 are both set to the output voltage of the array VSS generation circuit ARVSS_GEN1 (the voltage obtained by increasing the power supply voltage vss by the bias voltage Δvss).

  With reference to FIG. 25, the configuration of memory cell MC2 provided in the semiconductor device LSI according to the fourth embodiment will be described.

  The memory cell MC2 has a data holding circuit DH including a p-type transistor PU_L, a p-type transistor PU_R, an n-type transistor PD_L, and an n-type transistor PD_R. The drains of p-type transistor PU_L and n-type transistor PD_L are connected to data node Nd_L, and the gates of p-type transistor PU_R and n-type transistor PD_R are connected to data node Nd_L. The drains of p-type transistor PU_R and n-type transistor PD_R are connected to data node Nd_R, and the gates of p-type transistor PU_L and n-type transistor PD_L are connected to data node Nd_R.

  Each source of p-type transistors PU_L and PU_R is connected to power supply node arvdd, and the back gates of both transistors are connected to back gate node vdb. The source of n-type transistor PD_L is connected to power supply node arvss_l, the source of n-type transistor PD_R is connected to power supply node arvss_r, and the back gates of both transistors are connected to back gate node vssb.

  The data holding circuit DH is a latch circuit including an inverter composed of a p-type transistor PU_L and an n-type transistor PD_L and an inverter composed of a p-type transistor PU_R and an n-type transistor PD_R. By lowering the voltage of the power supply node arvdd with respect to the voltage of the back gate node vddb, it becomes possible to apply a back bias to the pair of p-type transistors including the p-type transistors PU_L and PU_R. Similarly, by raising the voltage of the power supply node arvss with respect to the voltage of the back gate node vssb, it is possible to apply a back bias to a pair of n-type transistors including the n-type transistors PD_L and PD_R.

  Memory cell MC2 further includes an n-type transistor PG_L having one of the source / drain connected to data node Nd_L of data holding circuit DH and the other of the source / drain connected to bit line node bt, and data holding circuit DH One source / drain is connected to the data node Nd_R, and an n-type transistor PG_R is connected to the bit line node bb. The gates of n-type transistor PG_L and n-type transistor PG_R are connected to word line node wl, and the back gates of both transistors are connected to back gate node vssb.

  A data write operation of the memory cell MC2 by the monitor cell write circuit ARY_WT included in the leak monitor circuit LEAK_MON1_4 of FIG. 24 will be described with reference to FIG.

  The data setting signal set_data is set to a high level, and the monitor cell write circuit ARY_WT is set to the data write mode. When the data selection signal sel_data is set to the high level, the cell power supply wiring arvss_l4 and the cell power supply wiring arvss_r4 are set to the high level (power supply voltage vdd1norm) and the low level (the voltage obtained by adding the bias voltage Δvss to the power supply voltage vss), respectively. Is done.

  When the cell power supply line arvss_l4 changes to high level, the source of the n-type transistor PD_L of the memory cell MC2 in the monitor cell array ARY4 becomes high level. At the same time, when the cell power supply line arvss_r4 changes to the low level, the source of the n-type transistor PD_R of the memory cell MC2 becomes the low level. As a result, in all the memory cells MC2 included in the monitor cell array ARY4, the data node Nd_L and the data node Nd_R of each data holding circuit DH are simultaneously set to the high level and the low level. When the data selection signal sel_data is set to the low level, the voltages of the cell power supply line arvss_l4 and the cell power supply line arvss_r4 are opposite to the above case, and the data node Nd_L and the data node Nd_R of the data holding circuit DH are set to the low level and the high level. Each is set. As a result, the same data can be simultaneously written into all the memory cells MC2.

  The monitor cell array ARY4 illustrated in FIG. 24 corresponds to, for example, the monitor cell array ARY2 illustrated in FIG. This is because when the data setting signal set_data of the monitor cell write circuit ARY_WT is set to a low level, the output voltage of the array VSS generation circuit ARVSS_GEN1 is applied to the power supply node arvss_l and the power supply node arvss_r. If the cell power supply wiring vssb4 is connected to the power supply wiring VSS, it corresponds to the monitor cell array ARY1. In the memory cell MC2, when it is difficult to separate the power supply node arvss into the power supply node arvss_l and the power supply node arvss_r for convenience of cell layout, the power supply node arvdd is separated into the power supply node arvdd_l and the power supply node arvdd_r and controlled. It doesn't matter.

The effect of the leak monitor circuit LEAK_MON1_4 will be described.
The leak current of the memory cell MC shown in FIG. 4 depends on the data held in the memory cell MC. The memory cell MC activated (powered on) by applying the power supply voltage holds data for which the leakage current is reduced. Therefore, when this memory cell MC is used in the monitor cell array ARY4 shown in FIG. 24, the leak current of the memory cell array CELL_ARRAY set in the standby mode is not accurately reflected. Although it is conceivable to write data into the monitor cell array ARY4 after power-on by the peripheral circuit PERI similar to the memory cell array CELL_ARRAY, the overhead for the circuit and write time for that is large.

  On the other hand, the leak monitor circuit LEAK_MON1_4 includes a monitor cell write circuit ARY_WT having a simple circuit configuration. This monitor cell write circuit ARY_WT makes it possible to rewrite the data held in the memory cell MC2 immediately after power-on to the same data at the same time. As a result, the leak current of the monitor cell array ARY4 can be brought close to a value reflecting the leak current of the memory cell array CELL_ARRAY.

<Embodiment 5>
The configuration of the semiconductor device LSI according to the fifth embodiment will be described with reference to FIG.

  The semiconductor device LSI according to the fifth embodiment compares the case where the back bias is applied to the p-type transistor constituting the memory cell MC with the leak monitor circuit LEAK_MONj and the case where it is not applied, and based on the comparison result (monitor signal result_monj). The standby mode of the memory module RAM_MODj is controlled by the regulator circuit REG_POWER and the cell power supply voltage control circuit ARVDD_CTL1.

  The semiconductor device LSI includes a memory module RAM_MODj, a leak monitor circuit LEAK_MONj, a monitor control circuit MON_CTLj, and a standby mode setting circuit RS_CTL. The memory module RAM_MODj includes a memory cell array CELL_ARRAY, a peripheral circuit PERI, and a cell power supply voltage control circuit ARVDD_CTL1. The configuration of the peripheral circuit PERI and the supply control of the power supply voltage vddj and the power supply voltage vss are the same as those shown in FIG.

  The memory module RAM_MODj is set to the normal operation mode and the standby mode, respectively, when the control signal rsj is at the low level and the high level. The standby mode of the memory module RAM_MODj is set to the RS mode and the LVRS mode, respectively, when the control signal ram_rs_cntj is low level and high level. The RS mode is a state in which the power supply voltage vdd1norm is applied to the back gate node vddb and a voltage obtained by lowering the power supply voltage vdd1norm by the bias voltage Δvdd is applied to the power supply node arvdd in the circuit diagram of the memory cell MC illustrated in FIG. means. The LVRS mode means a state where a voltage obtained by lowering the power supply voltage vdd1norm by the bias voltage Δvdd is applied to the back gate node vdb and the power supply node arvdd. In memory cell MC in both standby modes, power supply voltage vss is applied to power supply node arvss and back gate node vssb.

  The cell power supply voltage control circuit ARVDD_CTL1 is connected to the power supply wiring vddj and the cell power supply wiring arvddc, and controls the voltage value of the cell power supply wiring arvddc in response to the control signal pstb_mode. The NOR circuit NOR outputs, as a control signal pstb_mode, a NOR processing signal of a signal obtained by inverting the logic level of the control signal rsj by the inverter INV4 and the control signal ram_rs_cntj.

  The memory cell array CELL_ARRAY is supplied with the output of the cell power supply voltage control circuit ARVDD_CTL1 and the power supply voltage vddj via the cell power supply wiring arvddc and the cell power supply wiring vddbc, respectively, and via the cell power supply wiring arvssc and the cell power supply wiring vssbc. Thus, the power supply voltage vss is supplied. That is, the output of the cell power supply voltage control circuit ARVDD_CTL1 and the power supply voltage vddj are respectively applied to the power supply node arvdd and back gate node vddb of the memory cell MC, and both the power supply node arvss and back gate node vssb are supplied with power. A voltage vss is applied.

  The leak monitor circuit LEAK_MONj has a monitor cell array ARY1 and a monitor cell array ARY2 set in the RS mode and the LVRS mode, and outputs a comparison result of leak current values in each monitor cell array as a monitor signal result_monj. The standby mode setting circuit RS_CTL controls the voltage value of the output voltage vddj of the regulator circuit REG_POWER and the standby mode of the memory module RAM_MODj based on the monitor signal result_monj.

  With reference to FIG. 27, a specific configuration of cell power supply voltage control circuit ARVDD_CTL1 provided in the semiconductor device LSI according to the fifth embodiment will be described.

  FIG. 27A is a circuit diagram of a cell power supply voltage control circuit ARVDD_CTL1A which is a first specific example of the cell power supply voltage control circuit ARVDD_CTL1. The node Ncp1a is connected to the drains of the p-transistor PSW_ARY, the p-type transistor PDIOD, and the p-type transistor PRESI, and the node Ncp2a is connected to the sources of these transistors. The p-type transistor PSW_ARY operates as a power switch whose conduction state is controlled based on the logic level of the control signal pstb_mode applied to its gate. P-type transistor PDIOD operates as a MOS diode whose gate and drain are both connected to node Ncp1a. The p-type transistor PRESI has a power supply voltage vss applied to its gate and operates as a resistor having a predetermined impedance.

  When the control signal pstb_mode is at a low level, the p-type transistor PSW_ARY is in a conductive state (a state where the power switch is closed), and the power supply voltage vdd1 is applied to the cell power supply wiring arvddc. When the control signal pstb_mode is at a high level, the p-type transistor PSW_ARY is in a non-conducting state (a state in which the power switch is opened), and the voltage of the cell power supply wiring arvddc drops from the power supply voltage vdd1. The falling voltage is determined by the current flowing through the cell power supply line arvddc, the diode-connected p-type transistor PDIOD, and the p-type transistor PRESI operating as a resistor. Note that the p-type transistor PRESI may be omitted as necessary.

  FIG. 27B is a circuit diagram of a cell power supply voltage control circuit ARVDD_CTL1B which is a second specific example of the cell power supply voltage control circuit ARVDD_CTL1. The node Ncp1b is connected to the drains of the p-type transistor PSWD and the p-type transistor PRESI, and the node Ncp2b is connected to the sources of these transistors. The p-type transistor PRESI has a power supply voltage vss applied to its gate and operates as a resistor. The drain and the source of the p-type transistor PDG are connected to the drain and the gate of the p-type transistor PSWD, respectively, and the conduction state is controlled by the control signal pstb_mode. A power supply voltage vss is applied to the source of the n-type transistor ND, and its drain is connected to the gate of the p-type transistor PSWD. The control signal pstb_mode is connected to the gate of the n-type transistor ND.

  When the control signal nstb_mode is at a high level, the p-type transistor PDG is turned off and the n-type transistor ND is turned on. As a result, the p-type transistor PSWD is turned on, and the power supply voltage vdd1 is applied to the cell power supply wiring arvddc. When the control signal pstb_mode is at a low level, the n-type transistor ND is in a non-conductive state, but the p-type transistor PDG is in a conductive state, and the voltage of the cell power supply line arvddc drops below the power supply voltage vdd1. The falling voltage is determined by the current flowing through the cell power supply line arvddc, the diode-connected p-type transistor PSWD, and the p-type transistor PRESI operating as a resistor. Note that the p-type transistor PRESI may be omitted as necessary.

  With reference to FIG. 28, the configuration of leak monitor circuit LEAK_MON1_5 provided in the semiconductor device LSI according to the fifth embodiment will be described.

  The leak monitor circuit LEAK_MON1_5 includes a monitor cell array ARY1, a monitor cell array ARY2, a monitor voltage supply circuit ARVSS_SPLY, a comparator COMP5, and an array VDD generation circuit ARVDD_GEN1.

  The monitor cell array ARY1 includes a predetermined number of memory cells MC. The power supply node arvdd, the bit line node bt, and the bit line node bb of each memory cell MC are connected to the cell power supply line arvdd1. The array VDD generation circuit ARVDD_GEN1 generates a voltage obtained by stepping down the power supply voltage vdd1norm by the bias voltage Δvdd and applies it to the cell power supply wiring arvdd1. The word line node wl, the power supply node arvss, and the back gate node vssb of each memory cell MC are connected to the cell power supply line arvss1, and the voltage is controlled by the monitor voltage supply circuit ARVSS_SPLY. A power supply voltage vdd1norm is applied to the back gate node vddb.

  The monitor cell array ARY2 includes the same number of memory cells MC as the memory cells MC included in the monitor cell array ARY1. The power supply node arvdd, back gate node vddb, bit line node bt, and bit line node bb of each memory cell MC are connected to the cell power supply line arvdd2. The output voltage of the array VDD generation circuit ARVDD_GEN1 is applied to the cell power supply wiring arvdd2. The word line node wl, the power supply node arvss, and the back gate node vssb of each memory cell MC are connected to the cell power supply line arvss2.

  A back bias of the bias voltage Δvdd is applied to the p-type transistors PU_L and PU_R constituting the memory cell MC included in the monitor cell array ARY1 by the output voltage of the array VDD generation circuit ARVDD_GEN1. On the other hand, the output voltage of the array VDD generation circuit ARVDD_GEN1 is applied to both the power supply node arvdd and the back gate node vddb of the p-type transistor constituting the memory cell MC included in the monitor cell array ARY2, and no back bias is applied.

  The monitor voltage supply circuit ARVSS_SPLY has a drain connected to the cell power supply line arvss1, an n-type transistor ARVSS_PWS1 to which the power supply voltage vss is applied to the source, a drain connected to the cell power supply line arvss2, and a power supply voltage vss applied to the source. N-type transistor ARVSS_PWS2. The conduction states of the n-type transistors ARVSS_PWS1 and ARVSS_PWS2 are both controlled by the control signal arvss_en applied to the gates. The monitor voltage supply circuit ARVSS_SPLY supplies the power supply voltage vss to the monitor cell arrays ARY1 and ARY2 only during the period when the control signal arvss_en is at the high level.

  When the control signal arvss_en changes from the high level to the low level, the supply of the power supply voltage vss to the cell power supply line arvss1 and the cell power supply line arvss2 is cut off. When the supply of the power supply voltage vss is cut off, the voltage of the cell power supply wiring arvss1 starts to rise from the power supply voltage vss due to the leakage current of the monitor cell array ARY1 set in the RS mode. On the other hand, the voltage of the cell power supply wiring arvss2 starts to rise from the power supply voltage vss due to the leakage current of the monitor cell array ARY2 set in the LVRS mode.

  The voltages of the cell power supply line arvss1 and the cell power supply line arvss2 are input to the comparator COMP as the measurement output imageas1 and the measurement output imageas2. The comparator COMP compares the magnitudes of the measurement output imageas1 and the measurement output imageas2, and outputs the result as a monitor signal result_mon1 to the standby mode setting circuit RS_CTL.

  With reference to FIG. 34, the configuration of comparator COMP5 provided in the semiconductor device LSI according to the fifth embodiment will be described.

  The comparator COMP5 includes a selector IN_SEL5, a selector IN_SEL6, a ring oscillator ROS5, a ring oscillator ROS6, a selector OUT_SEL5, a selector OUT_SEL6, a counter CNT1, a counter CNT2, and a digital comparison circuit DIG_CMP. The comparator COMP5 is different from the comparator COMP21 shown in FIG. 14 in the following points. The ring oscillators ROS5 and ROS6 included in the comparator COMP5 are different from the ring oscillators ROS1 and ROS2 included in the comparator COMP21 illustrated in FIG. 14 in that the conductivity types of the transistors to which the measurement output images1 and the measurement output images2 are applied to the gates are switched. It is a configuration.

  The ring oscillator ROS5 is a ring oscillator in which inverters composed of p-type transistors P511 and P512 and an n-type transistor N511 are connected in cascade in a predetermined number of stages, and the inverter output of the final stage is input to one of the NAND circuits G51. In the p-type transistor P511, the power supply voltage vdd1norm is applied to the source, and the drain is connected to the drain of the p-type transistor P512. The signal of either the measurement output imageas1 or the measurement output imageas2 selected by the selector IN_SEL5 is applied to the gate of the p-type transistor P511 via the signal line gin5.

  The drain of the p-type transistor P512 is connected to the drain of the n-type transistor N511, and the power supply voltage vss is applied to the source of the n-type transistor N511. The gates of the p-type transistor P512 and the n-type transistor N511 are connected to the output of the NAND circuit G51. A control signal ros_en for controlling the oscillation of the ring oscillator ROS5 is input to the other input of the NAND circuit G51.

  The ring oscillator ROS6 has the same configuration as the ring oscillator ROS5, and the gate of the p-type transistor P521 is connected to the other of the measurement output images1 and the measurement output images2 selected by the selector IN_SEL6 via the signal wiring gin6. A signal is applied. A control signal ros_en for controlling the oscillation of the ring oscillator ROS6 is input to the other input of the NAND circuit G52 of the ring oscillator ROS6.

The operation of the comparator COMP5 will be described.
When the selection signal sel is set to the low level, the selector IN_SEL5 outputs the measurement output imageas1 to the ring oscillator ROS5, and the selector IN_SEL6 outputs the measurement output imageas2 to the ring oscillator ROS6. Over a predetermined period activated by the control signal ros_en, the ring oscillator ROS5 outputs an output signal ros_out5 having an oscillation frequency determined by the measurement output imageas1, and the ring oscillator ROS6 has an oscillation frequency determined by the measurement output imageas2. The output signal ros_out6 having the same is output.

  The selector OUT_SEL5 selects the output signal ros_out5 and outputs it to the counter CNT1, and the selector OUT_SEL6 selects the output signal ros_out6 and outputs it to the counter CNT2. Over a predetermined period activated by the control signal ros_en, the counter CNT1 counts the number of oscillations of the output signal ros_out5, and the counter CNT2 counts the number of oscillations of the output signal ros_out6.

  When the selection signal sel is set to a high level, the selector IN_SEL5 outputs the measurement output imageas2 to the ring oscillator ROS5, and the selector IN_SEL6 outputs the measurement output imageas1 to the ring oscillator ROS6. Again, over a predetermined period activated by the control signal ros_en, the ring oscillator ROS5 outputs an output signal ros_out5 having an oscillation frequency determined by the measurement output imageas2, and the ring oscillator ROS6 is an oscillation determined by the measurement output imageas1. An output signal ros_out6 having a frequency is output.

  The selector OUT_SEL5 selects the output signal ros_out6 and outputs it to the counter CNT1, and the selector OUT_SEL6 selects the output signal ros_out5 and outputs it to the counter CNT2. Over a predetermined period activated by the control signal ros_en, the counter CNT1 accumulates the count value in the period when the selection signal sel is at the low level, and counts the number of oscillations of the output signal ros_out6 corresponding to the measurement output imageas1. The counter CNT2 accumulates the count value during the period when the selection signal sel is at the low level, and counts the number of oscillations of the output signal ros_out5 corresponding to the measurement output imageas2.

  The outputs of the counter CNT1 and the counter CNT2 are compared by the digital comparison circuit DIG_CMP, and the magnitude comparison result of the measurement output imageas1 and the measurement output imageas2 is output to the standby mode setting circuit RS_CTL as the monitor signal result_mon1.

  When the leak current of the monitor cell array ARY1 set in the RS mode is larger than the leak current of the monitor cell array ARY2 set in the LVRS mode, the voltage increase rate of the cell power supply line arvss1 is larger than that of the cell power supply line arvss2. Therefore, when the measurement output imageas1 is larger than the measurement output imageas2, the standby mode setting circuit RS_CTL sets the memory module RAM_MOD1 to the LVRS mode with a smaller leakage current.

  A method in which the regulator circuit REG_POWER and the standby mode setting circuit RS_CTL set the memory module RAM_MOD1 to the RS mode and the LVRS mode based on the monitor signal result_mon1 will be described with reference to FIGS.

  In the RS mode, each node of the memory cell MC shown in FIG. 4 needs to be set as follows. That is, the power supply node arvdd is set to a voltage lower than the power supply voltage vdd1norm by the bias voltage Δvdd, the back gate node vdd is set to the power supply voltage vdd1norm, and the power supply node arvss and the back gate node vssb are set to the power supply voltage vss. In the RS mode, the regulator circuit REG_POWER sets the power supply voltage vdd1 to the power supply voltage vdd1norm based on the control signal vdd1_cnt output from the standby mode setting circuit RS_CTL. Accordingly, the power supply voltage vdd1norm is applied to the back gate node vddb.

  When the memory module RAM_MOD1 is set to the RS mode, the control signal pstb_mode becomes high level based on the control signal rs1 and the control signal ram_rs_cnt1 output from the standby mode setting circuit. Therefore, when the cell power supply voltage control circuit ARVDD_CTL1 is the cell power supply voltage control circuit ARVDD_CTL1A shown in FIG. 27A, the voltage of the node Ncp1a falls below the bias voltage Δvdd with respect to the voltage of the node Ncp2a (power supply voltage vdd1norm). As a result, the voltage of the cell power supply line arvddc connected to the node Ncp1a, that is, the voltage of the power supply node arvdd of the memory cell MC is set to a value obtained by lowering the power supply voltage vdd1norm by the bias voltage Δvdd. On the other hand, the voltage of the back gate node vssb of the memory cell MC connected to the cell power supply wiring vssbc and the power supply node arvss of the memory cell MC connected to the cell power supply wiring arvssc are set to the power supply voltage vss. As a result, the memory cell MC is set to the RS mode.

  In the LVRS mode, each node of the memory cell MC shown in FIG. 4 needs to be set as follows. That is, the voltage of the power supply node arvdd and the back gate node vddb is set to a voltage obtained by lowering the bias voltage Δvdd from the power supply voltage vdd1norm, and the power supply node arvss and the back gate node vssb are set to the power supply voltage vss. In the LVRS mode, the regulator circuit REG_POWER sets the power supply voltage vdd1 to a voltage that is lower than the power supply voltage vdd1norm by the bias voltage Δvdd.

  When the memory module RAM_MOD1 is set to the LVRS mode, the control signal pstb_mode becomes low level based on the control signal rs1 and the control signal ram_rs_cnt1 output from the standby mode setting circuit RS_CTL, and the voltage of the node Ncp1a of the cell power supply voltage control circuit ARVDD_CTL1A is It is set to the same voltage as the voltage of the node Ncp2a (the voltage that is lowered by the bias voltage Δvdd from the power supply voltage vdd1norm). On the other hand, the voltage of the back gate node vssb of the memory cell MC connected to the cell power supply wiring vssbc and the power supply node arvss of the memory cell MC connected to the cell power supply wiring arvssc are set to the power supply voltage vss.

  As described above, based on the monitor signal result_mon1, the regulator circuit REG_POWER and the standby mode setting circuit RS_CTL set the memory module RAM_MOD1 to the RS mode or the LVRS mode. Even when the cell power supply voltage control circuit ARVDD_CTL1 is the cell power supply voltage control circuit ARVDD_CTL1B shown in FIG. 27B, the voltage of the cell power supply wiring arvddc is controlled in the same manner as described above.

  The monitor voltage supply circuit ARVSS_SPLY is not limited to the circuit configuration shown in FIG. 28, and ARVDD_SPLYA shown in FIG. 7 or ARVDD_SPLYB shown in FIG. 8 can be used by appropriately changing the conductivity type of the transistors constituting the circuit. Further, the comparator COMP is not limited to the one using the ring oscillator shown in FIG. 34, and the current detection circuit using the comparator COMP1 and the operational amplifier shown in FIG. Can be used.

The effect of the leak monitor circuit LEAK_MON1_5 according to the fifth embodiment will be described.
By comparing the magnitude of the leakage current depending on the presence or absence of the back bias of the p-type transistor constituting the memory cell MC, an optimal leakage reduction method can be selected according to the difference in temperature, voltage, and threshold voltage, and the memory module RAM_MOD1 Leakage current can be minimized.

<Embodiment 6>
With reference to FIG. 29, a configuration of leak monitor circuit LEAK_MON1_6 provided in the semiconductor device LSI according to the sixth embodiment will be described.

  Leak monitor circuit LEAK_MON_1_6 can be applied to a leak monitor circuit including monitor voltage supply circuit ARVDD_SPLYC shown in FIG. 9 in the semiconductor device LSI according to each embodiment and its modification.

  Monitor voltage supply circuit ARVDD_SPLYC included in leak monitor circuit LEAK_MON1_6 in FIG. 29 supplies power supply voltage vdd1norm from node Na31 and node Na32 to monitor cell array ARY1 and monitor cell array ARY2, respectively. The comparator COMP detects the measurement output imageas1 and the measurement output image2 that are decreased by the leakage current of the monitor cell array ARY1 and the monitor cell array ARY2 after the supply of the power supply voltage vdd1norm by the p-type transistor ARVDD_PWS1 and the p-type transistor ARVDD_PWS2 is cut off by the comparator COMP. To do.

  When the leakage current of the monitor cell array ARY1 and the monitor cell array ARY2 is large and the voltage change of the cell power supply line arvss1 is fast, the measurement accuracy of the comparator COMP is affected by the coupling between the cell power supply lines of the monitor cell array ARY1 and the monitor cell array ARY2. May get worse. In order to reduce the influence of this coupling, the leak monitor circuit LEAK_MON1_6 has a stabilization capacitor arvss_cap connected to the cell power supply lines of the monitor cell arrays ARY1 and ARY2.

  The leak monitor circuit LEAK_MON1_5 according to the fifth embodiment shown in FIG. 28 cuts off the power supply voltage vss1 applied to the cell power supply line arvss1 and the cell power supply line arvss2 included in the monitor cell array ARY1 and the monitor cell array ARY2, thereby increasing or decreasing the leak current. It has the structure which compares. In this case, it is effective to connect a stabilization capacitor to the cell power supply wiring arvdd1 and the cell power supply wiring arvdd2.

<Embodiment 7>
With reference to FIG. 30, the configuration of the semiconductor device LSI according to the seventh embodiment will be described.

  The semiconductor device LSI includes a memory module RAM_MODj to which a power supply voltage vddj and a power supply voltage vss are applied, a standby mode setting circuit RS_CTL, a monitor control circuit MON_CTLj, and a leak monitor circuit LEAK_MONj.

  The memory module RAM_MODj includes a memory cell array CELL_ARRAY, a peripheral circuit PERI, a cell power supply voltage control circuit ARVDD_CTL2, and a cell power supply voltage control circuit ARVSS_CTL2. The peripheral circuit PERI has a row decoder, a word driver, a column decoder, a column selection switch, a sense amplifier, a write driver, and other control circuits necessary for writing and reading data to and from the memory cell array CELL_ARRAY.

  The cell power supply voltage control circuit ARVDD_CTL2 is connected to the power supply wiring vddj and the cell power supply wiring arvddc, and controls the voltage value of the cell power supply wiring arvddc in response to the control signal rsj, the control signal ram_rs_cntj_1, and the control signal ram_rs_cntj_2. The cell power supply voltage control circuit ARVSS_CTL2 is connected to the power supply wiring vss and the cell power supply wiring arvssc, and the voltage value of the cell power supply wiring arvssc in response to the control signal rsj inverted by the inverter INV, the control signal ram_rs_cntj_1, and the control signal ram_rs_cntj_2 To control. The memory cell array CELL_ARRAY is connected to the cell power supply line arvddc, the cell power supply line arvssc, the cell power supply line vddbc to which the power supply voltage vddj is applied, and the cell power supply line vssbc to which the power supply voltage vss is applied.

  The power supply wiring Icvss for supplying the power supply voltage to the peripheral circuit PERI is connected to the power supply wiring vss via the n-type transistor NSW_PERI. A signal obtained by inverting the logic level of the control signal rsj by the inverter INV is applied to the gate of the n-type transistor NSW_PERI.

  The leak monitor circuit LEAK_MONj has a monitor cell array ARY1, compares the leak current value in each standby mode set in the monitor cell array ARY1, and sets the standby mode in which the leak current is minimum to the standby mode setting circuit RS_CTL as the monitor signal result_monj. Output. The standby mode setting circuit RS_CTL outputs the control signal rsj, the control signal ram_rs_cntj_1, and the control signal ram_rs_cntj_2 to the memory module RAM_MOD1 based on the monitor signal result_monj, so that the leakage current of the memory module RAM_MOD1 is minimized. The ARVDD_CTL2 and the cell power supply voltage control circuit ARVSS_CTL2 are controlled.

  With reference to FIG. 31, a specific configuration of leak monitor circuit LEAK_MON1_7 provided in the semiconductor device LSI according to the seventh embodiment will be described.

  The leak monitor circuit LEAK_MON1_7 includes a monitor cell array ARY1, a monitor voltage supply circuit ARVDD_SPLYD, an array VSS generation circuit ARVSS_GEN3, an array VDD generation circuit ARVDD_GEN3, a ring oscillator ROS1, a level shifter LSF, and a counter CTN1.

  The monitor cell array ARY1 includes a predetermined number of memory cells MC. The power supply node arvdd, the bit line node bt, and the bit line node bb of each memory cell MC are connected to the cell power supply line arvdd1. The power supply node arvss is connected to the cell power supply line arvss1, and the output voltage of the array VSS generation circuit ARVSS_GEN3 is applied to the cell power supply line arvss1. The back gate node vddb is connected to the cell power supply line vddb1, and the power supply voltage vdd1norm is applied to the cell power supply line vddb1. The word line node wl and the back gate node vssb are connected to the cell power supply wiring vssb1, and the power supply voltage vss is applied to the cell power supply wiring vssb1.

  The monitor voltage supply circuit ARVDD_SPLYD has a p-type transistor ARVDD_PWS1 in which the output voltage of the array VDD generation circuit ARVDD_GEN3 is applied to the source, the drain is connected to the cell power supply line arvdd1, and the control signal arvdd_en is applied to the gate. The ring oscillator ROS1 has the same circuit configuration as that shown in FIG. 11, and the voltage fluctuation amount of the cell power supply line arvdd1 of the monitor cell array ARY1 after the supply of the power supply voltage vdd1norm is cut off for a predetermined time set by the control signal ros_en. The number of oscillations of the ring oscillator ROS1 is converted. The level shifter LSF converts the amplitude of the output voltage of the ring oscillator ROS1 to the power supply voltage applied to the counter CNT1, and outputs the converted voltage to the counter CNT1. The counter CNT1 outputs the stored count number as an output signal ros_out.

  With reference to FIG. 32, an operation mode of the memory module RAM_MOD1 provided in the semiconductor device LSI according to the seventh embodiment will be described.

  The operation mode is set based on the control signal rs1, the control signal ram_rs_cnt1_1, and the control signal ram_cnt1_2. When the control signal rs1 is at the low level, the memory module RAM_MOD1 is set to the normal operation mode regardless of the values of the control signal ram_rs_cnt1_1 and the control signal ram_cnt1_2. When the control signal rs1 is at a high level, the memory module RAM_MOD1 is set to three standby modes by the combination of the logic levels of the control signals ram_rs_cnt1_1 and ram_cnt1_2.

  When the control signal ram_rs_cnt1_1 is high level and the control signal ram_rs_cnt1_2 is low level, the memory module RAM_MOD1 is in the RS1 mode, the control signal ram_rs_cnt1_1 is low level, the control signal ram_rs_cnt1_2 is in the RS1 mode control signal s When both ram_rs_cnt1_2 are at a high level, the RS3 mode is set.

  The cell power supply voltage control circuit ARVDD_CTL2 and the cell power supply voltage control circuit ARVSS_CTL2 in each operation mode output voltages applied to the cell power supply wiring arvddc and the cell power supply wiring arvssc in the following combinations. In the normal operation mode, vdd1norm and vss are set, in the RS1 mode, in vdd1norm and vss + Δvss2, in the RS2 mode, set in vdd1norm−Δvdd1 and vss + Δvss1, and in the RS3 mode, set in vdd1norm−Δvdd2 and vss, respectively.

  Here, Δvdd1 and Δvdd2 are bias voltages, and are set to 0.1 V and 0.2 V, respectively, as an example. Δvss1 and Δvss2 are bias voltages, and are set to 0.1 V and 0.2 V, respectively, as an example. When the power supply voltage vdd1norm and the power supply voltage vss are 1.0 V and 0 V, the voltage between the cell power supply line arvddc and the cell power supply line arvssc in the normal operation mode is 1.0 V, whereas the RS1 mode and the RS2 mode And the voltage between the cell power supply line arvddc and the cell power supply line arvssc in the RS3 mode are both set to 0.8V.

  The node voltage of the memory cell MC (see FIG. 4) in each operation mode will be described. As shown in FIG. 30, the power supply voltage vdd1 is applied to the memory cell array CELL_ARRAY via the cell power supply wiring vddbc, and the power supply voltage vss is applied via the cell power supply wiring vssbc. Therefore, the power supply voltage vdd1norm is applied to the back gate node vddb of the memory cell MC connected to the cell power supply wiring vddbc, and the power supply voltage vssb is applied to the back gate node vssb connected to the cell power supply wiring vssbc.

  In the normal operation mode, the power supply voltage vdd1norm is applied to the power supply node arvdd of the memory cell MC connected to the cell power supply wiring arvddc, and the power supply voltage vsss is applied to the power supply node arvss connected to the cell power supply wiring arvssc. In the RS1 mode, power supply voltage vdd1norm, power supply voltage vss + bias voltage Δvss2 are applied to power supply node arvdd and power supply node arvss, respectively. In the RS2 mode, the power supply node arvdd and the power supply node arvss are applied with the power supply voltage vdd1norm−the bias voltage Δvdd1 and the power supply voltage vss + the bias voltage Δvss1, respectively. In the RS3 mode, power supply voltage vdd1norm−bias voltage Δvdd2 and power supply voltage vss are applied to power supply node arvdd and power supply node arvss, respectively.

  That is, the back bias of the bias voltage Δvss2 (0.2 V) is applied to the n-type transistor of the memory cell MC in the RS1 mode, and the subthreshold leakage current flowing through the n-type transistor is reduced. A state in which a back bias of a bias voltage Δvss1 (0.1 V) is applied to the n-type transistor of the memory cell MC in the RS2 mode, and a back bias of a bias voltage Δvdd1 is applied to the p-type transistor of the memory cell MC Therefore, the subthreshold leakage current of the n-type transistor and the p-type transistor is reduced. A back bias of a bias voltage Δvdd2 (0.2 V) is applied to the p-type transistor of the memory cell MC in the RS3 mode, and the subthreshold leakage current flowing through the p-type transistor is reduced.

  With reference to FIG. 31, a method for measuring the leakage current of monitor cell array ARY1 set in each standby mode will be described.

  The array VSS generation circuit ARVSS_GEN3 and the array VDD generation circuit ARVDD_GEN3 output the power supply voltage in the following three combinations. The first combination is the power supply voltage vss + bias voltage Δvss2 and the power supply voltage vdd1norm, and this combination corresponds to the RS1 mode. The second combination is the power supply voltage vss + the bias voltage Δvss1 and the power supply voltage vdd1norm−the bias voltage Δvdd1, and this combination corresponds to the RS2 mode. The third combination is the power supply voltage vss and the power supply voltage vdd1norm−bias voltage Δvdd2, and this combination corresponds to the RS3 mode.

  With the array VDD generation circuit ARVDD_GEN3 and the array VSS generation circuit ARVSS_GEN3 supplied with the RS1 mode power supply voltage to the monitor cell array ARY1, the control signal arvdd_en is set from the low level to the high level to supply the power supply voltage to the monitor cell array ARY1. Shut off. Over a predetermined period after the power supply voltage is cut off, the amount of change in potential of the cell power supply wiring arvdd1 is converted into the number of oscillations of the ring oscillator ROS1, and counted by the counter CNT1. Thereafter, the array VDD generation circuit ARVDD_GEN3 and the array VSS generation circuit ARVSS_GEN3 sequentially apply the RS2 mode and RS3 mode power supply voltages to the monitor cell array ARY1, and the number of oscillations of the ring oscillator ROS1 in each mode is measured by the counter CNT1. Note that the order of the standby modes set in the monitor cell array ARY1 may be changed as appropriate.

  In each standby mode, the ring oscillator ROS1 is supplied with the same output voltages of the array VDD generation circuit ARVDD_GEN3 and the array VSS generation circuit ARVSS_GEN3 as the monitor cell array ARY1. Further, the difference between the output voltages of the array VDD generation circuit ARVDD_GEN3 and the array VSS generation circuit ARVSS_GEN3 in each standby mode is set to be the same. Therefore, the output of the ring oscillator ROS1 is not affected by the power supply voltage applied in each standby mode, and has the number of oscillations determined by the voltage fluctuation amount of the cell power supply wiring arvdd1 in each standby mode. Accuracy is ensured.

  Among the three standby modes of the RS1 mode, the RS2 mode, and the RS3 mode, the output signal ros_out of the counter CNT1 is maximized in the standby mode in which the leak current of the monitor cell array ARY1 is minimized. Accordingly, the output signal ros_out of the counter CNT1 measured in each standby mode is compared by a comparison circuit (not shown), the standby mode corresponding to the maximum value of the output signal ros_out is determined, and is output to the standby mode setting circuit RS_CTL as the monitor signal result_mon1. To do.

  Based on the monitor signal result_mon1, the standby mode setting circuit RS_CTL determines the values of the control signal ram_rs_cnt1_1 and the control signal ram_rs_cnt1_2 corresponding to the standby mode to be set in the memory module RAM_MOD1, the cell power supply voltage control circuit ARVDD_CTL2, and the cell power supply voltage control circuit ARVSS_CTL2. Output to.

The effect of the semiconductor device LSI according to the seventh embodiment will be described.
The standby mode of the memory cell array CELL_ARRAY is set in consideration of the subthreshold leakage currents of the p-type transistor and the n-type transistor constituting the memory cell MC. Therefore, even when the threshold voltages of the p-type transistor and the n-type transistor fluctuate due to fluctuations in the manufacturing process of the semiconductor device LSI, it is possible to set a standby mode in which the leakage current of the memory cell array CELL_ARRAY is minimized.

  In the semiconductor device LSI according to each embodiment and the modification thereof, the generation of the monitor signal result_mon1 by the comparator COMP and the optimization of the standby mode may be performed even while the central processing unit CPU1 maintains the standby mode. it can. The leakage current of the memory module RAM_MOD1 can be controlled more finely by appropriately resetting the standby mode once set to an appropriate standby mode that matches the operating environment of the semiconductor device LSI.

  In addition, in a comparator using a ring oscillator and a counter as shown in FIG. 11, the count difference of the measurement result is stored and compared with the count difference when separately measured. It is determined that the leakage reduction effect by the standby method is very small, and switching is not performed. When switching is not performed, the count difference of the current measurement result is discarded, and the currently stored count difference is held as it is. When the count difference becomes equal to or greater than a certain value, the count number is used as retained data. Such control makes it possible to avoid an increase in power due to unnecessary control.

  In each of the embodiments, the regulator circuit is provided outside the semiconductor device LSI. However, the semiconductor circuit in the semiconductor device LSI, for example, the same semiconductor as the central processing unit CPU1 to the specific circuit function block IP2 each including the memory module RAM_MODj. It may be provided in the chip.

In addition, a part of the contents described in the embodiment will be described below.
(1) A semiconductor device includes a memory cell array including a plurality of memory cells each having a first power supply node, a second power supply node, and a third power supply node, and a first monitor having a predetermined number of memory cells set in a first standby mode. A monitor circuit including a cell array and a second monitor cell array having a predetermined number of memory cells set to the second standby mode, and a standby mode setting circuit for setting the standby mode of the memory cell array. The memory cell includes a first first conductivity type transistor having a source and a drain connected to a first power supply node and a first data node, and a backgate connected to a backgate node; a second power supply node; A source and a drain are connected to the second data node, and a second first conductivity type transistor is connected to the back gate node. The monitor circuit corresponds to one of the first standby mode and the second standby mode based on a comparison result between the voltage of the third power supply node in the first monitor cell array and the voltage of the third power supply node in the second monitor cell array. Output the monitor signal. The standby mode setting circuit generates a standby mode selection signal in response to the monitor signal, and the memory cell array is set to one of the first standby mode and the second standby mode in response to the standby mode selection signal. The

  (2) In the semiconductor device of (1), in response to the data selection signal, the monitor circuit sets the first data node to the voltage of either the first state or the second state, and sets the second data node to It has a monitor cell write circuit which is set to the other voltage of the first state or the second state.

  (3) A semiconductor device includes a memory cell array having a plurality of memory cells each having a first power supply node and a second power supply node, a monitor circuit having a monitor cell array having a predetermined number of memory cells, and a standby for setting a standby mode of the memory cell array A mode setting circuit. The memory cell includes a first conductivity type transistor having a source, a drain, and a back gate connected to a first power supply node, a first data node, and a first back gate node, respectively, a second power supply node, and a first data And a second conductivity type transistor having a source, a drain, and a back gate connected to the node and the second back gate node, respectively. The monitor circuit includes a voltage of the second power supply node in the monitor cell array set to the first standby mode, a voltage of the second power supply node in the monitor cell array set to the second standby mode, and a monitor set to the third standby mode. A monitor signal corresponding to any of the first standby mode, the second standby mode, and the third standby mode is output based on the comparison result of the voltage of the second power supply node in the cell array. The standby mode setting circuit generates a standby mode selection signal in response to the monitor signal. The memory cell array is set to one of the first standby mode, the second standby mode, and the third standby mode in response to the standby mode selection signal.

  (4) The semiconductor device of (3) further includes a first cell power supply voltage control circuit and a second cell power supply voltage control circuit. The first power supply node is connected to the output of the first cell power supply voltage control circuit, and the second power supply node is connected to the output of the second cell power supply voltage control circuit. In response to the standby mode, the first cell power supply voltage control circuit and the second cell power supply voltage control circuit apply a back bias to the first conductivity type transistor when the memory cell array is set to the first standby mode. When the second standby mode is set, a back bias is applied to the first conductivity type transistor and the second conductivity type transistor, and when the third standby mode is set, a back bias is applied to the second conductivity type transistor. .

  (5) In the semiconductor device of (4), the monitor circuit further includes a monitor voltage supply circuit, a first bias generation circuit, and a second bias generation circuit, the first power supply node of each memory cell in the monitor cell array, the first The two power supply nodes and the first back gate node are connected to the first cell power supply wiring, the second cell power supply wiring, and the third cell power supply wiring, respectively. A monitor voltage is applied to the second back gate node. The first bias generation circuit supplies the first array bias voltage or the second array bias voltage to the first cell power supply wiring. The second bias generation circuit supplies the third array bias voltage or the fourth array bias voltage to the second cell power supply wiring via the monitor voltage supply circuit.

  (6) A semiconductor device includes a ring oscillator in which a plurality of inverters each including a switching unit that inverts and outputs a logic level of an input signal and a current control unit that controls a current of the switching unit are connected in cascade, and an output of the ring oscillator A counter for counting the number of oscillations of the signal, the impedance of each current control unit in the ring oscillator is controlled by an input signal, and the first counter counts the number of oscillations of the first output signal in a predetermined period.

(7) In the semiconductor device of (6), the value of the input signal varies in a predetermined period.
(8) In the semiconductor device of (6), the inverter further includes a bias current unit that supplies a predetermined current to the switching unit.

  (9) The semiconductor device of (6) includes a timer in which a plurality of inverters each including a switching unit and a constant current supply unit that supplies a constant current to the switching unit are connected in a ring, and the oscillation frequency of the output signal of the timer is It is larger than the oscillation frequency of the output signal of the output signal of the ring oscillator.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  arvdd power node, arvdd_en control signal, ARVDD_SPLYA, ARVDD_SPLYB, ARVDD_SPLYC, ARVDD_SPLYD, ARVSS_SPLY monitor voltage supply circuit, arvdd1, arvdd2, arvdd3, arvdd4, arvsdc, arvsd cell power v , Arvss_r4, arvss1, arvss2, arvss3, arvssc cell power supply wiring, ARY1, ARY2, ARY3, ARY4 monitor cell array, bb, bt bit line node, CPU1, CPU2 central processing unit, DH data holding circuit, dig_comp_en control signal, fix_sig voltage, cvss power supply wiring, imageas1, images2, imagex measurement output, IP1, IP2 specific function circuit block, LAR1, LAR2, LARY1, LARY2 monitor logic array, lcvss power supply wiring, logic_offset signal, LSF level shifter, LSI semiconductor device, MC, MC2 memory cell , MON_CTL1, MON_CTL2, MON_CTL3, MON_CTL4, MON_CTLj, monitor control circuit, mon_en1, mon_enj, monitor enable signal, Nd_L, Nd_R data node, nstb_mode, pstb_mode, ram_cnt1_2, control signal, PMOD, RAM Memory module, ref1, ref2 reference voltage, reset, reset_meas_time reset signal, result_mon, result_mon1, result_monj monitor signal, ROS, ROS_T, ROS1, ROS2, ROS3, ROS4, ROS5, ROS6 ring oscillator, ros_en T rsj control signal, sel_data data selection signal, SEL_PWS1, SEL_PWS2 selector, sele selection signal, set_data data setting signal, tieh voltage, vdd1_cnt control signal, vdd1norm, vdd1, vdd2, vdd3, vdd1 power supply, vdd4, vdd1 power supply Cell power Line, Vddbc cell power supply lines, Vddj_cnt control signal, VDDM supply voltage, vref1 reference voltage, VSSB back gate node, vssb1, vssb2, vssb3, vssb4, vssbc cell power supply lines.

Claims (20)

A memory cell array including a plurality of memory cells connected to the first power supply wiring and the second power supply wiring; and a mode setting circuit for selectively setting the first standby mode and the second standby mode for the memory cell array, respectively. With
The memory cell has a first conductivity type first transistor having a source connected to the first power supply line, a drain connected to a first data node, and a gate connected to a second data node, and a source connected to the second power supply line. And a drain connected to the first data node, a gate connected to the second data node, a second conductivity type second transistor, a source connected to the first power line, and a drain connected to the second data node. A third transistor of a first conductivity type with a gate connected to the first data node, a source to the second power line, a drain to the second data node, and a gate to the first data node, respectively. A second transistor of the second conductivity type connected,
When the first standby mode is set by the mode setting circuit, a first power supply voltage is supplied to the first power supply wiring, and a second power supply voltage is supplied to the second power supply wiring,
When the second standby mode is set by the mode setting circuit, a third power supply voltage is supplied to the first power supply wiring, and a fourth power supply voltage is supplied to the second power supply wiring,
The third power supply voltage has a voltage value between the first power supply voltage and the second power supply voltage;
The semiconductor device, wherein the second power supply voltage has a voltage value between the third power supply voltage and the fourth power supply voltage. When the first standby mode is set by the mode setting circuit, the fourth power supply voltage is supplied to the respective back gates of the second transistor and the fourth transistor, and the first transistor, The first power supply voltage is supplied to each back gate of the third transistor,
When the second standby mode is set by the mode setting circuit, the fourth power supply voltage is supplied to the respective back gates of the second transistor and the fourth transistor, and the first transistor, The semiconductor device according to claim 1, wherein the second power supply voltage is supplied to each back gate of the third transistor. The first conductivity type is p-type, the second conductivity type is n-type,
The third power supply voltage is lower than the first power supply voltage and higher than the second power supply voltage;
The semiconductor device according to claim 2, wherein the fourth power supply voltage is lower than the second power supply voltage. A cell power supply voltage control circuit connected to the first power supply wiring;
The mode setting circuit supplies the fourth power supply voltage to the second power supply wiring when the memory cell array is set in a normal operation mode, and also supplies the first power supply wiring from the cell power supply voltage control circuit to the first power supply wiring. The semiconductor device according to claim 1, wherein one power supply voltage is supplied. A first monitor cell; a second monitor cell; and a monitor circuit that generates a signal for instructing the mode setting circuit to set the first standby mode or the second standby mode. ,
The first monitor cell is
A fifth transistor of the first conductivity type having a source connected to the third power supply line, a drain connected to the third data node, a gate connected to the fourth data node, and a back gate connected to the third power supply line;
The source is connected to the fourth power supply line, the drain is connected to the third data node, the gate is connected to the fourth data node, and the back gate is connected to the fifth power supply line to which a voltage higher than the fourth power supply voltage is applied. A second transistor of the second conductivity type;
A first conductivity type seventh transistor having a source connected to the third power supply line, a drain connected to the fourth data node, a gate connected to the third data node, and a back gate connected to the third power supply line;
A second conductivity type eighth transistor having a source connected to the fourth power supply line, a drain connected to the fourth data node, a gate connected to the third data node, and a back gate connected to the fifth power supply line; Have
The second monitor cell is
A ninth transistor of the first conductivity type having a source connected to the sixth power supply line, a drain connected to the fifth data node, a gate connected to the sixth data node, and a back gate connected to the sixth power supply line;
A second conductivity type tenth transistor having a source connected to the seventh power supply line, a drain connected to the fifth data node, a gate connected to the sixth data node, and an eighth power supply line connected to the back gate;
An eleventh transistor of the first conductivity type having a source connected to the sixth power supply line, a drain connected to the sixth data node, a gate connected to the fifth data node, and a back gate connected to the sixth power supply line;
A twelfth conductivity type twelfth transistor having a source connected to the seventh power supply line, a drain connected to the sixth data node, a gate connected to the fifth data node, and a back gate connected to the eighth power supply line; Have
A voltage is applied to the fifth power supply wiring so that the back gate with respect to the source of each of the sixth transistor and the eighth transistor is reverse-biased,
The same voltage is applied to the seventh power supply wiring and the eighth power supply wiring,
The monitor circuit is connected to the fourth power supply wiring and the sixth power supply wiring, and specifies whether the mode setting circuit sets the first standby mode or the second standby mode. The semiconductor device according to claim 1, further comprising a circuit that generates a signal. A memory cell array comprising a plurality of memory cells each having a first power supply node and a second power supply node;
A monitor circuit comprising: a first monitor cell array having a predetermined number of the memory cells set in the first standby mode; and a second monitor cell array having the predetermined number of the memory cells set in a second standby mode;
A standby mode setting circuit for setting a standby mode of the memory cell array,
The memory cell includes a first conductivity type transistor having a source and a drain connected to the first power supply node and the first data node, and a back gate connected to a back gate node,
The monitor circuit includes the first standby mode and the second standby based on a comparison result between the voltage of the second power supply node in the first monitor cell array and the voltage of the second power supply node in the second monitor cell array. Output a monitor signal corresponding to one of the modes,
The standby mode setting circuit generates a standby mode selection signal in response to the monitor signal,
The semiconductor device, wherein the memory cell array is set to one of the first standby mode and the second standby mode in response to the standby mode selection signal.   When the memory cell array is set to the first standby mode, a back bias of a first bias voltage is applied to the first conductivity type transistor, and when the memory cell array is set to the second standby mode, The semiconductor device according to claim 6, wherein no back bias is applied to the first conductivity type transistor. A power supply voltage control circuit connected to the first power supply wiring, the second power supply wiring, and the first power supply wiring;
In the memory cell of the memory cell array, the first power supply node is connected to an output of the cell power supply voltage control circuit, the second power supply node is connected to the second power supply wiring, and the back gate node is connected to the first power supply line. Connected to the power supply wiring,
When the memory cell array is set to the first standby mode, the cell power supply voltage control circuit applies a back bias of the first bias voltage to the first conductivity type transistor in response to the standby mode selection signal. Controlling the voltage of the first power supply node to
When the memory cell array is set to the second standby mode, the cell power supply voltage control circuit makes the voltage of the first power supply node equal to the voltage of the first power supply line in response to the standby mode selection signal. 8. The semiconductor device according to claim 7, wherein the semiconductor device is controlled. The standby mode setting circuit outputs a voltage control signal in response to the monitor signal,
In response to the voltage control signal, a voltage between the first power supply node and the second power supply node in the second standby mode is between the first power supply node and the second power supply node in the first standby mode. The semiconductor device according to claim 8, wherein a voltage of the second power supply wiring is controlled so that the first bias voltage decreases with respect to a voltage. In the monitor circuit, the first power supply node, the second power supply node, and the back gate node of each memory cell in the first monitor cell array include a first cell power supply line, a second cell power supply line, and a third cell power supply line. Each connected to the cell power wiring,
The first power supply node, the second power supply node, and the back gate node of each memory cell in the second monitor cell array are a fourth cell power supply wiring, a fifth cell power supply wiring, and a sixth cell power supply wiring, respectively. The semiconductor device according to claim 6, which is connected. The monitor circuit further includes a bias voltage generation circuit that generates an array bias voltage,
In the first monitor cell array, a back bias of an array bias voltage is applied to the first conductivity type transistor,
The semiconductor device according to claim 10, wherein no back bias is applied to the first conductivity type transistor in the second monitor cell array. The monitor circuit further includes a monitor voltage supply circuit and a comparator,
The monitor voltage supply circuit supplies a first monitor voltage to the second cell power supply line, a second monitor voltage to the fifth cell power supply line, and a voltage of the second cell power supply line. Output the voltage of the power supply wiring as the first measurement output and the second measurement output,
The semiconductor device according to claim 11, wherein the comparator outputs a comparison result between the first measurement output and the second measurement output as the monitor signal. The monitor circuit further includes a monitor voltage supply circuit and a comparator,
The monitor voltage supply circuit supplies a first monitor voltage to the second cell power line and the fifth cell power line, and the voltage of the second cell power line and the voltage of the fifth cell power line are Output as the first measurement output and the second measurement output,
The semiconductor device according to claim 11, wherein the comparator outputs a comparison result between the first measurement output and the second measurement output as the monitor signal. The comparator includes a first ring oscillator, a second ring oscillator, a first counter, a second counter, and a comparison circuit;
The oscillation frequency of the first ring oscillator is controlled by the first measurement output;
The oscillation frequency of the second ring oscillator is controlled by the second measurement output,
The first counter counts the number of oscillations of the first ring oscillator in a predetermined period after the supply of the first monitor voltage to the second cell power supply line is cut off,
The second counter counts the number of oscillations of the second ring oscillator in the predetermined period after the supply of the first monitor voltage to the fifth cell power supply line is cut off;
The semiconductor device according to claim 13, wherein the comparison circuit compares the count values of the first counter and the second counter and outputs the result as the monitor signal. The comparator includes a first ring oscillator, a second ring oscillator, a first input selector, a second input selector, a first counter, a second counter, and a comparison circuit,
When the selector selection signal is in the first state, the oscillation frequency of the first ring oscillator is controlled by the first measurement output selected by the first input selector, and the oscillation frequency of the second ring oscillator is Controlled by the second measurement output selected by the two-input selector, the first counter oscillates the first ring oscillator during a predetermined period after the supply of the first monitor voltage to the second cell power supply line is cut off. And the second counter counts the number of oscillations of the second ring oscillator in the predetermined period after the supply of the first monitor voltage to the fifth cell power supply line is cut off.
When the selector selection signal is in the second state, the oscillation frequency of the first ring oscillator is controlled by the second measurement output selected by the first input selector, and the oscillation frequency of the second ring oscillator is The first counter is controlled by the first measurement output selected by the second input selector, and the first counter is controlled by the second ring oscillator in a predetermined period after the supply of the first monitor voltage to the second cell power supply line is cut off. Counting the number of oscillations, the second counter counts the number of oscillations of the first ring oscillator in the predetermined period after the supply of the first monitor voltage to the fifth cell power supply line is cut off,
The comparison circuit compares the accumulated value of the first counter and the accumulated count value of the second counter when the selector selection signal is in the first state and the second state, and outputs the result as the monitor signal The semiconductor device according to claim 14. The comparator includes a ring oscillator, an input selector, a first counter, a second counter, and a comparison circuit,
When the selector signal is in the first state, the number of oscillations of the ring oscillator is controlled by the first measurement output, and the first counter is predetermined after the supply of the first monitor voltage to the second cell power supply line is cut off. Count the number of oscillations of the ring oscillator in the period,
When the selector signal is in the second state, the number of oscillations of the ring oscillator is controlled by the second measurement output, and the second counter is provided after the supply of the first monitor voltage to the fifth cell power supply line is cut off. Count the oscillation frequency of the ring oscillator in the predetermined period,
The semiconductor device according to claim 14, wherein the comparison circuit compares the count values of the first counter and the second counter and outputs the result as the monitor signal. A memory cell array comprising a plurality of memory cells each having a first power supply node and a second power supply node;
A monitor circuit comprising a monitor cell array having a predetermined number of the memory cells;
A standby mode setting circuit for setting a standby mode of the memory cell array,
The memory cell includes a first conductivity type transistor having a source and a drain connected to the first power supply node and the first data node, and a back gate connected to a back gate node,
The monitor circuit compares the voltage of the second power supply node in the monitor cell array set to the first standby mode with the voltage of the second power supply node in the monitor cell array set to the second standby mode. And outputting a monitor signal corresponding to one of the first standby mode and the second standby mode,
The standby mode setting circuit generates a standby mode selection signal in response to the monitor signal,
The semiconductor memory device, wherein the memory cell array is set to one of the first standby mode and the second standby mode in response to the standby mode selection signal.   The first power supply node, the second power supply node, and the back gate node of each memory cell in the monitor cell array are connected to a first cell power supply wiring, a second cell power supply wiring, and a third cell power supply wiring, respectively. The semiconductor device according to claim 17. The monitor circuit further includes a bias voltage generation circuit that generates an array bias voltage, and a selector,
The selector outputs a first power supply voltage and the array bias voltage when the selector selection signal is in the first state and the second state,
The array bias voltage is applied to the first power supply node,
When the selector selection signal is in the first state, the monitor cell array is set to the first standby mode in which the first power supply voltage is applied to the back gate node;
19. The semiconductor device according to claim 18, wherein when the selector selection signal is in the second state, the monitor cell array is set in the second standby mode in which the array bias voltage is applied to the back gate node. The monitor circuit further includes a first monitor logic array having a predetermined number of logic circuits, a second monitor logic array having a predetermined number of logic circuits, and a bias voltage generation circuit for generating an array bias voltage,
A high-order power supply wiring of the logic circuit in the first monitor logic array is connected to the second power supply node in the first monitor cell array;
A higher power supply wiring of the logic circuit in the second monitor logic array is connected to the second power supply node in the second monitor cell array;
A first power supply voltage is applied to the first power supply node in the first monitor cell array and the lower power supply wiring of the logic circuit in the first monitor logic array,
The array bias voltage is applied to the first power supply node in the second monitor cell array and the lower power supply wiring of the logic circuit in the second monitor logic array,
The monitor circuit includes the first standby mode and the second standby based on a comparison result between the voltage of the second power supply node in the first monitor cell array and the voltage of the second power supply node in the second monitor cell array. Output a monitor signal corresponding to one of the modes,
The standby mode setting circuit generates a standby mode selection signal in response to the monitor signal,
The semiconductor device according to claim 6, wherein the memory cell array is set to one of the first standby mode and the second standby mode in response to the standby mode selection signal.

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