JP2013247357A - Multilayer electronic structure with integral stepped stack structures - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer electronic structure which comprises an integral stepped via stack structure and is excellent in electrical connectivity and heat dissipation.SOLUTION: A multilayer electronic support structure 450 comprises a plurality of layers extending in an X-Y plane consisting of a dielectric material 410 surrounding metal via posts 400 that conduct in a Z direction perpendicular to the X-Y plane. A stacked via structure crossing at least two via layers of the plurality of layers comprises at least two via posts in neighboring via layers. The at least two stacked via posts in neighboring layers have different dimensions in the X-Y plane, such that the stacked via structure tapers.

Description

      The present invention is directed to improved interconnect structures, and in particular, but not limited to, integrated stepped via stacks and methods for their fabrication.

      Driven by the ever-increasing demand for miniaturization of increasingly complex electronic components, consumer electronics such as computers and telecommunications equipment are becoming more integrated. This has created a need for support structures such as IC substrates and IC interposers having a high density of multiple conductive layers and vias that are electrically isolated from each other by a dielectric material.

      The general requirements for this type of support structure are reliability and adequate electrical performance, thinness, stiffness, flatness, good heat dissipation and competitive unit cost.

      Of the various approaches to achieve these requirements, one widely realized manufacturing technique that creates interconnect vias between layers is the subsequent filling with metal, usually copper, deposited therein by plating techniques. For this purpose, a laser is used to drill through to the last metal layer in the subsequently placed dielectric substrate. This approach of creating vias is sometimes referred to as “drill and fill” and the vias created thereby can be referred to as “drill and fill vias”.

      The drill and fill via approach has several drawbacks. Since each via needs to be drilled separately, the processing rate is limited and the cost of fabricating sophisticated multi-via IC substrates and interposers is prohibitively high. With large arrays, it is difficult to produce high density high quality vias with different sizes and shapes in close proximity to each other by drill and fill methodologies. In addition, laser drilled vias have rough sidewalls and tapers inside through the thickness of the dielectric material. This tapering reduces the effective diameter of the via. It may also adversely affect electrical contact to the previous conductive metal layer, especially with ultra-small via diameters, thereby causing reliability problems. Moreover, where the perforated dielectric is a composite material comprising a polymer matrix glass or ceramic fiber, the sidewalls are particularly rough, and this roughness can create additional stray inductances.

      The process of filling the drilled via hole is usually achieved by electroplating of copper. Electroplating deposition techniques can lead to recess formation, where a small crater appears at the top of the via. Alternatively, overfill may occur where the via channel is filled with more copper than it can hold, and a hemispherical top surface is created that protrudes above the surrounding material. As needed when fabricating high density substrates and interposers, both recess formation and overfill tend to create difficulties when subsequently stacking vias one after the other. Furthermore, it will be appreciated that large via channels are difficult to fill uniformly, especially when they are in close proximity to smaller vias within the same interconnect layer of an interposer or IC board design. That is.

      Although the range of accepted sizes and reliability has improved over time, the above drawbacks are inherent in drill and fill technology and are expected to limit the range of possible via sizes. It is further noted that laser drilling is best for creating round via channels. Although slot-shaped via channels can theoretically be fabricated by laser milling, in practice the range of geometric shapes that can be fabricated is somewhat limited and within a given support structure The vias are generally cylindrical and substantially identical.

      Drill and fill via fabrication is expensive and it is difficult to uniformly and consistently fill via channels created by copper using a relatively cost effective electroplating process.

The size of vias drilled into the composite dielectric material is practically limited to a diameter of about 60 × 10 ⁻⁶ m, and nevertheless the required removal process results in the composite material being drilled. It suffers from significant tapering due to depth due to the nature, as well as rough sidewalls.

      In addition to the other limitations of laser drilling described above, the via channels are different when via channels of different drilling sizes are drilled and then filled with metal to produce different sized vias. There is an additional limitation of drill and fill technology in that it is difficult to fabricate vias of different diameters in the same layer because they fill at speed. Thus, the typical challenge of recess formation or overfill characterizing drill and fill technology is exacerbated, as it is impossible to simultaneously optimize the deposition technique for different sized vias. Thus, in practice, all drill and fill vias in a single layer are nominally the same diameter, although affected by removal and tapering.

      One alternative to overcoming many of the shortcomings of the drill and fill approach is to create vias by depositing copper or other metal into the pattern created in the photoresist, also known as “pattern plating” technology It is.

      In pattern plating, a seed layer is first deposited. A layer of photoresist is then placed on the seed layer and then exposed to create a pattern that is selectively removed to create a trench that exposes the seed layer. Via pillars are created by depositing copper in the photoresist trenches. The remaining photoresist is then removed, the seed layer is etched away, and a dielectric material, typically a polymer impregnated glass fiber prepreg, is laminated over and around the via post. Various techniques and processes are then used to remove a portion of the dielectric material, thereby planarizing and thinning the structure, exposing the top of the via post, and then building the next metal layer there Thereby, a conductive connection to ground can be made possible. By repeating this process to build the desired multilayer structure, subsequent layers of metal conductors and via posts can be deposited thereon.

      In an alternative but closely related technique, hereinafter known as “panel plating”, a continuous layer of metal or alloy is deposited onto the substrate. A layer of photoresist is deposited thereon, the pattern is developed therein, the developed photoresist pattern is stripped, selectively exposing the metal beneath it, which is then etched away Can do. Undeveloped photoresist protects the underlying metal from being etched away, leaving upright patterns and via patterns.

      After stripping the undeveloped photoresist, a dielectric material such as a polymer-impregnated glass fiber mat can be laminated around and on the upstanding copper features and / or via posts.

      Via layers created by the pattern plating or panel plating methodologies described above are generally known as “via pillars” and feature layers derived from copper.

      It will be appreciated that the overall driving force of the evolution of microelectronics is directed towards producing increasingly reliable, smaller, thinner and lighter and more powerful products. That is. The use of thick, cored interconnects prevents ultra-thin products from being reachable. In order to create increasingly denser structures within interconnect IC boards or “interposers”, increasingly more layers of increasingly smaller connections are required. In fact, sometimes it is desirable to stack components on top of each other.

      If the plated laminate structure is deposited on copper or other suitable sacrificial substrate, the substrate can be etched away, leaving a free standing coreless layered structure. Additional layers can be deposited on the side previously bonded to the sacrificial substrate, thereby allowing double-sided build-up, which helps minimize warpage and achieve planarity.

      One flexible technique for fabricating high density interconnects is to build a pattern or panel plated multilayer structure of metal vias or features in a dielectric matrix. The metal can be copper and the dielectric can be a fiber reinforced polymer, typically a polymer with a high glass transition temperature (Tg), such as polyimide, is used. These interconnects can have a core or be coreless and can include cavities for stacking components. They can have odd or even layers. The enabling technology is described in a previous patent granted to Amitec-Advanced Multilayer Interconnect Technologies.

      For example, U.S. Pat. No. 6,057,836 to Hurwitz et al. Describes a method of fabricating a free-standing film that includes a via array in a dielectric for use as a precursor in the construction of a superior electronic support structure. . It includes fabricating a film of conductive vias within the dielectric perimeter on the sacrificial carrier and separating the film from the sacrificial carrier to form a free-standing stacking array. Electronic substrates based on this type of free-standing film can be formed by thinning and planarizing the stacking arrangement and can continue to terminate the vias. This publication is incorporated herein in its entirety.

      U.S. Pat. No. 6,057,049 to Hurwitz et al. Is a method for fabricating an IC support for supporting a first IC die connected in series with a second IC die, the IC The support comprises a stack of alternating layers of copper features and vias in an insulating perimeter, the first IC die can be bonded onto the IC support, and the second IC die is within the cavity within the IC support A method is described which is bondable and the cavities are formed by etching away the copper base and selectively etching away the built-up copper. This publication is incorporated herein in its entirety.

      (Patent Document 3) granted to Hurwitz et al. Includes the following steps: (A) selecting a first base layer; and (B) a first etchant barrier on the first base layer. Depositing layers; (C) constructing a first half stack of alternating conductive and insulating layers, wherein the conductive layers are interconnected by vias through the insulating layers; and (D) first Applying a second base layer onto one half stack; (E) applying a protective coating of photoresist to the second base layer; and (F) etching away the first base layer. (G) removing the protective coating of the photoresist; (H) removing the first etchant barrier layer; and (I) alternating conductive layers and insulation. Constructing a second half stack, wherein the conductive layers are interconnected by vias through the insulating layer, the second half stack having a substantially symmetric layup on the first half stack; , (J) applying an insulating layer over the second half stack of alternating conductive layers and insulating layers; (K) removing the second base layer; and (L) vias on the outer surface of the stack. Terminating the substrate by exposing an end of the substrate and adding a termination to the substrate. This publication is incorporated herein in its entirety.

US Pat. No. 7,682,972, entitled “Advanced Multilayer Coreless Support Structures and Methods for Their Production” US Pat. No. 7,669,320, entitled “Coreless cavity substrates for chip packaging and their fabrication” U.S. Pat. No. 7,635,641, entitled “Integrated Circuit Support Structures and their Fabrication”

      One aspect of the present invention is a multilayer electronic support structure comprising a plurality of layers extending in an XY plane made of a dielectric material surrounding a metal via pillar conducting in a Z direction perpendicular to the XY plane, Stacked via structures that traverse at least two via layers of the plurality of layers comprise at least two via pillars in adjacent via layers, and the stacked via structures are adjacent so that they are tapered This at least two stacked via posts in the layer thus directed are directed to providing a structure having different dimensions in the XY plane.

      In some embodiments, the stacked via structure comprises at least three via posts.

      In some embodiments, each layer of stacked via structures is rectangular, each subsequent layer extends in one direction less than each previous layer, and stacked via structures are in one direction. It has a stepped outer shape.

      In some embodiments, each layer of the stacked via structure is rectangular, each subsequent via extends less than each previous via in two opposite directions, and the stacked via structure is generally trapezoidal. Has a shape.

      In some embodiments, each layer of the stacked via structure is rectangular, each subsequent via extends less than each previous via in three opposite directions, and the stacked via structure has three It has a generally pyramidal shape with stepped diagonal sides and one substantially smooth side perpendicular to the top and bottom surfaces of the multilayer composite electronic structure.

      In some embodiments, each layer of the stacked via structure is rectangular, each subsequent via extends less than each previous layer in four opposite directions, and the stack has a generally stepped pyramid shape .

      In some embodiments, each layer of the stacked via structure is circular, each subsequent via extends less than each previous via, and the stacked via structure has a generally stepped conical shape. Have

      In some embodiments, the multilayer electronic support structure comprises at least four vias.

      In some embodiments, the multilayer electronic support structure comprises at least 5 vias.

      In some embodiments, at least one metal layer comprises a metal seed layer.

      In some embodiments, the seed layer further comprises an adhesive metal layer that is initially placed to enhance adhesion to the dielectric material.

      In some embodiments, the adhesion metal layer comprises at least one of the group comprising titanium, chromium, tantalum and tungsten.

      In some embodiments, the bottom layer in the stacked via structure is at least 30% larger than the top layer.

      In some embodiments, the stacked via structure that traverses at least two layers of the plurality of layers comprises at least two adjacent via pillars, wherein the at least two adjacent via pillars are in the XY plane. And a seed layer inserted between two adjacent via pillars extends further in the XY plane than at least one of the two adjacent via pillars.

      In some embodiments, the seed layer extends further than two adjacent via pillars in the XY plane.

      In some embodiments, at least one of the seed layer and via stack metals comprises copper.

      In some embodiments, the dielectric material comprises a polymer.

      In some embodiments, the dielectric material further comprises a ceramic or glass inclusion.

      In some embodiments, the previous layer of the stack extends further in the XY plane than the subsequent layer, and the stacked via post structure has a generally pyramidal shape.

      In some embodiments, the previous layer of the stack extends in the XY plane less than the range of subsequent layers, and the stack has a generally inverted pyramid shape.

      In some embodiments, the multilayer electronic support structure comprises more than three layers, wherein at least one inner layer extends further than an adjacent outer layer on at least one side, and the stack is said at least one It has an outer shape that bends outward on one side.

      In some embodiments, the multilayer electronic support structure comprises more than three layers, at least one inner layer extends less than an adjacent outer layer on at least one side, and the stack is the at least one It has an outer shape that bends inwardly on one side.

A second aspect of the invention is a process for making a multilayer electronic support structure comprising the following steps:
(A) obtaining a substrate including a lower via layer that is processed to expose an end of the via in the lower via layer;
(B) covering the substrate with a seed layer;
(C) applying a layer of photoresist over the seed layer;
(D) exposing and developing the photoresist to form a negative pattern of features;
(E) depositing metal on a negative pattern to produce a layer of features;
(F) stripping the photoresist, leaving the layer of features upright;
(G) applying a second photoresist layer over the seed layer and the feature layer;
(H) exposing and developing a pattern of vias in the second photoresist layer;
(I) electroplating copper on the second pattern;
(J) stripping the second photoresist layer;
(K) removing the seed layer;
(L) depositing a dielectric material over at least one component in the via layer.

      In some embodiments, the process comprises the further step (m) of thinning the dielectric material to expose at least one component metal.

      In some embodiments, the process comprises a further step (n) of depositing a metal seed layer over the dielectric material thinned by the exposed metal component.

In some embodiments, the multilayer electronic support structure is further characterized by at least one of the following:
(I) the seed layer comprises copper;
(Ii) the metal layer comprises copper;
(Iii) the dielectric material comprises a polymer, and (iv) the dielectric material comprises a ceramic or glass reinforcement.

In some embodiments, the multilayer electronic support structure is further characterized by at least one of the following:
(I) the dielectric layer comprises a polymer selected from the group comprising polyimide, epoxy, bismaleimide, triazine and mixtures thereof;
(Ii) the dielectric layer comprises a glass fiber, and (iv) the dielectric layer comprises a particulate filler.

In some embodiments, the at least one via layer comprises the following steps:
(I) obtaining a substrate comprising a feature layer and having exposed copper;
(Ii) covering the feature layer with a seed layer;
(Iii) depositing a metal layer on the seed layer;
(Iv) applying a layer of photoresist over the metal layer;
(V) exposing and developing a positive pattern of vias in the photoresist;
(Vi) etching away the exposed metal layer;
(Vii) stripping the photoresist, leaving at least one component in the via layer upright;
(Viii) depositing a dielectric material over at least one component in the via layer.

      Optionally, the process includes a further step (ix) of thinning the dielectric material to expose the metal.

      Optionally, the process comprises a further step (x) of depositing a metal seed layer on the ground surface.

The term micron or μm refers to micrometer or 10 ⁻⁶ m.

      For a better understanding of the present invention and to show how it can be put into practice, reference will now be made, by way of example only, to the accompanying drawings.

      The details shown below will be emphasized by specific reference to the drawings in more detail, the details shown being by way of example only and for illustrative discussion of preferred embodiments of the invention, and of the present invention. It is presented to provide what is believed to be the most useful and easily understood description of the principles and conceptual aspects. In this regard, no attempt has been made to show the structural details of the present invention in more detail than is necessary for a basic understanding of the present invention, and how some forms of the present invention are practically problematic. The description is made with reference to the drawings to make it clear to those skilled in the art. In the accompanying drawings:

1 is a simplified cross-sectional view of a prior art multilayer composite support structure. 2 is a schematic cross-sectional view of a trapezoidal stack of vias according to one embodiment of the present invention. FIG. Shown are trapezoidal, pyramidal and conical vias from above. 4 is a cross section of a trapezoidal stack of vias and feature layers according to a second embodiment. and 5 is a flow diagram illustrating one method for fabricating the structure of FIG. and FIG. 5 is a second flow diagram illustrating another method for fabricating a layer of the structure of FIG. 2 or 4.

      In the following description, a supporting structure consisting of copper via posts in a polymer matrix, such as metal vias in a dielectric matrix, in particular polyimide, epoxy or BT (bismaleimide / triazine) or mixtures thereof, reinforced by glass fibers. The body is considered.

      As described in (Patent Document 1), (Patent Document 2), and (Patent Document 3) granted to Hurwitz et al. Incorporated here, there is no effective upper limit in the in-plane dimension of the feature. This is a feature of Access photoresist and pattern or panel plating and lamination techniques.

      FIG. 1 is a simplified cross-sectional view of a prior art multilayer composite support structure. Prior art multilayer support structure 100 includes functional layers 102, 104, 106 of components or features 108 separated by layers of dielectrics 110, 112, 114, 116 that insulate the individual layers. Vias 118 through the dielectric layer provide electrical connections between adjacent functional or feature layers. Accordingly, the feature layers 102, 104, 106 include features 108 and vias 118 that conduct current across the dielectric layers 110, 112, 114, 116 in the XY plane and generally disposed within the layers. The vias 118 are designed to have a minimum inductance and are well separated so as to have a minimum capacitance therebetween.

      Where vias are fabricated by drill and fill techniques, vias generally have a substantially circular cross section because they are fabricated by first drilling a laser hole in the dielectric. Because the dielectric is a heterogeneous and anisotropic polymer matrix with an inorganic filler and glass fiber reinforcement, its circular cross section generally has a rough edge, and its cross section is slightly distorted from a true circular shape become. In addition, vias tend to be somewhat tapered and are inverted frustoconical instead of cylindrical.

      For example, as described in (Patent Document 1), (Patent Document 2), and (Patent Document 3), the structure of FIG. 1 is plated in a pattern in a photoresist (pattern plating), or Alternatively, it can be fabricated by panel plating and then selectively etching, in any case leaving an upstanding via post and then laminating a dielectric prepreg thereon.

      Fabricating non-circular vias using the “drill and fill via” approach is prohibitively expensive due to difficulties in cross-section control and geometry. There is also a minimum via size of about 50-60 microns diameter due to laser drilling limitations. These difficulties have been previously described in detail in the background art, and among others, via formation due to recess formation and / or hemispherical molding due to the copper via fill electroplating process, laser drilling process. Related to tapering geometry and sidewall roughness, and higher cost due to the use of expensive laser drillers to mill the slots in a “routing” mode that creates grooves in the polymer / glass dielectric.

      In addition to the other limitations of laser drilling described above, the via channels differ when drilling different size via channels are drilled and then filled with metal to produce different size vias. There is an additional limitation of drill and fill technology in that it is difficult to create vias of different diameters in the same layer because of the speed filling. Thus, the typical challenge of recess formation or overfill characterizing drill and fill technology is exacerbated, as it is impossible to simultaneously optimize the deposition technique for different sized vias.

In addition, laser drilled vias in composite dielectric materials such as polyimide / glass or epoxy / glass or BT (bismaleimide / triazine) / glass or mixtures thereof with ceramic and / or other filler particles are practical. Is limited to a minimum size of about 60 × 10 ⁻⁶ m in diameter, and still a significant tapering shape due to the nature of the composite material to be drilled as a result of the required removal process , As well as suffering from rough sidewalls.

      Using the flexibility of plating and photoresist techniques, it has been surprisingly found that a wide range of via shapes and sizes can be produced cost-effectively. Furthermore, different via shapes and sizes can be fabricated in the same layer. The private via pillar approach developed by AMITEC enables a “conductor via” structure that takes advantage of the large dimensions of the via layer conducting in the xy plane. This is particularly facilitated when a copper pattern plating approach is used, where smooth, straight, non-tapered grooves are created in the photoresist material, and these are then used with a metal seed layer. The trenches can be filled by subsequent deposition of copper, and then filled by pattern plating of copper into the trenches. In contrast to the drill and fill via approach, the via post technique allows the grooves in the photoresist layer to be filled to obtain a copper connector without a recess and without a hemisphere. After copper deposition, the photoresist is then stripped, the metal seed layer is then removed, and a permanent, polymer glass dielectric is applied over and around. The “via conductor” structure created in this way can use the process flow described in (Patent Document 1), (Patent Document 2) and (Patent Document 3) given to Hurwitz et al.

      With reference to FIG. 2, a cross-sectional view of a tapered stack 200 of via posts is shown. The stack 200 consists of a first layer 202, a second layer 204, a third layer 206 and a fourth layer 208 surrounded by a dielectric material 210.

      Since each layer is deposited on a larger previous layer, it is possible to fabricate each layer by pattern plating on a subsequently deposited layer of photoresist without an intermediate copper conductor or pad in the XY plane.

In one example, it is possible lowermost layer 202 of the stack 200 is 940 × ^{10 -6} m (i.e. micron or μm) × 420x10 ^-6 m. The second layer 204 can be a 840x10 ^-6 m × 320x10 ^-6 m, the third layer 206 can be a ^{740x10 -6 m × 220 × 10 -6} m, and, in the fourth (top) layer 208 can be a 640x10 ^-6 m × 120x10 ^-6 m. Thus, each layer can be wider than 40 to 50 microns compared to the upper layer in all dimensions.

      FIG. 2 shows a trapezoidal stepped via stack including four layers. A trapezoidal stepped via stack tapers or slopes symmetrically in two directions. However, it will be appreciated that, with careful alignment, the stepped via stack can be configured not to be symmetrically inclined or to be inclined in only one direction.

      Referring to FIG. 3, from above, the stepped stack of vias 310 can be rectangular and can be tilted in two directions. Alternatively, the stack 320 can be square and tilted in four directions. Although not shown, it will be appreciated that stacks inclined to one or three dimensions can be fabricated by placing each subsequent layer asymmetrically.

      Furthermore, the stack 330 can comprise a disk-shaped layer and can be conical. Depending on the diameter and alignment of each disk, the stack can be regular or irregular.

      At least two in adjacent layers having different dimensions in the XY plane so that the stacked via structure traverses at least two layers of the plurality of layers in the interconnect structure and the stack tapers. Consists of overlapping via pillars. More generally, the via stack can comprise at least three layers and consist of four or more layers.

      In some embodiments, each layer of the stack is rectangular, each subsequent layer is less than each previous layer, extends in one direction, and the stack comprises a stepped structure in one direction . In other embodiments, each layer of the stack is rectangular, each subsequent layer extends in two opposite directions less than each previous layer, and the stack has a generally trapezoidal shape.

      In yet another embodiment, each layer of the stack is square or rectangular, each subsequent layer is less than each previous layer, extends in three opposite directions, and the stack has three stepped diagonal sides And has a generally pyramidal shape with one substantially smooth side perpendicular to the top and bottom layers.

      In yet another embodiment, each layer of the stack is rectangular, each subsequent layer is less than each previous layer, extends in four opposite directions, and the stack has a generally stepped pyramid shape.

      In some embodiments, each layer of the stack is circular, each subsequent layer extends shorter than each previous layer, and the stack has a generally stepped conical shape.

      In general, as shown in FIG. 1, an interconnect structure typically comprises alternating via layers and feature layers. Using Amitec's private technology, the via layer can also extend in the XY plane and need not be a simple cylindrical column, but can have other shapes.

      Even though the vertical pyramid comprises a layer of metal placed on a more outwardly extending layer, it may be necessary to place features on the dielectric in the area surrounding the interconnect structure. Thus, via layers can be interspersed with feature layers or pads to allow fabrication of tapered via stacks within the interconnect structure. These consist of a seed layer, which can generally be copper, and can be fabricated by sputtering or by electroless plating to adhere to the underlying dielectric. The seed layer can be 0.5 to 1.5 microns thick. On the seed layer, a relatively thick layer or pad of metal, typically copper, can be pattern or panel plated. To further assist the adhesion of the seed layer to the underlying dielectric, a very thin, typically 0.04 to 0.1 micron, adhesive metal such as titanium, tantalum, tungsten, chromium or mixtures thereof The layer can be applied first.

      In some embodiments, the bottom layer in the stack is at least 30% larger than the top layer.

      Referring to FIG. 4, a cross-sectional view of an interconnect structure 450 including a copper via post having a stepped profile and a stack 400 of feature layers is shown. The stack 400 is surrounded by a dielectric material 410. The stack 400 consists of four copper via layers, a first via layer 402, a second via layer 404, a third via layer 406 and a fourth via layer 408, surrounded by a dielectric material 410. Layers 402, 404, 406, 408 can be geometrically separated from each other, but can be electronically coupled together by copper conductors or pads in XY planes 413, 414, and 415. These pads 413, 414 and 415 are part of a feature layer that typically includes surrounding features in other parts of the interconnect structure not shown. Pads 413, 414 and 415 are sputtered to create the indicated stair nose, but more significantly to create surrounding features to allow the feature to be placed on the dielectric. In general, it includes a copper seed layer that can be plated or electrolessly plated and can be 0.5 to 1.5 microns thick. On the seed layer, additional thicknesses of pads or features can be built using electroplating. To further assist adhesion to the dielectric, a very thin layer of adhesive metal, such as titanium, tantalum, chromium, tungsten or mixtures thereof, can be first deposited. This thin adhesive metal layer is typically 0.04 microns to 0.1 microns thick.

      The IC chip 418 can be coupled to the top conductor layer 416 to the stack 400 via a termination 417 such as a ball grid array. The stack 400 thus formed can be a trapezoidal or pyramidal via stack, depending on its shape and whether it slopes in two or four directions. Where the individual layers are circular, the stack can be referred to as a conical via stack. The use of seed layers and alternating feature layers (pads) and vias allows vias 432 and more conventional structures 430 of features 434 to be fabricated together elsewhere in interconnect 450.

      In some embodiments, a stacked via structure that traverses at least two layers of the plurality of layers comprises at least two via posts in an adjacent layer, the at least two stacked in the adjacent layer. Via pillars have different dimensions in the XY plane and a feature layer is inserted between the previous and subsequent layers.

      The feature layer can extend further in the XY plane than at least one of the previous and subsequent layers.

      In some embodiments, the feature layer extends further in the XY plane than either the previous layer or the subsequent layer to give the structure of FIG. 4 or using the same mask, Subsequent via layers can be accurately deposited on the feature layer to provide such a structure as shown in FIG.

      In FIG. 4, the feature layer pads 413, 414, 415, and 416 in the XY plane can be the same size or several microns larger than the underlying via post. If the copper conductor or pad is the same size as the underlying via pillar, the appearance of the stack will be similar to that shown in FIG. 2, however, this manufacturing method will produce a surrounding feature layer and stack. Enable. The copper pad in the top layer 416 can be appropriately sized to an IC (integrated circuit) 418 and coupled to it by interconnect bumps 417 representing flip chip, die bonding or other suitable technology. Can be done. The bottom pad layer 412 (attached to the via post layer 402) can be attached to a printed circuit board (PCB), for example.

      With this type of trapezoidal or pyramidal stack 400 of via posts, the top pad layer 416 can be significantly smaller, perhaps about 28% of the area of the bottom pad layer 412. The via pillar region of the bottom layer 402 can be 3.5 times that of the via pillar top layer 408. One advantage of having such a large lower surface is that it allows for effective heat dissipation, so that the bottom layer 402 can be very useful as a heat sink. However, at the same time, having a small top surface of this type of via stack that can be sized as required by the size of the IC 418 does not significantly reduce the heat dissipation performance of the substrate without the 416 copper pads. The IC high density small pad size typified by is advantageously assisted by the board insertion probability density function by redistributing it to the PCB area pads represented by 412 copper pads.

      It can also be advantageous in that having a relatively small top structure allows more effective utilization of the surrounding surface. For example, components attached to the surrounding surface can be larger.

      Therefore, using the AMITEC technology described in (Patent Document 1), (Patent Document 2) and (Patent Document 3) granted to Hurwitz et al. It is possible to create via pillar structures with various cross-sectional profiles, such as trapezoidal, pyramidal, conical and triangular prism shaped via pillars that can be tilted in one or two directions. Something was found.

      It will be appreciated that where seed and feature layers are used, tapered via stacks can only be fabricated where each subsequently placed layer is smaller than the previous layer. Due to the feature layer allowing features in one layer to protrude beyond the features in the lower layer, a wider (convex) central or narrower (concave) via stack is created in the middle. Can. Via stacks can be deflected in one direction with flat opposing walls in two directions or in three or four directions.

      It will be further appreciated that, using this type of stacking and via pillar approach, via pillars in subsequent layers are x− in order to make the best use of the substrate where a trapezoidal via stack is not required. Tapered (ie trapezoidal or pyramidal) concave and convex via structures can be created very close to the more regular via pillar stack, maintaining its dimensions in the y-plane. It is.

      In some embodiments, the previous layer of the stack extends in the XY plane less than the range of subsequent layers, and the stack has a generally inverted pyramid shape.

      In some embodiments, the multilayer stack of vias in the multilayer electronic support structure comprises more than three layers, with at least one inner layer extending further than an adjacent outer layer on at least one side. The stack has a profile that flexes outwardly on the at least one side.

      In some embodiments, the stack in the multilayer electronic support structure comprises more than three layers, wherein at least one inner layer extends shorter than an adjacent outer layer on at least one side, An outer shape that flexes inwardly on the at least one side surface.

      Therefore, there is a lot of flexibility inherent in the plate and etching and selective pattern plating techniques developed by AMITEC and Access, and is incorporated herein by Hurwitz et al. (Patent Document 1), (Patent Document 2). ) And (Patent Document 3).

      Referring to FIG. 5, in some embodiments, the contoured via stack of FIG. 4 can be fabricated by the following steps: a substrate including a lower via layer that is processed to expose its copper Step (a), and covering the substrate, typically by a copper seed layer and generally by sputtering or by electroless plating-step (b). Optionally, a very thin, perhaps 0.04 to 0.1 micron layer of adhesive metal, such as tantalum, titanium, chromium or tungsten is first deposited before copper is deposited thereon. The A first layer of photoresist is then applied over the seed layer—step (c), and exposed and developed to form a negative pattern—step (d). A metal layer, typically copper, is electroplated into the negative pattern—step (e), and the photoresist is stripped—step (f), leaving the first layer of pads upright. A second photoresist layer can then be applied over the pad—step (g), and a pattern of the second via layer is exposed and developed in the second photoresist layer. -Step (h). A second via layer of metal may be deposited in the second pattern of grooves by either electroplating or electroless plating to create a via layer—step (i) and a second photo The resist layer can be stripped—step (j), stacked in sequence, leaving a stack of two layers, a feature or pad layer followed by a via layer.

      The seed layer is then removed—step (k). Optionally, for example, it is etched away by a wet etch of ammonium hydroxide or copper chloride, and a dielectric material is deposited on the upright copper of the pad and via layers (l).

      In order to allow further buildup of additional layers, the dielectric material can also be thinned to expose the metal by mechanical, chemical or mechanochemical grinding or polishing to flatten the top surface. -Step (m). A metal seed layer, such as copper, can then be deposited on the ground surface—step (n), repeating steps (c) to (n) to build additional layers. to enable.

      The dielectric material is generally a composite material comprising a polymer matrix, such as polyimide, epoxy, bismaleimide, triazine and mixtures thereof, and further glass fibers and ceramic particle fillers, and from knitted glass fibers in a polymer resin. It is generally applied as a prepreg.

      Referring to FIG. 6, in a modified fabrication route, at least one via layer can be fabricated by the following steps: obtaining a substrate including a subfeature feature layer that is polished to expose its copper—step ( i) covering the lower feature layer with a seed layer—step (ii), depositing a metal layer over the seed layer—step (iii), applying a photoresist layer over the metal layer—step (iv), Exposing a positive pattern of vias or features including appropriately sized layers of the contoured stack—step (v), and etching away the exposed metal layer—step (vi). Wet etching, such as a high temperature ammonium hydroxide solution, can be used. The photoresist is then stripped leaving the via / feature containing the layer of the stack upright—step (vii) and a dielectric material is deposited over the via / feature containing the layer of the stack (viii). .

      To allow further build-up, the dielectric layer can be thinned to expose the metal—step (ix). A metal seed layer, such as copper, can then be deposited on the thinned surface—step (x).

      Steps (i) to (x) can be repeated to place additional layers. The pattern plating process route of FIG. 5 can be combined with or alternated with the panel plating process route of FIG. 6 by different layers placed by different processes.

      Adjacent layers of the stack can be somewhat exaggerated, with stepped stacks that can be pyramid, inverted pyramid, bent outward or inward by layers with straight or curved edges give.

      The above description is provided for illustrative purposes only. It will be appreciated that the present invention is capable of many variations.

      Accordingly, those skilled in the art will recognize that the present invention is not limited to what has been particularly described above with reference to the figures. Rather, the scope of the invention is defined by the appended claims and variations and combinations of the various features described above, as well as variations thereof that would readily occur to those skilled in the art upon reading the foregoing description. And both variations.

      In the claims, the terms “comprise” and variations thereof, such as “comprises”, “comprising”, etc. include the recited components, but generally others It is suggested that this is not an exclusion of components.

100 multilayer support structure 102, 104, 106 functional layer or feature layer 108 feature 110, 112, 114, 116 dielectric 118 via 200 stack 202 stack first layer 204 stack second layer 206 stack third layer 208 stack fourth layer 210 Dielectric material 310 Via 320, 330 Stack 400 Stack 402 First via layer 404 Second via layer 406 Third via layer 408 Fourth via layer 410 Dielectric material 412 Bottom pad layer 413, 414, 415 XY plane pad 416 Top conductor layer 417 Termination interconnect bump 418 IC chip 430 structure 432 via 434 feature 450 interconnect structure

Claims (30)

      A multilayer electronic support structure comprising a plurality of layers extending in the XY plane made of a dielectric material surrounding a metal via pillar conducting in a Z direction perpendicular to the XY plane, wherein at least one of the plurality of layers A stacked via structure that traverses two via layers comprises at least two via pillars in adjacent via layers, and the stacked via structures are tapered so that they are tapered. The structure wherein the at least two stacked via pillars have different dimensions in the XY plane.       The multilayer electronic support structure of claim 1, wherein the stacked via structure comprises at least three via posts.       The stacked via structure is rectangular, each subsequent layer extends in one direction less than each previous layer, and the stacked via structure is stepped in one direction The multilayer electronic support structure according to claim 1, wherein the multilayer electronic support structure has an outer shape.       The stacked via structure is rectangular, and each subsequent via extends in two opposite directions less than each previous via, and the stacked via structure has a generally trapezoidal shape. The multilayer electronic support structure according to claim 1.       The stacked via structure is rectangular, and each subsequent via extends less than each previous via in three opposite directions, and the stacked via structure has three stepped diagonals The multilayer of claim 1 having a generally pyramidal shape with a substantially smooth side surface perpendicular to a side surface and a top surface and a bottom surface of the multilayer composite electronic structure. Electronic support structure.       The stacked via structure is rectangular, each subsequent via extends less than each previous via in four opposite directions, and the stack has a generally stepped pyramid shape The multilayer electronic support structure according to claim 1.       2. The shape of claim 1, wherein the vias are circular and each subsequent via extends less than each previous via, and the stacked via structure has a generally stepped conical shape. A multilayer electronic support structure as described.       The multilayer electronic support structure of claim 1, wherein the stacked via structure comprises at least four vias.       The multilayer electronic support structure of claim 1, wherein the stacked via structure comprises at least five vias.       The multilayer electronic support structure of claim 1, wherein the at least one metal layer comprises a metal seed layer.       The multilayer electronic support structure of claim 10, wherein the seed layer further comprises an adhesive metal layer that is initially placed to promote adhesion to the dielectric material.       The multilayer electronic support structure of claim 11, wherein the adhesive metal layer comprises at least one of the group comprising titanium, chromium, tantalum, and tungsten.       The multilayer electronic support structure of claim 1, wherein the bottom layer in the stacked via structure is at least 30% larger than the top layer.       A stacked via structure that traverses at least two layers of the plurality of layers comprises at least two adjacent via posts, wherein the at least two adjacent via posts have different dimensions in the XY plane. And a seed layer inserted between the two adjacent via pillars extends further in the XY plane than at least one of the two adjacent via pillars. The multilayer electronic support structure according to claim 1.       The multilayer electronic support structure of claim 14, wherein the seed layer extends further into the XY plane than the two adjacent via pillars.       The multilayer electronic support structure of claim 15, wherein the seed layer comprises copper.       The multilayer electronic support structure of claim 1, wherein the dielectric material comprises a polymer.       18. The multilayer electronic support structure of claim 17, wherein the dielectric material comprises at least one of the group consisting of glass fibers, ceramic particle inclusions and glass particle inclusions.       The previous via of the stacked via structure extends further into the XY plane than the subsequent via, and the stacked via structure has a generally pyramidal shape. 2. The multilayer electronic support structure according to 1.       The previous via of the stacked via structure extends in the XY plane less than the range of subsequent vias, and the stack has a generally inverted pyramid shape. A multilayer electronic support structure according to 1.       The stacked via structure comprises more than three via layers, at least one inner via extends further than an outer via, and the stacked via structure has the at least one side; The multilayer electronic support structure according to claim 1, wherein the multilayer electronic support structure has an outer shape that bends outward.       The stacked via structure comprises more than three layers, at least one inner via extends less than an adjacent outer via, and the stack is internal on the at least one side The multilayer electronic support structure according to claim 21, wherein the multilayer electronic support structure has a flexible outer shape. The multilayer electronic support structure of claim 1, wherein the at least one via layer comprises the following steps:
(A) obtaining a substrate including said lower via layer that is processed to expose the end of the via in the lower via layer;
(B) covering the substrate with a seed layer;
(C) applying a layer of photoresist over the seed layer;
(D) exposing and developing the photoresist to form a negative pattern of features;
(E) depositing metal on the negative pattern to produce a layer of features;
(F) stripping the photoresist and leaving the layer of features upright;
(G) applying a second photoresist layer over the seed layer and the feature layer;
(H) exposing and developing a pattern of vias in the second photoresist layer;
(I) electroplating copper on the second pattern;
(J) stripping the second photoresist layer;
(K) removing the seed layer;
(L) the structure comprising: the feature comprising the at least one via layer; and depositing a dielectric material over the via.       24. The multilayer electronic support structure of claim 23, wherein the process includes the further step (m) of thinning the dielectric material to expose the metal of the at least one component.       24. The multilayer electronic support structure of claim 23, wherein the process includes the further step (n) of depositing a metal seed layer over the thinned dielectric material with the exposed metal component. body. The multilayer electronic support structure of claim 23,
(I) the seed layer comprises copper;
(Ii) the metal layer comprises copper;
The structure further characterized by at least one of (iii) the dielectric material comprises a polymer, and (iv) the dielectric material comprises a ceramic or glass reinforcement. The multilayer electronic support structure of claim 23,
(I) the dielectric layer comprises a polymer selected from the group comprising polyimide, epoxy, bismaleimide, triazine and mixtures thereof;
A structure further characterized by at least one of (ii) the dielectric layer comprising glass fibers, and (iv) the dielectric layer comprising particulate filler. The multilayer electronic support structure of claim 1, wherein the at least one via layer comprises the following steps:
(I) obtaining a substrate comprising a feature layer and having exposed copper;
(Ii) covering the feature layer with a seed layer;
(Iii) depositing a metal layer on the seed layer;
(Iv) applying a layer of photoresist over the metal layer;
(V) exposing a positive pattern of vias in the photoresist;
(Vi) etching away the exposed metal layer;
(Vii) stripping the photoresist to leave the at least one component in the via layer upright;
And (viii) depositing a dielectric material over the at least one component in the via layer.       29. The multilayer electronic support structure of claim 28, further comprising the further step (ix) of thinning the dielectric material to expose the metal.       29. The multilayer electronic support structure of claim 28, further comprising the further step (x) of depositing a metal seed layer on the ground surface.