JP2013246250A - Tft array substrate and liquid crystal panel with the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal panel of a lateral electric field system, using a TFT array substrate capable of preventing the occurrence of a line defect failure during a manufacturing process and the occurrence of a line defect during the use of a product, in a liquid crystal display device of a lateral electric field system having a configuration for preventing an electric field other than a pixel electrode and a common electrode from influencing a liquid crystal.SOLUTION: In a TFT array substrate 100 used for the liquid crystal panel of a lateral electric field system, a second common electrode 7 is provided separately from a first common electrode 6, on source wiring 2. The second common electrode 7 is provided along the source wiring 2 and independently corresponding to a pixel region, via a substrate protective film 95 on the source wiring 2. In addition, the second common electrode 7 is connected to a second TFT 10 that is different from a first TFT 3 used for driving a pixel electrode 5 and is provided on gate wiring 1 composing the first TFT 3.

Description

  The present invention relates to a TFT (Thin Film Transistor: hereinafter referred to as TFT) array substrate which is a switching element for driving a liquid crystal formed in a horizontal electric field type liquid crystal panel, and a liquid crystal panel using the TFT array substrate. is there.

  A liquid crystal display device equipped with a horizontal electric field type liquid crystal panel has a wider viewing angle than a conventional TN (twisted nematic) type liquid crystal display device, and is IPS (in-plane) due to the structure of the TFT array substrate. Switching: In-Plane Switching (hereinafter referred to as IPS) method and FFS (Fringe Field Switching: hereinafter referred to as FFS) method have been developed.

  Among the horizontal electric field type liquid crystal display devices, for example, an IPS type liquid crystal display device applies an electric field to the liquid crystal between the pixel electrode formed in a comb shape in the pixel region of the TFT array substrate and the common electrode serving as the counter electrode. Thus, the alignment of the liquid crystal is controlled and the transmittance of the liquid crystal panel is controlled.

  Therefore, as a structure of the TFT array substrate, a structure in which an electric field other than the pixel electrode and the common electrode does not affect the liquid crystal has been proposed.

  The liquid crystal display device disclosed in Patent Document 1 discloses a configuration in which a first conductive layer CND1 wider than the drain signal line DL is formed on the drain signal line DL formation region and covers the drain signal line DL. Yes. Thus, light leakage due to an electric field is shielded.

JP 2002-131767 (7th page, FIG. 3)

  Since the lateral electric field type TFT array substrate disclosed in Patent Document 1 is configured to cover the drain signal line DL with the first conductive layer CND1, foreign matter or the like generated in the TFT array manufacturing process is prevented from flowing into the drain signal line. When mixed between DL and the first conductive layer CND1, the insulating film between the drain signal line DL and the first conductive layer CND1 is deficient, insulation between both electrodes is not maintained, and the drain signal line DL and the first conductive layer CND1 are not maintained. One conductive layer CND1 might be short-circuited.

  That is, when foreign matter or the like adheres to the wiring after the formation of the drain signal line DL, there is a portion where the drain signal line DL cannot be sufficiently covered due to the presence of foreign matter in the insulating film to be formed thereafter, and the insulating film is not formed. Occur. When the first conductive layer CND1 is formed thereon, a portion where the insulating film is not formed in the foreign matter portion is generated, so that each drain signal line DL wiring is exposed, and the drain signal line DL and the first conductive layer CND1 are exposed. A portion where the layer CND1 is in direct contact is generated. As a result, a short circuit between the drain signal line DL and the first conductive layer CND1 is caused.

  When the drain signal line DL and the first conductive layer CND1 are short-circuited, the potential of the drain signal line DL becomes substantially the potential of the first conductive layer CND1, and a normal drain signal cannot be supplied. As a result, all the pixels along the drain signal line DL are not displayed. In particular, in the case of the IPS system, a normally black mode that becomes black when the signal is OFF is recognized as a black line defect along the drain signal line DL.

  In the case of an open defect in wiring, it is possible to identify the defect position by electrical inspection or lighting display inspection, so use redundant wiring called repair wiring, modify the wiring by laser repair, etc. Although it is possible to improve the yield, it is difficult to detect the defect position both electrically and in the display state in the case of a short circuit as described above. It was causing a decline.

  In addition, if the short defect is a minute leak, it cannot be detected at the time of manufacture, and the amount of leak gradually increases when the power is turned on after shipment, resulting in a defective line defect during use of the product, causing a quality problem. There was a problem.

  The present invention relates to a horizontal electric field type liquid crystal display device having a configuration for preventing an electric field other than the pixel electrode and the common electrode from affecting the liquid crystal, and has been made to solve the above problems. The present invention aims to obtain a horizontal electric field type liquid crystal panel using a TFT array substrate that can prevent the occurrence of a line defect in the manufacturing process and can prevent the occurrence of a line defect during use of the product. .

  A TFT array substrate and a liquid crystal panel according to the present invention include a source wiring and a gate wiring arranged in a matrix on the substrate, a first TFT (Thin Film Transistor) formed at an intersection of the source wiring and the gate wiring, A pixel electrode connected to the first TFT and arranged in a pixel region surrounded by a source wiring and a gate wiring, and arranged at a predetermined distance from the pixel electrode, and applies a parallel electric field to the substrate together with the pixel electrode. A second common electrode formed along the first common electrode and the source wiring is further provided. The second common electrode extends over the gate wiring, and is a second TFT provided on the gate wiring. It is characterized by being connected to.

  According to the liquid crystal panel using the lateral electric field type TFT array substrate of the present invention, it has a configuration for preventing an electric field other than the pixel electrode and the common electrode from affecting the liquid crystal and has a defective line defect during the manufacturing process. The occurrence of line defects can be reduced while the product is in use.

It is a top view which shows the structure of 1 pixel on the TFT array substrate which comprises the liquid crystal panel of this invention. It is AA sectional drawing of FIG. It is BB sectional drawing of FIG. It is a figure which shows the electric potential of the liquid crystal panel in this invention. It is a top view which shows the structure of 1 pixel on the TFT array substrate which comprises the liquid crystal panel of this invention. It is CC sectional drawing of FIG. It is DD sectional drawing of FIG. It is EE sectional drawing of FIG.

Embodiment 1 FIG.
Hereinafter, embodiments of a TFT array substrate and a liquid crystal panel according to the present invention will be described with reference to the drawings. In the drawings, the same reference numerals denote substantially the same components.

  FIG. 1 is a plan view showing a configuration of one pixel which is a pixel region on a TFT array substrate constituting a liquid crystal panel of the present invention, FIG. 2 is a cross-sectional view taken along line AA in FIG. 1, and FIG. It is.

  As shown in FIGS. 1 to 3, the TFT array substrate 100 constituting the IPS liquid crystal panel of the present invention is formed with a gate wiring 1 and a gate wiring 1 formed on an insulating substrate 101 such as glass. A source line 2 is provided through a gate insulating film 31 so as to intersect the common line 4, the gate line 1 and the common line 4 in a matrix. A first TFT 3 which is a switching element of the liquid crystal panel is formed at the intersection of the gate wiring 1 and the source wiring 2. The first TFT 3 includes a gate insulating film 31 formed on the gate wiring 1, a semiconductor layer 32 such as a-Si, a semiconductor electrode 32, and a source electrode 21 and a drain electrode extending from the source wiring 2. 81, and a substrate protective film 95 is laminated. In the pixel region on the substrate protective film 95, the pixel electrode 5 and the first common electrode 6 are formed.

  The pixel electrode 5 is connected to the first TFT 3 through a contact hole 8 formed in the substrate protective film 95 on the drain 81. The first common electrode 6 is connected to the common wiring 4 through a contact hole 9 formed in the gate insulating film 31 and the substrate protection film 95 on the common wiring 4. The pixel electrode 5 and the first common electrode 6 are electrodes having a width of several μm, and are parallel to each other at intervals of several μm to several tens of μm in the pixel region of one pixel, and are in the same layer so as to be opposed to each other. Is arranged. A storage capacitor electrode that holds a voltage is formed on the common wiring 4 via a gate insulating film 31 and is connected to the pixel electrode 5 through a contact hole 36 provided on the storage capacitor electrode 35. Yes.

  The TFT array substrate 100 formed in this manner is bonded to a counter substrate (not shown) on which a color filter or a black matrix is formed at a predetermined interval, liquid crystal is sealed between the two substrates, and a polarizing plate (on each surface) A liquid crystal panel is completed by attaching (not shown). Furthermore, a liquid crystal display device is completed by mounting a driving IC (not shown), a backlight (not shown), and the like on the liquid crystal panel.

  In the horizontal electric field type liquid crystal panel of the present invention, the pixel electrode 5 and the first common electrode 6 are formed in a comb-like shape and are arranged to face each other, and therefore, between the pixel electrode 5 and the first common electrode 6. An electric field is applied to the liquid crystal (not shown) to be arranged. Therefore, an electric field is generated in the direction parallel to the insulating substrate 101 over the entire pixel region, thereby controlling the alignment of the liquid crystal and controlling the transmittance of the liquid crystal panel. Further, the voltage applied to the pixel electrode 5 is held by the storage capacitor electrode 35 formed on the common wiring 4.

  As shown in FIGS. 1 and 3, in the TFT array substrate 100 of the present invention, a second common electrode 7 is provided on the source wiring 2 separately from the first common electrode 6. . The second common electrode 7 is independently provided on the source wiring 2 via the substrate protective film 95 along the source wiring 2 and corresponding to the pixel region. The second common electrode 7 is a TFT different from the first TFT 3 used for driving the pixel electrode 5, and is a second TFT 10 provided on the gate wiring 1 constituting the first TFT 3. Connected to. The second TFT 10 includes a source electrode 22 and a drain electrode 81 formed on the gate wiring 1 through the gate insulating film 31 and the semiconductor layer 32 in the same layer as the source wiring 2. Further, the second common electrode 7 and the second TFT 10 are connected by a contact hole 12 provided in the substrate protective film 95 on the second TFT 10. The second TFT 10 is connected to the first common electrode 6 formed in the previous stage via a contact hole 11 provided in the substrate protective film 95 on the second TFT 10.

  Next, a manufacturing method of the TFT array substrate 100 constituting the liquid crystal panel will be described with reference to FIGS.

  The TFT array substrate 100 forms a gate wiring 1 and a common wiring 4 by forming a metal such as Cr or Al on an insulating substrate 101 such as glass and patterning it. Next, SiN, which is an insulating film, a-Si (i, n layer), etc., which are semiconductors, are sequentially formed, and a-Si (i, n layer), etc. are formed in the first TFT 3 and the second TFT 10. The gate insulating film 31 and the semiconductor layer 32 are formed by patterning in an island shape in the region where the film is formed.

  Next, a metal such as Cr or Al is formed and patterned to form the source wiring 2, the source electrode 21, the drain electrode 81, the source electrode 22, and the storage capacitor electrode 35. Thereafter, in the island-shaped semiconductor layer 32 formed at the position of the first TFT 3 and the second TFT 10, the surface of the semiconductor layer 32 not covered with the source 2 and drain electrode 81 is the source wiring 2 (source electrode 21). The n layer having a high surface conductivity is etched using the pattern of the drain electrode 81 as a mask to form a channel region of a TFT (thin film transistor), and the first TFT 3 and the second TFT 10 are completed simultaneously.

  Thereafter, SiN or the like is formed and patterned to form a substrate protective film 95. Next, the contact hole 8 on the drain electrode 81 of the first TFT 3, the contact hole 9 on the common wiring 4, and the contact hole 11 that connects the second TFT 10 and the first common electrode 6 to the substrate protective film 95. Then, a contact hole 12 connecting the second TFT 10 and the second common electrode 7 and a contact hole 36 formed in the storage capacitor electrode 35 are formed.

  Thereafter, a transparent electrode such as ITO is formed and patterned, whereby the pixel electrode 5, the first common electrode 6 in the pixel, and the second common electrode 7 on the source wiring 2 are formed.

  The pixel electrode 5 is connected to the drain electrode 81 of the first TFT 3 through the contact hole 8 and the storage capacitor electrode 35 through the contact hole 36. The first common electrode 6 is connected to the common wiring 4 through the contact hole 9 and the second TFT 10 through the contact hole 11. The second common electrode 7 is connected to the second TFT 10 through the contact hole 12.

  As described above, the second common electrode 7 and the second TFT 10 connected to the second common electrode 7 can be formed without adding a new process, and the cost is not increased.

  In the liquid crystal panel using the TFT array substrate 100 according to the present invention, when a voltage is applied to the gate wiring 1, the common wiring 4 and the source wiring 2, a voltage is applied to the pixel electrode 5 through the first TFT 3. In addition, a voltage is applied to the common electrode 6 through the second TFT 10. By applying an electric field between the pixel electrode 5 and the common electrode to the liquid crystal, the alignment of the liquid crystal is controlled, and an image is displayed on the liquid crystal panel.

  Next, the operation of the liquid crystal panel using the TFT array substrate 100 in the present invention will be described.

  FIG. 4 is a diagram showing the potential applied to the liquid crystal panel, FIG. 4 (a) is a diagram showing the potential applied to an arbitrary source line 2 when operating normally, and FIG. FIG. 4C is a diagram showing the potential applied to the arbitrary wiring 1, and FIG. 4C is a diagram showing the potential applied to the common wiring 4. 4D is a diagram showing the potential of an arbitrary second common electrode 7 (common electrode on the source wiring 2), and FIG. 4E is an arbitrary second common electrode 7 (on the source wiring 2). FIG. 4F shows the potential applied to the source wiring 2 when the common electrode) and the source wiring 2 are short-circuited. FIG. 4F shows the source wiring when the common electrode and the source wiring are short-circuited in the conventional liquid crystal panel. It is a figure which shows the electric potential. Here, the potential center voltage in FIGS. 4A to 4F is set to a voltage substantially equal to the potential of the common wiring 4 shown in FIG. 4C.

  First, a method for applying a source voltage applied from the source wiring 2 to the pixel electrode 5 will be described. A source voltage having a voltage waveform shown in FIG. 4A is applied to the source wiring 2 in a normal state. A gate voltage having a voltage waveform shown in FIG. 4B is applied to the gate wiring 1. In general, when one frame is driven at a period of 60 Hz, the gate wiring 1 is applied with a potential once in 16.7 msec, and the gate potential becomes high. In addition, as the source voltage, a voltage corresponding to the number of the gate wirings 1 is applied during one frame (16.7 msec), and an arbitrary source voltage is selected at a timing when the gate voltage increases. In order to avoid deterioration of the liquid crystal, an AC voltage is selected for each frame centered on the potential center (the potential of the common wiring 4).

As the source voltage selection operation, when the gate voltage is increased, when a-Si is used for the semiconductor layer 32 of the first TFT 3, the channel resistance (not shown) has a low resistance value on the order of 10 ⁶ Ω. The voltage of the wiring 2 is supplied from the source wiring 2 to the pixel electrode 5 and is held in the capacitance between the storage capacitor electrode 35 and the pixel electrode 5 and the first common electrode 6. When the gate voltage is lowered, the first TFT 3 has a high resistance of about 10 ¹² Ω, so that the potential applied to the pixel electrode 5 is transferred to the storage capacitor electrode 35 and the capacitance between the pixel electrode 5 and the first common electrode 6. Keep it held.

Next, a method for applying a potential to the second common electrode 7 will be described. Similar to the voltage application operation to the pixel electrode 5 described above, the potential of the second common electrode 7 shown in FIG. 4D is changed to the first at the timing when the gate voltage of the gate wiring 1 shown in FIG. The channel resistance of the second TFT 10 has a low resistance value of about 10 ⁶ Ω, and is supplied to the second common electrode 7 via the second TFT 10 to apply a potential. Thereafter, when the gate potential of the gate wiring 1 is lowered, the channel resistance of the second TFT 10 becomes an extremely high resistance value of about 10 ¹² Ω. Therefore, the common electrode potential applied to the second common electrode 7 is As shown in FIG. 4D, the voltage is held for a period until the gate voltage increases. This operation is continuously repeated while the liquid crystal panel is being driven.

  As a result, the potential of the second common electrode 7 has the waveform shown in FIG. 4C, and maintains the same potential as the potential of the common wiring 4 shown in FIG. With such a configuration, the influence of the electric field of the source wiring 2 does not affect the liquid crystal in the pixel region. Therefore, the orientation of the liquid crystal in the pixel region can be controlled. It is possible to prevent light leakage that has occurred due to disturbance.

  Next, the operation when the source wiring 2 and the second common electrode 7 are short-circuited will be described in comparison with a liquid crystal panel having a conventional structure.

  As shown in FIG. 4F, the source potential which is the potential of the source wiring 2 when the common electrode 4 and the source wiring 2 are short-circuited in the structure of the conventional liquid crystal panel is substantially the same as the potential of the common wiring 4. Therefore, the voltage of the common wiring 4 is applied to all the pixel electrodes 5 connected to the source wiring 2. Since the potential of the common wiring 4 is substantially the same as the potential center of the source voltage, the pixel electrode 5 connected to the source wiring 2 has the same potential as the common wiring 4, and no voltage is applied to the liquid crystal of the pixel electrode 5. Therefore, in the normally black mode, all the pixels along the source wiring 2 become black spots, so that they are visually recognized as black lines along the direction in which the source wiring 2 is formed.

Next, the operation in the case where an insulation failure due to foreign matter or the like occurs in the substrate protective film 95 on the source wiring 2 in the structure of the liquid crystal panel of the present invention will be described. As described above, since the voltage is supplied to the second common electrode 7 through the second TFT 10, the second TFT 10 is turned on and the first common electrode 6 and the first common electrode 6 have a low resistance of about 10 ⁶ Ω. For example, when the number of gate lines is 480 and the frame frequency is 60 Hz, the connection time is as extremely short as 60 Hz (16.7 msec) / 480 lines = 34.7 μsec. As shown in FIG. 4D, when the source wiring 2 and the second common electrode 7 are short-circuited, the source wiring 2 and the common electrode 6 are short-circuited with a low resistance only for the above extremely short time. The output from the source driver IC (not shown) to the source line 2 maintains a normal voltage, and as a result, the source line 2 is less susceptible to the potential of the common line 4. Therefore, since the potential of the source line 2 does not substantially change from the normal state (FIG. 4A), the potential applied to the pixel electrode 5 connected to the source line 2 is substantially the same as when there is no short circuit. Applied. Therefore, even if the source wiring 2 is short-circuited with the second common electrode 7, the occurrence of line defects can be prevented.

  As described above, according to the liquid crystal panel using the TFT array substrate 100 of the present invention, the second common electrode 7 is formed on the source wiring 2 independently of the first common electrode 6 formed in the pixel region. Since it is formed, it is possible to prevent the electric field other than the pixel electrode and the common electrode from affecting the liquid crystal. Further, since the second common electrode 7 is driven by a second TFT 10 different from the first TFT 3 that drives the pixel electrode 5, a source caused by a short circuit between the source wiring 2 and the second common electrode 7 is used. Line defects in the wiring 2 are reduced. Therefore, the yield of the liquid crystal display device is improved.

  In addition, as described above, the line defects caused by the short circuit between the source wiring 2 and the second common electrode 7 are greatly reduced. Therefore, after the product is shipped, it is caused by the short circuit between the source wiring 2 and the second common electrode 7. The occurrence of line defects is also reduced, and the reliability of the liquid crystal display device is improved.

Embodiment 2. FIG.
5 is a partial plan view of a TFT array substrate according to Embodiment 2 of the present invention, FIG. 6 is a sectional view taken along the line CC in FIG. 5, FIG. 7 is a sectional view taken along the line DD in FIG. Sectional drawing of EE of is shown.

  In the first embodiment, the structure of the TFT array substrate constituting the IPS liquid crystal panel has been described. However, in the second embodiment, the present invention is applied to the TFT array substrate constituting the FFS liquid crystal panel. An example will be described. In addition, those having the same configurations and effects as those of the first embodiment will not be described.

  In the IPS type TFT array substrate described in the first embodiment, the pixel electrode 5 and the first common electrode 6 are formed in the same layer. However, as shown in FIGS. In the FFS method, the pixel electrode 5 is formed below the first common electrode 61 via a substrate protective film 95 that is an insulating film. An opening 13 is formed in the common electrode 61. Further, as shown in FIG. 7, in the first TFT 39, the pixel electrode 5 is formed after the drain electrode 81 is formed, and the drain electrode 81 and the pixel electrode 5 are directly connected without passing through the contact hole. .

  As shown in FIG. 6, in the structure in which the common electrode 61 connected to the common wiring 4 is connected to the second common electrode 71 via the second TFT 19, the TFT array substrate described in the first embodiment is used. And the same structure. Therefore, in the FFS method shown in the second embodiment, the second common electrode 71 is formed independently along the source wiring 2 and connected to the common wiring 4 through the second TFT 19. In this configuration, the influence of the electric field from the source wiring 2 is prevented, and even when the second common electrode 71 formed on the source 2 wiring 2 and the source wiring 2 are short-circuited by a foreign substance or the like, a line defect may be caused. It is greatly reduced. Therefore, similarly to the liquid crystal panel of the first embodiment, the same effect as that of the first embodiment is also obtained in the FFS liquid crystal panel.

DESCRIPTION OF SYMBOLS 1 Gate wiring 2 Source wiring 21, 22 Source electrode 3, 39 1st TFT
31 Gate insulating film 32 Semiconductor layer 35 Retention capacitance electrode 4 Common wiring 5 Pixel electrode 6, 61 First common electrode 7, 71 Second common electrode 8, 9, 11, 12, 36 Contact hole 81 Drain electrode 95 Substrate protection Films 10 and 19 Second TFT
100 TFT array substrate 101 Insulating substrate.

Claims (5)

Source wiring and gate wiring arranged in a matrix on the substrate,
A first TFT (Thin Film Transistor) formed at an intersection of the source wiring and the gate wiring;
A pixel electrode connected to the first TFT and disposed in a pixel region surrounded by the source wiring and the gate wiring;
A first common electrode that is disposed at a predetermined distance from the pixel electrode and applies a parallel electric field to the substrate together with the pixel electrode;
A second common electrode formed along the source wiring,
The TFT array substrate, wherein the second common electrode is connected to a second TFT provided on the gate wiring. Source wiring and gate wiring arranged in a matrix on the substrate,
A first TFT (Thin Film Transistor) formed at an intersection of the source wiring and the gate wiring;
A pixel electrode connected to the first TFT and disposed in a pixel region surrounded by the source wiring and the gate wiring;
A first common electrode disposed via an insulating film at a position facing the pixel electrode;
The first common electrode is applied with an electric field parallel to the substrate together with the pixel electrode,
A second common electrode formed along the source wiring,
The TFT array substrate, wherein the second common electrode is connected to a second TFT provided on the gate wiring. 3. The TFT array substrate according to claim 1, wherein the second common electrode is provided independently corresponding to each pixel region. 4. The TFT array substrate according to claim 1, wherein the second common electrode is formed in the same layer as the first common electrode. 5. The TFT array substrate according to any one of claims 1 to 4,
A counter substrate disposed opposite to the TFT array substrate;
A liquid crystal disposed between the two substrates,
A horizontal electric field type liquid crystal panel that displays an image by applying an electric field in a direction parallel to the two substrates.

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