JP2013239697A - Semiconductor device - Google Patents

Abstract

A semiconductor device capable of preventing an electrostatic failure without using a removable antistatic member.
A chip resistor 16 as an anti-static member for connecting between a pair of external lead-out terminals 13 and 14 which are a gate terminal and an emitter terminal of an IGBT chip 4 is detachable by being provided in a resin case 15. Thus, it is possible to prevent an electrostatic failure that occurs in the storage / shipping process without using an IC foam that is a static electricity countermeasure member mounted outside the resin case 15.
[Selection] Figure 1

Description

The present invention relates to a semiconductor device in which a resistance against static electricity is inserted between the gate and emitter of an IGBT (insulated gate bipolar transistor) or between the gate and source of a power MOSFET.

A semiconductor device mounted with a semiconductor chip having a MOS structure such as an IGBT or a power MOSFET is stored and shipped after completion of the device shipping test. The generated static electricity may be applied to the gate of the semiconductor chip. When the static voltage is high, the gate insulating film is destroyed and a gate short circuit is caused. In order to prevent this, in the storage / shipment process, the gate terminal and the emitter terminal of the IGBT and the gate terminal and the source terminal of the power MOSFET are connected by a member for preventing static electricity. As this antistatic member, a urethane sheet having a resistance of about 1 MΩ / □ called IC foam is often used. In addition to the IC foam, the antistatic member includes a conductive copper foil adhesive tape having a resistance of several ohms, an antistatic bag for inserting an element, and a copper bar for short-circuiting terminals. These antistatic members are detachable, and these members are removed and disposed after the semiconductor device is delivered to the customer.

 8A and 8B show a package 600a and a circuit of a semiconductor device 600 with a static electricity countermeasure member attached to the outside. FIG. 8A is a plan view of the main part of the package 600a, and FIG. 8B is a circuit diagram of the semiconductor device 600. It is. Here, an IGBT module is taken as an example of the semiconductor device 600. The package 600a includes a resin case 615, external lead-out terminals 610 to 614, and the like.

 On the top of the resin case 615, there are external lead-out terminals 610 such as gate terminals G1, G2, collector terminal C1, emitter-collector terminal C2E1, and emitter auxiliary terminals E1, E2 connected to the emitter E2 (the same reference numerals are used for the emitter terminals). ˜614 are derived. Control signals during operation of the semiconductor device are input to the gate terminals G1, G2 and the emitter auxiliary terminals E1, E2. Between the gate terminals G1 and G2 and the emitter auxiliary terminals E1 and E2, an antistatic member such as an IC foam 616 is disposed for the purpose of preventing static electricity in the storage / shipment process, and the IC form 616 that is a resistor is interposed. The gate terminals G1, G2 and the auxiliary emitter terminals E1, E2 are connected.

 When the external lead-out terminal 613 serving as the gate terminals G1 and G2 and the external lead-out terminal 614 serving as the emitter auxiliary terminals E1 and E2 are connected to the IC form 616, both the external lead-out terminals 613 and 614 are shown in FIG. The gap is connected through a resistor 616a of about several hundred kΩ, for example. By mounting the IC form 616 on the external lead-out terminals 613 and 614 of the IGBTs 604 and 607, it is possible to prevent static electricity failure that occurs in human work such as packing in the storage / shipment process.

 Moreover, in patent document 1, either one of the gate terminal of a module and a source terminal is comprised with an elastic member, and both terminals are contacted and short-circuited with the elastic force, and the gate short circuit by the application of static electricity is prevented. . Further, it is described that when a module is used, the module is insulated with an insulating film of a Faston terminal so that the function can be exhibited, thereby preventing electrostatic breakdown of the module.

Further, in Patent Document 2, the gate / emitter terminal serving as the connector connecting faston terminal provided on the upper surface of the outer case of the semiconductor device is normally short-circuited between both terminals, and responds to the insertion of the connector into the terminal. A movable contact type short-circuit bar for releasing the short-circuit state is constructed.
Patent Document 3 describes that a protective resistor for preventing electrostatic breakdown of a semiconductor element is attached to a circuit pattern of a printed circuit board, and then the semiconductor element is attached to the circuit pattern.

 In Non-Patent Document 1, a resistance of about 10 kΩ is connected between the gate and emitter of an IGBT (insulated gate bipolar transistor), and when the gate circuit fails, a voltage is applied to the main circuit with the gate open. However, it is described that the IGBT does not fail.

JP-A-1-268160 JP-A-8-32022 JP 11-340412 A

Fuji IGBT Module Application Manual, Rh984, Fuji Electric Device Technology Co., Ltd., February 2004

However, when the IC form 616 is used as an anti-static member in the storage / shipment process, the IC form 616 is likely to be detached from the external lead-out terminals 613 and 614 during long-term storage. Further, since the IC form 616 is an elastic body, the IC form 616 is deformed and mounted depending on the terminal arrangement and the terminal shape, which causes a problem that it is difficult to mount.

In addition, the detachable antistatic member such as the IC form 616 described above is not preferable from the viewpoint of environmental load because it is removed and discarded by the customer when using the semiconductor device.
Further, Patent Documents 1 to 3 and Non-Patent Document 1 take countermeasures against static electricity outside the case, and do not describe attaching a member for countermeasures against static electricity in the case.
Further, there are examples in which a polysilicon resistor or the like is formed on a semiconductor chip or a resistor is provided in a case with a power IC (integrated circuit) or the like. However, there is no literature suggesting a semiconductor device in which the gate and the emitter (or the source) are connected by an antistatic member (for example, a resistor having a large resistance value) in the case to prevent the electrostatic failure.
An object of the present invention is to solve the above-described problems and provide a semiconductor device capable of preventing electrostatic failure without using a detachable antistatic member.

In order to achieve the above object, according to one aspect of the present invention, there is provided a heat dissipation base, an insulating substrate with a conductive pattern thin film placed on the heat dissipation base, a main electrode and a gate electrode, and the conductive pattern thin film A semiconductor chip placed on an insulated substrate; a case placed on the heat dissipation base and covering the semiconductor chip; and from the inside of the case through the case and led out of the case; A pair of first external lead-out terminals and a second external lead-out terminal to which a control signal is input to the gate electrode, and an anti-static member having a pair of first and second terminals, It is installed in the case, and the first terminal is electrically connected to the first external lead terminal, and the second terminal is electrically connected to the second external lead terminal.

According to the above means, in a semiconductor device mounting a semiconductor chip having a MOS structure, an electrical connection is made between a pair of external lead-out terminals (gate terminal and emitter terminal or gate terminal and source terminal) to which a control signal is input. By providing an anti-static member with a pair of terminals connected to the inside of the case, it is possible to prevent static electricity damage that occurs in the storage and shipping process without using an anti-static member that is detachable and attached outside the case. be able to.
As a result, it is possible to prevent static electricity failure due to erroneous dropping of the static electricity countermeasure member, and it is not necessary to attach the static electricity countermeasure member, thereby simplifying the manufacturing of the semiconductor device. Furthermore, since the detachable antistatic member that has been discarded when the apparatus is used is unnecessary, it can contribute to the reduction of the environmental load.

BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic block diagram of the semiconductor device 100 concerning 1st Example of this invention, (a) is typical sectional drawing, (b) is a partial top view. 3 is a plan view of a principal part of a package 100a of a semiconductor device 100. 1 is a circuit diagram of a semiconductor device 100. FIG. It is a principal part top view of the semiconductor device 200 concerning 2nd Example of this invention. It is a principal part top view of the semiconductor device 300 concerning 3rd Example of this invention. It is a principal part top view of the semiconductor device 400 concerning 4th Example of this invention. The package 500a and sectional drawing of the semiconductor device 500 concerning 5th Example of this invention are shown, (a) is a principal part top view of the package 500a, (b) is principal part sectional drawing of the package 600a. The package 600a and the circuit of the semiconductor device 600 with the static electricity countermeasure member attached to the outside are shown. FIG.

Embodiments of the present invention will be described in the following examples.
<Example 1>
1A and 1B are schematic configuration diagrams of a semiconductor device 100 according to a first embodiment of the present invention, in which FIG. 1A is a schematic sectional view and FIG. 1B is a partial plan view. Here, the semiconductor device 100 is exemplified by a 2-in-1 IGBT module.

2 and 3 show a package 100a and a circuit of the semiconductor device 100, FIG. 2 is a plan view of a main part of the package 100a, and FIG. 3 is a circuit diagram of the semiconductor device 100. In FIG. 2, the package 100 a includes a resin case 15 and external lead-out terminals 10 to 14. FIG. 3 is a circuit diagram of a 2-in-1 IGBT module. A circuit in which an IGBT chip 4 and an FWD (free wheeling diode) chip 4a are connected in reverse parallel, and an IGBT chip 7 and an FWD (free wheeling diode). Two circuits in which the chips 7a are connected in antiparallel are connected in series to form one phase of the inverter circuit.
The IGBT chip 4 and the IGBT chip 7 are known semiconductor chips having a MOS structure. The IGBT chip 4 includes an emitter electrode 5 and a gate electrode 6 on the front (front) surface, and a collector electrode (not shown) on the back surface. The gate electrode 6 constitutes a MOS structure. Similarly, the IGBT chip 7 includes an emitter electrode 8, a gate electrode 9, and a collector electrode (not shown).

 In FIG. 1, an insulating substrate 2 with a conductive pattern thin film is placed on a heat dissipation base plate 1, an IGBT chip 4 is formed on a conductive pattern thin film 3a constituting the insulating substrate 2 with a conductive pattern thin film, and an electrostatic is formed on the conductive pattern thin film 3c. A chip resistor 16 is mounted as a countermeasure member. The insulating substrate with a conductive pattern thin film 2 includes conductive pattern thin films 3a to 3f constituting a pattern of a plurality of regions. The chip resistor 16 includes a pair of terminals. The emitter electrode 5 of the IGBT chip 4 and the conductive pattern thin film 3 e are connected by a bonding wire 26.

        The gate electrode 6 of the IGBT chip 4 and one terminal of the chip resistor 16 are connected by a bonding wire 21. The conductive pattern thin film 3 c on which the other terminal of the chip resistor 16 is placed and the emitter electrode 5 of the IGBT chip 4 are connected by a bonding wire 23. On the conductive pattern thin film 3f, the external lead-out terminal 11 that becomes the emitter terminal E2 is placed. One terminal of the chip resistor 16 and the external lead-out terminal 13 that becomes the gate terminal G <b> 1 are connected by a bonding wire 22. The conductive pattern thin film 3a on which the collector electrode of the IGBT chip 4 is placed and the conductive pattern thin film 3b on which the external lead-out terminal 10 serving as the collector terminal C1 is placed are connected by a bonding wire 25. The semiconductor chip 4 is covered with a resin case 15, and the lower part of the resin case 15 is fixed to the heat dissipation base plate 1. Here, the external derivation terminals 10, 11, and 12 are main terminals, and the external derivation terminals 13 and 14 are a pair of terminals to which a control signal is input. The leading ends of these external lead terminals 10 to 14 are led to the upper surface of the resin case 15. The heat radiating base plate 1 is exposed from the lower side of the resin case 15. The bonding wire 23 may be arranged like the bonding wire 23a.

 In addition to the IGBT chip 4, the semiconductor device 100 includes an IGBT chip 7. The IBGT chip 7 is placed on the conductive pattern thin film 3 d constituting the insulating substrate 2 with the conductive pattern thin film, and includes an emitter electrode 8 and a gate electrode 9. A chip resistor 16 is similarly connected between the emitter electrode 8, the gate electrode 9, the external lead-out terminal 14 as the emitter auxiliary terminal E2, and the external lead-out terminal 13 as the gate terminal G2.

The chip resistor 16 which is the above-mentioned static electricity countermeasure member is often used for surface mounting and is also referred to as a chip resistor or a resistor chip. In this chip resistor, for example, impurity atoms are diffused into a semiconductor wafer (for example, a silicon wafer) having a very high specific resistance to obtain a desired resistance value. Then, a conductive film such as Al-Si (aluminum added with a small amount of silicon) is deposited on both sides of the semiconductor wafer to form a pair of terminals, and the semiconductor wafer is cut into chips by a dicing cutter. The The chip resistor 16 is a resistor using a semiconductor. Some chip resistors 16 are made of a metal or carbon material other than a semiconductor. The resistance range has been put to practical use from about 10Ω to the order of MΩ.
The resistance value of the chip resistor 16 is 5 kΩ to 500 kΩ, preferably 10 kΩ to 100 kΩ. When the resistance value exceeds 500 kΩ, the voltage drop of the chip resistor 16 due to the current flowing due to static electricity generated in the storage / shipping process becomes large. When this voltage drop increases to exceed the breakdown voltage of the gate insulating film of the IGBT chip 4, the gate insulating film is broken down. As a result, a gate short circuit occurs, which is not preferable.

On the other hand, if it is less than 5 kΩ, the current flowing through the chip resistor 16 becomes large, and the power consumption of a gate drive circuit (not shown) increases, which is not preferable. In addition, when the IGBT chip 4 is driven, the gate signal voltage is divided by the recommended gate resistance and the chip resistor 16 to be lowered, and the IGBT chip 4 may malfunction.
That is, the larger value (500 kΩ) of the resistance value of the chip resistor 16 is the maximum value of the resistance value necessary for preventing electrostatic failure. On the other hand, the smaller value (5 kΩ) of the resistance value of the chip resistor 16 is the minimum value of the resistance value required for normal operation of the IGBT.

The resistance value of the chip resistor 16 may be set to about 1000 times the recommended gate resistance inserted in series with the gate terminals G1 and G2 of the IGBT chip 4.
The chip resistor 16 is provided in the resin case 15 so that the external connection terminal 13 that is the gate terminal G1 exposed outside the resin case 15 and the external output terminal 14 that is the emitter auxiliary terminal E1 are attached and detached. Possible conventional static electricity countermeasure members are not required. Therefore, this semiconductor device 100 is a semiconductor device with a small environmental load.
Further, in the semiconductor device 100, it is not necessary to attach a conventional antistatic member that can be detached in the storage / shipping process, and the handling of the semiconductor device 100 can be simplified. In addition, as in the past, detachable antistatic members (IC foam, etc.) do not come off the terminals 13 and 14 in the storage / shipping process and cause electrostatic troubles. Can be reliably prevented.

Although the chip resistor 16 has been described as an example of the static electricity countermeasure member here, the present invention is not limited to this, and a resistor such as a metal film resistor may be used.
In some cases, the bonding wire is replaced with a conductive plate such as a lead frame.

<Example 2>
FIG. 4 is a plan view of an essential part of a semiconductor device 200 according to the second embodiment of the present invention. FIG. 4 is a diagram corresponding to FIG. Hereinafter, differences from the semiconductor device 100 will be described, and common configurations will be omitted.

The difference from the semiconductor device 100 is that the chip resistor 16 is disposed on the IGBT chip 4. Specifically, one terminal of the chip resistor 16 is connected by being placed on the emitter electrode 5, and the other terminal is a bonding wire 21, 21a, which leads to the gate electrode 6 and the gate terminal G1. It is connected to the terminal 13. Further, the emitter electrode 5 and the external lead-out terminal 14 that becomes the emitter auxiliary terminal E1 are connected by a bonding wire 23b. The bonding wire 23b may be arranged like the bonding wire 23a. In Example 2, the same effect as in Example 1 can be obtained.
It should be noted that the external lead-out terminal 13 and the gate electrode 6 may be directly connected by the bonding wire 21c instead of the bonding wire 21a for connecting the other terminal of the chip resistor 16 and the external lead-out terminal 13 as indicated by a dotted line.

<Example 3>
FIG. 5 is a plan view of an essential part of a semiconductor device 300 according to the third embodiment of the present invention. FIG. 5 is a view corresponding to FIG. Hereinafter, differences from the semiconductor device 100 will be described, and common configurations will be omitted.
The difference from the semiconductor device 100 is that the chip resistor 16 is disposed on the semiconductor chip 4. Specifically, one terminal of the chip resistor 16 is connected by being placed on the gate electrode 6, and the other terminal is connected to the emitter electrode 5 by a bonding wire 21c. The gate electrode 6 and the external lead-out terminal 13 that becomes the gate terminal G1 are connected by a bonding wire 21b. Furthermore, the emitter electrode 5 and the external lead-out terminal 14 that becomes the emitter auxiliary terminal E1 are connected by a bonding wire 23b. The bonding wire 23b may be arranged like the bonding wire 23a. The effect similar to Example 1 is acquired also in Example 3.

<Example 4>
FIG. 6 is a plan view of the main part of a semiconductor device 400 according to the fourth embodiment of the present invention. FIG. 6 is a diagram corresponding to FIG. Hereinafter, differences from the semiconductor device 100 will be described, and common configurations will be omitted.
The difference from the semiconductor device 100 is that the chip resistor 16 is disposed on the semiconductor chip 4. Specifically, a pair of terminals are provided at both ends of the chip resistor 16, and the terminals are connected by being placed on the gate electrode 6 and the emitter electrode 5, respectively. The gate electrode 6 and the external lead-out terminal 13 that becomes the gate terminal G1 are connected by a bonding wire 21c. Furthermore, the emitter electrode 5 and the external lead-out terminal 14 that becomes the emitter auxiliary terminal E1 are connected by a bonding wire 23b. The bonding wire 23b may be arranged like the bonding wire 23a. The effect similar to Example 1 is acquired also in Example 4.

<Example 5>
7A and 7B show a package 500a of a semiconductor device 500 according to a fifth embodiment of the present invention and a cross-sectional view of the main part thereof. FIG. 7A is a plan view of the main part of the package 500a, and FIG. It is an AA 'sectional view of). Hereinafter, differences from the semiconductor device 100 will be described, and common configurations will be omitted.

The difference from the semiconductor device 100 is that the chip resistor 16 is disposed inside the frame of the case 15. Specifically, one terminal of the chip resistor 16 inside the frame of the case 15 is connected to the external lead-out terminal 13 that becomes the gate terminal G1. The other terminal is connected to the external lead-out terminal 14 which becomes the emitter auxiliary terminal E1.
Similarly, a pair of terminals of the chip resistor 16 are connected to the external lead-out terminal 13 serving as the gate terminal G2 and the external lead-out terminal 14 serving as the emitter auxiliary terminal E2, respectively.
In the semiconductor device 500, before molding the case 15 made of, for example, resin, the respective terminals of the chip resistor 16 are joined to the external lead-out terminals 13 and 14 using a technique such as soldering, and then externally lead out. It can be manufactured by incorporating the terminals 13 and 14 and the chip resistor 16 into a mold and molding the case 15. In Example 5, the same effect as in Example 1 can be obtained.

 In this embodiment, the chip resistor 16 is disposed inside the frame of the case 15 and can be regarded as being installed in the case as in the first to fourth embodiments. Because the chip resistor 16 is not exposed to the outside of the semiconductor device 500 as in the first to fourth embodiments, it is possible to prevent static electricity failure due to erroneous dropping of the static electricity countermeasure member, and it is not necessary to attach the static electricity countermeasure member. For this reason, it is possible to simplify the manufacturing of the semiconductor device.

DESCRIPTION OF SYMBOLS 1 Heat radiation base board 2 Insulation board | substrate 3a-3f with conductive pattern thin film Conductive pattern thin film 4, 7 IGBT chip | tip 4a, 7a FWD chip | tip 5, 8 Emitter electrode 6, 9 Gate electrode 10 External lead-out terminal (C1)
11 External lead-out terminal (E2)
12 External lead-out terminal (C2E1)
13 External lead-out terminal (gate terminal)
14 External lead-out terminal (emitter auxiliary terminal)
DESCRIPTION OF SYMBOLS 15 Resin case 16 Chip resistors 21-27, 21a-21c, 23a, 23b Bonding wire 100, 200, 300, 400, 500, 600 Semiconductor device

Claims (11)

A heat dissipation base, an insulating substrate with a conductive pattern thin film placed on the heat dissipation base, a semiconductor chip having a main electrode and a gate electrode and placed on the insulating substrate with a conductive pattern thin film, and the heat dissipation base A case that is mounted on the semiconductor chip and covers the semiconductor chip, and a pair of first external lead terminals that pass through the case from the inside of the case and are led to the outside of the case, and a control signal is input to the main electrode and the gate electrode And a second external lead-out terminal, and a static electricity countermeasure member having a pair of first and second terminals, wherein the static electricity countermeasure member is installed in the case, and the first terminal is the first external A semiconductor device, wherein the lead-out terminal and the second terminal are electrically connected to the second external lead-out terminal. The insulating substrate with a conductive pattern thin film includes a first conductive pattern thin film and a second conductive pattern thin film, the semiconductor chip is placed on the first conductive pattern thin film, and the first terminal is connected to the second conductive pattern thin film. The second conductive pattern thin film is electrically connected to the main electrode and the first external lead terminal, and the second terminal is electrically connected to the gate electrode and the second external lead terminal. The semiconductor device according to claim 1, wherein: The first terminal is placed on the main electrode, the second terminal is the gate electrode, the main electrode is the first external lead terminal, and the second terminal or the gate electrode is the second external lead. The semiconductor device according to claim 1, wherein the semiconductor device is electrically connected to a terminal. The first terminal is placed on the gate electrode, the main electrode is electrically connected to the second terminal and the first external lead terminal, and the gate electrode is electrically connected to the second external lead terminal. The semiconductor device according to claim 1, wherein: The first terminal is placed on the gate electrode, the second terminal is placed on the main electrode, the gate electrode is the second external lead terminal, and the main electrode is the first external lead terminal. The semiconductor device according to claim 1, wherein the semiconductor device is electrically connected to each other. The static electricity countermeasure member is installed inside a member constituting the case, the first terminal constitutes the first external lead terminal, the second terminal constitutes the second external lead terminal, and the case. The semiconductor device according to claim 1, wherein the semiconductor device is electrically connected inside the member. The semiconductor device according to claim 1, wherein the static electricity countermeasure member is a resistor. The semiconductor device according to claim 7, wherein the resistor is a chip resistor for surface mounting. 9. The semiconductor device according to claim 7, wherein a resistance value of the resistor is 5 kΩ or more and 500 kΩ or less. 9. The semiconductor device according to claim 7, wherein a resistance value of the resistor is 10 kΩ or more and 100 kΩ or less. The semiconductor device according to claim 1, wherein a member constituting the case is a resin.