JP2013211447A - Silicon carbide vertical mosfet and manufacturing method of the same - Google Patents

Abstract

Even if the impurity concentration of the drift layer of a silicon carbide vertical MOSFET is increased, a depletion layer is generated at the junction surface between the drift layer, which is an n-type withstand voltage region, and a high-concentration p-type layer. Achieve both reductions.
A silicon carbide vertical MOSFET is sandwiched between a first conductivity type well region, a first conductivity type source region 5 and a first conductivity type well region which are selectively formed on the surface of a substrate 1. An interlayer insulating film 13 formed on at least a part of the exposed surface of the second conductive type third semiconductor layer 21 via a gate insulating film 8 and a gate poly-Si electrode 9; It has a source electrode 10 in common contact with the surfaces of conductive type source region 5 and third semiconductor layer 21, and drain electrode 11 provided on the back surface of silicon carbide substrate 1. Then, at least one high-concentration second conductive semiconductor layer 3, 31 formed at the same position as the first semiconductor layer 2 is formed.
[Selection] Figure 9

Description

  The present invention relates to a vertical MOSFET and a manufacturing method thereof, and more particularly, to a structure of a vertical MOSFET that realizes both improvement of device breakdown voltage and reduction of on-resistance and a manufacturing method thereof.

An N-channel MOSFET which is a switching device made of silicon carbide (hereinafter also referred to as “SiC”) is manufactured by the following procedure as an example. In this example, the first conductivity type is n-type, the second conductivity type is p-type, the high concentration is + (plus), and the low concentration is not marked.
(1) A low-concentration n-type SiC layer (n ⁻ breakdown voltage region drift layer) is formed by epitaxial growth on the surface of a high-concentration n ⁺ -type SiC substrate, and a plurality of p ^{+ is} further formed on the surface of the n-type SiC layer. A mold region is selectively formed.
(2) A plurality of n ⁺ type source regions and p type contact regions are formed on the surface of each p ⁺ type region, and a source electrode is formed on the surface of the n ⁺ type source region and the p type contact region.
(3) A gate electrode is formed on the p-type contact region between the n ⁺ -type source region and the n-type SiC layer via a gate insulating film, and a drain electrode is formed on the back side of the n ⁺ -type SiC substrate. It is formed.

Such an N-channel SiC-MOSFET is known to have a high breakdown voltage, but the following Patent Document 1 proposes a manufacturing method for reducing the on-resistance of such an N-channel SiC-MOSFET. .
FIG. 1 is a schematic cross-sectional view for explaining a unit cell of a silicon carbide vertical MOSFET in this prior art.

In FIG. 1, for example, an n-type drift layer b doped with nitrogen and having a lower concentration than the substrate a is deposited on the surface of the high-concentration n ⁺ -type substrate a having a (0001) plane doped with nitrogen. ing. A high-concentration p ⁺ -type layer c doped with aluminum is deposited on the surface of the low-concentration n-type drift layer b, and a lower concentration than the p ⁺ -type layer c doped with aluminum is deposited on the upper surface thereof. A p-type layer d is deposited.

For example, a high-concentration n ⁺ type source region e selectively doped with phosphorus is formed on the surface portion of the p-type layer d, and is selectively formed in the high-concentration p ⁺ type layer c. A first region consisting of a notch is provided, and a second region consisting of a notch wider than the notch is formed in the low-concentration p-type layer d.

In the first and second regions, a low-concentration n-type base region f doped with nitrogen is provided in direct contact with the n-type drift layer b, and the second wide layer in the low-concentration p-type layer d is provided. In this region, the channel resistance component is reduced, and the on-resistance of the silicon carbide semiconductor device can be reduced.
A low-concentration base region g is formed on the surface layer of the high-concentration p ⁺ -type layer c at the intermediate portion between the n-type base region f and the high-concentration n ⁺ -type source region e. A gate electrode i is provided on the gate electrode i via a gate insulating film h. A high concentration n ⁺ type source region e and a low concentration p type layer d are provided on the gate electrode i via an interlayer insulating film j. A source electrode k connected to each other at low resistance is formed.
Note that p is a drain electrode.

Thus, a part m of the low-concentration n-type drift layer b is exposed on the surface, and the high-concentration p ⁺ -type layer c is provided in direct contact with the low-concentration n-type drift layer b. without any surface of the low concentration n-type drift layer b is covered with the high-concentration p ⁺ -type layer c, the high-concentration p ⁺ -type layer c is, by implanting n-type impurity ions of low concentration n-type base region f Except for the region to be formed, all are composed of a low-concentration p-type layer d. Therefore, after n-type impurity ion implantation, a portion m in contact with the n-type drift layer b of the n-type base region f is highly concentrated. Thus, the on-resistance can be reduced.

JP 2001-23757 A JP 2009-59949 A JP 2007-115791 A

According to the above-described prior art, the portion m in contact with the n-type drift layer b of the n-type base region f can be made high in concentration and the on-resistance can be reduced, but generally lower than that in the high-concentration n ⁺ -type substrate a. The drift layer b, which is an n-type SiC layer (n-type withstand voltage region), has a large potential drop in the drift layer b when a current flows between the source and drain electrodes. As a result, the resistance during current conduction increases. End up.
In order to prevent this, if the impurity concentration of the drift layer b is increased, the depletion layer extending from the junction between the low-concentration p-type layer m and the low-concentration n-type drift layer b becomes insufficient, and local breakdown occurs. However, the withstand voltage decreases.

  As described above, in the SiC-MOSFET, the drift layer b itself is a factor that hinders both further improvement of the device breakdown voltage and reduction of the on-resistance, and further reduces the on-resistance after securing the device breakdown voltage. Therefore, improvement of the drift layer b is demanded.

In order to achieve both improvement in device breakdown voltage and reduction in on-resistance, Patent Document 2 discloses that a p-type diffusion region is formed in an n-type diffusion region of an LDMOS transistor (lateral double diffusion MOS transistor) and a gate edge on the drain side is formed. It describes that the electric field concentration in the surrounding area is alleviated. Patent Document 3 describes that a p-type buried region is formed in the n-type drain drift layer of the lateral MOSFET to increase the breakdown voltage and reduce the on-resistance.
However, both of these are premised on LDMOS transistors and lateral MOSFETs, and cannot be applied to silicon carbide vertical MOSFETs as they are, and further reduce the on-resistance while ensuring the device breakdown voltage. I can't.

That is, in the case of a vertical element, since the current flows in the vertical direction, a highly accurate alignment accuracy between the p-type regions is required so as not to disturb the current flowing in the direction perpendicular to the p-type buried region.
On the other hand, since a current flows in parallel with the p-type buried region, the lateral element does not require any high alignment accuracy. In the case of a lateral element, the current flowing in the element concentrates on the surface, so that the effect of increasing the concentration of the n-type layer and reducing the on-resistance achieved by applying the p-type buried layer Although it is limited to the flowing surface layer, in the case of a vertical element, since the current flows uniformly throughout the element, the effect of the high concentration layer of n layers due to the application of the p-type buried layer affects the entire element. As a result, the effect of reducing the on-resistance is remarkably greater than that of the lateral element.

Accordingly, an object of the present invention is to form an impurity in the drift layer by forming a high-concentration p ⁺ -type layer as an intermediate layer in the drift layer of the silicon carbide vertical MOSFET at the same position as the high-concentration n ⁺ -type source region. Even if the concentration is increased, a depletion layer is generated at the junction surface between the drift layer which is the n-type breakdown voltage region and the high concentration p ⁺ -type layer, and the voltage applied to both ends of the depletion layer changes even when the drain electrode voltage is increased. This is to realize both improvement in device breakdown voltage and reduction in on-resistance.

In order to achieve the above object, the following technical means were taken in the vertical MOSFET of the present invention. That is, the vertical MOSFET of the present invention is
(1) A first conductive type semiconductor substrate (1) made of silicon carbide and a first conductive type first semiconductor having a lower concentration than the semiconductor substrate 1 formed on the semiconductor substrate (1). A layer (2), a second semiconductor layer (3) that is selectively formed on the first semiconductor layer (2) and has a second conductivity type with a high concentration, and the first semiconductor layer ( 2) and a third semiconductor layer (21) formed on the second semiconductor layer (3) with the same conductivity type and the same concentration as the first semiconductor layer (2); A high-concentration second conductivity type fourth semiconductor layer (31) selectively formed on the same surface as the second semiconductor layer (3) on the surface of the semiconductor layer (21); On the third semiconductor layer (21) and the fourth semiconductor layer (31), a second conductivity type low-concentration base layer (4) and the base layer (4) A source region of the first conductivity type selectively formed in a surface layer (5),
A well region (6) of the first conductivity type formed so as to penetrate the base layer (4) from the surface and reach the third semiconductor layer (21), the source region (5), and the well A gate electrode layer (9) provided on at least a part of the surface exposed portion of the base layer (4) between the region (6) via a gate insulating film (8), and the base layer ( 4) and a source electrode (12) in common contact with the surface of the source region (5), and a drain electrode (11) provided on the back surface of the semiconductor substrate (1).

(2) In the vertical MOSFET, a plurality of the second semiconductor layers (3) and the third semiconductor layers (21) are alternately formed.

In addition, in order to efficiently manufacture the vertical MOSFET, the vertical MOSFET manufacturing method of the present invention includes the following steps. That is, the manufacturing method of the vertical MOSFET of the present invention is as follows.
(3) A first semiconductor layer (2) of the first conductivity type and having a lower concentration than the semiconductor substrate (1) is formed on the first conductivity type semiconductor substrate (1) by epitaxial growth. A first step of selectively forming a second semiconductor layer (3) having a high concentration of the second conductivity type on the first semiconductor layer (2) by ion implantation using a mask; And a third semiconductor layer (21) having the same concentration as that of the first semiconductor layer (2) on the first semiconductor layer (2) and the second semiconductor layer (3). A third step formed by epitaxial growth and a second high-concentration second layer on the third semiconductor layer (21) at the same location as the second semiconductor layer (3) formed in the second step. A fourth semiconductor layer (31) of a conductive type is selectively formed by epitaxial growth. A fourth step of forming a second conductive type low-concentration base layer (4) by epitaxial growth on the third semiconductor layer (21) and the fourth semiconductor layer (31); And a sixth step of selectively forming a first conductivity type well region on the base layer (4) by ion implantation using a mask so as to directly reach the surface of the fourth semiconductor layer. A second conductivity type contact region (12) and a first conductivity type source region (5) are formed on the inside of the base layer (4) by ion implantation, and the source region (5). And a gate electrode layer (9) provided via a gate insulating film (8) on a part of the exposed surface portion of the base layer (4) sandwiched between the well layer (6) and the well layer (6). The source region (5) and the contact region ( To form a source electrode (12) so as to contact common to 2), constituting a eighth step of forming drain electrodes (11) on the back surface of the semiconductor substrate (1).

(4) In the above vertical MOSFET manufacturing method, the second step is performed again after the third step, and the step of performing the third step is repeated at least once.

According to the present invention, when a high voltage is applied between the source electrode and the drain electrode, the depletion layer can be expanded in the lateral direction starting from the second semiconductor layer and the fourth semiconductor layer. it can.
As a result, even if the concentration of the semiconductor layer 2 is set higher than that of the conventional MOSFET, the depletion layer is easily extended, and thus a high breakdown voltage can be realized. Therefore, a high breakdown voltage characteristic and a low on-resistance due to the increased concentration of the semiconductor layer 2 It is possible to achieve both characteristics.

Diagram showing the structure of a conventional vertical MOSFET The figure which shows the structure formed by the 1st process in an Example. The figure which shows the structure formed by the 2nd process in an Example. The figure which shows the structure formed by the 3rd process in an Example. The figure which shows the structure formed by the 4th process in an Example. The figure which shows the structure formed by the 5th process in an Example. The figure which shows the structure formed by the 6th process in an Example. The figure which shows the structure formed by the 7th process in an Example. The figure which shows the structure of the vertical MOSFET of this invention produced after completion | finish of the 8th process in an Example.

  Embodiments of the present invention will be described below with reference to the drawings.

The procedure for manufacturing a SiC-N channel MOSFET as a switching device according to the present embodiment is as follows.
In this embodiment, the first conductivity type is N-type, the second conductivity type is P-type, high concentration is indicated by + (plus), and low concentration is indicated by-(minus). May be P-type and the second conductivity type may be N-type.

(First step)
As shown in FIG. 2, on the surface of a high-concentration semiconductor substrate 1 (N ⁺ -type SiC substrate) having a first conductivity type and having a (000-1) plane doped with nitrogen, the first conductivity type is formed. A first semiconductor layer 2 (N ⁻ type SiC layer) having a lower concentration than that of the semiconductor substrate 1 is formed by epitaxial growth. In this embodiment, the impurity concentration is 6 × 10 ¹⁶ cm ⁻³ and the thickness is 4.5 μm.

(Second step)
As shown in FIG. 3, a 1.5 μm thick SiO ₂ film deposited by low pressure CVD is formed on the surface of the first semiconductor layer 2 (N ⁻ -type SiC layer) by patterning by photolithography. Then, using this as a mask, ions of aluminum or boron are ion-implanted to selectively form the second semiconductor layer 3 (P ⁺ -type region) having a high concentration of the first conductivity type. At this time, the semiconductor substrate 1 is heated to about 500 ° C. to perform ion implantation. As a result, the second semiconductor layer 3 having a thickness of 0.5 μm is formed.

(Third step)
As shown in FIG. 4, after removing the SiO ₂ film used as a mask, on the surface of the first semiconductor layer 2 (N ⁻ type SiC layer) on which the second semiconductor layer 3 (P ⁺ type region) is formed. In addition, a third semiconductor layer 21 formed at substantially the same concentration as the first semiconductor layer 2 is formed by epitaxial growth. The thickness was 4.5 μm, which is the same as that of the semiconductor layer 2.

(Fourth process)
As shown in FIG. 5, after forming a mask obtained by patterning a SiO ₂ film on the surface of the third semiconductor layer 21 at the same position as in the second step, the same procedure as in the second step is performed. By ion-implanting aluminum or boron, the second semiconductor layer 3 (P ⁺ type region) is almost at the same position as viewed from the axial direction (the surface side of the third semiconductor layer 21 in FIG. 2D). A fourth semiconductor layer 31 (P ⁺ -type region) having a high concentration of the first conductivity type is formed with a thickness of 0.5 μm.

(Fifth step)
As shown in FIG. 6, a base layer (4) having a relatively low concentration of 5 × 10 ¹⁵ cm ^{−3 of} the second conductivity type is epitaxially grown on the surface of the fourth semiconductor layer 31 (P ⁺ -type region). It is formed with a thickness of 0.5 μm.

(Sixth step)
As shown in FIG. 7, the position where the fourth semiconductor layer 31 (P ⁺ -type region) is formed on the surface of the base layer 4 is avoided, and the first conductivity type well is formed by ion implantation using a mask for the base layer 4. Region 6 is selectively formed. The first conductivity type well region 6 penetrates the base layer (4) from the surface and reaches the third semiconductor layer 21.

(Seventh step)
As shown in FIG. 8, aluminum ions are implanted into the base layer 4 to form a contact region 12 (P ⁺ portion) that comes into contact with a source electrode 10 to be described later, and phosphorus ions are implanted into the contact region 12 (P ^A source region 5 (n ⁺ portion) having a high concentration of the first conductivity type is formed so as to be in contact with the surfaces of the ⁺ portion and the base layer 4 in common.
Then, the gate insulating film 8 is formed on a part of the surface exposed portion of the base layer 4, and the gate poly-Si 9 and the interlayer insulating film 13 are formed.

(Eighth step)
As shown in FIG. 9, after forming the source electrode 10 so as to be in common contact with the surfaces of the first conductivity type source region 5 and the base layer 4 in the eighth step, the drain electrode is formed on the back surface of the semiconductor substrate 1. 11 is formed.

  Note that it is possible to return to the second step again after the third step and to form a plurality of third semiconductor layers 21.

Through such a process, a silicon carbide vertical MOSFET having a structure as shown in FIG. 9 is obtained. When a high voltage is applied between the source electrode 10 and the drain electrode 11, the second semiconductor layer 3 is obtained. In addition, the fourth semiconductor layer 31 (P ⁺ -type region) is the starting point, and the depletion layer can spread in the lateral direction. As a result, even if the concentration of the semiconductor layer 2 is set higher than that of the conventional MOSFET, the depletion layer is easily extended, and thus a high breakdown voltage can be realized. Therefore, a high breakdown voltage characteristic and a low on-resistance due to the increased concentration of the semiconductor layer 2 The characteristics can be compatible.

  As described above, according to the vertical MOSFET structure of the present invention, the depletion layer extends not only in the conventional vertical direction but also in the horizontal direction. As a result, the concentration of the semiconductor layer 2 is set higher than that of the conventional MOSFET. Even so, since the depletion layer is easy to extend, high breakdown voltage is realized, and by increasing the concentration of the semiconductor layer, both low on-resistance characteristics can be achieved, so it is widely used in vertical MOSFETs with high breakdown voltage and low on-resistance. It can be expected to be adopted.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 1st semiconductor layer 3 2nd semiconductor layer 4 6th semiconductor layer 5 1st conductivity type source region 6 1st conductivity type well layer 8 Gate poly-Si insulating film 10 Source electrode 11 Drain electrode layer 12 Contact region 13 Gate insulating film 21 Third semiconductor layer 31 Fourth semiconductor layer

Claims (4)

A first conductivity type semiconductor substrate (1) made of silicon carbide;
A first conductivity type first semiconductor layer (2) formed on the semiconductor substrate (1) and having a lower concentration than the semiconductor substrate (1);
A second semiconductor layer (3), which is selectively formed on the first semiconductor layer (2) and has a second conductivity type of high concentration;
A third semiconductor layer (first conductivity type) formed on the first semiconductor layer (2) and the second semiconductor layer (3) at the same concentration as the first semiconductor layer (2). 21) and
A fourth semiconductor layer (second conductivity type of high concentration) selectively formed on the surface of the third semiconductor layer (21) at the same position as the second semiconductor layer (3). 31) and
On the third semiconductor layer (21) and the fourth semiconductor layer (31), a second conductivity type low-concentration base layer (4);
A first conductivity type source region (5) selectively formed on the surface layer of the base layer (4);
A well region (6) of the first conductivity type formed so as to penetrate the base layer (4) from the surface and reach the third semiconductor layer (21);
A gate electrode layer provided at least partially on the surface exposed portion of the base layer (4) between the source region (5) and the well region (6) via a gate insulating film (8). (9) and
A source electrode (12) in common contact with the surface of the base layer (4) and the source region (5);
A vertical MOSFET comprising a drain electrode (11) provided on the back surface of the semiconductor substrate (1).   The vertical MOSFET according to claim 1, wherein a plurality of the second semiconductor layers (3) and the third semiconductor layers (21) are alternately formed. A first semiconductor layer (2) made of silicon carbide and having a first conductivity type and a lower concentration than the semiconductor substrate (1) is formed on the first conductivity type semiconductor substrate (1) by epitaxial growth. Process,
A second step of selectively forming, on the first semiconductor layer (2), a second semiconductor layer (3) having a high concentration of the second conductivity type by ion implantation using a mask;
A third semiconductor layer (21) having the same concentration as the first semiconductor layer (2) is formed on the first semiconductor layer (2) and the second semiconductor layer (3) by epitaxial growth. 3 steps,
On the third semiconductor layer (21), a fourth semiconductor layer having the second conductivity type of high concentration at the same location as the second semiconductor layer (3) formed in the second step. A fourth step of forming (31) selectively by epitaxial growth;
A fifth step of forming a second conductivity type low-concentration base layer (4) on the third semiconductor layer (21) and the fourth semiconductor layer (31) by epitaxial growth;
A sixth step of selectively forming a first conductivity type well region on the base layer (4) by ion implantation using a mask so as to directly reach the surface of the fourth semiconductor layer;
A second conductivity type contact region (12) and a first conductivity type source region (5) are formed therein by ion implantation on the base layer (4), and the source region (5) A gate electrode layer (9) provided via a gate insulating film (8) is formed on a part of the surface exposed portion of the base layer (4) sandwiched between the well layers (6). Process,
A source electrode (12) is formed so as to be in common contact with the source region (5) and the contact region (12), and a drain electrode (11) is formed on the back surface of the semiconductor substrate (1). A method of manufacturing a vertical MOSFET comprising the steps. 2. The method of manufacturing a vertical MOSFET according to claim 1, wherein after the third step, the second step is performed again, and the step of performing the third step is repeated at least once.

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