JP2013196746A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of shortening the time required for recovering from a power supply cut-off state.SOLUTION: A memory is equipped with a plurality of memory banks which include: memory cell arrays including a plurality of non-volatile memory cells; and a sense amplifier sections each of which is provided corresponding to each of the plurality of memory cell arrays and detects data of the memory cell arrays to temporarily store the data in data read-out operation or data writing operation. A plurality of switches are severally provided between a power supply and the plurality of memory banks. The controller controls conduction state of each of the plurality of switches. In the case where the controller receives a first command of instructing transition to a power supply cut-off state in the data read-out operation or the data writing operation, it keeps the conduction state for a switch corresponding to a memory bank which is selected for reading out data or writing data and sets other switches to a non-conduction state.

Description

  Embodiments described herein relate generally to a semiconductor memory device.

  In general, a volatile memory such as a DRAM (Dynamic Random Access Memory) can comply with JEDEC's LPDDR2 (Low Power Double Data Rate 2) standard. In LPDDR2, a DPD (Deep Power Down) state is defined. The DPD state is a state in which the elements of the DRAM are shut off from the external power source in order to reduce power consumption in the standby state. For example, a DPD command is issued when a long standby state is expected.

  Since the power supply is cut off when the state shifts to the DPD state, in the volatile memory such as a DRAM, data in the memory cell and the mode register are lost. Therefore, when returning to the energized state (idle state), it is necessary to rewrite data into the memory cell and the mode register. For this reason, the conventional DRAM has a problem that it takes a long time to recover from the DPD state.

Japanese Patent Laid-Open No. 11-297071

  Provided is a semiconductor memory device capable of reducing the time required for returning from a power-off state.

  The semiconductor memory device according to the present embodiment is provided corresponding to each of a memory cell array including a plurality of nonvolatile memory cells and a plurality of memory cell arrays, and detects data in the memory cell array in a data read operation or a data write operation. And a plurality of memory banks including a sense amplifier section for temporarily storing the data. A plurality of switches are respectively provided between the power supply and the plurality of memory banks. The controller controls the conduction state of each of the plurality of switches. When receiving the first command instructing the transition to the power-off state during the data read operation or data write operation, the controller conducts the switch corresponding to the memory bank selected for data read or data write. Leave the other switches in the non-conducting state while remaining in the state.

1 is a block diagram showing an MRAM and a chip controller CC according to a first embodiment. 1 is a block diagram showing a configuration of an MRAM according to a first embodiment. 3 is an explanatory diagram showing a configuration of a single memory cell MC. FIG. The state diagram of MRAM by a 1st embodiment. The figure which shows the structure and state of the memory bank BNK and its peripheral part of MRAM by 1st Embodiment. The circuit diagram which shows the structure of switch controller SWCn and SWC20n-SWC23n. FIG. 5 is a timing chart showing the operation of the MRAM according to the first embodiment. The figure which shows the structure and state of the memory bank BNK and its peripheral part of MRAM by 2nd Embodiment. The state diagram of MRAM by a 2nd embodiment. FIG. 9 is a timing chart showing the operation of the MRAM according to the second embodiment. The figure which shows the structure and state of the memory bank BNK and its peripheral part of MRAM by 3rd Embodiment. FIG. 10 is a timing chart showing the operation of the MRAM according to the third embodiment. The figure which shows the structure and state of the memory bank BNK and its peripheral part of MRAM by 4th Embodiment. FIG. 10 is a timing chart showing the operation of the MRAM according to the fourth embodiment. The figure which shows the modification 1 which applied the mode register MRv by 2nd Embodiment to 1st Embodiment. The figure which shows the modification 2 which applied the mode register MRnv by 3rd Embodiment to 1st Embodiment.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

  In the following embodiments, a magnetic random access memory (MRAM), a resistance random access memory (ReRAM), a phase-change random access memory (PRAM), a ferroelectric The present invention can be applied to various types of nonvolatile memories such as a body memory (FeRAM: ferromagnetic random access memory).

  In the following embodiments, an MRAM will be described as an example of a resistance change memory.

(First embodiment)
FIG. 1 is a block diagram showing an MRAM and a chip controller CC according to the first embodiment. The chip controller CC includes a CPU, ROM, SRAM, and LPDDR2 controller. The LPDDR2 controller outputs a chip selection signal CS, a clock enable signal CKE, a command / address signal CA, a clock signal CK, data DQ, a strobe signal DQS, mask data DM, and the like to the MRAM. The LPDDR2 controller controls the MRAM by these signals.

  In general, the JEDEC LPDDR2 standard is applied to a volatile memory such as a DRAM. In this embodiment, the LPDDR2 is applied to an MRAM that is a nonvolatile memory.

  FIG. 2 is a block diagram showing the configuration of the MRAM according to the first embodiment. The MRAM according to the present embodiment includes a memory cell array MCA, a power generator PG, a logic circuit LC, a clock enable receiver CKER, a command / address receiver CAR, a data buffer DQB, and an input / output unit I / O. Yes.

  The memory cell array MCA includes, for example, a plurality of memory cells MC that are two-dimensionally arranged in a matrix. The memory cell MC is a nonvolatile memory cell and includes, for example, an MTJ element. Each memory cell MC is connected to a bit line pair (for example, bit line BL1 and bit line BL2 as shown in FIG. 2) and a word line WL. That is, one end of the memory cell MC is connected to one bit line BL1 of the bit line pair, and the other end is connected to the other bit line BL2 of the bit line pair. The bit line pair BL1, BL2 extends in the column direction. The word line WL extends in the row direction orthogonal to the column direction.

  The memory cell array MCA further includes a sense amplifier unit SA, a write driver WD, a column decoder CD, a row decoder RD, a main controller MCNT, and a write / read buffer WRB.

  The sense amplifier unit SA is connected to the memory cell MC through, for example, the bit line BL1, and has a function of detecting data in the memory cell MC. The bit line BL2 is connected to a reference voltage (ground). The write driver WD is connected to the memory cell MC via, for example, the bit line BL1, and has a function of writing data to the memory cell MC.

  The main controller MCNT transfers the data received from the DQ buffer DQB to the write driver WD so as to write to the memory cell MC of the desired column under the control of the command controller CCNT, or receives the control of the command controller CCNT. Then, the data read from the memory cell MC of the desired column is transferred to the DQ buffer DQB.

  The column decoder CD is configured to select a bit line pair of a certain column according to the column address from the command / address receiver CAR.

  The row decoder RD selects the word line WL according to the row address from the command / address receiver CAR.

  The write / read buffer WRB temporarily stores write data input via the input / output unit I / O and the data buffer DQB, or temporarily stores read data from the memory cell MC.

  The data buffer DQB outputs read data to the outside via the input / output unit I / O or transfers the write data taken from the outside via the input / output unit I / O to the inside. Hold temporarily.

  The clock enable receiver CKER receives a clock enable signal CKE that determines whether or not a clock signal can be received, and effectively passes the clock signal when the clock enable signal CKE is activated.

  The power generator PG generates a power supply voltage for driving the memory cell array MCA. For example, the power generator PG generates a power supply voltage VDD or a reference voltage VSS by stepping up or down a power supply voltage from the outside. Alternatively, the external power supply voltage may be directly supplied to the inside as the power supply voltage VDD or the reference voltage VSS without providing the power generator PG.

  The logic circuit LC includes a power controller PC and a command controller CCNT. The power controller PC controls the power generator PG, the main controller MCNT, and the command / address receiver CAR. The power controller PC can selectively set the power generator PG, the main controller MCNT, and the command / address receiver CAR to a start state (on state) or a sleep state (off state).

  The command controller CCNT receives commands indicating various operations such as a read operation and a write operation from the command / address receiver CAR, and controls the main controller MCNT in accordance with those commands.

  The command / address receiver CAR receives a command and an address that determine the operation of the memory cell array MCA. The command / address receiver CAR receives, for example, a column address, a row address, and the like as an address. The command / address receiver CAR uses, for example, an active command ACT, a refresh command REF, a self-refresh command SREF, a power-down command PD, a deep power-down command DPD, an MR write command MRW, an MR read command MRR, a reset command RST, etc. Receive. With these commands, the memory cell array MCA can execute various operations. Each command will be described later. These commands can be distinguished according to the logic combination of signals such as the clock enable signal CKE and / or the chip select signal CS.

  FIG. 3 is an explanatory diagram showing a configuration of a single memory cell MC. Each memory cell MC includes a magnetic tunnel junction element (MTJ (Magnetic Tunnel Junction) element) and a cell transistor CT. The MTJ element is an STT (Spin Transfer Torque) -MTJ element. The MTJ element and the cell transistor CT are connected in series between the bit line BL1 and the bit line BL2. In the memory cell MC, the cell transistor CT is disposed on the bit line BL2 side, and the MTJ element is disposed on the bit line BL1 side. The gate of the cell transistor CT is connected to the word line WL.

  An STT-MTJ element using the TMR (tunneling magnetoresistive) effect has a laminated structure composed of two ferromagnetic layers and a nonmagnetic layer (insulating thin film) sandwiched between them, and is magnetized by a spin-polarized tunnel effect. Digital data is stored by changing resistance. The MTJ element can take a low resistance state and a high resistance state depending on the magnetization arrangement of the two ferromagnetic layers. For example, if the low resistance state is defined as data “0” and the high resistance state is defined as data “1”, 1-bit data can be recorded in the MTJ element. Of course, the low resistance state may be defined as data “1”, and the high resistance state may be defined as data “0”. For example, the MTJ element is configured by sequentially laminating a fixed layer P, a tunnel barrier layer B, and a recording layer Fr as shown in FIG. The fixed layer P and the recording layer Fr are made of a ferromagnetic material, and the tunnel barrier layer B is made of an insulating film. The fixed layer P is a layer whose magnetization direction is fixed, and the recording layer Fr has a variable magnetization direction, and stores data according to the magnetization direction.

  When a current equal to or greater than the reversal threshold current is passed in the direction of the arrow A1 during writing, the recording layer Fr is in an anti-parallel state with respect to the magnetization direction of the fixed layer P, and is in a high resistance state (data “1”). When a current equal to or greater than the inversion threshold current is passed in the direction of the arrow A2 at the time of writing, the magnetization directions of the fixed layer P and the recording layer Fr are in a parallel state and a low resistance state (data “0”). Thus, the MTJ element can write different data depending on the direction of current.

  FIG. 4 is a state diagram of the MRAM according to the first embodiment. FIG. 4 shows transitions to various states centering on the idle state. In the idle state as the start mode, the command / address receiver CAR, the power generator PG, and the memory cell array MCA are all in the start state (ON state). Thus, the command / address receiver CAR is in a state where it can receive commands and addresses, so that the MRAM can transition to the active state and various other states in a short time.

  In FIG. 4, a thin arrow indicates that the state of the MRAM changes when a command is received. A thick arrow indicates that the state of the MRAM automatically changes after the operation is completed without receiving a command.

  When the MRAM receives the active command ACT, the MRAM transitions from the idle state to the active state. In the active state, a data read operation or a data write operation can be performed by receiving a read command or a write command.

  When the MRAM receives the power down command PD or the deep power down command DPD, the MRAM transits from the idle state to the PD state or the DPD state.

  Usually, the memory consumes relatively large power in the idle state. Therefore, to reduce power consumption, when not used for a predetermined period, the MRAM transitions from the idle state to the PD state or DPD state where power consumption is reduced.

  In the DPD state, the power controller PC sets all of the memory cell array MCA, the power generator PG, and the command / address receiver CAR to a dormant state. Since the memory cell array MCA, the power generator PG, and the command / address receiver CAR are set in the dormant state, power consumption is very low in the DPD state. However, the return time from the DPD state to the idle state is relatively long.

  In the PD state, the power controller PC activates the memory cell array MCA and the power generator PG, and puts the command / address receiver CAR in a dormant state. Since the memory cell array MCA and the power generator PG are in the activated state, in the PD state, the return time to the idle state is shorter than the return time from the DPD state to the idle state. However, power consumption in the PD state is larger than that in the DPD state.

  The refresh command REF and the self-refresh command SREF are issued to execute a refresh operation in a volatile memory such as a DRAM. Generally, in a volatile memory such as a DRAM, a refresh operation and a self-refresh operation are performed in order to retain data in memory cells.

  However, since a nonvolatile memory such as an MRAM can hold data in a nonvolatile state, a refresh operation and a self-refresh operation are not required. Therefore, when a nonvolatile memory such as MRAM is applied to a volatile memory standard (for example, LPDDR2), the commands REF and SREF for the refresh operation and the self-refresh operation are not used. When the commands REF and SREF are issued, the MRAM according to the present embodiment may maintain the previous state (for example, the idle state).

  MR (Mode Register) read and MR write indicate a data read or write operation of the mode register MR. The mode register MR stores the operation state of the MRAM and the like. For example, the mode register MR stores the burst type, burst length, latency period, and the like. When the command MRR is issued, the MRAM executes MR read. When the command MRW is issued, the MRAM executes MR write.

  The clock enable receiver CKER that receives the clock enable signal CKE and the clock signals CK_t and CK_c maintains the activated state (ON state) in any state. When the clock enable receiver CKER receives the clock enable signal CKE, the power controller PC activates the command / address receiver CAR. As a result, the command / address receiver CAR can receive a command such as the command PDX.

  This embodiment further has a direct partial DPD state. When the MRAM receives the command DP-DPD as the first command, the MRAM directly transitions from the active state to the direct partial DPD state. Further, upon receiving the DP-DPD exit command DP-DPDX as the second command, the MRAM directly returns from the direct partial DPD state to the active state. The direct partial DPD state is not a state based on the LPDDR2 standard, but a new state.

  In the direct partial DPD state, the main controller MCNT maintains power supply to the sense amplifier unit SA of the memory bank BNK selected for data reading or data writing, and supplies power to the other non-selected memory banks BNK. Shut off the power supply. Further, the main controller MCNT cuts off the power supply to the memory cell array MCA of the memory bank BNK selected for data reading or data writing. At this time, the non-selected memory bank BNK is in the same state as the above-described DPD state. The memory cell array MCA of the selected memory bank BNK is also almost in the same state as the above DPD state. However, the sense amplifier unit SA of the selected memory bank BNK maintains the activated state.

  When the MRAM receives the DP-DPD exit command DP-DPDX as the second command, the MRAM directly returns from the direct partial DPD state to the active state. The DP-DPD exit command DP-DPDX is a command issued when returning from the direct partial DPD state to the active state. At this time, the main controller MCNT restores the power supply to the other memory banks BNK while maintaining the activated state of the sense amplifier SA of the memory bank BNK selected for data reading or data writing. The main controller MCNT also restores power supply to the memory cell array MCA of the selected memory bank BNK.

  FIG. 5A to FIG. 5D are diagrams showing configurations and states of the memory bank BNK and its peripheral part of the MRAM according to the first embodiment. The MRAM according to the present embodiment includes four memory banks BNK0 to BNK3. Memory banks BNK0 to BNK3 include memory cell arrays MCA0 to MCA3, sense amplifier units SA0 to SA3, a write driver WD shown in FIG. 2, a main controller MCNT, and the like.

  Memory cell arrays MCA0 to MCA3 are provided corresponding to memory banks BNK0 to BNK3, respectively. The sense amplifier units SA0 to SA3 are provided corresponding to the memory cell arrays MCA0 to MCA3, respectively. Each of the sense amplifier units SA0 to SA3 includes a latch circuit that temporarily stores data in the memory cell arrays MCA0 to MCA3 corresponding to the data read operation or data write operation. Broken lines shown in FIGS. 5A to 5D indicate boundaries between the memory cell arrays MCA0 to MCA3 and the sense amplifier units SA0 to SA3.

  The power supply PS may be the power supply voltage VDD generated by the power generator PG shown in FIG. Alternatively, when the power generator PG is not provided, the external power supply voltage is directly used as the power supply voltage VDD as it is. First switches SW10n to SW13n are provided between the power supply PS and the memory cell arrays MCA0 to MCA3, respectively. Second switches SW20n to SW23n are provided between the power supply PS and the sense amplifier units SA0 to SA3, respectively. The first switches SW10n to SW13n and the second switches SW20n to SW23n are each formed using a P-type FET (Field Effect Transistor). The first switches SW10n to SW13n and the second switches SW20n to SW23n are controlled by the switch controllers SWCn and SWC20n to SWC23n shown in FIG.

  Note that the first switches SW10n to SW13n perform the same operation as described later with reference to FIG. Accordingly, the memory cell arrays MCA0 to MCA3 do not necessarily need to include the individual first switches SW10n to SW13n, respectively. That is, the first switches SW10n to SW13n may be a single common switch SWn. In this case, a single common switch SWn is provided between the memory cell arrays MCA0 to MCA3 and the power source PS. Hereinafter, the first switch is referred to as SW10n to SW13n (SWn).

  In the present embodiment, the memory cell arrays MCA0 to MCA3 of the memory banks BNK0 to BNK3 are connected to the power supply PS or disconnected from the power supply PS depending on the conduction states of the first switches SW10n to SW13n (SWn), respectively. . The sense amplifier sections SA0 to SA3 of the memory banks BNK0 to BNK3 are connected to the power supply PS or disconnected from the power supply PS depending on the conduction state of the second switches SW20n to SW23n, respectively.

  The sense amplifier units SA0 to SA3 detect data of the corresponding memory cell arrays MCA0 to MCA3 via the multiplexer MUX (see FIG. 2). The write driver WD writes data to the corresponding memory cell arrays MCA0 to MCA3 via the multiplexer MUX.

  The number of memory banks, the number of memory cells in the memory bank, the number of bit lines BL, the number of word lines WL, the type of power supply PS, the types of first and second switches, and the first and second The number of the two switches is not limited to this embodiment.

  In FIG. 5A, all of the memory banks BNK0 to BNK3 are in an idle state. At this time, the first switches SW10n to SW13n and the second switches SW20n to SW23n are all in a conductive state. Next, in the active state, for example, as shown in FIG. 5B, it is assumed that the memory bank BNK0 is selected. In this case, data reading or data writing is executed with respect to the selected memory bank BNK0. In the data read or data write operation, in the selected memory bank BNK0, the sense amplifier unit SA0 once reads the data of the selected page of the memory cell array MCA0. Since the sense amplifier unit SA0 has a latch circuit therein, the read data is temporarily stored in the sense amplifier unit SA0. Also at this time, the first switches SW10n to SW13n and the second switches SW20n to SW23n are in a conductive state.

  When the direct partial DPD command DP-DPD is received when the MRAM is in the active state, the main controller MCNT changes the MRAM from the active state to the direct partial DPD state. In the direct partial DPD state, as shown in FIG. 5C, the main controller MCNT maintains the power supply to the sense amplifier unit SA0 of the selected memory bank BNK0 and selects the memory cell array MCA0 and the selected memory bank BNK0. Power supply to unselected memory banks BNK1 to BNK3 other than the memory bank BNK0 is cut off. At this time, only the second switch SW20n is in a conductive state, and the other second switches SW21n to SW23n and the first switches SW10n to SW13n are in a nonconductive state. Therefore, only the sense amplifier unit SA of the selected memory bank BNK is in the activated state, and the other elements are in the DPD state. Thereby, the power consumption in the direct partial DPD state becomes very low.

  When the MRAM receives the exit command DP-DPDX, the main controller MCNT changes the MRAM from the direct partial DPD state to the active state or the idle state. At this time, the main controller MCNT restores power supply to the memory cell array MCA0 of the selected memory bank BNK0 and the non-selected memory banks BNK1 to BNK3 other than the selected memory bank BNK0. That is, the first switches SW10n to SW13n and the second switches SW20n to SW23n are all returned to the conductive state. Thereby, as shown in FIG. 5D, the memory cell array MCA0 is in an active state, and the non-selected memory banks BNK1 to BNK3 are in an idle state. Of course, the sense amplifier unit SA0 maintains an active state.

  The page data to be read or written in the selected memory bank BNK0 is kept latched in the sense amplifier unit SA0. Therefore, it is not necessary to read data again to the sense amplifier unit SA0 in the selected memory bank BNK0. Thereby, after returning to the active state, the MRAM can immediately restart the sequence of the data read or data write operation. As a result, the return time from the direct partial DPD state to the active state can be shorter than the time required to return from the DPD state to the idle state and return from the idle state to the active state.

  FIG. 6A is a circuit diagram illustrating a configuration of a switch controller SWCn that controls the first switches SW10n to SW13n (SWn). FIG. 6B is a circuit diagram illustrating a configuration of the switch controllers SWC20n to SWC23n that control the second switches SW20n to SW23n.

  The switch controller SWCn shown in FIG. 6A functions as a buffer that applies the logical state of the direct partial DPD command DP-DPD to the first switches SW10n to SW13n (SWn) as they are. The switch controller SWCn is provided in common to the first switches SW10n to SW13n (SWn). Accordingly, when the direct partial DPD command DP-DPD is in an inactive state (logic low), the first switches SW10n to SW13n (SWn) are maintained in the conductive state in common. As a result, the memory cell arrays MCA0 to MCA3 enter an idle state or an active state. When the direct partial DPD command DP-DPD becomes active (logic high), the first switches SW10n to SW13n (SWn) are commonly switched to the non-conductive state. As a result, the memory cell arrays MCA0 to MCA3 enter the DPD state.

  The switch controllers SWC20n to SW23n shown in FIG. 6B are provided corresponding to the second switches SW20n to SW23n, respectively. The switch controller SWC20n controls the second switch SW20n based on the direct partial DPD command DP-DPD and the activation command of the memory bank BNK0. The switch controller SWC21n controls the second switch SW21n based on the direct partial DPD command DP-DPD and the activation command of the memory bank BNK1. The switch controller SWC22n controls the second switch SW22n based on the direct partial DPD command DP-DPD and the activation command of the memory bank BNK2. The switch controller SWC23n controls the second switch SW23n based on the direct partial DPD command DP-DPD and the activation command of the memory bank BNK3.

  When the direct partial DPD command DP-DPD is in an inactive state (logic low), the second switches SW20n to SW23n maintain the conductive state regardless of the activation commands of the memory banks BNK0 to BNK3. Thereby, the memory cell arrays MCA0 to MCA3 can be in an idle state or an active state.

  When the direct partial DPD command DP-DPD is activated (logic high), the second switches SW20n to SW23n are switched depending on the activation commands of the memory banks BNK0 to BNK3.

  For example, when the direct partial DPD command DP-DPD is activated while the memory bank BNK0 is selected in the active state, the activation command of the memory bank BNK0 is activated to logic high. Therefore, even if the direct partial DPD command DP-DPD is activated, the second switch SW20n maintains the conductive state. On the other hand, the activation commands of the other memory banks BNK1 to BNK3 are logic low. Accordingly, the second switches SW21n to SW23n are turned off. That is, only the sense amplifier SA of the memory bank BNK0 selected at the time of data reading or data writing is maintained in the active state, and the memory cell array MCA and the memory banks BNK1 to BNK3 of the memory bank BNK0 are in the DPD state.

  The switch controllers SWCn and SWC20n to SWC23n shown in FIGS. 6A and 6B may be incorporated in the main controller MCNT shown in FIG.

  Next, the operation of the MRAM according to the present embodiment will be described in more detail.

  FIG. 7 is a timing chart showing the operation of the MRAM according to the first embodiment. The MRAM operates based on the clock signal CK. In FIG. 7, a direct partial DPD command (first command) DP-DPD for shutting off the power supply PS is issued during the data read operation or data write operation.

  Note that the first switches SW10n to SW13n perform the same operation as shown in FIG. Therefore, as described above, the first switches SW10n to SW13n may be a single common switch SWn.

  Before t1, the memory banks BNK0 to BNK3 are in an idle state (standby state). At this time, since the direct partial DPD command DP-DPD is deactivated to logic low, the switch controllers SWCn and SWC20n to SWC23n are connected to the first and second switches SW10n to SW13n (SWn) and SW20n to SW23n, respectively. A logic low is input to the gate electrode. Accordingly, the first and second switches SW10n to SW13n (SWn) and SW20n to SW23n are in a conductive state (ON state). The memory banks BNK0 to BNK3 are all supplied with power from the power source PS.

  Next, at t1, an active command ACT is issued. At this time, for example, the memory bank BNK0 is selected. As a result, the memory bank BNK0 changes from the idle state to the active state. Since the direct partial DPD command DP-DPD maintains a logic low, the switch controllers SWCn and SWC20n to SWC23n input a logic low to the gate electrodes of the first and second switches SW10n to SW13n and SW20n to SW23n. ing. Therefore, from t1 to t2, the first switches SW10n to SW13n (SWn) and the second switches SW20n to SW23n are kept in the conductive state (ON state).

  In the active state, the memory bank BNK0 is activated to read or write data, and the selected word line WLs is activated to logic high. As a result, the data of the selected page in the memory cell array MCA0 is read out to the sense amplifier unit SA0 via the bit line BL.

  Thereafter, when a read command is issued, the data stored in the sense amplifier unit SA0 is output to the outside of the MRAM via the data buffer DQB and the input / output unit I / O. When a write command is issued, the data stored in the sense amplifier unit SA0 is updated with external write data, and the updated data is written back to the memory bank BNK0.

  On the other hand, when the direct partial DPD command DP-DPD is issued during the data read or data write operation (t2), the switch controllers SWCn and SWC21n to SWC23n shown in FIGS. 6 (A) and 6 (B) The second switches SW21n to SW23n and the first switches SW10n to SW13n (SWn) other than the second switch SW20n are turned off. The switch controller SWC20n maintains the second switch SW20n corresponding to the sense amplifier unit SA0 in a conductive state.

  Since the first switches SW10n to SW13n (SWn) are turned off, the selected word line WLs of the selected memory bank BNK0 is also deactivated. Accordingly, the data on the bit line BL is not maintained in the selected memory bank BNK0.

  However, the sense node SN0 (latch circuit) of the sense amplifier unit SA0 retains data by receiving power supply from the power source PS. Thereby, even when the MRAM transitions from the active state to the direct partial DPD state, the data of the sense amplifier unit SA0 is retained.

  When the DP-DPD exit command DP-DPDX is issued at t3, the DP-DPD command is inactivated. As a result, the memory banks BNK0 to BNK3 return from the direct partial DPD state to the active state or the idle state. At this time, the switch controllers SWCn and SWC20n to SWC23n maintain the conduction state of the second switch SW20n of the memory bank BNK0 selected for data reading or data writing, and the second switches SW21n to SW23n and the second switches SW21n to SW23n. 1 switches SW10n to 13n (SWn) are turned on.

  The sense node SN0 of the sense amplifier unit SA0 continues to hold data in the memory cell array MCA0. Therefore, the MRAM can immediately shift the memory bank BNK0 to the active state without reissuing the active command ACT. That is, the operation of reading data from the memory cell array MCA0 to the sense amplifier SA0 in the selected memory bank BNK0 can be omitted. Accordingly, the read latency can be shortened. As a result, the MRAM according to the present embodiment can read or write the data of the sense amplifier SA0 in a short time after returning from the direct partial DPD state to the active state. Further, the MRAM can continuously execute the data reading or data writing operation interrupted at t2 from t3.

  In the direct partial DPD state, the memory cell array MCA0 and the memory banks BNK1 to BNK3 other than the sense amplifier SA0 of the selected memory bank BNK0 are disconnected from the power supply PS. Therefore, the MRAM according to the present embodiment can suppress power consumption as much as possible while maintaining a high-speed operation.

  As described above, in the MRAM according to the present embodiment, in each of the memory banks BNK0 to BNK3, the power supply path (first switch) of the memory cell arrays MCA0 to MCA3 and the power supply path (second switch) of the sense amplifier units SA0 to SA3. ) Individually. That is, in the direct partial DPD state, a region where the power is cut off is partitioned. Thereby, when the direct partial DPD command DP-DPD is issued during the data read operation or the data write operation, the second switch SW20n corresponding to the selected sense amplifier SA0 is kept in the conductive state, and the other second second The switches SW21n to SW23n and the first switches SW10n to SW13n (SWn) can be turned off. As a result, the MRAM according to the present embodiment can shorten the time required to return from the direct partial DPD state to the active state or the idle state, and can suppress power consumption.

(Second Embodiment)
FIG. 8A to FIG. 8C are diagrams showing configurations and states of the memory bank BNK and its peripheral part of the MRAM according to the second embodiment. The MRAM according to the second embodiment does not include the second switches SW20n to SW23n. First switches SW10n to SW13n (SWn) provided between the power source PS and the memory cell array MCA supply power to the memory cell arrays MCA and sense amplifier units SA in the memory banks BNK0 to BNK3, respectively, or Shut off the power. Accordingly, the memory banks BNK0 to BNK3 are each supplied with power as a whole memory bank. Alternatively, power supply to the memory banks BNK0 to BNK3 is cut off as a whole memory bank. The first switches SW10n to SW13n may be a single common switch SWn similarly to the first switch of the first embodiment.

  One mode register MRv for holding the operation state of the MRAM is provided for the MRAM chip. As described above, the mode register MRv stores the operation state of the MRAM. For example, the mode register MRv stores the burst type, burst length, latency period, and the like. The mode register MRv is composed of a volatile memory and continuously receives power from the power source PS. The mode register MRv is, for example, a D flip-flop.

  Other configurations of the second embodiment may be the same as the corresponding configurations of the first embodiment.

  In FIG. 8A, the memory bank BNK0 selected in the data read operation or data write operation is in the active state, and the memory banks BNK1 to BNK3 are in the idle state. When the MRAM receives the direct partial DPD command (first command) DP-DPD when the selected memory bank BNK0 is in the active state in this way, the main controller MCNT keeps the mode register MRv connected to the power supply, The first switches SW10n to SW13n (SWn) are turned off. Thereby, as shown in FIG. 8B, the memory banks BNK0 to BNK3 transition from the active state or the idle state to the DPD state.

  At this time, the data in the mode register MRv is held. Therefore, the DP-DPD state according to the second embodiment is also different from the DPD state in the LPDDR2 standard.

  Then, after receiving the first command DP-DPD, when receiving the exit command (second command) DP-DPDX for returning to the state of the data read operation or the data write operation, the main controller MCNT receives the first command DP-DPD. The switches SW10n to SW13n (SWn) are turned on. Thereby, as shown in FIG. 8C, the memory banks BNK0 to BNK3 return to the idle state. Further, the selected memory bank BNK0 returns from the idle state to the active state.

  Here, the first switches SW10n to SW13n (SWn) control the power supply of the entire memory banks BNK0 to BNK3, respectively. Therefore, the selected memory bank BNK0 cannot hold the data latched in the sense amplifier SA when the active memory state transitions to the direct partial DPD state. Therefore, as shown in FIG. 9, in the second embodiment, when the MRAM returns from the direct partial DPD state to the active state, the MRAM temporarily passes through the idle state, whereby the data is transferred to the sense amplifier SA of the selected memory bank BNK0. Need to be reloaded. That is, the MRAM according to the second embodiment can transition from the active state to the direct partial DPD state. However, when returning from the direct partial DPD state to the active state, the MRAM returns to the active state once after passing through the idle state. To do.

  FIG. 9 is a state diagram of the MRAM according to the second embodiment. As shown in FIG. 9, when returning from the direct partial DPD state to the active state, the MRAM according to the second embodiment temporarily returns to the active state after passing through the idle state. Other state transitions of the second embodiment are the same as the corresponding state transitions of the first embodiment.

  FIG. 10 is a timing chart showing the operation of the MRAM according to the second embodiment. First, the memory bank BNK0 is in an active state, and data is read from the memory cell array MCA0 of the memory bank BNK0 to the sense amplifier SA0.

  When the direct partial DPD command (first command) DP-DPD is issued at t1, the main controller MCNT sets the switches SW10n to SW13n (SWn) to the non-conduction state (off state). As a result, the memory banks BNK0 to BNK3 are disconnected from the power source PS and the power supply is cut off. Therefore, the memory banks BNK0 to BNK3 transition from the active state or the idle state to the DPD state.

  On the other hand, from t1 to t2, the mode register MRv continues to receive power from the power source PS.

  When the exit command DP-DPDX as the second command is issued at t2, the main controller MCNT returns the switches SW10n to SW13n (SWn) to the conductive state (ON state). As a result, the memory banks BNK0 to BNK3 return to the idle state. Since the mode register MRv continues to receive power from the power source PS, it is not necessary to write data to the mode register MRv when the memory banks BNK0 to BNK3 return to the idle state. Accordingly, the time for returning from the direct partial DPD state to the idle state is shortened.

  Thereafter, when an active command ACT is issued at t3, the selected memory bank BNK0 returns from the idle state to the active state. At this time, the mode register MR and the sense amplifier SA of the selected memory bank BNK0 hold the original data. Therefore, the MRAM can continuously execute the data reading or data writing operation interrupted at t1 from t3.

(Third embodiment)
FIG. 11A to FIG. 11C are diagrams showing configurations and states of the memory bank BNK and its peripheral part of the MRAM according to the third embodiment. The MRAM according to the third embodiment includes a register switch SWRn between the mode register MRnv and the power supply PS. The mode register MRnv is composed of a nonvolatile memory. The mode register MRnv is, for example, an MRAM. Other configurations of the third embodiment may be the same as the corresponding configurations of the second embodiment.

  In FIG. 11A, the memory bank BNK0 selected in the data read operation or the data write operation is in the active state, and the memory banks BNK1 to BNK3 are in the idle state. At this time, the register switch SWRn is in a conductive state (on state), and the mode register MRnv is supplied with power from the power source PS.

  When the MRAM receives the direct partial DPD command DP-DPD when the selected memory bank BNK0 is in the active state, the main controller MCNT turns off the first switches SW10n to SW13n (SWn). Thereby, as shown in FIG. 11B, the memory banks BNK0 to BNK3 transition from the active state or the idle state to the DPD state.

  Further, the main controller MCNT sets the register switch SWRn in a non-conduction state (off state) and disconnects the mode register MRnv from the power source. Since the mode register MRnv is composed of a nonvolatile memory, the data in the mode register MRnv is retained even when the power is turned off.

  After receiving the direct partial DPD command DP-DPD, when receiving the DP-DPD exit command (second command) DP-DPDX for returning to the state of the data read operation or the data write operation, the main controller MCNT The first switches SW10n to SW13n (SWn) and the register switch SWRn are turned on. As a result, as shown in FIG. 11C, the memory banks BNK0 to BNK3 return to the idle state. Further, the selected memory bank BNK0 returns from the idle state to the active state. Note that the first switches SW10n to SW13n may be a single common switch SWn as in the first embodiment.

  The state diagram of the MRAM according to the third embodiment may be the same as the state diagram shown in FIG.

  FIG. 12 is a timing chart showing the operation of the MRAM according to the third embodiment. First, the memory bank BNK0 is in an active state, and data is read from the memory cell array MCA0 of the memory bank BNK0 to the sense amplifier SA0.

  When the first command DP-DPD is issued at t1, the main controller MCNT sets the switches SW10n to SW13n (SWn) to a non-conduction state (off state). As a result, the memory banks BNK1 to BNK3 are disconnected from the power source PS and the power supply is cut off. Therefore, the memory banks BNK1 to BNK3 transition from the active state or the idle state to the DPD state.

  Furthermore, the main controller MCNT sets the register switch SWRn to a non-conduction state (off state). Thereby, mode register MRnv is disconnected from power supply PS.

  When the exit command DP-DPDX as the second command is issued at t2, the main controller MCNT returns the first switches SW10n to SW13n (SWn) and the register switch SWRn to the conductive state (ON state). As a result, the memory banks BNK0 to BNK3 return to the idle state. Since the mode register MRnv is a non-volatile memory and holds data, it is not necessary to write data to the mode register MRnv. Accordingly, the time for returning from the direct partial DP-DPD state to the idle state is shortened.

  Since the mode register MRnv is a nonvolatile memory, it is disconnected from the power source PS in the DP-DPD state. Thereby, the MRAM according to the third embodiment can further reduce the power consumption in the DPD state.

  Thereafter, when an active command ACT is issued at t3, the selected memory bank BNK0 returns from the idle state to the active state. At this time, the mode register MR and the sense amplifier SA of the selected memory bank BNK0 hold the original data. Therefore, the MRAM can continuously execute the data reading or data writing operation interrupted at t1 from t3.

(Fourth embodiment)
FIG. 13A to FIG. 13D are diagrams showing configurations and states of the memory bank BNK and its peripheral part of the MRAM according to the fourth embodiment.

  In the fourth embodiment, the switches SW10n to SW13n are individually provided between the power source PS and the memory banks BNK0 to BNK3. However, the second switches SW20n to SW23n are not provided. That is, the fourth embodiment does not have separate power switches for the memory cell array and the sense amplifier in the memory bank.

  The switches SW10n to SW13n control the overall power supply of the memory banks BNK0 to BNK3, respectively.

  The switches SW10n to SW13n can be controlled by switch controllers SWC20n to SWC23n shown in FIG. 6B, respectively.

  In the fourth embodiment, the memory banks BNK0 to BNK3 are connected to the power supply PS or disconnected from the power supply PS according to the conduction states of the switches SW10n to SW13n, respectively.

  In FIG. 13A, all of the memory banks BNK0 to BNK3 are in an idle state. At this time, the switches SW10n to SW13n are all in a conductive state. Next, in the active state, for example, as shown in FIG. 13B, it is assumed that the memory bank BNK0 is selected. In this case, data reading or data writing is executed with respect to the selected memory bank BNK0. In the data read or data write operation, in the selected memory bank BNK0, the sense amplifier unit SA0 once reads the data of the selected page of the memory cell array MCA0. Since the sense amplifier unit SA0 has a latch circuit therein, the read data is temporarily stored in the sense amplifier unit SA0. Also at this time, the switches SW10n to SW13n are all in a conductive state.

  When the direct partial DPD command DP-DPD is received when the MRAM is in the active state, the main controller MCNT changes the MRAM from the active state to the direct partial DPD state. In the direct partial DPD state, as shown in FIG. 13C, the main controller MCNT maintains power supply to the selected memory bank BNK0 and supplies power to the other non-selected memory banks BNK1 to BNK3. Cut off. At this time, only the switch SW10n is conductive, and the other switches SW11n to SW13n are nonconductive. Therefore, only the selected memory bank BNK0 is in the activated state, and the other memory banks BNK1 to BNK3 are in the DPD state. Therefore, the power consumption in the direct partial DPD state is very low.

  When the MRAM receives the DP-DPD exit command DP-DPDX, the main controller MCNT transitions the MRAM from the direct partial DPD state to the active state or the idle state. At this time, the switch controllers SWC21n to SWC23n restore the power supply to the non-selected memory banks BNK1 to BNK3. That is, the switches SW11n to SW13n are returned to the conductive state. Thereby, as shown in FIG. 13D, the non-selected memory banks BNK1 to BNK3 are in an idle state. Note that the selected memory bank BNK0 maintains an active state.

  The page data to be read or written in the selected memory bank BNK0 is kept latched in the sense amplifier unit SA0. Therefore, it is not necessary to read data again to the sense amplifier unit SA0 in the selected memory bank BNK0. Thereby, after returning to the active state, the MRAM can immediately restart the sequence of the data read or data write operation. As a result, the return time from the DPD state to the active state can be short.

  FIG. 14 is a timing chart showing the operation of the MRAM according to the fourth embodiment. The MRAM operates based on the clock signal CK. The clock signal CLK, command CMD, direct partial DPD command DP-DPD, and activation commands for the memory banks BNK0 to BNK3 may be the same as those operations shown in FIG.

  In the fourth embodiment, the switches SW10n to SW13n operate in the same manner as the second switches SW20n to SW23n of the first embodiment.

  Before t1, the memory banks BNK0 to BNK3 are in an idle state (standby state). At this time, since the direct partial DPD command DP-DPD is deactivated to logic low, the switch controllers SWC20n to SWC23n input logic low to the gate electrodes of the switches SW10n to SW13n. Therefore, the switches SW10n to SW13n are in a conductive state (ON state). That is, the memory banks BNK0 to BNK3 are all supplied with power from the power source PS.

  Next, at t1, an active command ACT is issued. At this time, the memory bank BNK0 is selected. In this case, the memory bank BNK0 changes from the idle state to the active state. Since the direct partial DPD command DP-DPD still maintains a logic low, the switch controllers SWC20n to SWC23n input a logic low to the gate electrodes of the switches SW10n to SW13n. Therefore, from t1 to t2, the switches SW10n to SW13n are kept in the conductive state (ON state).

  In the active state, the memory bank BNK0 is activated to read or write data, and the selected word line WLs is activated to logic high. As a result, the data of the selected page in the memory cell array MCA0 is read out to the sense amplifier unit SA0 via the bit line BL.

  In the fourth embodiment, when the direct partial DPD command DP-DPD is activated during the data read operation or data write operation (t2), the switch controllers SWC21n to SWC23n shown in FIG. SW13n is turned off. The switch controller SWC20n maintains the switch SW10n corresponding to the selected memory bank BNK0 in the conductive state. At this time, the sense node SN0 (latch circuit) held in the sense amplifier unit SA0 in the memory bank BNK0 holds data by receiving power supply from the power supply PS. Thereby, even if the MRAM transitions from the active state to the direct partial DPD state, the data in the memory bank BNK0 is retained.

  When the DP-DPD exit command DP-DPDX is issued at t3, the direct partial DPD command DP-DPD is inactivated. As a result, the memory banks BNK0 to BNK3 return from the direct partial DPD state to the active state or the idle state. At this time, the switch controllers SWC21n to SWC23n return the switches SW11n to SW13n to the conductive state while maintaining the conductive state of the switch SW10n of the selected memory bank BNK0.

  The sense node SN0 of the sense amplifier unit SA0 continues to hold data in the memory cell array MCA0. Therefore, the MRAM can immediately shift the memory bank BNK0 to the active state without reissuing the active command ACT. That is, the operation of reading data from the memory cell array MCA0 to the sense amplifier SA0 in the selected memory bank BNK0 can be omitted. Accordingly, the read latency can be shortened. As a result, the MRAM according to the present embodiment can read or write the data of the sense amplifier SA0 in a short time after returning from the direct partial DPD state to the active state.

  In the direct partial DPD state, the memory banks BNK1 to BNK3 other than the selected memory bank BNK0 are disconnected from the power source PS. Therefore, the MRAM according to the present embodiment can sufficiently suppress power consumption while maintaining a high speed operation.

  As described above, the MRAM according to the fourth embodiment can reduce the time required to return from the direct partial DPD state to the active state or the idle state, and can suppress power consumption.

(Modification 1)
FIG. 15 shows a first modification in which the mode register MRv according to the second embodiment is applied to the first embodiment. Thus, the second embodiment can be easily combined with the first embodiment. The operation of the MRAM according to the first modification can be easily understood from the first and second embodiments. Modification 1 can achieve the effects of both the first and second embodiments. In the first modification, the selected memory bank BNK0 can directly return from the direct partial DPD state to the active state. That is, the operations of the memory banks BNK0 to BNK3 in the first modification may be the same as those in the first embodiment. The operation of the memory register MRv of Modification 1 may be the same as that of the second embodiment.

(Modification 2)
FIG. 16 shows a second modification in which the mode register MRnv according to the third embodiment is applied to the first embodiment. As described above, the third embodiment can be easily combined with the first embodiment. The operation of the MRAM according to the second modification can be easily understood from the first and third embodiments. Modification 2 can achieve the effects of both the first and third embodiments. In the second modification, the selected memory bank BNK0 can directly return from the direct partial DPD state to the active state. That is, the operations of the memory banks BNK0 to BNK3 in the second modification may be the same as those in the first embodiment. The operation of the memory register MRv of Modification 2 may be the same as that of the third embodiment.

  Needless to say, the mode register MRv or MRnv can be easily applied to the MRAM according to the fourth embodiment. The configuration of the MRAM combining the second and fourth embodiments may be the same as the configuration shown in FIG. The configuration of the MRAM combining the third and fourth embodiments may be the same as the configuration shown in FIG. Thereby, the effect of 2nd and 4th embodiment or the effect of 3rd and 4th embodiment can be acquired.

  In the reading or writing of the above embodiment, the example in which the memory bank BNK0 is selected has been given, but it goes without saying that other memory banks BNK1 to BNK3 may be selected.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

MCA0 to MCA3... Memory cell array, BNK0 to BNK3... Memory bank, BL... Bit line, WL... Word line, PG. ..Sense amplifier section, WD... Write driver, PS .. power supply, SW10n to SW13n... First switch, SW20n to SW23n... Second switch, MRv, MRnv. SWRn ・ ・ ・ Register switch

Claims (9)

A memory cell array including a plurality of nonvolatile memory cells;
A sense amplifier that is provided corresponding to each of the plurality of memory cell arrays and detects and temporarily stores data in the memory cell array in a data read operation or a data write operation;
At least one first switch provided between a power source and the plurality of memory cell arrays;
A plurality of second switches respectively provided between a power source and the plurality of sense amplifier units;
A controller for controlling a conduction state of each of the first switch and the plurality of second switches,
When receiving the first command instructing the transition to the power-off state during the data read operation or the data write operation, the controller corresponds to the sense amplifier unit selected for data read or data write. 2. A semiconductor memory device, wherein the second switch and the first switch other than the second switch are made non-conductive while the second switch is made conductive. A memory cell array including a plurality of nonvolatile memory cells and a sense amplifier provided corresponding to each of the plurality of memory cell arrays and detecting and temporarily storing data in the memory cell array in a data read operation or a data write operation A plurality of memory banks including
A plurality of switches respectively provided between a power source and the plurality of memory banks;
A controller for controlling the conduction state of each of the plurality of switches,
When receiving a first command instructing a transition to a power-off state during a data read operation or a data write operation, the controller corresponds to the memory bank selected for data read or data write. A semiconductor memory device, wherein the other switches are made nonconductive while the switches are made conductive. The plurality of switches include at least one first switch provided between a power supply and the plurality of memory cell arrays, and a plurality of second switches provided between the power supply and the plurality of sense amplifier units, respectively. Including a switch,
When receiving the first command instructing the transition to the power-off state during the data read operation or the data write operation, the controller corresponds to the sense amplifier unit selected for data read or data write. 3. The semiconductor memory device according to claim 2, wherein the second switch and the first switch other than the second switch are set in a non-conductive state while the second switch is in a conductive state.   When receiving the second command for returning to the state of the data read operation or the data write operation after receiving the first command, the controller selects the sense amplifier selected for the data read or the data write. 4. The semiconductor memory device according to claim 3, wherein the second switch and the first switch other than the second switch corresponding to a part are turned on. 5.   The controller controls the plurality of switches based on an activation command for selecting any of the plurality of memory cell arrays and the first command in a data read operation or a data write operation. The semiconductor memory device according to claim 2. A mode register for holding an operating state of the semiconductor memory device;
6. The controller according to claim 2, wherein the controller keeps the mode register connected to a power source when receiving a first command for shutting off the power source during a data read operation or a data write operation. Any one of the semiconductor memory devices. A mode register for holding the operating state of the semiconductor memory device;
A register switch provided between a power source and the mode register;
7. The controller according to claim 2, wherein, when receiving the first command during a data read operation or a data write operation, the controller sets the register switch to a non-conductive state. 8. Semiconductor memory device. A plurality of memory cell arrays including a plurality of nonvolatile memory cells;
A plurality of first switches respectively provided between a power supply and the plurality of memory cell arrays;
A mode register for holding the operating state of the semiconductor memory device;
A controller for controlling a conduction state of each of the plurality of first switches,
When receiving the first command instructing the transition to the power-off state during the data read operation or the data write operation, the controller sets the first switch to the non-conductive state while keeping the mode register connected to the power source. A semiconductor memory device. A mode register for holding the operating state of the semiconductor memory device;
A register switch provided between a power source and the mode register;
9. The semiconductor device according to claim 8, wherein when the first command is received during a data read operation or a data write operation, the controller turns off the first switch and the register switch. Storage device.

Images