JP2013187712A - Level shifter circuit, semiconductor integrated circuit, and method of controlling level shifter circuit - Google Patents

Abstract

Provided are a level shifter circuit for holding a state so that a through current does not flow when an input signal is powered off without using a control signal, a semiconductor integrated circuit including the level shifter circuit, and a control method for the level shifter circuit .
An input circuit unit to which power is supplied from a first power supply system, and a first power supply system in which power is supplied from a second power supply system having an absolute value higher than that of the first power supply system and logically inverted from each other. A pair of input terminals, an amplitude conversion circuit unit that converts the signal into a complementary output signal of the second power supply system whose absolute value is higher than that of the first power supply system, and outputs the complementary output signal from the pair of output terminals; And a feedback circuit unit that converts the voltage of the output terminal into a low voltage signal and feeds back to the pair of input terminals so that no through current flows.
[Selection] Figure 1

Description

  The present invention relates to a level shifter circuit, a semiconductor integrated circuit, and a level shifter circuit control method. In particular, the present invention relates to a level shifter circuit that shifts a level of a low voltage system signal to a higher voltage signal, a semiconductor integrated circuit including the level shifter circuit, and a control method for the level shifter circuit.

  In recent semiconductor integrated circuits, internal circuits have been lowered in voltage for low power consumption operation. Most of the circuits mounted on the semiconductor integrated circuit are occupied by circuits operating at this low voltage (internal circuit). However, in order to achieve voltage level matching with the outside of the semiconductor integrated circuit, an input / output interface circuit (hereinafter simply referred to as an input circuit) is used. A circuit that operates with a high-voltage power supply having the same voltage level as the outside is used. In such a semiconductor integrated circuit, in order to transmit a signal from a circuit operating in a power supply system having a low absolute value of the power supply voltage to a circuit operating in a power supply system having a high absolute value, the signal of the power supply system having a lower signal amplitude A circuit that boosts the signal to the signal of the higher power supply system and converts the signal amplitude is required. In order to realize this function, a level shifter circuit is generally used.

  Further, in an internal circuit whose voltage has been lowered, the absolute value of the threshold voltage of the MOS transistor used there is also low. As a result, the off-leakage current of the MOS transistor becomes large, causing an increase in current consumption. As a technique for reducing the off-leakage current, a power-off technique that reduces current by stopping supply of power to an internal circuit that is not operating is widely used.

  In the step-up circuit of the level shifter circuit described above, for example, when a low voltage circuit in the internal circuit is shut off, the input of the high voltage circuit becomes unstable, a through current flows through the high voltage circuit, increasing power consumption and reducing element life. There was a problem that would become.

  In order to solve this problem, Patent Document 1 describes a technique for suppressing a through current of a high-voltage circuit using a signal for controlling the power-off when the power of the low-voltage circuit is cut off. FIG. 5 is a circuit diagram showing the configuration of the level shifter circuit described in Patent Document 1. In FIG.

  In FIG. 5, a signal from a circuit operating with a low-voltage power supply input from an input terminal A is input to the inverter 101, 102 operating with a low-voltage power supply, which constitutes the input circuit unit 150. Converted into two signals. The output of the inverter 102 includes an Nch transistor 110 that receives an input signal C for performing power-off control at the gate, and a Pch transistor 109 that receives a signal in the opposite phase of the input signal C generated by the inverter 116 operating with a high-voltage power supply at the gate. Through the analog switch 161, the signal having the opposite phase of the input signal C is connected to the gate, the source is connected to the drain of the Nch transistor 113 connected to the GND level, and the source is connected to the GND level. Connected to the gate of the Nch transistor 103. The signal converted into the reverse phase by the inverter 101 is an analog signal composed of an Nch transistor 112 that receives the input signal C at the gate and a Pch transistor 111 that receives the signal having the reverse phase of the input signal C generated by the inverter 116 at the gate. Through the switch 162, the signal having the opposite phase of the input signal C is connected to the gate, the source is connected to the drain of the Nch transistor 114 connected to the GND level, and the Nch transistor 104 has the source connected to the GND level. Connected to the gate.

  Further, the drain of the Nch transistor 103 is connected to the gate of a signal having an opposite phase to the input signal C generated by the inverter 116, and the drain of the Pch transistor 115 whose source is connected to the high voltage power source is connected to the source. The drain of the Pch transistor 115 is connected to the gate of the Pch transistor 106 connected to the source. The drain of the Nch transistor 104 is connected to the gate of the Pch transistor 105 and is connected to the drain of the Pch transistor 106, and is output from the output terminal Y of the level shifter circuit via the inverters 107 and 108 operating with a high voltage power supply. The

  Further, the output of the inverter 107 is returned to the input of the inverter 107 via the inverter 117 operated by a high voltage power supply, thereby constituting a latch circuit L. The Nch transistors 103 and 104, the Pch transistors 105 and 106, and the inverters 107, 108, and 117 constitute an output circuit unit 140.

  Hereinafter, the operation of the level shifter circuit described in Patent Document 1 configured as described above will be described. As an operation example, assume that the input terminal A is set to H level and the power cutoff control input terminal C is set to H level. At this time, the Pch transistor 109 and the Pch transistor 111 to be formed of the analog switches 161 and 162 constituting the first switch circuit, respectively, have their input signals C reversed in phase by the inverter 116 at their gates. Since a level signal is input, the signal is set to the ON state. The Nch transistor 110 and the Nch transistor 112 that form the analog switches 161 and 162, respectively, are set to the ON state because the same H level signal as the input signal C is input to their gates. Therefore, the gate of the Nch transistor 103 is set at the H level and turned ON, and conversely, the gate of the Nch transistor 104 is set at the L level and turned OFF.

  Since the Nch transistors 113 and 114 connected to the gates of the Nch transistors 103 and 104 receive the L level at the gate in which the H level signal input from the power cutoff control input terminal C is reversed in phase by the inverter 116. These Nch transistors 113 and 114 are set in the OFF state and do not affect the operation of this circuit while the signal inputted from the power cutoff control input terminal C is at the H level. Further, the Pch transistor 115 is set to the ON state because the gate receives the L level which is the opposite phase of the input terminal C. Therefore, in this state in which the signal input from the power cutoff control input terminal C is at the H level, this circuit operates exactly the same as the conventional level shifter circuit.

  When the signal C of the power cutoff control input terminal changes to L level, the gate voltages of the Pch transistors 109 and 111 and the Nch transistors 110 and 112 are inverted, so that the analog switches 161 and 162 are set to the OFF state, and , Nch transistors 113 and 114 are turned on by applying an H level which is the reverse phase of input signal C to their gates, whereby Nch transistors 103 and 104 apply an L level to their gates. Both are turned off. In addition, since the Pch transistor 115 receiving the H level which is the opposite phase of the input signal C is set to the OFF state, the sources of the Pch transistors 105 and 106 are disconnected from the high voltage power source, and the input of the inverter 107 is The value immediately before switching the input signal C is held by the inverter 117.

  Thus, in the level shifter circuit according to the prior art described in Patent Document 1, the signal amplitude of a circuit that is provided in a semiconductor integrated circuit that operates with a plurality of power supplies having different potentials and that operates with a low-voltage power supply operates with a high-voltage power supply. A level shifter circuit that converts the signal amplitude of the circuit to be operated includes an input circuit section that receives an input signal from a circuit that operates with the low-voltage power supply, and a latch circuit that holds an output signal to the circuit that operates with the high-voltage power supply An output circuit unit, a first switch circuit for stopping output of a signal from the input circuit unit to the output circuit unit in response to a control signal applied from the outside, and a control signal applied from the outside, And a second switch circuit for stopping the supply of power to the output circuit section excluding the latch circuit, and when the low voltage power supply is cut off, The output of the input circuit unit 150 that has become indefinite at the time of switching is disconnected from the output circuit unit 140 by the first switch circuits 161 and 162 in accordance with the control signal C from the outside, and the output circuit unit by the transistors 113 and 114 Nch when the low voltage power supply is shut off by fixing the potential input to 140 and stopping the power supply to the output circuit section 140 by the second switch circuit 115 according to the control signal C. Generation of a through current in the transistors 103 and 104 and the Pch transistors 105 and 106 can be prevented. Further, by providing the output circuit unit 140 with a latch circuit including the inverters 107 and 117, the output from the level shifter circuit can be held at a value immediately before the low-voltage power supply is shut off.

JP 2004-128590 A

  The following analysis is given by the present invention.

  In the conventional level shifter circuit described in Patent Document 1, when the power supply of the circuit that supplies the input signal is interrupted or becomes unstable, the logic level of the input signal becomes unstable, and the level shifter circuit Therefore, it is necessary to control the level shifter circuit using a control signal (for example, the control signal C of Patent Document 1) so that a leak current does not flow through the output signal or the output signal of the level shifter circuit becomes unstable. there were. For this reason, a circuit that receives the control signal and fixes the input signal so as to prevent a through current from flowing (for example, the first switch circuits 161 and 162 and the second switch circuit 115 of Patent Document 1 and the inverter 116 and the transistor) 113, 114, etc.) and the configuration becomes complicated.

  For the purpose of reducing power consumption, most internal circuits of recent semiconductor integrated circuits are low voltage circuits. However, the conventional level shifter circuit requires a high-voltage power supply control circuit to generate the control signal (input signal C) for blocking the through current, and the high-voltage power supply control signal generated by the control circuit. It is necessary to route (input signal C). The need for a control circuit increases the overall circuit scale, and the parallel running of high-voltage power supply wiring and low-voltage power supply wiring is likely to cause malfunction due to charge sharing. The signal requires special considerations such as wiring away from the signal of the low-voltage power supply, which raises the problem of increasing the complexity of the design.

  According to the first aspect of the present invention, power is supplied from the first power supply system, and the first input signal and the second input signal of the first power supply system are logically inverted from each other based on the signal of the first power supply system. , A first input terminal to which power is supplied from a second power supply system whose absolute value is higher than that of the first power supply system and to which the first input signal is connected, and the second power supply system. A voltage of the second power supply system in which the voltage levels of the first and second input signals are logically inverted from each other based on the voltage of the second input terminal to which the input signal is connected, and the first input terminal and the second input terminal. An amplitude conversion circuit unit having a first output terminal and a second output terminal for converting to a level and outputting the voltage; and converting the voltages of the first output terminal and the second output terminal into a low voltage system signal and The first input terminal and the second input signal as a feedback signal and a second feedback signal. Connected to the input terminal, when the power of the first power supply system is not supplied, a feedback circuit for maintaining the logic of the amplitude conversion circuit unit, a level shifter circuit comprising a are provided.

  According to a second aspect of the present invention, an internal circuit to which power is supplied from a first power supply system and an input / output to which power is supplied from a second power supply system whose absolute value is higher than that of the first power supply system. A level shifter circuit that receives a first power supply system signal from the internal circuit, converts the first power supply system signal into the second power supply system signal, and transmits the signal to the input / output circuit, the level shifter circuit comprising: An input circuit section for generating a first input signal and a second input signal of the first power supply system that are logically inverted from each other based on a signal supplied with power from the first power supply system and input from the internal circuit; A first input terminal to which power is supplied from the second power supply system and to which the first input signal is connected; a second input terminal to which the second input signal is connected; and the first input terminal and the second input terminal. The first input signal based on the voltage with the input terminal; An amplitude conversion circuit unit having a first output terminal and a second output terminal for converting the voltage level of the two input signals into a voltage level of a second power supply system obtained by logically inverting each other, and outputting the first output terminal and the second output terminal 2 The voltage of the output terminal is converted into a low voltage system signal and transmitted to the first input terminal and the second input terminal, and the logic of the amplitude conversion circuit unit is maintained when the power of the first power supply system is not supplied. And a feedback circuit unit.

  According to the third aspect of the present invention, the first input terminal and the second input terminal receive the first input signal and the second input signal, which are output from the first power supply system circuit and whose logics are inverted, respectively. A control method for a level shifter circuit that outputs a first output signal and a second output signal of the second power supply system whose absolute values are higher than those of the first power supply system and whose logics are inverted from each other. When power is not supplied to the circuit of the power system, feedback of high output impedance that is fed back to the first input terminal and the second input terminal based on the output voltage of the first output signal and the second output signal The state of the level shifter circuit is maintained by the system, and the voltage having the higher absolute value of the voltage output from the feedback system is set to a voltage as low as the power supply voltage of the first power supply system at most. Power is supplied to the level shifter circuit. The feedback system and method of controlling a level shifter circuit to allow no through current flows between the circuit of the first power supply system is provided when you are.

  According to the first aspect of the present invention, the first and second output terminal voltages of the amplitude conversion circuit unit are converted into low voltage signals regardless of whether or not the power of the first power supply system is supplied. Since the feedback circuit unit that feeds back to the first and second input terminals is provided, when the power supply of the first power supply system is shut off without giving a control signal from the outside, the state before shutting down It is possible to hold the operation. In addition, since the output terminal voltage is converted into a low voltage system signal and connected to the input terminal, it is possible to prevent leakage current from flowing between the first power system circuit.

  According to the second aspect of the present invention, an internal circuit to which power is supplied from a first power supply system, an input / output circuit to which power is supplied from a second power supply system having a higher absolute value, and an internal circuit In a semiconductor integrated circuit including a level shifter circuit that converts the level of the signal and transmits the level to the input / output circuit, the level shifter circuit does not use a control signal, and the through current is not generated when the power of the internal circuit is cut off. When the state is fixed so that it does not flow and the internal circuit is operating, the signal can be transmitted to the input / output circuit.

  According to the third aspect of the present invention, when power is not supplied to the circuit of the first power supply system, feedback is made to the input terminal based on the output voltage of the output signal, and the state of the level shifter circuit is changed to the through current. The level shift operation can be prevented from being prevented when the power supply is supplied to the circuit of the first power supply system while maintaining no flow. The level shifter circuit can be controlled without using a control signal indicating whether power is supplied to the circuit of the first power supply system.

It is a circuit block diagram of the level shifter circuit by one Embodiment of this invention. 2 is a timing chart showing a voltage conversion operation of the level shifter circuit shown in FIG. 1 and an operation when a low voltage power supply is cut off. It is a functional block diagram which shows the concept of the level shifter circuit by one Embodiment of this invention. It is a block diagram of the semiconductor integrated circuit by another embodiment. 10 is a circuit configuration diagram of a conventional level shifter circuit described in Patent Document 1. FIG.

  An outline of an embodiment of the present invention will be described.

  As shown in FIG. 1 and FIG. 3 as an example, the level shifter circuit (100) of one embodiment is supplied with power (LVcc) from the first power supply system, and based on the signal (A) of the first power supply system, An input circuit section (150) for generating a first input signal (VL−; N101) and a second input signal (VL +; N102) of the first power supply system which is logically inverted is provided. The level shifter circuit (100) is supplied with power (HVcc) from a second power supply system whose absolute value is higher than that of the first power supply system, and is connected to the first input signal (VL−; N101). Based on the voltages of the input terminal, the second input terminal to which the second input signal (VL +; N102) is connected, and the first input terminal and the second input terminal, the voltage levels of the first and second input signals are mutually changed. An amplitude conversion circuit section (130) having a first output terminal (node N103) and a second output terminal (node N104) for converting to a voltage level of the logically inverted second power supply system and outputting the voltage level is provided. Further, the level shifter circuit (100) converts the voltages (VH + and VH−; voltages of the nodes N103 and N104) at the first output terminal and the second output terminal into low-voltage signals (VLL− and VLL +). When the first power supply system (LVcc) is not supplied and connected to the first input terminal (node N101) and the second input terminal (node N102) as one feedback signal and second feedback signal, And a feedback circuit unit (170) for maintaining logic.

  The feedback circuit unit (170) is a level shifter that applies the voltages of the first output terminal (node N103) and the second output terminal (node N104) of the second power supply system that are logically inverted to each other regardless of whether the first power supply system is operating or shut off. Since it is converted into a low voltage signal that does not flow through the circuit (100) and is fed back to the first input terminal (node N101) and the second input terminal (node N102), the second level shifter circuit (100) from the outside It is possible to prevent a through current from flowing through the level shifter circuit without giving a control signal indicating whether the single power supply system is operating or shut off.

  The output impedance of the feedback circuit unit (170) is preferably higher than the output impedance of the input circuit unit (150) when the first power supply system is supplied to the input circuit unit (150). The amplitude conversion circuit unit (130) operates based on a signal input from the input circuit unit (150) regardless of the output of the feedback circuit unit (170).

  The first input terminal (node N101) is connected to the first input signal and the first feedback signal output from the feedback circuit. The second input terminal (node N102) is connected to the second input signal and the second feedback signal output from the feedback circuit unit (170). The output impedances of the first feedback signal and the second feedback signal output from the feedback circuit unit (170) are preferably higher than the output impedances of the first input signal and the second input signal output from the input circuit unit (150).

  Of the first feedback signal and the second feedback signal, the voltage having the higher absolute value is preferably as low as the power supply voltage of the first power supply system. When the first power supply system is supplied, it is possible to prevent a constant current from flowing between the input circuit unit (150) and the feedback circuit unit (170) except when the input signal is switched.

  Of the first feedback signal and the second feedback signal, the voltage having the higher absolute value voltage is low enough to sufficiently suppress the current flowing from the feedback circuit unit (170) to the circuit of the first power supply system (LVcc). It is. Furthermore, it is preferable that the potential difference between the first feedback signal and the second feedback signal is sufficient to maintain the logic state of the amplitude conversion circuit unit (130) when the first power supply system (LVcc) is shut off.

  The output of the feedback circuit unit (170) is also connected to the output of the input circuit unit (150), which is a circuit of the first power supply system, and is connected to the input terminals (N101, N102) of the amplitude conversion circuit unit (130). When the output voltage of the feedback circuit unit (170) is higher than the power supply voltage of the circuit of the first power supply system connected to the input terminals (N101, N102), the output terminal of the feedback circuit unit to the input terminal (N101, N102). There is a risk of current flowing through the circuit of the first power supply system to be connected. Therefore, whether the first power supply circuit is operating or the power supply is shut off, the voltage must be low (a voltage close to the ground voltage) so that no current flows into the first power supply circuit. Is desirable from the viewpoint of current consumption suppression. If the potential difference between the first feedback signal and the second feedback signal is sufficient to be amplified by the amplitude conversion circuit unit (130) when the first power supply system (LVcc) is shut off, the amplitude conversion circuit unit (130). Is amplified, and the output signal is converted into a low voltage signal and fed back, so that the state of the amplitude conversion circuit section (130) can be maintained.

  As shown in FIG. 1, the feedback circuit unit is substantially connected to one input terminal of the first input terminal and the second input terminal based on the output voltages of the first output terminal and the second output terminal. It is preferable to output a ground voltage and output a low voltage having an absolute value higher than the ground voltage to the other input terminal.

  As an example, as shown in FIG. 1, the feedback circuit unit includes a plurality of transistors in a stacked configuration, and a high voltage input due to a voltage drop caused by pinch-off of at least one transistor from the transistors connected to the second power supply system. Decrease level potential

  As shown in FIG. 1, the feedback circuit unit (170) includes a first voltage drop element (1109), a second voltage drop element (1112), and a gate connected to the second output terminal (N104). A first transistor having a current path between the source and the drain connected in series with the first voltage drop element (1109) between the second power supply system (HVcc) and the first input terminal (N101). 1108). The feedback circuit unit (170) has a gate connected to the first output terminal (N103), and a current path between the source and the drain connected between the ground and the first input terminal (N101). Two transistors (1110). Further, the feedback circuit unit (170) has a gate connected to the first output terminal (N103), and a current path between the source and the drain is connected in series with the second voltage drop element (1112) in the second power supply system (HVcc). ) And the second input terminal (N102), the third transistor (1111) connected between the gate and the second output terminal (N104), the current path between the source and the drain is grounded And a fourth transistor (1113) connected between the second input terminal (N102).

  As shown in FIG. 1, the first and second voltage drop elements are fifth and sixth transistors, respectively, whose gates are connected to the drain and cause a voltage drop between the drain and the source. The first to sixth transistors are preferably field effect transistors of the same conductivity type.

  In addition, a plurality of voltage drop elements are connected in series with the first transistor (1108) between the second power supply system (HVcc) and the first input terminal (N101), and the second power supply system (HVcc) and the second input terminal (N101). A plurality of voltage drop elements may be connected in series with the third transistor (1111) between the input terminal (N102). When it is necessary to greatly reduce the voltage of the feedback signal, the voltage to be lowered can be increased by connecting a plurality of voltage drop elements in series.

  As an example, as shown in FIG. 4, the semiconductor integrated circuit (200) of the embodiment has an internal circuit (201) to which power (LVcc) is supplied from the first power supply system and an absolute value higher than that of the first power supply system. An input / output circuit (202) to which power (HVcc) is supplied from a second power supply system, which is a voltage, and a second power supply (HVcc) system in response to a signal from the first power supply (LVcc) system from an internal circuit (201) The semiconductor integrated circuit (200) includes a level shifter circuit (100) that converts the signal into a signal and transmits the signal to the input / output circuit (202). As shown in FIG. 1 and FIG. 3, the level shifter circuit (100) is supplied with power (LVcc) from the first power supply system and is logically inverted from each other based on a signal input from the internal circuit (201). An input circuit unit (150) for generating a first input signal and a second input signal of the first power supply system is provided. The level shifter circuit (100) is supplied with power (HVcc) from the second power supply system, and has a first input terminal to which the first input signal is connected, a second input terminal to which the second input signal is connected, A first output terminal for converting the voltage level of the first input signal and the second input signal into a voltage level of a second power supply system obtained by logically inverting each other based on the voltages of the first input terminal and the second input terminal; And an amplitude conversion circuit unit (130) having a second output terminal. Further, the voltage of the first output terminal and the second output terminal is converted into a low voltage system signal and transmitted to the first input terminal and the second input terminal, and when the power of the first power system is not supplied, the amplitude conversion circuit And a feedback circuit unit (170) that maintains the logic of the unit (130).

  In one embodiment, a level shifter circuit control method uses a first input signal and a second input terminal, which are output from a first power supply (LVcc) circuit and whose logics are inverted to each other. Respectively, a method of controlling a level shifter circuit for outputting a first output signal and a second output signal of the second power supply (HVcc) system, whose absolute values are higher than those of the first power supply system, whose logics are inverted from each other. . In the above control method, when the power (LVcc) is not supplied to the circuit of the first power supply system, the first input terminal and the second output are based on the output voltages of the first output signal and the second output signal. The state of the level shifter circuit is maintained by a high output impedance feedback system that feeds back to the input terminal. Further, in the above control method, power is supplied to the circuit of the first power supply system by setting the voltage having the higher absolute value of the voltage output from the feedback system to a voltage as low as the power supply voltage of the first power supply system. A through current is prevented from flowing between the feedback system and the first power supply system circuit when the level shifter circuit is operating.

  Further, it is preferable that the output impedance of the feedback system connected to the first input terminal and the second input terminal is controlled to be higher than the first input signal and the second input signal. When power is not supplied to the circuit of the first power supply system, the state of the level shifter circuit is maintained by the feedback system, and the output impedance of the feedback system is higher than that of the first input signal and the second input signal even during operation. If it is impedance, the level shift operation based on the input signal is not hindered. Therefore, control based on the operation state of the first power supply system circuit can be performed without externally supplying a control signal indicating the operation state of the first power supply system circuit.

  Further, the feedback system is such that the voltage of the output signal having the higher absolute value of the first output signal and the second output signal is low enough to prevent current from flowing between the first power supply circuit and the circuit. In addition, the potential difference between the first input terminal and the second input terminal is converted into a voltage that provides a potential difference that maintains the logic of the level shifter output, and is based on the output voltage between the first output signal and the second output signal. Thus, it is preferable to feed back to the first input terminal and the second input terminal.

  The outline of the embodiment is as described above, but the drawing reference numerals attached to the outline are merely examples for facilitating understanding, and are not intended to limit the scope of the invention to the illustrated embodiment. Next, specific embodiments will be described in more detail with reference to the drawings.

[First Embodiment]
FIG. 3 is a functional block diagram of the level shifter circuit 100 according to the first embodiment. The input circuit unit 150 receives the signal A and outputs signals VL + and VL−. The signal A is an input signal from a circuit that operates by being supplied with the low voltage power supply LVcc. The input circuit unit 150 shapes the waveform of the input signal A of the low voltage power supply LVcc system, and outputs it as a non-inverted signal VL + and an inverted signal VL− of the low voltage power supply LVcc system. The input circuit unit 150 is connected to a low voltage power supply LVcc and a ground as a power supply. Both the non-inverted signal VL + and the inverted signal VL- are signals whose high level is LVcc level and whose low level is ground level. When the input signal A is at a high level, the non-inverted signal VL + outputs a high level and the inverted signal VL- outputs a low level. Conversely, when the input signal A is at a low level, the non-inverted signal VL + outputs a low level and the inverted signal VL- outputs a high level. When the low voltage power supply LVcc is cut off, the voltage level of the signal A becomes indefinite and no power is supplied to the input circuit unit 150 itself. Therefore, the non-inverted signal VL + and the inverted signal VL that are output signals of the input circuit unit 150 Both − are in the output high impedance state.

  The amplitude conversion circuit unit 130 inputs the low voltage power supply LVcc non-inverted signal VL + and the inverted signal VL− output from the input circuit unit 150, converts the voltage amplitude of the signal, and converts the high voltage power supply HVcc non-inverted signal. An inverted output signal VH + and an inverted output signal VH− are output. The inverted signal VL− is connected to the first input terminal of the amplitude conversion circuit unit 130 and the second input terminal of the non-inverted signal VL + amplitude conversion circuit unit 130, and the non-inverted output signal VH + is the first output terminal and the inverted output signal. VH- is output from the second output terminal.

  The amplitude conversion circuit unit 130 is connected to a high voltage power supply HVcc and the ground as a power supply. The high voltage power supply HVcc is supplied with a power supply voltage having an absolute value higher than that of the low voltage power supply LVcc. The non-inverted signal VL + and the inverted signal VL−, which are input signals to the amplitude conversion circuit unit 130, have a high level of LVcc and a low level of ground, whereas the non-inverted output signal VH + and inverted output signal VH− have a high level. Is a signal with the HVcc level and the low level with the ground level. That is, the high level input signal level LVcc is raised to the HVcc level and output as a high level signal. The low level is the ground level for both the input signal and the output signal.

  When the non-inverted signal VL + is higher in voltage (high level) than the inverted signal VL−, the amplitude conversion circuit unit 130 outputs a high level as the non-inverted output signal VH + and a low level as the inverted output signal VH−. On the contrary, when the non-inverted signal VL + is at a lower voltage (low level) than the inverted signal VL−, the low level is output as the non-inverted output signal VH + and the high level is output as the inverted output signal VH−.

  When it is necessary to further form the output signals VH + and VH− of the amplitude conversion circuit unit 130 and output them to the outside, the output signals VH + and VH− of the amplitude conversion circuit unit 130 are received and the waveform is generated by an inverter or the like. A waveform shaping unit 135 for shaping can be provided. Note that the waveform shaping unit 135 can freely output a non-inverted signal and an inverted signal to the outside depending on the number of stages of inverters and the like. In FIG. 3, the output signal VH− is inverted and output as a level shifter output signal Y, and the output signal VH + is inverted and output as a level shifter output signal YB.

  The feedback circuit unit 170 receives the non-inverted output signal VH + and the inverted output signal VH− output from the first and second output terminals by the amplitude conversion circuit unit 130, converts them into low-voltage signals, and performs amplitude conversion. Output to the first and second input terminals of the circuit unit 130. The output signal of the input circuit unit 150 is also connected to the first and second input terminals of the amplitude conversion circuit unit 130, but the output signal of the feedback circuit unit 170 is converted into a low-voltage signal and output. Thus, it is possible to prevent a constant current from flowing from the output of the feedback circuit unit 170 to the output of the input circuit unit 150.

  The feedback circuit unit 170 feeds back the output signal of the amplitude conversion circuit unit 130 to the input terminal of the amplitude conversion circuit unit 130 when the low voltage power supply LVcc is cut off and no power is supplied to the input circuit unit 150. The logic of the amplitude conversion circuit unit 130 before the power supply of the input circuit unit 150 is cut off is held. Further, since the state of the input terminal of the amplitude conversion circuit unit 130 is fixed, an unnecessary through current does not flow through the amplitude conversion circuit unit 130.

  On the other hand, when the low voltage power supply LVcc is supplied to the input circuit unit 150 and the input circuit unit 150 is operating based on the logic of the input signal A, the amplitude conversion circuit unit is based on the output signal of the input circuit unit 150. The output signal of the feedback circuit unit 170 has a higher output impedance than the output signal of the input circuit unit 150 so that 130 operates. Therefore, when the input circuit unit 150 is operating, the amplitude conversion circuit unit 130 operates based on the output signal of the input circuit unit 150 regardless of the logic of the output signal of the feedback circuit unit 170.

  Next, a specific circuit configuration of each functional block according to the first embodiment will be described. FIG. 1 is a circuit configuration diagram of a level shifter circuit 100 according to the first embodiment. The input circuit unit 150 includes inverter circuits 101 and 102. A signal A from an internal circuit (low voltage circuit: not shown) operating from the low voltage power supply LVcc inputted from the level shifter input terminal IN is inverted by the inverter circuit 101 and its output is connected to the node N101. The node N101 is connected to the input of the inverter circuit 102, and the output of the inverter circuit 102 is connected to the node N102. Both inverter circuits 101 and 102 are circuits to which power is supplied from the low voltage power supply LVcc.

  The amplitude circuit converter 130 includes N-channel transistors (hereinafter simply referred to as Nch transistors) 103 and 104, and P-channel transistors (hereinafter simply referred to as Pch transistors) 105 and 106. As the Nch transistor and the Pch transistor, a MOS transistor can be preferably used. In addition, an inverter 1107 is provided as a waveform shaping circuit that outputs an output signal to the outside.

  The node N101 is connected to the gate of the Nch transistor 103 which is the first input terminal of the amplitude conversion circuit unit 130. The source of the Nch transistor 103 is grounded, and the drain is connected to the node N103. The node N103 is a node serving as a first output terminal of the amplitude conversion circuit unit 130. The drain of the Nch transistor 103 is connected to the drain of the Pch transistor 105 and the gate of the Pch transistor 106.

  The node N102 is connected to the gate of the Nch transistor 104 that is the second input terminal of the amplitude conversion circuit unit 130. The source of Nch transistor 104 is grounded, and the drain of Nch transistor 104 is connected to node N104. The node N104 is a node that serves as the second output terminal of the amplitude conversion circuit unit 130. The drain of the Nch transistor 104 is connected to the drain of the Pch transistor 106 and the gate of the Pch transistor 105. Note that the sources of the Pch transistor 105 and the Pch transistor 106 are both connected to a high-voltage power supply HVcc. The inverter 1107 receives the node N104 as an input, and an output is output to the outside as a level shifter circuit output signal Y.

  In the example illustrated in FIG. 1, the feedback circuit unit 170 includes six Nch transistors 1108, 1109, 1110, 1111, 1112, and 1113. The source of the Nch transistor 1110 is connected to the ground, and the gate is connected to the node N103 which is the first output terminal of the amplitude conversion circuit unit 130. The drain of the Nch transistor 1110 is connected to the node N101 that is the first input terminal of the amplitude conversion circuit unit 130 together with the source of the Nch transistor 1109. The drain and gate of Nch transistor 1109 are connected in common to the source of Nch transistor 1108. The drain of the Nch transistor 1108 is connected to the high voltage power supply HVcc, and the gate is connected to the node N104 which is the second output terminal of the amplitude conversion circuit unit 130.

  Further, the source of the Nch transistor 1113 of the feedback circuit unit 170 is connected to the ground, and the gate is connected to the node N104 that is the second output terminal of the amplitude conversion circuit unit 130. The drain of the Nch transistor 1113 is connected to the node N102 which is the second input terminal of the amplitude conversion circuit unit 130 together with the source of the Nch transistor 1112. The drain and gate of the Nch transistor 1112 are commonly connected to the source of the Nch transistor 1111. The drain of the Nch transistor 1111 is connected to the high voltage power supply HVcc, and the gate is connected to the node N103 which is the first output terminal of the amplitude conversion circuit unit 130.

  The Nch transistors 1108 to 1110 and the Nch transistors 1111 to 1113 have symmetrical circuit configurations, and the source and drain are connected in series in three stages between the high voltage power supply HVcc and the ground. In particular, the sources and drains of the Nch transistors 1108 and 1109 are connected in series between the high voltage power supply HVcc and the node N101 which is the first input terminal of the amplitude conversion circuit unit 130, and the feedback circuit unit 170 functions as a feedback circuit. Sometimes it is driven to a high level via Nch transistors 1108 and 1109. As a result, the voltage when the high level is fed back to the first input terminal can be made sufficiently low. That is, both the Nch transistors 1108 and 1109 are pinched off when the potential difference between the gate and the source is equal to or lower than the threshold value of the Nch transistor, and no current flows between the drain and the source. Therefore, the voltage applied to the node N101, which is the first input terminal of the amplitude conversion circuit unit 130, by the Nch transistors 1108 and 1109 is lower than the high voltage power supply HVcc by two threshold levels of the Nch transistor (both Nch transistors 1108 and 1109 are pinched off). Higher voltage).

  Similarly, the sources and drains of the Nch transistors 1111 and 1112 are connected in series between the high voltage power supply HVcc and the node N102 which is the second input terminal of the amplitude conversion circuit unit 130, and the feedback circuit unit 170 functions as a feedback circuit. At this time, it is driven to a high level via Nch transistors 1111 and 1112. As a result, the voltage when applying a high level to the second input terminal can be made sufficiently low. That is, both the Nch transistors 1111 and 1112 are pinched off when the potential difference between the gate and the source becomes equal to or less than the threshold value of the Nch transistor, and no current flows between the drain and the source. Therefore, the voltage applied to the node N102 which is the second input terminal of the amplitude conversion circuit unit 130 by the Nch transistors 1111 and 1112 is lower than the high voltage power supply HVcc by two threshold levels of the Nch transistor (both Nch transistors 1111 and 1112 are pinched off). Higher voltage).

  In the circuit shown in FIG. 1, the high-level voltage applied to the input terminal is made low by using two-stage Nch transistors connected in series between the high-voltage power supply HVcc and the input terminal of the amplitude conversion circuit unit 130. By arbitrarily changing the number of stages of transistors connected in series, the high level voltage applied to the input terminal can be arbitrarily reduced. The high level voltage applied to the input terminal can also be controlled by changing the channel width or channel length of the transistor.

  Further, the Nch transistor and the Pch transistor constituting the circuit of the first embodiment shown in FIG. 1 are only examples, and any of them may be used as long as they have the same operation and characteristics. For example, when using a negative power supply voltage lower than the ground for the high-voltage and low-voltage power supplies, the same functions as the circuit shown in FIG. 1 can be obtained by replacing all the Nch transistors and Pch transistors shown in FIG. Can be realized using a negative power supply voltage. In this case, the high-voltage power supply voltage is supplied with a negative power supply voltage lower (higher in absolute value) than the low-voltage power supply voltage during operation.

  Next, the operation of the first embodiment will be described using the timing chart of FIG.

  FIG. 2 is a timing chart showing the voltage conversion operation of the level shifter circuit according to the first embodiment shown in FIG.

  FIG. 2 shows a waveform of each node in the circuit of FIG. 1. From the top, a signal A (level shifter input terminal IN) from a circuit operating with a low-voltage power supply and a node N101 (first of the amplitude conversion circuit unit 130) are shown. Input terminal), node N102 (second input terminal of amplitude conversion circuit unit 130), node N103 (first output terminal of amplitude conversion circuit unit 130), node N104 (second output terminal of amplitude conversion circuit unit 130), level shifter An output signal Y (level shifter output terminal OUT) of the entire circuit 100 is shown.

  First, when the signal A input from the input terminal IN changes from the high level to the low level of the low voltage power supply LVcc at the timing T1, the input circuit unit 150 has the output of the inverter circuit 101 (node N101) of the low voltage power supply LVcc. It becomes high level, and the output (node N102) of the inverter circuit 102 becomes low level. In the amplitude conversion circuit unit 130, the high level of the low voltage power supply LVcc is input to the node N101 which is the first input terminal, and the low level of the ground level is input to the node N102 which is the second input terminal. In the ON state, the Nch transistor 104 is set in the OFF state. Then, since a current flows between the source and drain of the Nch transistor 103, the voltage of the node N103 which is the first output terminal of the amplitude conversion circuit unit 130 drops toward the ground level. When the voltage at the node N103 decreases, the Pch transistor 106 is turned ON, and the voltage at the node N104 increases. Further, the voltage rise at the node N104 turns off the Pch transistor 105. In this way, the amplitude conversion circuit unit 130 is in a stable state with the node N103 as the first output terminal at the low level and the node N104 as the second output terminal at the high level of the high voltage power supply HVcc. Further, the logic of the node N104 is inverted via the inverter 1107, and a low level is output from the level shifter circuit output signal Y (level shifter output terminal OUT).

  In this state, in the feedback circuit unit 170, the Nch transistors 1110, 1111 and 1112 are turned off, and the Nch transistors 1108, 1109 and 1113 are turned on. At this time, the node N101 is supplied from the high level of the low voltage power supply LVcc output from the input circuit unit 150 (inverter 101) and the high voltage power supply HVcc output from the feedback circuit unit 170 through the Nch transistors 1108 and 1109. Levels will compete. However, the high level output from the feedback circuit unit 170 is supplied from the high voltage power supply HVcc to the node N101 by a voltage lower than the high voltage power supply HVcc by at least the sum of the threshold value of the Nch transistor 1108 and the threshold value of the Nch transistor 1109. If the high level voltage output from the feedback circuit unit 170 is substantially the same voltage as the low voltage power supply LVcc or lower than the low voltage power supply LVcc, the output of the input circuit unit 150 (inverter 101) and the feedback circuit unit 170 A current does not flow constantly through the node N101. The high level voltage output from the feedback circuit unit 170 to the node N101 is lower than the high level voltage output from the input circuit unit 150 (inverter 101), and the potential difference between the gate and the source of the Nch transistor 1109 is equal to or less than the threshold even if there is a potential difference. Since the voltage is applied, the Nch transistor 1109 is turned off. Further, since the P well in which Nch transistor 1109 is formed is also connected to a low potential (for example, ground potential), the PN junction between the source of Nch transistor 1109 connected to node N101 and the P well is also reverse-biased. As long as the reverse breakdown voltage of the PN junction is not exceeded, no leakage current flows.

  Next, an operation when the signal A input from the input terminal IN shifts from the low level to the high level of the low voltage power supply LVcc at the timing T2 will be described.

  In the input circuit unit 150, the output of the inverter circuit 101 (node N101) becomes low level, and the output of the inverter circuit 102 (node N102) becomes high level of the low voltage power supply LVcc. In the amplitude conversion circuit unit 130, the low level is input to the node N101 which is the first input terminal, and the high level of the low voltage power supply LVcc is input to the node N102 which is the second input terminal, so that the Nch transistor 103 is turned off. The Nch transistor 104 is set to the ON state. Then, since a current flows between the source and drain of the Nch transistor 104, the voltage at the node N104, which is the second output terminal of the amplitude conversion circuit unit 130, drops toward the ground level. When the voltage at the node N104 drops, the Pch transistor 105 is turned on, and the voltage at the node N103 rises. Further, the voltage increase at the node N103 turns off the Pch transistor 106. In this way, in the amplitude conversion circuit unit 130, the node N103 as the first output terminal is in a stable state at the high level of the high voltage power supply HVcc, and the node N104 as the second output terminal is at the low level. The logic of the node N104 is inverted via the inverter 1107, and the high level of the high voltage power supply HVcc is output from the level shifter circuit output signal Y (level shifter output terminal OUT).

  In this state, in the feedback circuit unit 170, the Nch transistors 1110, 1111 and 1112 are turned on, and the Nch transistors 1108, 1109 and 1113 are turned off. At this time, the node N102 is supplied through the Nch transistors 1111 and 1112 from the high level of the low voltage power supply LVcc output from the input circuit section 150 (inverter 102) and the high voltage power supply HVcc output from the feedback circuit section 170. Levels will compete. However, the high level output from the feedback circuit unit 170 is supplied from the high voltage power supply HVcc to the node N102 by a voltage lower than the high voltage power supply HVcc by at least the sum of the threshold value of the Nch transistor 1111 and the threshold value of the Nch transistor 1112. If the high level voltage output from the feedback circuit unit 170 is substantially the same voltage as the low voltage power supply LVcc or a voltage lower than the low voltage power supply LVcc, the output of the input circuit unit 150 (inverter 102) and the feedback circuit unit 170 There is no steady current flow through the node N102 therebetween.

  Up to here, the operation of a normal level shifter has been described. Next, the operation when the low voltage power supply LVcc is shut off at timing T3 will be described.

  When the low voltage power supply LVcc is cut off, power is not supplied to the input circuit unit 150, and the outputs (nodes N101 and N102) of the inverter circuits 101 and 102 become unstable potentials. However, since the Nch transistors 1111, 1112, and 1110 are ON, the potentials of the nodes N101 and N102 are stabilized at the low level and the high level, respectively, while maintaining the state. As a result, the state of the amplitude conversion circuit 130 is maintained, and the level shifter output terminal OUT continues to stably output the high level of the high voltage as the level shifter circuit output Y.

  Further, in the first embodiment, although not shown in the timing chart of FIG. 2, the low output can be stably performed even during the low output voltage conversion by the same operation as described above.

  In the first embodiment, the plurality of Nch transistors constituting the feedback circuit unit 170 have a driving capability weaker than that of the inverter circuits 101 and 102 constituting the input circuit unit 150. Thus, during normal operation, the change in the output signal of the input circuit unit 150 that has received the change in the input signal A inverts the output voltage of the feedback circuit unit 170 and is transmitted to the amplitude conversion circuit 130 to perform the level shift operation. I can do it.

  In the first embodiment, feedback (positive feedback) from the output terminals (nodes N103 and N104) of the amplitude conversion circuit unit 130 operated by the high voltage power supply HVcc to the input terminals (nodes N101 and N102) via the feedback circuit unit 170. )doing. Specifically, the low level is fed back through Nch transistors 1110 and 1113, and the high level is fed back through a two-stage configuration of Nch transistors 1108 and 1109 and a two-stage configuration of Nch transistors 1111 and 1112. doing. Due to the action of the feedback circuit unit 170, even when the power supply of the input circuit unit 150 operating with the low voltage power supply LVcc is cut off, the indefinite state from the input circuit unit 150 is not affected to the amplitude conversion circuit unit 130. It is possible to prevent generation of unnecessary through current, and to maintain the output from the level shifter circuit 100 at a value immediately before the low voltage power supply is cut off.

  In addition, at the node N101 and the node N102, the voltage drop from the high voltage power supply HVcc is caused by the pinch-off of the two-stage configuration of the Nch transistors 1108 and 1109 in the feedback circuit unit 170 and the two-stage configuration of the Nch transistors 1111 and 1112. If the potential and the high level of the low-voltage power supply LVcc of the output of the input circuit section 150 are set to substantially the same potential, normal operation can be performed without any unnecessary current flowing through the nodes N101 and N102.

Further, even if the high level output from the feedback circuit unit 170 to the node N101 or the node N102 is lower than the low voltage power supply LVcc, the Nch transistor 1109 or the Nch transistor 1112 is turned off, so that no current flows constantly. . This is because when the source potential of the Nch transistor 1109 or the Nch transistor 1112 is increased by the current flowing from the low voltage power supply LVcc, the gate-source voltage of the Nch transistor is biased to be in an OFF state.

  Further, when the low voltage power supply LVcc of the input circuit unit 150 is cut off, the high level output from the feedback circuit unit 170 to the node N101 or N102 is not shown in the inverter circuit (101 or 102) of the input circuit unit 150. It is also conceivable that a current flows from the drain of the Pch transistor to the low voltage power supply LVcc through the N well, which further leaks to the ground. If the leakage current is at a problem level, the high level voltage output from the feedback circuit unit 170 to the node N101 or N102 can be set to a voltage lower than that of the low voltage power supply LVcc. This is because if the high-level voltage output from the feedback circuit unit 170 is low, the leakage current flowing into the input circuit unit 150 where the power is cut off can be further reduced. In addition, if the high-level voltage applied to the nodes N101 and N102 which are input terminals is a voltage equal to or higher than the threshold value of the Nch transistors 103 and 104, the amplitude conversion circuit unit 130 is connected to the output terminal by the amplification function of the amplitude conversion circuit unit 130. A certain node N103, N104 can be driven to a sufficiently high level and low level to maintain the state. Therefore, if the voltage applied to the nodes N101 and N102 is equal to or higher than the threshold value of the Nch transistors 103 and 104, the high level voltage output from the feedback circuit unit 170 can be lowered.

  As a result, the additional circuit for interrupting the through current when the low-voltage power supply is interrupted, which is necessary in the prior art as described in Patent Document 1, is reduced, and the effect of reducing the circuit scale of the level shifter circuit can be obtained. .

  In addition, since it is not necessary to use a power-off control signal as shown in the above embodiment, it is not necessary to route a high-voltage control signal, which is a problem in the prior art, and the circuit scale of a semiconductor integrated circuit having a level shifter is reduced. The effect is also obtained.

[Second Embodiment]
FIG. 4 is a block diagram of a semiconductor integrated circuit according to the second embodiment. A semiconductor integrated circuit 200 according to the second embodiment shown in FIG. 4 is an embodiment in which the level shifter circuit 100 of the first embodiment is used inside the semiconductor integrated circuit 200. In other words, the second embodiment is an application example of the first embodiment.

  The semiconductor integrated circuit 200 includes an internal circuit 201 and an input / output circuit 202 that performs input / output operations between the internal circuit 201 and the outside. The internal circuit 201 is supplied with a low voltage power supply LVcc, which is a low power supply voltage, so that the power supply voltage can be lowered and a finer circuit can be used. Further, the high voltage power supply HVcc, which is a higher power supply voltage, is supplied to the input / output circuit 202 that performs input / output operations with the outside for the purpose of interfacing with the external circuit. The level shifter of the first embodiment further converts the amplitude of a low-voltage power supply LVcc logic signal output from the internal circuit 201 operating with the low-voltage power supply LVcc into a high-voltage power supply HVcc logic signal and transmits it to the input / output circuit 202. The circuit 100 is provided between the internal circuit 201 and the input / output circuit 202.

  The power supply circuit 203 supplies the power supplied from the power supply terminal 205 including the ground terminal to the input / output circuit 202 as it is as the high voltage power supply HVcc. In addition, the power supply circuit 203 includes an internal voltage generation circuit (not shown), reduces the power supply voltage supplied from the power supply terminal 205 to generate a low voltage power supply LVcc, and supplies the low voltage power supply LVcc to the internal circuit 201. An input / output terminal 204 is connected to the input / output circuit 202, and data is input / output to / from the outside via the input / output terminal 204. A signal output from the internal circuit 201 to the input / output circuit 202 is output via the level shifter circuit 100, but a signal input from the input / output circuit 202 to the internal circuit 201 does not pass through the level shifter circuit or the like. The signal is directly connected from the input / output circuit 202 to the internal circuit 201.

  In FIG. 4, the internal circuit 201 is schematically shown as one. However, in an actual semiconductor integrated circuit, the internal circuit 201 is divided into a plurality of blocks, and the power source is managed for each block. The power supplied to the unused block among the plurality of blocks is shut off. In such a case, the level shifter circuit 100 does not need to be controlled by the control signal from the internal circuit 201, and if the power of the block of the corresponding internal circuit 201 is cut off, the current flows through the state of the input terminal by the feedback circuit. The output state of the level shifter circuit 100 is maintained in a stable state. On the other hand, when power is supplied to the corresponding block of the internal circuit 201 and the block is operating, the feedback circuit does not hinder the level shift operation of the signal input from the internal circuit 201 to the level shifter circuit 100.

  Within the scope of the entire disclosure (including claims and drawings) of the present invention, the examples and the examples can be changed and adjusted based on the basic technical concept. Further, various combinations or selections of various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) within the scope of the claims of the present invention. Is possible. That is, the present invention naturally includes various modifications and changes that could be made by those skilled in the art according to the entire disclosure including the claims and the drawings, and the technical idea.

100: Level shifter circuit 101, 102: Inverter 103, 104, 110, 112, 113, 114, 1108, 1109, 1110, 1111, 1112, 1113: Nch transistor 105, 106, 109, 111, 115 : Pch transistors 107, 108, 116, 117, 1107: Inverter operating with high voltage power supply 130: Amplitude conversion circuit unit 135: Waveform shaping unit 140: Output circuit unit 150: Input circuit unit 170: Feedback circuit unit 200: Semiconductor integrated Circuit 201: Internal circuit 202: Input / output circuit 203: Power supply circuit 204: Input / output terminal 205: Power supply terminal N101, N102, N103, N104: Circuit connection node LVcc: Low voltage system (first power supply system) power supply HVcc: High Voltage system (second Source system) Power IN: level shifter input terminal OUT: level shifter output A: signal from a circuit operating at a low voltage power supply C: signal set at L level at the time of power shutoff Y: a level shifter circuit output

Claims (14)

An input circuit unit that is supplied with power from the first power supply system and generates a first input signal and a second input signal of the first power supply system that are logically inverted from each other based on a signal of the first power supply system;
A power is supplied from a second power supply system whose absolute value is higher than that of the first power supply system, a first input terminal to which the first input signal is connected, and a second input to which the second input signal is connected. A voltage level of the first and second input signals is converted to a voltage level of a second power supply system obtained by logically inverting the first and second input signals based on the voltage of the terminal and the first and second input terminals, and is output. An amplitude conversion circuit unit having an output terminal and a second output terminal;
The voltage of the first output terminal and the second output terminal is converted into a low voltage system signal and connected to the first input terminal and the second input terminal as the first feedback signal and the second feedback signal, and the first power supply A feedback circuit unit that maintains the logic of the amplitude conversion circuit unit when the system power is not supplied;
A level shifter circuit comprising:   2. The level shifter circuit according to claim 1, wherein an output impedance of the feedback circuit unit is higher than an output impedance of the input circuit unit when a first power supply system is supplied to the input circuit unit. The first input terminal is connected to the first input signal and a first feedback signal output from the feedback circuit unit;
The second input terminal is connected to the second input signal and a second feedback signal output from the feedback circuit unit,
The output impedance of the first feedback signal and the second feedback signal output from the feedback circuit unit is higher than the output impedance of the first input signal and the second input signal output from the input circuit unit. Or the level shifter circuit of 2 description.   4. The voltage having a higher absolute value of the first feedback signal and the second feedback signal is a low voltage at most about the power supply voltage of the first power supply system. The level shifter circuit according to claim 1.   Of the first feedback signal and the second feedback signal, the voltage having the higher absolute value voltage is low enough to sufficiently suppress the current flowing from the feedback circuit unit to the circuit of the first power supply system, and 5. The potential difference between the first feedback signal and the second feedback signal when the first power supply system is shut off has a potential difference sufficient to maintain the logic state of the amplitude conversion circuit unit. The level shifter circuit according to claim 1. The feedback circuit unit includes:
Based on the output voltages of the first output terminal and the second output terminal, a ground voltage is substantially output to one input terminal of the first input terminal and the second input terminal, and a ground voltage is applied to the other input terminal. 6. The level shifter circuit according to claim 1, wherein a low voltage having a higher absolute value is output.   The feedback circuit unit has a vertically stacked configuration of a plurality of transistors, and lowers an input high-level potential by a voltage drop due to pinch-off of at least one transistor from a transistor connected to the second power supply system. The level shifter circuit according to any one of claims 1 to 6. The feedback circuit unit includes:
A first voltage drop element;
A second voltage drop element;
A first gate connected to the second output terminal, and a current path between the source and drain connected in series with the first voltage drop element between the second power supply system and the first input terminal. Transistors
A second transistor having a gate connected to the first output terminal and a current path between a source and a drain connected between ground and the first input terminal;
A third gate is connected to the first output terminal, and a current path between the source and the drain is connected in series with the second voltage drop element between the second power supply system and the second input terminal. Transistors
A fourth transistor having a gate connected to the second output terminal and a current path between a source and a drain connected between ground and the second input terminal;
8. The level shifter circuit according to claim 1, further comprising: The first and second voltage drop elements are fifth and sixth transistors, respectively, whose gates are connected to the drain and cause a voltage drop between the drain and the source,
9. The level shifter circuit according to claim 8, wherein the first to sixth transistors are field effect transistors of the same conductivity type. A plurality of voltage drop elements are connected in series with the first transistor between the second power supply system and the first input terminal,
10. The level shifter circuit according to claim 8, wherein a plurality of voltage drop elements are connected in series with a third transistor between the second power supply system and the second input terminal. An internal circuit to which power is supplied from the first power supply system;
An input / output circuit to which power is supplied from a second power supply system whose absolute value is higher than that of the first power supply system;
A level shifter circuit that receives a signal of the first power supply system from the internal circuit, converts the signal to the second power supply system, and transmits the signal to the input / output circuit;
A semiconductor integrated circuit comprising:
The level shifter circuit includes:
An input circuit unit that generates a first input signal and a second input signal of the first power supply system that are logically inverted from each other based on a signal that is supplied with power from the first power supply system and that is input from the internal circuit;
A first input terminal to which power is supplied from the second power supply system and to which the first input signal is connected; a second input terminal to which the second input signal is connected; and the first input terminal and the second input. A first output terminal and a second output terminal for converting the voltage level of the first input signal and the second input signal into a voltage level of a second power supply system obtained by logically inverting each other based on the voltage with the terminal; Having an amplitude conversion circuit unit;
The voltage at the first output terminal and the second output terminal is converted into a low voltage system signal and transmitted to the first input terminal and the second input terminal, and the amplitude when the power of the first power system is not supplied. A feedback circuit unit that maintains the logic of the conversion circuit unit;
A semiconductor integrated circuit comprising: A first input signal and a second input signal, which are output from the first power supply system circuit and whose logics are inverted, are respectively received by the first input terminal and the second input terminal, and an absolute value is obtained from the first power supply system. A method for controlling a level shifter circuit that outputs a first output signal and a second output signal of a second power supply system that are high voltages and whose logics are inverted from each other,
High power that is fed back to the first input terminal and the second input terminal based on the output voltage of the first output signal and the second output signal when no power is supplied to the circuit of the first power supply system Maintain the state of the level shifter circuit by the impedance feedback system,
By making the voltage having the higher absolute value of the voltage output from the feedback system as low as the power supply voltage of the first power supply system, power is supplied to the circuit of the first power supply system, and the level shifter circuit operates. A level shifter circuit control method for preventing a through current from flowing between the feedback system and the circuit of the first power supply system.   13. The level shifter circuit according to claim 12, wherein an output impedance of the feedback system connected to the first input terminal and the second input terminal is controlled to be higher than that of the first input signal and the second input signal. Control method.   The feedback system has a voltage of an output signal having a higher absolute value of the first output signal and the second output signal at a low voltage so that no current flows between the first power supply system and the circuit. In addition, the potential difference between the first input terminal and the second input terminal is converted to a voltage that provides a potential difference that maintains the logic of the level shifter output, and is converted into an output voltage between the first output signal and the second output signal. 14. The shifter circuit control method according to claim 12, wherein feedback is made to the first input terminal and the second input terminal based on the first input terminal.

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