JP2013182986A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

In a capacitor using the inner wall and outer wall of a bottomed cylinder type lower electrode as a capacitor, a support structure that supports the upper part of the lower electrode is formed. This causes the phenomenon that the electrode depends.
A laminated structure of a second insulating film and a first insulating film having a wet etching rate slower than that of a core insulating film is used. When the core insulating film is removed, first and second support structures are used. Capacitor lowering of the capacitor lower electrode 18 is suppressed as a thick film support structure by the laminated structure of the insulating film, and then the second insulating film 14 is removed to form a support structure by the first insulating film 13. The decrease in the outer wall area of the lower electrode is suppressed.
[Selection] Figure 5

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a method of forming an electrode support structure in a semiconductor device having a capacitor including a bottomed cylinder type electrode.

  In a semiconductor device provided with a memory element such as a DRAM (Dynamic Random Access Memory), a capacitor holds charges. However, the electrode area for securing a storage capacitor Cs necessary for holding charges with the miniaturization is the same as the conventional type. Capacitor structures are becoming difficult. For this reason, as a capacitor electrode structure, there has been proposed a technique using inner and outer walls of a bottomed cylinder-type (crown structure) lower electrode (storage node electrode). When forming a lower electrode having a thickness of about 10 nm, a hole is formed in the core insulating film to be a mold to form a lower electrode conductor, and then the core insulating film is removed to expose the inner wall and the outer wall of the lower electrode. Let Wet etching is mainly used to remove the core insulating film, but the lower electrode collapses at that time, and there is a problem that a short circuit occurs due to defective formation of the capacitive film or contact between the lower electrodes. Arise. In order to prevent this, a technique of forming a support structure for supporting an electrode on the upper portion of the lower electrode and an insulating separation structure on the lower electrode is known (Patent Documents 1 to 5).

JP 2003-142605 A JP 2003-297852 A Japanese Patent Laying-Open No. 2005-064504 JP 2005-150747 A JP 2005-229097 A

  However, as the miniaturization further progresses and the electrode thickness becomes about 5 nm, the phenomenon that the electrode is swung occurs only with the support structure on the upper part of the electrode, and the yield is lowered due to poor formation of the capacitive film. ing.

  Although it is conceivable that the support structure is made thicker to prevent the electrodes from swaying, the outer wall area serving as the capacitance of the capacitor lower electrode is reduced by that amount, so that there is a limit to the thickness of the support structure.

  In the present invention, the first insulating film formed as the support structure has a structure of two or more stages, and the wet etching rate therebetween is lower than that of the core insulating film and faster than that of the first insulating film formed as the support structure. A manufacturing method is provided in which the insulating film is interposed to prevent the electrodes from swaying and then the second insulating film is removed to prevent the electrode area from decreasing.

That is, according to one embodiment of the present invention, after the core insulating film is formed on the substrate to a predetermined thickness, a stacked structure of at least the first insulating film, the second insulating film, and the first insulating film is formed. And a process of
Forming a plurality of holes through the laminated structure and the core insulating film by dry etching;
Forming a conductive film on the bottom and side walls of the hole;
Forming an opening through the laminated structure and exposing the core insulating film by dry etching;
Removing the core insulating film by wet etching through the opening;
And
The second insulating film has a wet etching rate faster than the first insulating film and slower than the core insulating film in the wet etching, and the second second insulating film is formed by the wet etching. And a support structure for the conductor film made of the first insulating film is formed to provide a method for manufacturing a semiconductor device.

According to another embodiment of the present invention, a transistor formed on a semiconductor substrate;
A semiconductor device having a plurality of memory cells including a capacitor electrically connected to one of the source / drain diffusion layers of the transistor,
The lower electrode of the capacitor is a bottomed cylinder-type electrode, and is held together by a support structure that connects the outer walls of the upper part,
There is provided a semiconductor device, wherein the support structure includes an insulator in which silicon nitride is doped with carbon and includes at least two layers of structures separated in a height direction of the lower electrode.

  In the present invention, the first insulating film formed as the support structure has a structure of two or more stages, and the wet etching rate therebetween is lower than that of the core insulating film and faster than that of the first insulating film formed as the support structure. By interposing the insulating film, a thick support structure composed of the first insulating film and the second insulating film is once formed to reduce the warp of the electrode, and then the second insulating film is formed. By removing the film, it is possible to suppress a decrease in the area of the outer wall of the lower electrode used as a capacitor.

8A and 8B are a process cross-sectional view (a) and a plan view (b) illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. 2A and 2B are a process cross-sectional view (a) and a plan cross-sectional view (b) illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. 8A and 8B are a process cross-sectional view (a) and a plan view (b) illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. 8A and 8B are a process cross-sectional view (a) and a plan view (b) illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. 8A and 8B are a process cross-sectional view (a) and a plan view (b) illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. 8A and 8B are a process cross-sectional view (a) and a plan view (b) illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. 8A and 8B are a process cross-sectional view (a) and a plan view (b) illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. It is a graph which shows the relationship between the doping amount (trimethylsilane flow rate) of a carbon-doped silicon nitride film and the etching rate (wet and dry). Process sectional drawing explaining the manufacturing method of the semiconductor device which becomes another example of embodiment of this invention is shown. Process sectional drawing explaining the manufacturing method of the semiconductor device which becomes another example of embodiment of this invention is shown.

  Hereinafter, exemplary embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the exemplary embodiments.

Embodiment 1
With reference to FIGS. 1-8, the manufacturing method of the semiconductor device of the example of this embodiment is demonstrated. 1 to 7, (a) is a cross-sectional view taken along line AA ′ of (b), and (b) is a plan view (only FIG. 2 (b) is a cross-sectional view taken along line BB ′ of FIG. 2 (a)). .

  In FIG. 1, a semiconductor element such as a transistor including a gate insulating film 2 and a gate electrode 3 is formed on a semiconductor substrate 1 partitioned by an element isolation region (not shown) according to a conventional method. One of the source / drain 4 of the transistor is connected to the capacitor contact pad 10 via the substrate contact plug 6 and the capacitor contact plug 9, and the other is connected to the bit line 7 via the substrate contact plug 6. Reference numerals 5 and 8 denote interlayer insulating films.

A first silicon nitride film as a stopper film 11 is deposited on the capacitor contact pad 10 as a stopper film 11 with a thickness of 50 nm, a silicon oxide film as a core insulating film 12 is formed with a thickness of 1000 nm, and a first nitride film is formed as a first insulating film 13 thereon. The silicon film 13a is 50 nm, the second insulating film 14 is the second silicon nitride film 14a 80 nm, the third insulating film 15 is the silicon oxide film 20 nm, and the second insulating film 14 is the second silicon nitride film 14b. The first silicon nitride film 13b is formed to a thickness of 50 nm as the first insulating film 13, and the silicon oxide film is further formed as the fourth insulating film 16 to a thickness of 100 nm. A storage node hole pattern (not shown) having a hole diameter of 40 nm is formed by lithography, and the storage node hole 17 is opened using this as a mask. Here, the first silicon nitride film (11, 13a, 13b) and the second silicon nitride film (14a, 14b) are formed of silane (SiH ₄ ), ammonia (NH ₃ ), and trimethylsilane ((CH ₃ ) _3. A silicon nitride film having a different wet etching rate for hydrofluoric acid (HF) is formed by adjusting the flow rate ratio of trimethylsilane as shown in FIG. Can be formed. In addition, the dry etching rate of these silicon nitride films hardly changes regardless of the flow rate ratio of trimethylsilane. In FIG. 1, the first silicon nitride film is a film having a slow wet etching rate, and the second silicon nitride film is a film having a fast wet etching rate. The wet etching rate of the first silicon nitride film is preferably 3/4 or less, more preferably 1/2 or less, and most preferably 1/5 or less of the wet etching rate of the second silicon nitride film. Note that the second silicon nitride film has a sufficiently slow wet etching rate with respect to the silicon oxide film, and, as will be described later, in the wet etching process, the second silicon nitride film is also in a stage where the silicon oxide film is completely removed. A part of the silicon nitride film remains. Here, the first silicon nitride film is formed as an insulating film (silicon carbonitride film) obtained by carbon doping silicon nitride, and the second silicon nitride film has a smaller amount of carbon doping than the first silicon nitride film. It is formed as a silicon nitride film (silicon carbonitride film) or a carbon non-doped silicon nitride film. The first silicon nitride film and the second silicon nitride film are not limited to the plasma CVD method using the source gas, and the amount of carbon introduced is adjusted using a source having a silicon source, a carbon source, and a nitrogen source. It can also be formed by other CVD methods or ALD methods. The amount of carbon introduced can be adjusted by adjusting the flow rate as described above and using carbon sources having different carbon contents. Note that the carbon source may also serve as a silicon source or a nitrogen source. For example, the trimethylsilane serves as both a carbon source and a silicon source, and if an organic amine is used, it can serve as a carbon source and a nitrogen source.

  The thinner the insulating film as the support structure, the smaller the area of the outer wall surface of the lower electrode used as a capacitor can be suppressed. However, the thinner the insulating film, the easier it is for cracks to occur during wet etching. Although not particularly limited, the thickness of the first insulating film at the time of film formation is preferably 70 nm or less, and more preferably 60 nm or less. Moreover, it is preferable that it is 30 nm or more, and it is more preferable that it is 40 nm or more. Further, it is preferable that a film thickness of 20 nm or more remains after wet etching.

  Next, as shown in FIG. 2, a conductor film (titanium nitride film) 18 to be a capacitor lower electrode is formed to a thickness of about 10 nm using a CVD method.

  Next, as shown in FIG. 3, a 20 nm thick silicon oxide film is formed as the protective film 19, and an antireflection film and a photoresist 20 are applied thereon by a spin coating method. A slit pattern 20A having an opening width of 40 nm is formed in the photoresist by lithography. In this example, the silicon oxide film as the protective film 19 is formed up to the bottom of the lower electrode (titanium nitride film 18). You may make it close only. A plurality of slit patterns 20A are formed as rectangles extending in the Y direction (first direction), which is the direction in which the boundary between the memory cell region and the peripheral circuit region extends. One slit pattern 20A is formed by arranging a plurality of lower electrodes on two long sides constituting the slit pattern 20A so that a part of the lower electrode that is circular in plan view overlaps. FIG. 3B shows an example in which the center of the long axis of the two slit patterns 20A is formed on a straight line in the X direction (second direction) perpendicular to the Y direction. However, the present invention is not limited to this, and it may be formed in a zigzag shape with the center of the long axis shifted in the X direction. The length of the long side of each slit pattern 20A may be different. Further, the plurality of slit patterns 20A may be rectangular extending in the X direction. Furthermore, the plurality of slit patterns 20A may be rectangles extending in the third direction inclined in the Y direction and the X direction.

  Next, as shown in FIG. 4, by using a dry etching method, the protective film 19 and the conductor film 18 are etched using the photoresist as a mask to form an opening 19A. Further, as shown in FIG. 5, with the conductor film 18 as a mask, a silicon oxide film (16, 15), a first silicon nitride film (13b, 13a), a second silicon nitride film (14b, 14a) are sequentially etched to expose the underlying core insulating film 12. Thereby, in order from the top, the silicon oxide film 16 (fourth insulating film), the first silicon nitride film 13b (first insulating film), the second silicon nitride film 14b (second insulating film), the oxidation A slit pattern 20A penetrating through the silicon film 15 (third insulating film), the second silicon nitride film 14a (second insulating film), and the first silicon nitride film 13a (first insulating film) is formed. .

  Next, the core insulating film 12 is removed by a wet etching method using hydrofluoric acid (HF). At this time, the silicon oxide films (16, 15, 12) are first etched, then the second silicon nitride films (14a, 14b) are etched, and the first silicon nitride is formed on the upper and intermediate portions of the capacitor lower electrode. A support structure consisting of the membranes (13a, 13b) can be left. In addition, since the first silicon nitride film formed as the stopper film 11 remains, it is possible to prevent the etching solution from penetrating into the lower interlayer insulating film. Further, since the silicon oxide film 15 is sandwiched between the second silicon nitride films (14a, 14b), the second silicon nitride film (14a, 14b) is also etched from the surface from which the silicon oxide film 15 has been removed. As a result, the second silicon nitride films (14a, 14b) can be efficiently removed. FIG. 6 shows a state in the middle of etching removal of the second silicon nitride films (14a, 14b).

  Thereafter, as shown in FIG. 7, the capacitor film 21 and the upper electrode 22 are formed by using the CVD method, and the plate electrode 23 is further formed by a metal film such as tungsten by the CVD method. Note that the upper electrode 22 does not need to be a single layer film, and it is preferable to bury polysilicon on the titanium nitride film to reduce the level difference. Thereafter, the memory cell region is completed by forming an interlayer insulating film covering the plate electrode 23, an upper layer wiring connected to the plate electrode, and the like. In addition, a semiconductor device is completed by forming peripheral circuit region wirings and the like around the memory cell region.

  As described above, according to the present invention, when the silicon oxide film is removed, the thick silicon nitride film remains, and the film thickness is decreased step by step. The phenomenon of depending on the support structure can be prevented. In addition, a support structure can be formed at two locations, the upper portion and the middle portion of the lower electrode, using the relatively thin first silicon nitride film (13a, 13b), thereby reducing the area of the outer wall of the lower electrode used as a capacitor. Can be suppressed.

Embodiment 2
In the first embodiment, the first insulating film (first silicon nitride film) as the support structure has two places, the upper part and the middle part, but is not limited to this, and there are three or more places, that is, Three or more first insulating films may be formed. However, since the area of the outer wall of the lower electrode is reduced when the number of support portions is increased, it is necessary to make the first insulating film left as a support structure thinner.

  9 and 10 are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to this embodiment. 9 shows a state in which the storage node hole 17 is formed as in FIG. 1, and FIG. 10 shows a state after wet etching. In these drawings, the structure under the stopper film 11 is omitted.

  As shown in FIG. 9, in this embodiment, on the core insulating film 12, first, the second silicon nitride film 14a is 50 nm, the first silicon nitride film 13a is 30 nm, and the second silicon nitride film 14b is 50 nm. The silicon oxide film 15a is 20 nm, the second silicon nitride film 14c is 50 nm, the first silicon nitride film 13b is 30 nm, the second silicon nitride film 14d is 50 nm, the silicon oxide film 15b is 20 nm, and the second silicon nitride. A film 14e is formed with a thickness of 50 nm, a first silicon nitride film 13c is formed with a thickness of 30 nm, a second silicon nitride film 14f is formed with a thickness of 50 nm, and a silicon oxide film is further formed thereon as a fourth insulating film 16 with a thickness of 100 nm.

  Thereafter, as in the first embodiment, the conductor film 18 to be the lower electrode is formed, and as shown in FIG. 10, the silicon oxide film removal and the second nitride film are removed, thereby removing the lower electrode in the height direction. It is possible to form a structure that supports at three locations.

  Thus, by forming the second insulating film on both the upper and lower surfaces of the first insulating film, the first insulating film is mainly exposed to the etching from the side surface during the wet etching, and can be used for the upper and lower surface etching. Less time to be exposed. As a result, even if the thickness of the first insulating film is reduced, the amount of decrease in the thickness is reduced, and a necessary thickness as a support structure can be secured even after wet etching. As described above, by supporting the structure at three locations, it is possible to prevent the deflection of the electrodes more effectively and to suppress a decrease in the area of the outer wall of the lower electrode even if the number of support locations is increased.

  The configuration in which the second insulating film is formed on both the upper and lower surfaces of the first insulating film can also be applied to a structure that supports two places as in the first embodiment.

  In the above example, the third insulating film (silicon oxide film) 15 is interposed between the second insulating film (second silicon nitride film) 14. When a sufficient etching rate ratio is obtained with the second insulating film 14, the single-layer second insulating film 14 may be used without the third insulating film 15 interposed therebetween. From the viewpoint of shortening the etching time of the second insulating film and reducing the etching amount of the first insulating film, the third insulating film 15 having a higher etching rate than the second insulating film is provided between the second insulating films. It is preferable to interpose and separate into two layers.

  The stopper film 11 is formed of the first silicon nitride film. The stopper film 11 is formed so that the etching solution can be prevented from penetrating into the lower layer while the second silicon nitride film is etched away. However, in order to function as a bottom holding member that supports the capacitor lower electrode at the bottom, it is equivalent to or lower than the first silicon nitride film. It preferably has an etching rate.

  Further, the upper fourth insulating film 16 may be omitted. In addition, the opening is formed by dry etching the first insulating film 13 and the second insulating film 14 using the conductor film 18 on the fourth insulating film 16 as a mask. After the conductor film 18 on 16 is removed in advance by etching back, the opening may be formed by dry etching the first insulating film 13 and the second insulating film 14 using a photomask. When the conductor film 18 is etched back in advance and separated into individual capacitor lower electrodes, the protective film 19 is formed in order to prevent the conductor film 18 on the inner wall and the bottom of the storage node hole 17 from being exposed to etching. In addition to the silicon oxide film, an organic coating film (resist or the like) may be used.

  As a transistor constituting a memory cell of a semiconductor device, a planar type transistor is exemplified. However, the present invention is not limited to this, and it is advantageous for miniaturization to use a transistor having a recessed gate structure, a buried gate structure, or a vertical transistor. . Further, the capacitor contact pad is not essential, and a structure in which the capacitor contact plug and the lower electrode are connected may be employed.

  The support structure according to the present invention can also be applied to the lower electrode of the compensation capacitor formed in the same shape as the capacitor lower electrode of the memory cell.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Gate insulating film 3 Gate electrode 4 Source / drain 5 Interlayer insulating film 6 Substrate contact plug 7 Bit line 8 Interlayer insulating film 9 Capacitance contact plug 10 Capacitance contact pad 11 Stopper film (first silicon nitride film)
12 Core insulation film (silicon oxide film)
13 First insulating film (first silicon nitride film)
14 Second insulating film (second silicon nitride film)
15 Third insulating film (silicon oxide film)
16 Fourth insulating film (silicon oxide film)
17 Storage node hole 18 Conductor film (titanium nitride film)
19 Protective film (silicon oxide film)
20 Photoresist 21 Capacitance film 22 Upper electrode 23 Plate electrode

Claims (17)

Forming a laminated structure of at least a first insulating film, a second insulating film, and a first insulating film after forming a core insulating film on the substrate to a predetermined thickness;
Forming a plurality of holes through the laminated structure and the core insulating film by dry etching;
Forming a conductive film on the bottom and side walls of the hole;
Forming an opening through the laminated structure and exposing the core insulating film by dry etching;
Removing the core insulating film by wet etching through the opening;
And
The second insulating film has a wet etching rate faster than the first insulating film and slower than the core insulating film in the wet etching, and the second insulating film is also removed by the wet etching. And forming a support structure for the conductor film made of the first insulating film.   2. The semiconductor device manufacture according to claim 1, wherein the second insulating film is separated into two layers with a third insulating film having a wet etching rate faster than that of the second insulating film interposed therebetween. Method.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film is formed in contact with both upper and lower surfaces of the first insulating film.   4. The semiconductor device manufacturing according to claim 1, wherein the core insulating film and the third insulating film include silicon oxide, and the first insulating film and the second insulating film include silicon nitride. 5. Method.   The method of manufacturing a semiconductor device according to claim 4, wherein the wet etching is performed using hydrofluoric acid, and the wet etching rate of the first insulating film is 3/4 or less of the wet etching rate of the second insulating film. .   The first insulating film is formed as a silicon carbonitride film in which silicon nitride is carbon-doped, and the second insulating film is a silicon carbonitride film having a carbon doping amount less than that of the first insulating film or a carbon non-doped film. The method for manufacturing a semiconductor device according to claim 4, wherein the method is formed as a silicon nitride film.   The method of manufacturing a semiconductor device according to claim 6, wherein the first and second insulating films are formed by using a raw material including a silicon source, a carbon source, and a nitrogen source and adjusting a carbon introduction amount.   8. The first and second insulating films are formed by adjusting the flow rate of trimethylsilane by plasma CVD using silane as the silicon source, trimethylsilane as the carbon source, and ammonia as the nitrogen source. The manufacturing method of the semiconductor device of description.   The method of manufacturing a semiconductor device according to claim 8, wherein dry etching rates of the first insulating film and the second insulating film are substantially equal.   10. The method of manufacturing a semiconductor device according to claim 1, wherein the substrate has a stopper film having a slower wet etching rate than the second insulating film on a surface in contact with the core insulating film.   The substrate includes a transistor formed on a semiconductor substrate, an interlayer insulating film covering the transistor, and a contact plug that penetrates the insulating film and is connected to one of the source and drain diffusion layers of the transistor. The method of manufacturing a semiconductor device according to claim 10, wherein the hole is formed in a portion where electrical connection with the contact plug is possible, and the conductor film is formed so as to be electrically connected to the contact plug. .   The conductor film is a lower electrode of a capacitor, and has a step of forming a capacitor film on the inner wall and outer wall of the exposed lower electrode after the wet etching, and a step of forming an upper electrode on the capacitor insulating film. A method for manufacturing a semiconductor device according to claim 11.   The method further includes forming a fourth insulating film having a wet etching rate faster than the second insulating film on the stacked structure, and the hole portion extends from the fourth insulating film to the core insulation under the stacked structure. After the conductor film is formed also on the fourth insulating film, a protective film is formed in the hole portion by closing at least the upper end of the hole portion, and the conductive film is formed on the fourth insulating film. The method of manufacturing a semiconductor device according to claim 1, wherein after the pattern is transferred to the conductor film, the stacked structure is dry-etched using the conductor film as a mask.   The method of manufacturing a semiconductor device according to claim 1, wherein the opening is formed by exposing a part of the outer wall of the conductor film on the side wall of the hole. A transistor formed on a semiconductor substrate;
A semiconductor device having a plurality of memory cells including a capacitor electrically connected to one of the source / drain diffusion layers of the transistor,
The lower electrode of the capacitor is a bottomed cylinder-type electrode, and is held together by a support structure that connects the outer walls of the upper part,
The said support structure is a semiconductor device provided with the structure of the at least 2 layer isolate | separated in the height direction of the said lower electrode containing the insulator which doped the carbon to silicon nitride.   The semiconductor device according to claim 15, further comprising a bottom holding member including an insulator in which carbon is doped in silicon nitride around the bottom of the lower electrode of the capacitor.   The semiconductor device according to claim 16, wherein the insulator constituting the support structure and the insulator constituting the bottom holding member are the same type of insulator.

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