JP2013175585A - Stacked semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a stacked semiconductor device that has improved reliability and electrical connectivity by improving the filling property of an underfill resin into spaces of a chip stack while suppressing the creeping-up of the underfill resin.SOLUTION: A stacked semiconductor device 1 includes a chip stack 7 disposed above a wiring substrate 2. A plurality of semiconductor chips 6 are electrically connected to one another via through electrodes 10 and bump electrodes 11. A semiconductor chip 6D located at the top of the chip stack 7 is disposed so as to be displaced with respect to a semiconductor chip 6C directly thereunder. Spaces among the plurality of semiconductor chips 6 are collectively filled with an underfill resin 12.

Description

  Embodiments described herein relate generally to a stacked semiconductor device.

  In order to realize miniaturization and high functionality of a semiconductor device, a semiconductor device having a SiP (System in Package) structure in which a plurality of semiconductor chips are stacked and sealed in one package has been put into practical use. A semiconductor device having a SiP structure is required to transmit and receive electrical signals between semiconductor chips at high speed. For this reason, through electrodes and bump electrodes provided in the semiconductor chips have been used for electrical connection between the stacked semiconductor chips. Such a semiconductor device is manufactured, for example, by stacking a plurality of semiconductor chips on a wiring board and electrically connecting the plurality of semiconductor chips with bump electrodes. Underfill resin is filled in the gaps between the plurality of semiconductor chips.

  In filling underfill resin in the gap between the chip stacks in which a plurality of semiconductor chips are stacked, there is concern that the fillability of the underfill resin may decrease as the number of stacked semiconductor chips increases. In particular, unfilling of the underfill resin tends to occur on the upper layer side of the chip stack. Also, in order to suppress unfilling of the underfill resin, if the resin supply amount is increased, the underfill resin may crawl on the uppermost semiconductor chip, and the electrical connection between the semiconductor chip and the wiring board may be impaired. There is. For this reason, it is required to improve the reliability of the chip laminate by suppressing the creep of the underfill resin and enhancing the filling property of the underfill resin into the gaps of the chip laminate. .

JP 2006-301863 A JP 2007-207805 A JP 2010-056139 A

  The problem to be solved by the present invention is to improve reliability and electrical connectivity by increasing the filling property of the underfill resin into the gaps of the chip stack while suppressing the creeping of the underfill resin. Another object of the present invention is to provide a stacked semiconductor device.

  The stacked semiconductor device according to the embodiment includes a first semiconductor chip having a first electrode, a second electrode, and a through electrode electrically connected thereto, and the through electrode is connected to the first electrode and the first electrode. A second semiconductor chip stacked on the first semiconductor chip while being electrically connected via one bump electrode; a third electrode; and a through electrode electrically connected thereto, A third semiconductor chip stacked on the second semiconductor chip while electrically connecting the through electrode via the second electrode and the second bump electrode; and the first semiconductor chip and the second semiconductor A chip stack including a gap between the chips and an underfill resin filled in a gap between the second semiconductor chip and the third semiconductor chip is provided. The first, second, and third semiconductor chips have the same outer shape, and the third semiconductor chip is arranged with the outer shape shifted from the second semiconductor chip.

It is sectional drawing which shows the laminated semiconductor device by embodiment. FIG. 2 is an enlarged cross-sectional view showing an example of a connection structure between semiconductor chips in the stacked semiconductor device shown in FIG. 1. FIG. 5 is an enlarged cross-sectional view illustrating another example of a connection structure between semiconductor chips in the stacked semiconductor device illustrated in FIG. 1. FIG. 10 is a cross-sectional view showing a first modification of the stacked semiconductor device shown in FIG. 1. FIG. 10 is a cross-sectional view showing a second modification of the stacked semiconductor device shown in FIG. 1. FIG. 10 is a cross-sectional view showing a third modification of the stacked semiconductor device shown in FIG. 1. It is sectional drawing which shows the manufacturing method of the laminated semiconductor device by 1st Embodiment. It is sectional drawing which shows the manufacturing method of the laminated semiconductor device by 2nd Embodiment.

  Hereinafter, the stacked semiconductor device of the embodiment will be described with reference to the drawings. FIG. 1 is a cross-sectional view illustrating a configuration of a stacked semiconductor device according to an embodiment. 2 and 3 are enlarged cross-sectional views showing an example of a connection structure between semiconductor chips by through electrodes and bump electrodes of the stacked semiconductor device shown in FIG.

  A stacked semiconductor device 1 shown in FIG. 1 includes a wiring substrate 2 as an interposer substrate. The wiring substrate 2 is provided with a wiring network (not shown) on the surface or inside of an insulating resin substrate, for example, specifically, an insulating resin such as glass-epoxy resin or BT resin (bismaleimide / triazine resin). A printed wiring board (multi-layer printed circuit board or the like) using is used. The wiring board 2 has a first surface 2a that serves as a surface for forming external terminals, and a second surface 2b that serves as a surface for forming internal terminals and a mounting surface for chip stacks.

  External terminals 3 are formed on the first surface 2 a of the wiring board 2. When the stacked semiconductor device 1 is used as a BGA package, the external terminal 3 is constituted by a protruding terminal made of a solder ball, solder plating or the like. When the stacked semiconductor device 1 is used as an LGA package, a metal land made of Au plating or the like is provided as the external terminal 3. Internal terminals 4 are provided on the second surface 2 b of the wiring board 2. The internal terminal 4 functions as a connection portion when connected to the chip stack, and is electrically connected to the external terminal 3 via the wiring network of the wiring substrate 2. Furthermore, a chip mounting area 5 is provided on the second surface 2 b of the wiring board 2.

  On the chip mounting area 5 on the second surface 2b of the wiring board 2, a chip stack 7 having a plurality of semiconductor chips 6 (6A to 6D) is disposed. The chip stacked body 7 is configured by sequentially stacking a plurality of semiconductor chips 6B to 6D on a semiconductor chip 6A located at the lowest level. The plurality of semiconductor chips 6A to 6D have the same outer shape. A specific example of the semiconductor chip 6 is a memory chip such as a NAND flash memory, but is not limited thereto. In FIG. 1, the chip stack 7 is configured by four semiconductor chips 6 </ b> A to 6 </ b> D, but the number of stacked semiconductor chips 6 is not limited to this. The chip stacked body 7 may be any structure in which three or more semiconductor chips 6 are stacked, and the specific number of stacked semiconductor chips 6 is appropriately set according to the use and performance of the stacked semiconductor device 1. It is.

  The chip laminated body 7 is formed by bonding the lower surface (non-circuit surface) of the semiconductor chip 6A located at the lowermost stage to the second surface 2b (chip mounting region 5) of the wiring substrate 2 with an adhesive layer 8. 2 is mounted on the second surface 2b. The semiconductor chip 6A located at the lowest stage of the chip stack 7 is only bonded to the second surface 2b of the wiring board 2 with an adhesive layer 8 made of an insulating resin or the like. 2 is not directly electrically connected to the wiring (internal terminal 4 or the like) provided on the second surface 2b. A thermosetting resin, a photosensitive resin, or the like is used for the adhesive layer 8 that bonds the lowermost semiconductor chip 6A and the wiring substrate 2 together.

  Electrodes 9 are respectively provided on the upper surfaces (circuit surfaces) of the semiconductor chips 6A to 6D constituting the chip stack 7. The electrodes 9 of the semiconductor chips 6A to 6D include through electrodes (Through Silicon Via (TSV)) 10 provided inside the semiconductor chips 6B to 6D from the second stage to the uppermost stage, and these through electrodes, respectively. Electrical connection is made in order via bump electrodes 11 connecting the 10. The lowermost semiconductor chip 6A is only bonded to the second surface 2b of the wiring board 2 with the adhesive layer 8, and is electrically connected only to the second-stage semiconductor chip 6B. . For this reason, the through electrode in the semiconductor chip 6A is not necessarily required.

  Underfill resin 12 is filled in the gaps between the semiconductor chips 6 connected via the bump electrodes 11 described above, that is, the gaps between adjacent semiconductor chips 6. The underfill resin 12 is supplied to the side surface of the chip stack 7 and is filled in the gaps between the semiconductor chips 6 using a capillary phenomenon or the like. As the underfill resin 12, for example, a thermosetting resin is used. The underfill resin 12 is collectively filled in the gaps between the plurality of semiconductor chips 6 and then subjected to a heat curing process (curing process) or the like to become a cured product.

  Incidentally, the outer shapes of the semiconductor chips 6A to 6D constituting the chip stacked body 7 are the same rectangular shape as described above. When a plurality of semiconductor chips 6A to 6D having the same outer shape, specifically, three or more semiconductor chips 6A to 6D are stacked while being electrically connected by the through electrode 10 and the bump electrode 11, a stacked type is used. In order to reduce the size of the semiconductor device (semiconductor package), it is conceivable that all semiconductor chips 6A to 6D are stacked with the same outer shape. The semiconductor chip 6 has a thickness of, for example, about 70 μm or less. As the number of stacked semiconductor chips 6 increases, the filling property of the underfill resin 12 with respect to the gap between the semiconductor chip 6D located at the uppermost stage and the semiconductor chip 6C located immediately below the semiconductor chip 6D tends to be lowered.

  That is, when the outer shapes of the plurality of semiconductor chips 6A to 6D are aligned and stacked, the unfilled defect of the underfill resin 12 is likely to occur in the gap between the semiconductor chip 6C and the semiconductor chip 6D. On the other hand, when the supply amount of the underfill resin 12 is increased in order to suppress the occurrence of unfilled defects of the underfill resin 12, the underfill resin 12 creeps on the upper surface (circuit surface) of the uppermost semiconductor chip 6D. Is likely to occur. On the upper surface of the uppermost semiconductor chip 6D, a rewiring layer, a connection portion with a metal wire, and the like are formed as described later. For this reason, if the underfill resin 12 crawls up to the upper surface of the uppermost semiconductor chip 6D, the chip stack 7 and the wiring board 2 may not be electrically connected with a metal wire or the like.

  In contrast, in the stacked semiconductor device 1 according to the embodiment, the uppermost semiconductor chip 6D is arranged with its outer shape shifted from the semiconductor chip 6C immediately below in a direction parallel to the chip surface. . As described above, unfilled defects of the underfill resin 12 are likely to occur in the gap between the uppermost semiconductor chip 6D and the semiconductor chip 6C immediately below the uppermost semiconductor chip 6D, so that only the uppermost semiconductor chip 6D is replaced with the other semiconductor chips 6A to 6C. It is arranged with respect to. The other semiconductor chips 6A to 6C except the uppermost semiconductor chip 6D are stacked with the same outer shape so as not to impair the miniaturization of the stacked semiconductor device (semiconductor package) 1.

  Since the uppermost semiconductor chip 6D is arranged by being shifted by a distance L with respect to the semiconductor chip 6C immediately below, the upper surface of the semiconductor chip 6C is exposed by the distance L. The underfill resin (liquid resin) 12 is supplied by, for example, a dispenser with the exposed portion of the semiconductor chip 6C as a target. The supplied underfill resin 12 flows from the exposed portion of the semiconductor chip 6C into the gap between the uppermost semiconductor chip 6D and the semiconductor chip 6C immediately below the lower semiconductor chip 6A. The liquid flows into the gaps between the semiconductor chips 6A to 6C while being transmitted through the side surfaces of -6C. By using the exposed portion of the semiconductor chip 6C, it is possible to sufficiently supply the underfill resin 12 to the gap between the uppermost semiconductor chip 6D and the semiconductor chip 6C immediately below it.

  In this way, by arranging the uppermost semiconductor chip 6 in a shifted manner, it is possible to suppress the occurrence of unfilled defects in the underfill resin 12 in the gap between the uppermost semiconductor chip 6D and the semiconductor chip 6C immediately below the uppermost semiconductor chip 6D. it can. Furthermore, since the exposed portion of the semiconductor chip 6C functions as a receiving portion for the underfill resin 12, it is possible to suppress the underfill resin 12 from creeping up to the upper surface of the uppermost semiconductor chip 6D. That is, an electrical connection failure between the chip stack 7 and the wiring board 2 due to the underfill resin 12 creeping up on the upper surface of the uppermost semiconductor chip 6D while suppressing the occurrence of unfilling failure of the underfill resin 12. Can be suppressed. Therefore, it is possible to provide the stacked semiconductor device 1 with improved reliability and electrical connectivity.

  The shift amount (L) of the uppermost semiconductor chip 6D with respect to the semiconductor chip 6C is preferably in the range of 0.1 to 1 mm. If the shift amount (L) is less than 0.1 mm, the function of the underfill resin 12 as a receiving portion is insufficient, and the creep of the underfill resin 12 may not be suppressed. On the other hand, even if the amount of shift (L) of the semiconductor chip 6D is set to exceed 1 mm, not only the effect cannot be increased, but also the stacked semiconductor device (semiconductor package) 1 is increased in size accordingly. End up. The shift amount (L) of the uppermost semiconductor chip 6D is more preferably in the range of 0.3 to 0.5 mm. Note that the amount of deviation due to dicing accuracy, bump electrode formation accuracy, and the like when stacking a plurality of semiconductor chips 6 is about 20 to 30 μm, and does not exceed 50 μm (0.05 mm) at the maximum.

  FIG. 1 shows a state in which the uppermost semiconductor chip 6D is shifted in one direction (a direction parallel to one outer side of the semiconductor chip 6C). The uppermost semiconductor chip 6D may be shifted in two directions (directions parallel to the two outer sides of the semiconductor chip 6C). In some cases, the uppermost semiconductor chip 6D may be shifted in a direction not parallel to the outer side of the semiconductor chip 6C. However, the uppermost semiconductor chip 6D is shifted in parallel in one direction in order to effectively suppress unfilling and scooping up of the underfill resin 12 while reducing the size of the stacked semiconductor device (semiconductor package) 1. It is preferable.

  As described above, when the uppermost semiconductor chip 6D is shifted from the semiconductor chip 6C immediately below the uppermost semiconductor chip 6D, the penetrating electrode 10 provided on the uppermost semiconductor chip 6D and the semiconductor chip 6C immediately below the through electrode 10 are provided. The position of the through electrode 10 is shifted in accordance with the shift amount (L) of the semiconductor chip 6D. Therefore, it is necessary to rearrange the bump electrodes 11 that connect the through electrodes 10. A connection structure between the semiconductor chips 6 in the case where the uppermost semiconductor chip 6D is arranged in a shifted manner will be described with reference to FIGS.

  The lowermost semiconductor chip 6A to the third semiconductor chip 6C are sequentially connected through the through electrode 10 and the bump electrode 11. That is, the electrode 9A of the lowermost semiconductor chip 6A is electrically connected to the through electrode 10A provided in the second-stage semiconductor chip 6B via the first bump electrode 11A. Specifically, a lower bump 13 electrically connected to the electrode 9A is formed on the circuit surface (upper surface) of the lowermost semiconductor chip 6A. An upper bump 14 electrically connected to the through electrode 10A is formed on the non-circuit surface (lower surface) of the second-stage semiconductor chip 6B. The second-stage semiconductor chip 6B is stacked on the lowermost-stage semiconductor chip 6A while the upper bump 14 is connected to the lower bump 13.

  The lowermost semiconductor chip 6A and the second semiconductor chip 6B are electrically and mechanically connected via a connection body (first bump electrode 11A) of the lower bump 13 and the upper bump 14. . The same applies to the third-stage semiconductor chip 6C. That is, the lower bump 13 electrically connected to the electrode 9B is formed on the circuit surface (upper surface) of the second-stage semiconductor chip 6B. An upper bump 14 electrically connected to the through electrode 10B is formed on the non-circuit surface (lower surface) of the third-stage semiconductor chip 6C. The second-stage semiconductor chip 6B and the third-stage semiconductor chip 6C are electrically and mechanically connected via a connection body (second bump electrode 11B) of the lower bump 13 and the upper bump 14. Yes. When five or more semiconductor chips 6 are stacked, the connection is basically the same except for the uppermost semiconductor chip 6.

  As for the uppermost semiconductor chip 6D, the position of the through electrode 10C is shifted from the position of the through electrode 10B of the third stage semiconductor chip 6C as described above. Therefore, as shown in FIG. 2, a rewiring layer 15 electrically connected to the electrode 9C is provided in advance on the circuit surface (upper surface) of the third-stage semiconductor chip 6C. 3 bump electrodes 11C are rearranged. That is, a rewiring layer 15 having one end electrically connected to the electrode 9C is provided on the circuit surface (upper surface) of the third-stage semiconductor chip 6C. Lower bumps 13 are formed at the ends. On the non-circuit surface (lower surface) of the uppermost semiconductor chip 6D, an upper bump 14 electrically connected to the through electrode 10C is formed.

  The uppermost semiconductor chip 6D is stacked on the third-stage semiconductor chip 6C while the upper bump 14 is connected to the lower bump 13. The electrode 9C of the third-stage semiconductor chip 6C and the electrode 9D of the uppermost-stage semiconductor chip 6D are the connection body (third bump electrode 11C) of the rewiring layer 15, the lower bump 13, and the upper bump 14 and the through electrode. It is electrically connected via 10C. The lower bumps 13 provided on the third-stage semiconductor chip 6C are rearranged by the rewiring layer 15 so as to be aligned with the upper bumps 14 provided on the uppermost semiconductor chip 6D. Therefore, it is possible to electrically connect the third-stage semiconductor chip 6C and the uppermost-stage semiconductor chip 6D with the third bump electrode 11C.

  FIG. 2 shows a connection structure in which the rewiring layer 15 is provided on the circuit surface (upper surface) of the third-stage semiconductor chip 6C. As shown in FIG. 3, the rewiring layer 15 may be provided on the non-circuit surface (lower surface) of the uppermost semiconductor chip 6D. On the non-circuit surface of the uppermost semiconductor chip 6D shown in FIG. 3, a rewiring layer 15 having one end portion electrically connected to the through electrode 10C is provided. The upper bump 14 provided on the non-circuit surface of the uppermost semiconductor chip 6D is re-reduced by the rewiring layer 15 so as to be aligned with the lower bump 13 provided on the electrode 9C of the third-stage semiconductor chip 6C. Has been placed. Therefore, it is possible to electrically connect the third-stage semiconductor chip 6C and the uppermost-stage semiconductor chip 6D with the third bump electrode 11C.

  In this way, for the electrical connection between the third-stage semiconductor chip 6C and the uppermost semiconductor chip 6D, the redistribution layer 15 provided on the upper surface of the third-stage semiconductor chip 6C or the uppermost semiconductor chip 6C. Any of the rewiring layers 15 provided on the lower surface of 6D may be used. The rewiring layer 15 is formed in advance by, for example, a wafer process. Examples of the material for forming the rewiring layer 15 include Cu, Cu alloy, Al, and Al alloy. As will be described later, the same applies when a rewiring layer is formed on the surface of the uppermost semiconductor chip 6D, and the rewiring layer is often formed of Cu, Cu alloy, Al, Al alloy, or the like. In such a case, the outermost surface layer may be formed of Au, an Au alloy, or the like in consideration of connectivity.

  As described above, when the bumps 13 and 14 are formed on both the adjacent semiconductor chips 6, a combination of solder / solder, Au / solder, solder / Au, Au / Au, or the like can be applied. As the solder constituting the bumps 13 and 14, Pb-free solder made of Sn alloy such as Sn—Cu alloy, Sn—Ag alloy, Sn—Ag—Cu alloy is often used. Further, the metal constituting the bumps 13 and 14 may be Cu, Ni, Sn, Pd, Ag or the like instead of Au. These metals are not limited to a single layer film, and may be a laminated film of a plurality of metals. Examples of the shape of the bumps 13 and 14 include a projection shape such as a hemispherical shape and a columnar shape, but a flat shape such as a pad can also be applied. Examples of the combination of the bumps 13 and 14 include a combination of protrusion-shaped bodies, a combination of a protrusion-shaped body and a flat-shaped body, and the like. The bump electrodes 11 have a diameter of about 5 to 50 μm, for example, and are formed at a pitch of about 10 to 100 μm.

  In the stacked semiconductor device 1 shown in FIG. 1, the first-stage semiconductor chip 6A to the third-stage semiconductor chip C are stacked with the same outer shape, and only the uppermost semiconductor chip 6D is stacked on the other semiconductor chips 6A-6C. It is arranged to be offset. In order to achieve both the miniaturization of the stacked semiconductor device 1 and the improvement of the filling property of the underfill resin 12, it is preferable to apply the stacked structure shown in FIG. However, the semiconductor chip 6 whose position is shifted is not limited to the uppermost semiconductor chip 6D. When the number of stacked semiconductor chips 6 further increases, the position of the semiconductor chip 6 in the middle may be shifted in addition to the uppermost semiconductor chip 6.

  A stacked semiconductor device 1 shown in FIG. 4 includes a chip stacked body 7 in which eight semiconductor chips 6A to 6H are stacked. When the chip stack 7 having a large number of stacked semiconductor chips 6 is applied, the position of the semiconductor chip 6 in the middle (the fourth-stage semiconductor chip 6D in FIG. 4) is shifted in addition to the uppermost semiconductor chip 6H. May be. By shifting the position of the semiconductor chip 6D to expose a part of the upper surface of the semiconductor chip 6C, the exposed portion of the semiconductor chip 6C functions as a receiving portion for the underfill resin 12, and therefore the underfill resin 12 faces downward. It begins to flow gradually. Therefore, it becomes possible to improve the filling property of the underfill resin 12 into the gaps between the semiconductor chips 6E to 6G located above the semiconductor chip 6D.

  As for the gap between the uppermost semiconductor chip 6H and the semiconductor chip 6G immediately below the uppermost semiconductor chip 6H, the underfill resin 12 is improved by shifting the uppermost semiconductor chip 6H, as in the stacked semiconductor device 1 shown in FIG. Can be filled. In the stacked semiconductor device 1 shown in FIG. 4, the first-stage semiconductor chip 6A to the third-stage semiconductor chip 6C are stacked with the same outer shape, and the fourth-stage semiconductor chip 6D is the third-stage semiconductor chip. The outer shape is shifted from the chip 6C. Further, the fifth-stage semiconductor chip 6E to the seventh-stage semiconductor chip 6G are laminated with the same shape as the fourth-stage semiconductor chip 6D, and the uppermost semiconductor chip 6H is the seventh-stage semiconductor chip. The outer shape is shifted with respect to 6G.

  In FIG. 4, the position of the fourth-stage semiconductor chip 6 </ b> D is shifted, but the semiconductor chip 6 whose position is shifted can be appropriately set according to the number of stacked chips, the fluidity of the underfill resin 12, and the like. For example, in addition to the uppermost semiconductor chip 6H, the positions of two or more semiconductor chips 6 in the middle may be shifted. Shifting the position of the uppermost semiconductor chip 6H is indispensable for preventing the underfill resin 12 from creeping up, but the positions of the other semiconductor chips 6 can be shifted appropriately. However, if the number of the semiconductor chips 6 to be shifted is increased too much, the stacked semiconductor device 1 becomes larger, and therefore the position of the semiconductor chip 6 may be shifted in consideration of the final size of the stacked semiconductor device 1. preferable.

  When a memory chip is used as the semiconductor chip 6, the chip stack 7 (in FIG. 1) is placed on the semiconductor chip 6 (the semiconductor chip 6 </ b> D in FIG. 1 and the semiconductor chip 6 </ b> H in FIG. 4) positioned at the top of the chip stack 7. A semiconductor chip 16 that performs data communication between the semiconductor chips 6A to 6D (semiconductor chips 6A to 6H in FIG. 4) and an external device, for example, a controller chip, an interface chip, a mixed chip of a controller circuit and an interface circuit, and the like are mounted. The An underfill resin 17 is filled between the semiconductor chip 16 and the chip stack 7. The semiconductor chip 16 such as a controller chip that performs data communication with an external device may be installed outside.

  The semiconductor chip 16 has an internal connection electrode 18 that is electrically connected to the chip stack 7 and performs data communication with the plurality of semiconductor chips 6. The internal connection electrode 18 of the semiconductor chip 16 is electrically connected to the electrode 9 of the uppermost semiconductor chip 6 via the bump electrode 19. The semiconductor chip 16 is flip-chip connected (FC connection) to the semiconductor chip 6 located at the uppermost stage. Further, the semiconductor chip 16 has an external connection electrode 20 that performs data communication with an external device via the wiring board 2.

  In order to electrically connect the external connection electrode 20 of the semiconductor chip 16 and the internal terminal 4 of the wiring substrate 2, a rewiring layer 21 is formed on the upper surface of the uppermost semiconductor chip 6. One end of the rewiring layer 21 is electrically connected to the external connection electrode 20 of the semiconductor chip 16 via the bump electrode 19. The other end of the rewiring layer 21 and the internal terminal 4 of the wiring board 2 are electrically connected via a bonding wire (a metal wire such as an Au wire) 22. That is, the external connection electrode 20 of the semiconductor chip 16 is electrically connected to the internal terminal 4 of the wiring board 2 via the bump electrode 19, the rewiring layer 21 and the bonding wire 22.

  On the second surface 2b of the wiring board 2, a sealing resin layer 23 made of an insulating resin such as an epoxy resin is molded, for example, so as to seal the chip stack 7 and the semiconductor chip 16 together with the bonding wires 22 and the like. Has been. In this way, the stacked semiconductor device (semiconductor package) 1 of the embodiment is configured. When a memory chip such as a NAND flash memory is used as the semiconductor chip 6, a high-capacity semiconductor memory device can be provided according to the number of stacked memory chips (6). In the case where the semiconductor chip 16 for data communication is not mounted, a rewiring layer 21 whose one end is electrically connected to the electrode 9 is formed on the upper surface of the uppermost semiconductor chip 6, and the rewiring layer is formed. What is necessary is just to electrically connect between the other end part of 21 and the internal terminal 4 of the wiring board 2 with the bonding wire 22.

  The chip stacked body 7 may be formed by sequentially stacking a plurality of semiconductor chips 6 on the wiring substrate 2, or may be disposed on the wiring substrate 2 after the plurality of semiconductor chips 6 are stacked in advance. A chip stacked body 7 formed by previously stacking a plurality of semiconductor chips 6 can be used in addition to the stacked semiconductor device 1 having the structure shown in FIGS. For example, the present invention can be applied to various device structures such as the chip stack 7 being FC-connected to the wiring board 2 and the data communication semiconductor chip 16 being FC-connected to the wiring board 2. Even in such a case, the filling property of the underfill resin 12 can be improved by shifting the semiconductor chip 6 positioned at the uppermost stage when the chip stacked body 7 is manufactured.

  FIG. 5 shows a stacked semiconductor device 31 in which the chip stack 7 is inverted and arranged on the wiring board 2 and the chip stack 7 is FC-connected to the wiring board 2. Similar to the stacked semiconductor device 1 shown in FIG. 1, the stacked semiconductor device 31 includes a chip stacked body 7 having semiconductor chips 6 </ b> A to 6 </ b> D and a semiconductor chip 16 FC-connected to the chip stacked body 7. Yes. The chip stack 7 is inverted with respect to the stacking order at the time of filling the underfill resin 12 so that the semiconductor chip 6D positioned at the uppermost stage is positioned on the wiring board 2 side when the underfill resin 12 is filled. Is arranged on the wiring board 2. Accordingly, the semiconductor chip 16 mounted on the chip stack 7 is also located on the side close to the wiring board 2.

  The external connection electrode 20 of the semiconductor chip 16 is electrically connected to one end of the rewiring layer 21 provided on the upper surface of the uppermost semiconductor chip 6D via the bump electrode 19. The other end of the rewiring layer 21 is electrically connected to the internal terminal 4 of the wiring board 2 via the bump electrode 32. An underfill resin 33 is filled between the chip stack 7 on which the semiconductor chip 16 is mounted and the wiring board 2. When the semiconductor chip 16 is not mounted on the chip stack 7, the electrode 9 </ b> D of the uppermost semiconductor chip 6 </ b> D or the rewiring layer 21 connected to the electrode 9 </ b> D and the internal terminal 4 of the wiring board 2 are connected to the bump electrode 32. It is electrically connected via.

  When the semiconductor chip 16 is mounted on the chip stack 7, as shown in FIG. 6, the electrode 18 of the semiconductor chip 16 and the internal terminal 4 of the wiring board 2 are electrically and mechanically connected via the bump electrode 32. You may connect. When the connection structure with the wiring board 2 shown in FIG. 6 is applied, the semiconductor chip 16 has a through electrode 34 as in the semiconductor chips 6B to 6D. The electrode 18 of the semiconductor chip 16 is electrically connected to the electrode 9D of the semiconductor chip 6D located at the uppermost stage via the through electrode 34 and the bump electrode 19.

  The stacked semiconductor device 1 described above is manufactured, for example, as follows. A manufacturing process of the stacked semiconductor device 1 according to the first embodiment will be described with reference to FIG. First, as shown in FIG. 7A, a first-stage semiconductor chip 6A having a lower bump 13 and a second-stage semiconductor chip 6B having an upper bump 14 are prepared. The semiconductor chip 6B is arranged on the semiconductor chip 6A placed on the stage 31. Next, by applying pressure while applying heat, ultrasonic waves, or the like, the lower bump 13 and the upper bump 14 are connected to form the bump electrode 11, and the second-stage semiconductor chip 6B is formed on the first-stage semiconductor chip 6A. Are laminated. Similarly, the third-stage semiconductor chip 6C is stacked on the second-stage semiconductor chip 6B.

  In this case, it is preferable to use the stage 31 made of a ceramic such as aluminum nitride or silicon carbide, which has been surface-treated with a fluorine resin or the like having a low adhesive strength to the underfill resin. This is also effective for the stage 31. Further, instead of the stage 31, a resin film such as a polyimide resin film having an adhesive layer or a metal frame may be used. When using a resin film or a metal frame, after the lamination of the semiconductor chips 6A to 6D and the filling of the underfill resin 12 is finished, the resin film or the metal frame is cut, and the resin film or the metal frame corresponding to the shape of the laminated body is cut. It is good also as the chip laminated body 7 which has.

  Next, as shown in FIG. 7B, a fourth-stage semiconductor chip 6D is stacked on the third-stage semiconductor chip 6C. A rewiring layer 15 is formed on the upper surface of the third-stage semiconductor chip 6 </ b> C, and a lower bump 13 is formed on the rewiring layer 15. Upper bumps 14 are formed on the lower surface of the fourth-stage semiconductor chip 6D. While aligning the lower bump 13 of the third-stage semiconductor chip 6C and the upper bump 14 of the fourth-stage semiconductor chip 6D, the fourth-stage semiconductor chip 6D is shifted and arranged. Next, by applying pressure while applying heat, ultrasonic waves, or the like, the lower bump 13 and the upper bump 14 are connected to form the bump electrode 11, and the fourth-stage semiconductor chip is formed on the third-stage semiconductor chip 6C. Laminate 6D. As shown in FIG. 3, the rewiring layer 15 may be formed on the lower surface of the fourth-stage semiconductor chip 6D.

  In this manner, chip stacking in which only the fourth-stage semiconductor chip 6D positioned at the uppermost stage is stacked with the outer shape being shifted while stacking with the same outer shape from the first-stage semiconductor chip 6A to the third-stage semiconductor chip 6C. A body 7 is produced. Although the case where the four semiconductor chips 6A to 6D are stacked has been described here, the number of stacked semiconductor chips 6 is not particularly limited as long as it is three or more. When stacking five or more semiconductor chips 6 to produce the chip stack 7, the stacking process shown in FIG. 7A may be repeated according to the number of stacked semiconductor chips 6. As shown in FIG. 4, when the position of the semiconductor chip 6 in the middle is shifted in addition to the semiconductor chip 6 located at the uppermost stage, the stacking process shown in FIG. 7A and the process shown in FIG. What is necessary is just to implement a lamination process repeatedly.

  Next, as shown in FIG. 7C, the underfill resin 12 is filled in a gap (a gap between adjacent semiconductor chips 6) between the chip stacks 7. As described above, the uppermost semiconductor chip 6D is arranged so as to be shifted from the semiconductor chip 6C, so that the upper surface of the semiconductor chip 6C is exposed according to the shift amount. The underfill resin (liquid resin) 12 is supplied by, for example, a dispenser with the exposed portion of the semiconductor chip 6C as a target. The underfill resin 12 flows from the exposed portion of the semiconductor chip 6C into the gap between the uppermost semiconductor chip 6D and the semiconductor chip 6C immediately below it, and the lower-stage semiconductor chips 6A to 6C are stacked with the same outer shape. It flows into each gap between the semiconductor chips 6A to 6C while traveling along the side surface.

  In addition, by disposing the uppermost semiconductor chip 6D with respect to the semiconductor chip 6C, a part of the semiconductor chip 6D protrudes from the semiconductor chip 6C in an eave shape. The underfill resin (liquid resin) 12 may be supplied by a dispenser, for example, targeting the lower part of the eaves portion of the semiconductor chip 6D. In this case, the underfill resin 12 flows into the gaps between the semiconductor chips 6A to 6D from the liquid reservoir below the eaves portion of the semiconductor chip 6D.

  After the underfill resin 12 is cured, the chip stack 7 is removed from the stage 31. The chip stack 7 removed from the stage 31, that is, the chip stack 7 in which the semiconductor chips 6A to 6D are fixed with the underfill resin 12 is formed on the second surface 2b of the wiring board 2 as shown in FIG. Is mounted via an adhesive layer 8. Thereafter, by performing a wire bonding step, a mounting step of the semiconductor chip 16, a sealing step of the underfill resin between the semiconductor chip 16 and the chip laminated body 7, a sealing step with the mold resin 23, etc., as shown in FIG. The stacked semiconductor device 1 shown is obtained.

  The mounting process of the semiconductor chip 16 may be performed simultaneously with the stacking process of the semiconductor chips 6A to 6D. The underfill resin sealing step between the semiconductor chip 16 and the chip stack 7 may be performed simultaneously with the underfill resin sealing step between the semiconductor chips 6A to 6D. Note that the chip stack 7 removed from the stage 31 can also be applied to a stacked semiconductor device having a structure different from that in FIG. 1, and in this case as well, based on the effect of improving the filling property of the underfill resin 12. Reliability and the like can be improved.

  Next, the manufacturing process of the stacked semiconductor device 1 according to the second embodiment will be described with reference to FIG. First, as shown in FIG. 8A, the first-stage semiconductor chip 6A is disposed on the second surface 2b of the wiring board 2 with the adhesive layer 8 interposed therebetween. Next, as shown in FIG. 8B, the step of stacking and connecting the second-stage semiconductor chip 6B on the first-stage semiconductor chip 6A, and the third-stage semiconductor chip on the second-stage semiconductor chip 6B. A step of stacking and connecting 6C is performed. The specific connection process is the same as the connection process according to the first embodiment.

  Next, as shown in FIG. 8C, the fourth-stage semiconductor chip 6D is stacked on the third-stage semiconductor chip 6C while shifting the position. The specific lamination and connection process is the same as the lamination and connection process according to the first embodiment. On the second surface 2 b of the wiring board 2, only the fourth-stage semiconductor chip 6 </ b> D positioned at the uppermost stage is externally shaped while the outer shapes are laminated from the first-stage semiconductor chip 6 </ b> A to the third-stage semiconductor chip 6 </ b> C. The chip laminated body 7 laminated by shifting is manufactured. Thereafter, as shown in FIG. 8 (d), the underfill resin 12 is filled in a gap between the chip stacks 7 (a gap between adjacent semiconductor chips 6). The filling process of the underfill resin 12 is the same as that in the first embodiment.

  As in the first embodiment, the underfill resin (liquid resin) 12 is supplied to the exposed portion of the semiconductor chip 6C, thereby suppressing the occurrence of unfilled defects in the underfill resin 12 and the uppermost semiconductor chip. It is possible to suppress the occurrence of poor electrical connection due to the underfill resin 12 creeping up on the upper surface of 6D. After the underfill resin 12 is cured, a wire bonding process, a semiconductor chip 16 mounting process, an underfill resin sealing process between the semiconductor chip 16 and the chip stack 7, a molding resin 23 sealing process, and the like are performed. By doing so, the stacked semiconductor device 1 shown in FIG. 1 is obtained. Also in this manufacturing example, the mounting process of the semiconductor chip 16 is a stacking process of the semiconductor chips 6A to 6D, and the underfill resin sealing process between the semiconductor chip 16 and the chip stack 7 is between the semiconductor chips 6A to 6D. The underfill resin sealing step may be performed at the same time.

  In addition, although several embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and at the same time included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Stacked-type semiconductor device, 2 ... Wiring board, 2a ... 1st surface, 2b ... 2nd surface, 3 ... External terminal, 4 ... Internal terminal, 5 ... Chip mounting area, 6, 6A-6H ... Semiconductor chip , 7 ... chip laminated body, 8 ... adhesive layer, 9 ... electrode, 10 ... penetrating electrode, 11 ... bump electrode, 12 ... underfill resin, 15 ... rewiring layer, 23 ... sealing resin layer.

Claims (5)

A wiring board having a first surface including external terminals and a second surface including internal terminals and a chip mounting region;
A first semiconductor chip having a first electrode; a second electrode; and a through electrode electrically connected to the second electrode. The through electrode is connected to the first electrode and the first electrode. The second semiconductor chip stacked on the first semiconductor chip, the third electrode, and the through-hole electrically connected to the third electrode while being electrically connected via the bump electrode A third semiconductor chip stacked on the second semiconductor chip while electrically connecting the through electrode via the second electrode and the second bump electrode; An underfill resin filled in a gap between the first semiconductor chip and the second semiconductor chip, and a gap between the second semiconductor chip and the third semiconductor chip; and the first, second and second 3 of the wiring board so as to seal the semiconductor chip 3 And a sealing resin layer provided above, includes a chip stack disposed on the chip mounting region of the wiring board,
The first, second and third semiconductor chips have the same outer shape, the first and second semiconductor chips are arranged with the same outer shape, and the third semiconductor chip is the first semiconductor chip. The outer shape is shifted with respect to the semiconductor chip of 2,
The second electrode is a redistribution layer provided on the second electrode forming surface of the second semiconductor chip, or the opposite side of the third electrode forming surface of the third semiconductor chip. Electrically connected to the through electrode provided in the third semiconductor chip via the rewiring layer provided on the surface and the second bump electrode,
The stacked semiconductor device, wherein the third semiconductor chip is electrically connected to the internal terminal of the wiring board via a metal wire or a bump electrode. A first semiconductor chip having a first electrode;
Having a second electrode and a through electrode electrically connected to the second electrode, and electrically connecting the through electrode via the first electrode and the first bump electrode, A second semiconductor chip stacked on the first semiconductor chip;
Having a third electrode and a through electrode electrically connected to the third electrode, and electrically connecting the through electrode via the second electrode and the second bump electrode, A third semiconductor chip stacked on the second semiconductor chip;
A chip stack including an underfill resin filled in a gap between the first semiconductor chip and the second semiconductor chip and a gap between the second semiconductor chip and the third semiconductor chip; ,
The first, second, and third semiconductor chips have the same outer shape, and the third semiconductor chip is arranged with the outer shape shifted from the second semiconductor chip. A stacked semiconductor device. The stacked semiconductor device according to claim 2,
The second electrode is a redistribution layer provided on the second electrode formation surface of the second semiconductor chip, or the opposite side of the third electrode formation surface of the third semiconductor chip. And a through-electrode provided in the third semiconductor chip via a rewiring layer provided on the surface and the second bump electrode. Type semiconductor device. The stacked semiconductor device according to claim 2 or 3,
And a wiring board having a first surface including external terminals and a second surface including internal terminals and a chip mounting region.
The chip stack is disposed on the chip mounting region of the wiring board such that the first semiconductor chip is located on the wiring board side,
The stacked semiconductor device, wherein the third semiconductor chip is electrically connected to the internal terminal of the wiring board via a metal wire. The stacked semiconductor device according to claim 2 or 3,
And a wiring board having a first surface including external terminals and a second surface including internal terminals and a chip mounting region.
The chip stack is disposed on the chip mounting region of the wiring board such that the third semiconductor chip is positioned on the wiring board side;
The stacked semiconductor device, wherein the third semiconductor chip is electrically connected to the internal terminal of the wiring board via a bump electrode.

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