JP2013168786A - Time-lag digital converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To acquire a digital value with high conversion accuracy without performing calibration or the like on the digital value.SOLUTION: A time-lag digital converter comprises an FET switch 8 which is turned on during a period in which a conversion starting signal is inputted, a constant current source 9 which generates a constant current I/Nand extracts electric charges charging a capacitor 6 when the FET switch 8 is turned on, a comparator 10 which outputs a conversion ending signal when a ramp voltage Vof the capacitor 6 becomes equal to a ground potential, and a counter 12 which counts clock of a term Tduring a period from input of the conversion starting signal to the output of the conversion ending signal from the comparator 10.

Description

  The present invention relates to a time difference digital conversion device for converting a time difference between two input signals or a pulse width of a pulse signal into a digital value.

In the time difference digital conversion device disclosed in the following Non-Patent Document 1, an analog / digital converter (ADC) converts a time difference, which is an output voltage of a time to amplitude converter (TAC), into an analog / digital converter (ADC). The time difference is read and converted to a digital value.
Normally, an ADC is configured on a semiconductor substrate and generates a ramp voltage by a current source and a capacitor. Generally, however, the absolute value of an element configured on the semiconductor substrate has a variation temperature characteristic. It is assumed that it varies depending on the sample.
Therefore, in order for the ADC to digitally convert the output voltage of the TAC to obtain an accurate digital value, it is necessary to acquire calibration data and calibrate the digital value using a lookup table or the like.

In the time difference digital conversion device disclosed in Non-Patent Document 2 below, the time difference is digitized using a delay time of a buffer or the like without converting the time difference signal into an analog voltage value.
However, since the minimum value of the time difference to be measured is determined by the delay time of a buffer or the like, it is necessary to use a fine semiconductor process with a high operating speed in order to increase the measurement resolution.
Further, in order to remove the influence of variations in semiconductor elements, complicated calibration means are required.

Tanaka, M., “Development of monolithic time-to-amplitude converter for high precision TOF measurement”, Nuclear Science, IEEE Transactions on Nuclear Science, IEEE Transactions on Volume: 38, Issue: 2, Part: 1-2 1991, Page (s): 301-305 Staszewski, R.B., “TDC-based frequency synthesizer for wireless applications” Radio Frequency Integrated Circuits (RFIC) Symposium, 2004. Digest of Papers 2004, Page (s): 215-218

Since the conventional time difference digital conversion device is configured as described above, when the ADC uses a method of converting the time difference into a digital value (Non-patent Document 1), calibration data is acquired to obtain an accurate digital value. There has been a problem that digital values need to be calibrated using a lookup table or the like.
In addition, when using a method of digitizing the time difference using a delay time of a buffer or the like (Non-patent Document 2), it is necessary to use a fine semiconductor process with a high operating speed in order to increase the measurement resolution. There was a problem. Moreover, in order to remove the influence of the dispersion | variation in a fine semiconductor element, the subject which requires a complicated calibration means occurred.

  The present invention has been made to solve the above-described problems, and an object thereof is to obtain a time difference digital conversion device capable of acquiring a digital value with high conversion accuracy without performing digital value calibration or the like. To do.

  The time difference digital conversion device according to the present invention includes a constant current source that generates a constant current, a switch that is turned on during a period in which a pulse signal is input, and a switch that is turned on when the switch is turned on. A lamp voltage generation circuit composed of a capacitor that charges electric charge by the generated constant current, a switch that is turned on during the period when the conversion start signal is input, and a lamp that is turned on when the switch is turned on. A constant current source that generates a constant current that is a predetermined ratio times the constant current generated from the constant current source of the voltage generation circuit and draws out the charge charged in the capacitor; and the voltage value of the capacitor is the ground potential When the potential is the same, a comparator that outputs a conversion end signal and a clock with a known period during the period from when the conversion start signal is input until the conversion end signal is output from the comparator. Tsu is obtained so as to include a voltage-to-digital converter is composed of a counter for counting the click.

  According to the present invention, a constant current source that generates a constant current, a switch that is turned on during a period in which a pulse signal is input, and a constant current generated from the constant current source when the switch is turned on. A ramp voltage generating circuit configured to charge a charge by current, a switch that is turned on during the period when the conversion start signal is input, and when the switch is turned on, the lamp voltage generating circuit A constant current source that generates a constant current that is a predetermined ratio times the constant current generated from the constant current source and pulls out the charge charged in the capacitor, and the voltage value of the capacitor is equal to the ground potential A comparator that outputs a conversion end signal and a counter that counts a clock with a known period during the period from when the conversion start signal is input until the conversion end signal is output from the comparator. Since it is configured to include a voltage-to-digital converter is composed of a printer, without performing such calibration of the digital value, conversion precision is effective that it is possible to acquire high digital value.

It is a block diagram which shows the time difference digital conversion apparatus by Embodiment 1 of this invention. It is a timing chart which shows operation | movement of the time difference digital converter by Embodiment 1 of this invention. It is a block diagram which shows the time difference digital conversion apparatus by Embodiment 2 of this invention. It is a timing chart which shows operation | movement of the time difference digital conversion apparatus by Embodiment 2 of this invention.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a time difference digital conversion apparatus according to Embodiment 1 of the present invention.
In FIG. 1, when a signal A (first signal) and a signal B (second signal) are input, the XOR circuit 1 has a pulse signal having a pulse width corresponding to the difference in input time between the signal A and the signal B. Is a pulse signal generation circuit for generating
The D flip-flop circuit 2 is an order information output circuit that outputs a sign bit indicating a signal input first among the signals A and B.

The ramp voltage generating circuit 3 is a circuit composed of a constant current source 4, an FET switch 5 and a capacitor 6.
The constant current source 4 is a current source that generates a constant current I _c .
The FET switch 5 is turned on while receiving the pulse signal from the XOR circuit 1, the constant current I _c generated from the constant current source 4 flows between the drain and the source, and the pulse signal is sent from the XOR circuit 1. if not received, the constant current I _c, which is generated from the constant current source 4 turned off state drain - not flow between the source.
The capacitor 6 is a charging circuit having a capacitance value of C _{1. When} the FET switch 5 is turned on, the capacitor 6 is charged with a constant current I _c generated from the constant current source 4.

The voltage digital conversion circuit 7 is a circuit including an FET switch 8, a constant current source 9, a comparator 10, an XOR circuit 11 and a counter 12.
The FET switch 8 is a switching element that is turned on during the period when the conversion start signal is input.
When the FET switch 8 is turned on, the constant current source 9 generates a constant current I _c / N ₁ (a constant current that is 1 / N ₁ times the constant current I _c generated from the constant current source 6) and has a capacitance. 6 is a current source that pulls out the electric charge charged to 6.

Comparator 10 when the lamp voltage V _P which is generated in the capacitor 6 becomes the ground potential and the same potential is a device that outputs an end of conversion signal.
The XOR circuit 11 is a circuit that outputs a counter enable signal to the counter 12 when a conversion start signal is input, and stops outputting the counter enable signal to the counter 12 when a conversion end signal is received from the comparator 10.
The counter 12 is a circuit that counts a clock having a known cycle during a period when the counter enable signal is received from the XOR circuit 11.
The setting circuit 13 is a circuit for setting the constant current source 9 to N ₁ which is a current ratio between the constant current source 4 and the constant current source 9.

Next, the operation will be described.
FIG. 2 is a timing chart showing the operation of the time difference digital conversion apparatus according to Embodiment 1 of the present invention.
When the signals A and B are input, the XOR circuit 1 generates a pulse signal having a pulse width corresponding to the time difference T from the rising edge of the signal A to the rising edge of the signal B, and the pulse signal is generated as a ramp voltage generation circuit. 3 is output to the gate of the FET switch 5.

In addition, when the signal A and the signal B are input, the D flip-flop circuit 2 outputs a sign bit indicating the previously input signal of the signals A and B.
That is, the D flip-flop circuit 2 holds the state of the signal A at the rising edge of the signal B. Therefore, when the signal A is already input, the D flip-flop circuit 2 outputs an H level sign bit and the signal A is not input yet. If not, L level code bits are output.
In the example of FIG. 2, since the signal A is input before the signal B, the H-level code bit is output.

The constant current source 4 of the lamp voltage generation circuit 3 generates a constant current I _c .
When the FET switch 5 receives a pulse signal from the XOR circuit 1 (when the output signal of the XOR circuit 1 becomes H level), the FET switch 5 is turned on, and the constant current I _c generated from the constant current source 4 is between the drain and the source. Flowing.
As a result, the constant current I _c generated from the constant current source 4 flows into the capacitor 6, and the capacitor 6 is charged with the constant current I _c .
Thereafter, when the output signal of the XOR circuit 1 becomes L level, the FET switch 5 is turned off, and the constant current I _c generated from the constant current source 4 does not flow between the drain and the source.
As a result, the constant current I _c generated from the constant current source 4 does not flow into the capacitor 6, and the ramp voltage V _P generated in the capacitor 6 is maintained. This lamp voltage V _P is expressed by the following equation (1).

The FET switch 8 of the voltage digital conversion circuit 7 is turned on during the period when the conversion start signal is input.
That is, the FET switch 8 is turned on when an H level signal is input to the base.
When the FET switch 8 is turned on, the constant current source 9 generates a constant current I _c / N ₁ (a constant current that is 1 / N ₁ times the constant current I _c generated from the constant current source 6).
Thereby, extraction of the electric charge charged in the capacitor 6 is started.

The XOR circuit 11 outputs a counter enable signal (H level signal) to the counter 12 when a conversion start signal (H level signal) is input.
When the counter 12 receives a counter enable signal (H level signal) from the XOR circuit 11, the counter 12 starts an operation of counting a clock having a known cycle.
Note that the start timing of the count operation by the counter 12 and the start timing of extracting charges in the capacitor 6 are the same.

Here, the ramp voltage V _P generated in the capacitor 6 decreases linearly with a slope of I _c / N ₁ C ₁ with respect to time due to the extraction of charges.
The comparator 10 outputs a conversion end signal (H level signal) to the XOR circuit 11 when the ramp voltage V _P generated in the capacitor 6 decreases and the ramp voltage V _P becomes the same potential as the ground potential. .

When receiving the conversion end signal (H level signal) from the comparator 10, the XOR circuit 11 stops outputting the counter enable signal to the counter 12.
That is, the XOR circuit 11 outputs an L level signal to the counter 12 when receiving a conversion end signal (H level signal) from the comparator 10.
When the counter 12 receives the L level signal from the XOR circuit 11, the counter 12 stops the clock counting operation.

カウンタ１２がカウントするクロックの周期がＴ_clkであるとすると、カウンタ１２のカウント値Ｍは、下記の式（３）で表される。

Here, the pulse width T _E of the counter enable signal output from the XOR circuit 11 is expressed by the following equation (2).

Assuming that the clock cycle counted by the counter 12 is T _clk , the count value M of the counter 12 is expressed by the following equation (3).

式（４）において、クロックの周期Ｔ_clkは既知であるため、定電流源４から発生された定電流Ｉ_cと、定電流源９から発生された定電流Ｉ_c／Ｎ₁との電流比Ｎ₁が既知であれば、時間差Ｔの測定値Ｔ^*は、カウンタ１２のカウント値Ｍでデジタル化されていることになる。
なお、電流比Ｎ₁は、設定回路１３により事前に設定される値であるため既知である。 For this reason, the measured value T ^* of the time difference T between the signal A and the signal B is expressed by the following equation (4).

In the equation (4), since the clock cycle T _clk is known, the current ratio between the constant current I _c generated from the constant current source 4 and the constant current I _c / N ₁ generated from the constant current source 9. If N ₁ is known, the measured value T ^* of the time difference T is digitized with the count value M of the counter 12.
The current ratio N ₁ is known because it is a value set in advance by the setting circuit 13.

As is apparent from the above, according to the first embodiment, the constant current source 4 that generates the constant current I _c , the FET switch 5 that is turned on during the input of the pulse signal, and the FET switch When 5 is turned on, the ramp voltage generating circuit 3 composed of the capacitor 6 that charges the electric charge by the constant current I _c generated from the constant current source 4 and the period during which the conversion start signal is input, When the FET switch 8 is turned on, when the FET switch 8 is turned on, a constant current I _c / N ₁ is generated, and the constant current source 9 that draws out the charge charged in the capacitor 6, and the capacitor 6 When the ramp voltage V _P becomes equal to the ground potential, the comparator 10 outputs a conversion end signal, and the period T _clk during the period from when the conversion start signal is input until the conversion end signal is output from the comparator 10. of Since the voltage digital conversion circuit 7 constituted by the counter 12 that counts the lock is provided, it is possible to acquire a digital value with high conversion accuracy without calibrating the digital value. Play.

That is, as apparent from the equation (4), the constant current I _c generated from the constant current source 4 and the constant current source 9 are affected by variations in the elements constituting the time difference digital conversion device. Only the current ratio N ₁ with the generated constant current I _c / N ₁ is obtained. Generally current value on the same semiconductor substrate is not good accuracy of the absolute value, it is possible to easily obtain a high relative precision in the use of such a current mirror circuit, the current ratio N ₁ is a semiconductor substrate In the case of the configuration, it becomes almost non-scattering. For this reason, this time difference digital conversion apparatus does not require complicated calibration means and is not affected by the environment or sample variations.

Further, according to the first embodiment, since the setting circuit 13 for setting the current ratio N ₁ between the constant current source 4 and the constant current source 9 to the constant current source 9 is provided, the current ratio N ₁ can be easily changed. There is an effect that can be done. When the current ratio N ₁ is set to a large value, the discharge lamp time becomes long, so that the measurement time when the same time difference T is measured becomes long, but the resolution of 1 bit is improved.

  In the first embodiment, the description is omitted because it is not directly related to the time measurement operation. However, after the time measurement is completed, the capacitor 6 is charged by a reset switch or the like before starting the next measurement. It is necessary to reset the generated charge.

Embodiment 2. FIG.
FIG. 3 is a block diagram showing a time difference digital conversion apparatus according to Embodiment 2 of the present invention. In the figure, the same reference numerals as those in FIG.
The voltage digital conversion circuit 21 is a circuit including a constant current source 22, an FET switch 23, a capacitor 24, a comparator 25, an XOR circuit 26 and a counter 27.
The constant current source 22 is a current source that generates a constant current I _c / N ₁ (a constant current that is 1 / N ₁ times the constant current I _c generated from the constant current source 6).

The FET switch 23 is a switching element that is turned on during the period when the conversion start signal is input.
The capacitor 24 is a charging circuit having a capacitance value C ₂ that is a predetermined ratio times the capacitance 6. When the FET switch 23 is turned on, the capacitor 24 is charged by the constant current I _c / N ₁ generated from the constant current source 22. To charge.

The comparator 25 is an element that outputs a conversion end signal when the ramp voltage V _r ′ generated in the capacitor 6 becomes the same potential as the ramp voltage V _r generated in the capacitor 6.
The XOR circuit 26 is a circuit that outputs a counter enable signal to the counter 27 when a conversion start signal is input, and stops outputting the counter enable signal to the counter 27 when receiving a conversion end signal from the comparator 25.
The counter 27 is a circuit that counts a clock having a known cycle during a period when the counter enable signal is received from the XOR circuit 26.

Next, the operation will be described.
FIG. 4 is a timing chart showing the operation of the time difference digital conversion apparatus according to Embodiment 2 of the present invention.
When the signals A and B are input, the XOR circuit 1 generates a pulse signal having a pulse width corresponding to the time difference T from the rising edge of the signal A to the rising edge of the signal B, and the pulse signal is generated as a ramp voltage generation circuit. 3 is output to the gate of the FET switch 5.

In addition, when the signal A and the signal B are input, the D flip-flop circuit 2 outputs a sign bit indicating the previously input signal of the signals A and B.
That is, the D flip-flop circuit 2 holds the state of the signal A at the rising edge of the signal B. Therefore, when the signal A is already input, the D flip-flop circuit 2 outputs an H level sign bit and the signal A is not input yet. If not, L level code bits are output.
In the example of FIG. 4, since the signal A is input before the signal B, the H-level code bit is output.

The constant current source 4 of the lamp voltage generation circuit 3 generates a constant current I _c .
When the FET switch 5 receives a pulse signal from the XOR circuit 1 (when the output signal of the XOR circuit 1 becomes H level), the FET switch 5 is turned on, and the constant current I _c generated from the constant current source 4 is between the drain and the source. Flowing.
As a result, the constant current I _c generated from the constant current source 4 flows into the capacitor 6, and the capacitor 6 is charged with the constant current I _c .
Thereafter, when the output signal of the XOR circuit 1 becomes L level, the FET switch 5 is turned off, and the constant current I _c generated from the constant current source 4 does not flow between the drain and the source.
As a result, the constant current I _c generated from the constant current source 4 does not flow into the capacitor 6, and the lamp voltage V _r generated in the capacitor 6 is maintained. This lamp voltage V _r is expressed by the following equation (5).

The constant current source 22 of the voltage digital conversion circuit 21 generates a constant current I _c / N ₁ (a constant current that is 1 / N ₁ times the constant current I _c generated from the constant current source 6).
The FET switch 23 is turned on when a conversion start signal (H level signal) is input, and the constant current I _c / N ₁ generated from the constant current source 22 flows between the drain and the source.
As a result, the constant current I _c / N ₁ generated from the constant current source 22 flows into the capacitor 24, and the capacitor 24 is charged with the constant current I _c / N ₁ .

Further, when the conversion start signal (H level signal) is input, the XOR circuit 26 outputs a counter enable signal (H level signal) to the counter 27.
When the counter 27 receives a counter enable signal (H level signal) from the XOR circuit 26, the counter 27 starts an operation of counting a clock having a known cycle.
Note that the count operation start timing by the counter 27 and the charge charge start timing by the capacitor 24 are the same.

Here, the lamp voltage V _r ′ generated in the capacitor 24 rises linearly with a slope of I _c / N ₁ C ₂ with respect to time due to charge charging.
When the ramp voltage V _r ′ generated in the capacitor 24 rises and the ramp voltage V _r ′ becomes the same potential as the ramp voltage V _r generated in the capacitor 6, the comparator 25 converts the conversion end signal ( H level signal) is output to the XOR circuit 26.

When receiving the conversion end signal (H level signal) from the comparator 25, the XOR circuit 26 stops outputting the counter enable signal to the counter 27.
That is, when receiving the conversion end signal (H level signal) from the comparator 25, the XOR circuit 26 outputs an L level signal to the counter 27.
When the counter 27 receives the L level signal from the XOR circuit 26, the counter 27 stops the clock counting operation.

カウンタ２７がカウントするクロックの周期がＴ_clkであるとすると、カウンタ２７のカウント値Ｍは、下記の式（７）で表される。

Here, the pulse width T _E of the counter enabling signal output from the XOR circuit 26 is expressed by the following equation (6).

Assuming that the clock cycle counted by the counter 27 is T _clk , the count value M of the counter 27 is expressed by the following equation (7).

式（８）において、クロックの周期Ｔ_clk、容量値Ｃ₁，Ｃ₂は既知であるため、定電流源４から発生された定電流Ｉ_cと、定電流源２２から発生された定電流Ｉ_c／Ｎ₁との電流比Ｎ₁が既知であれば、時間差Ｔの測定値Ｔ^*は、カウンタ２７のカウント値Ｍでデジタル化されていることになり、上記実施の形態１と同様の測定結果が得られる。
なお、電流比Ｎ₁は、設定回路１３により事前に設定される値であるため既知である。 For this reason, the measured value T ^* of the time difference T between the signal A and the signal B is expressed by the following equation (8).

In the equation (8), since the clock cycle T _clk and the capacitance values C ₁ and C ₂ are known, the constant current I _c generated from the constant current source 4 and the constant current I generated from the constant current source 22 are known. _If the current ratio N ₁ to _c / N ₁ is known, the measured value T ^* of the time difference T is digitized by the count value M of the counter 27, and the same measurement as in the first embodiment is performed. Results are obtained.
The current ratio N ₁ is known because it is a value set in advance by the setting circuit 13.

In the case of the second embodiment, as compared with the first embodiment, there is a possibility that the influence of the variation is generated by the amount of the capacitance values C ₁ and C ₂ .
However, in the first embodiment, the lamp voltage V _P in the capacitor 6 of the lamp voltage generating circuit 3 is discharged during digital conversion, so that the lamp voltage V _P cannot be reused. Then, since the lamp voltage V _P in the capacitor 6 is held without being discharged even after digital conversion, it can be reused, for example, when digital conversion is performed a plurality of times.

  In the present invention, within the scope of the invention, any combination of the embodiments, or any modification of any component in each embodiment, or omission of any component in each embodiment is possible. .

  1 XOR circuit (pulse signal generation circuit), 2 D flip-flop circuit (order information output circuit), 3 ramp voltage generation circuit, 4 constant current source, 5 FET switch, 6 capacity, 7 voltage digital conversion circuit, 8 FET switch, 9 constant current source, 10 comparator, 11 XOR circuit, 12 counter, 13 setting circuit, 21 voltage digital conversion circuit, 22 constant current source, 23 FET switch, 24 capacitance, 25 comparator, 26 XOR circuit, 27 counter.

Claims (5)

A constant current source that generates a constant current, a switch that is turned on while a pulse signal is input, and a charge that is charged by the constant current generated from the constant current source when the switch is turned on. A ramp voltage generating circuit composed of a capacitor;
A switch that is turned on during the period when the conversion start signal is input, and when the switch is turned on, generates a constant current that is a predetermined ratio times the constant current generated from the constant current source of the lamp voltage generation circuit. Then, a constant current source that pulls out the charge charged in the capacitor, a comparator that outputs a conversion end signal when the voltage value of the capacitor becomes equal to the ground potential, and the conversion start signal are input. And a voltage digital conversion circuit comprising a counter that counts a clock having a known cycle during a period from when the comparator outputs a conversion end signal. A constant current source that generates a constant current, a switch that is turned on while a pulse signal is input, and a charge that is charged by the constant current generated from the constant current source when the switch is turned on. A ramp voltage generating circuit composed of a capacitor;
A constant current source that generates a constant current that is a predetermined ratio times a constant current generated from the constant current source of the lamp voltage generation circuit; a switch that is turned on during a period when a conversion start signal is input; and the lamp The capacitor has a capacitance value that is a predetermined ratio times the capacitance of the voltage generation circuit, and when the switch is turned on, the capacitance that charges the constant current generated from the constant current source and the voltage value of the capacitance are When it becomes the same potential as the voltage value of the capacitor of the ramp voltage generation circuit, the comparator outputs a conversion end signal, and the period during the period from the input of the conversion start signal to the output of the conversion end signal from the comparator A time difference digital conversion apparatus comprising: a voltage digital conversion circuit configured by a counter that counts a known clock.   When the first signal and the second signal are input, a pulse signal generation circuit that generates a pulse signal having a pulse width corresponding to the difference between the input times of the first and second signals is provided. 3. The time difference digital conversion apparatus according to claim 1, wherein the pulse signal generated by the circuit is input to the ramp voltage generation circuit.   4. The time difference digital conversion apparatus according to claim 3, further comprising an order information output circuit for outputting information indicating a signal input first among the first signal and the second signal.   2. A setting circuit for setting a current ratio between a constant current generated from a constant current source of a lamp voltage generation circuit and a constant current generated from a constant current source of a voltage digital conversion circuit is provided. The time difference digital conversion device according to claim 1.

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