JP2013165199A - Charged particle optical system and exposure device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a charged particle optical system and an optical element array structure having a favorable optical characteristic by effectively reducing warpage of a substrate through reduction of a temperature rise of a principal surface of the substrate and a temperature gradient of the substrate.SOLUTION: A charged particle optical system includes a first substrate 1 provided with a counter electrode array including counter electrodes that form an electric field acting on a charged particle beam in a charged particle optical manner. When an optical axis of the charged particle beam is referred to as a normal line, a surface of the first substrate, on which the counter electrodes are formed, is referred to as a first principal surface, a surface on a side opposite to the first principal surface is referred to as a second principal surface, and a dimension in a direction from the first principal surface to the second principal surface is referred to as a thickness, the first surface 1 includes an area 7 that extends from the second principal surface in a thickness direction and is provided with a first filling material whose thermal conductivity is higher than that of the first substrate 1.

Description

The present invention belongs to a technical field such as a charged particle optical system used in an apparatus using a charged particle beam such as an electron beam, and particularly relates to a charged particle optical system used in an exposure apparatus and the like, and an exposure apparatus using the same. .

In the production of semiconductor devices, the electron beam exposure technique is a promising candidate for lithography that enables fine pattern exposure of 0.1 μm or less. In such an exposure apparatus, an electro-optical element for controlling the optical characteristics of the electron beam is used. In the electron beam exposure technique, there has been proposed a multi-beam system that simultaneously draws a pattern with a plurality of electron beams without using a mask. In the multi-beam system, an electro-optical element in which electro-optical elements are arranged in a one-dimensional or two-dimensional array is used. In such an electro-optic element array, a deflection electrode and a multipole lens can be formed by a micro electro mechanical system (MEMS) manufacturing technique, and one element can be miniaturized and arranged at a high density to produce a large-scale array. Furthermore, the control circuit is also integrated on the same substrate as the substrate on which the deflection electrode is formed, so that high speed and large scale array can be realized. (Refer to Patent Document 1 and Non-Patent Document 1) In addition, the astigmatism corrector can be downsized by using the MEMS manufacturing technique and using the facing electrode structure similar to the deflection electrode. (See Non-Patent Document 1)

In such an electro-optical element array, higher precision is required for alignment between the optical element arrays as one element is reduced in size and density, and smaller optical aberrations are required as the drawing pattern becomes finer. Or Therefore, it is important to realize an electro-optic element array with small thermal deformation.

International publication WO20091727658

Microelectronic Engineering 84 (2007) PP1027-1032.

In a device in which the electro-optic element array and the control circuit are integrated on the same substrate, there is a concern that heat generated by the control circuit causes thermal deformation of the electro-optic element array on the substrate. In particular, the control circuit also has an optical interface unit such as a photodiode for inputting a control signal to the device or an electrical interface unit such as a metal bump or a metal pad on the same surface side of the substrate. For this reason, it is difficult to say that it is easy to enlarge the exhaust heat exhaust area on this surface side. Therefore, there is a problem that thermal deformation cannot be sufficiently reduced. On the other hand, it is conceivable to cool from the back surface opposite to this surface. In this case, due to the thermal resistance of the substrate, it may not be possible to exhaust heat sufficiently, or a temperature gradient may occur in the thickness direction of the substrate, causing bending stress. Therefore, also in this case, there is a problem that thermal deformation cannot be sufficiently reduced.

In view of the above problems, the charged particle optical system of the present invention includes a first substrate provided with a counter electrode array including a plurality of counter electrodes that form an electric field that acts on a plurality of charged particle beams in a charged particle optical manner. Having the optical axis of the charged particle beam as a normal line, the surface of the first substrate on which the counter electrode is formed as a first main surface, and a surface opposite to the first main surface. The second main surface, the thickness in the direction from the first main surface to the second main surface as a thickness, the first substrate extends in the thickness direction from the second main surface, Having a region provided with a first filling material having a higher thermal conductivity than the first substrate, and the second main surface acting as a heat exhaust surface for exhausting heat from the counter electrode array to the outside. It is characterized by.

In view of the above problems, the optical element array structure of the present invention has a first substrate such as a silicon substrate having a plurality of openings through which a charged particle beam passes, and the optical axis of the charged particle beam is a normal line. The one surface of the first substrate is the first main surface, the surface opposite to the first main surface is the second main surface, and the direction from the first main surface to the second main surface is The first substrate having a dimension as thickness has a region provided with a first filling material extending in a thickness direction from the second main surface and having higher thermal conductivity than the first substrate, The second main surface functions as a heat exhaust surface that exhausts heat to the outside.

The charged particle optical system and the optical element array structure of the present invention have a region in which a filling material having higher thermal conductivity than a substrate such as a silicon substrate extends from the second main surface to the first main surface. As a result, the thermal resistance of the substrate can be effectively reduced. Therefore, even in a structure in which a control circuit, an interface unit, and the like are formed on the first main surface side, the heat generated from the first main surface side portion is exhausted from the second main surface to It is possible to reduce the temperature rise of the main surface. In addition, the temperature gradient in the thickness direction of the substrate can be reduced. By reducing both the temperature rise of the first main surface and the temperature gradient of the substrate, the warpage of the substrate can be effectively reduced. Therefore, for example, errors in the position / tilt of the counter electrode array and the gap between the electrodes are reduced, so that the counter electrode array having good charged particle optical characteristics can be obtained. Further, since the cooling means can be installed on the second main surface side, for example, the area for forming the interface portion of the control signal and the counter electrode can be made larger than when the cooling means is placed on the first main surface. That is, it is possible to increase the number of arrays such as the counter electrode array with the same device size. Therefore, a device can be manufactured at a lower cost. And in the structure using a silicon substrate, the control circuit using semiconductor devices, such as CMOS, can be integrally formed on a board | substrate with a semiconductor manufacturing technique. Therefore, a control circuit corresponding to a large number of large counter electrode arrays can be realized. In addition, since the counter electrode can also be created using the MEMS manufacturing technology, a fine and highly accurate counter electrode array can be formed on a large scale.

The figure which shows the upper surface and cross section of the counter electrode array of Example 1 of the charged particle optical system of this invention. The conceptual diagram which shows the example of the exposure apparatus using the charged particle optical system of this invention. FIG. 3 is a diagram illustrating a cross-section of the upper surface of the counter electrode formation region and the counter electrode portion of Example 1. The top view in the case of a pair of counter electrodes and two pairs. The figure which shows the upper surface and cross section of the counter electrode array of Example 2 of the charged particle optical system of this invention. The graph explaining the deformation | transformation reduction effect of this invention. The figure which shows the cross section and upper surface of the unit of the counter electrode array of Example 3, and an opening array.

A feature of the present invention is that in a charged particle optical system or an optical element array structure, a filling material having a higher thermal conductivity than a substrate and extending in the thickness direction from the second main surface to the first main surface side is provided. The substrate has the provided region. The optical element array structure that allows a charged particle beam to pass through is a blanker device, a beam forming member, a charged particle optical system that controls the progress of the charged particle beam optically (electrostatic lens, for deflecting the charged particle beam) And the like. For example, a blanker device used in a charged particle beam exposure apparatus generates heat in a non-beam area and generates heat distribution. Further, when the exposure system is miniaturized, a configuration in which a blanker device and an aperture array are combined can be considered. In such a case, a heat dissipation measure (cooling measure) is required. On the other hand, in the case of the combined configuration as described above, it is difficult to secure a heat radiation path in terms of space. In order to solve such a problem, the present invention arranges or fills a heat dissipation path in a substrate with a material having high thermal conductivity. Based on such a concept, the charged particle optical system or optical element array structure of the present invention has the basic configuration as described in the means for solving the above-mentioned problems.

Embodiments of the present invention will be described below.
A charged particle optical system according to an embodiment of the present invention includes a light source that generates a plurality of charged particle beams, and a counter electrode array that acts in a charged particle optical manner corresponding to the plurality of charged particle beams. Yes. The counter electrode array has a plurality of counter electrodes, a control circuit, and an interface unit for supplying a control signal to the control circuit from the outside on a substrate such as a silicon substrate as a first substrate. The plurality of counter electrodes are controlled by the control circuit based on the control signal. The interface unit may be one that electrically exchanges (receives and transmits) control signals (for example, metal bumps) or one that converts light to an electric signal (for example, photodiodes). The counter electrode has, for example, a gap between a pair of two electrodes in order to form an electric field for optically acting on the charged particle beam. As the charged particle beam passes through this gap, the beam is optically affected by the electric field. The optical action can be any of a deflector, a lens, an aberration corrector, or a combination thereof, depending on the number of counter electrodes and the method of applying a potential to one charged particle beam. Since these counter electrodes are controlled by a control circuit on the same substrate, the operation speed can be increased. In addition, if a circuit for serial-parallel conversion of a signal received at the interface unit is included, the number of wires to the counter electrode can be reduced.

The counter electrode array also releases heat to the outside of the device on the surface (second main surface) opposite to the surface (first main surface) on which the counter electrode, control circuit, and interface section are formed. It has a heat exhaust surface. Here, the optical axis of the charged particle beam is the normal line, the surface of the first substrate on which the counter electrode is formed is the first main surface, and the surface opposite to the first main surface is the second main surface. A surface is a thickness, and a dimension in a direction from the first main surface to the second main surface is a thickness. The cooling means can come into thermal contact with the heat removal surface to discharge the heat. As the cooling means, means capable of transporting heat to the outside of the system, for example, a heat sink, a cooling element using a refrigerant, a Peltier element, a heat pipe, or the like is used. Moreover, you may have a heating means in the said heat exhaust surface. This heating means can also be used for temperature stabilization in the initial stage of driving. As the heating means, a general resistance heating element, a ceramic heater, or the like can be used. In this manner, when the cooling means is installed on the second main surface side, the area for forming the interface portion of the control signal and the counter electrode can be increased as compared with the case where the cooling means is provided on the first main surface. That is, the number of counter electrode arrays can be increased with the same device size. Therefore, the device can be manufactured at a lower cost. Further, in the counter electrode array of the present embodiment, a filling material (first filling material) having higher thermal conductivity than the substrate is arranged extending from the second main surface to the first main surface in the thickness direction. Or a filled region. This region reduces the thermal resistance of the substrate and can reduce the thermal deformation of the device even when cooling is performed from the second main surface. For this reason, errors in the position / tilt of the counter electrode array and the gap between the electrodes are reduced, so that the counter electrode array having good charged particle optical characteristics can be obtained. For example, a metal such as copper or tungsten can be used as the material.

By reducing the thermal resistance of the substrate, both the temperature of the first main surface and the temperature distribution in the thickness direction of the silicon substrate can be reduced. The reason why the temperature of the first main surface and the temperature gradient of the substrate are important is as follows. The temperature of the first main surface is related to thermal stress of a material having a linear expansion coefficient different from that of the substrate, such as a wiring layer (including an insulating film), a counter electrode, and an interface portion with respect to the control circuit formed on the substrate. If a large thermal stress is generated only on the first main surface side, the entire substrate is warped in a direction corresponding to the direction of the stress. The temperature gradient of the substrate is a gradient of thermal stress in the thickness direction within the silicon substrate. Since the stress gradient in the thickness direction becomes a bending moment, the substrate is warped. As described above, the substrate on which the counter electrode is formed is warped due to both or any one of the above two factors. Such warpage results in errors in the position / tilt of the counter electrode and the gap between the counter electrodes. In the present invention, by providing a substrate such as a silicon substrate with a material having better thermal conductivity than the substrate, the thermal resistance of the substrate can be reduced, and the above two warping factors can be reduced. Thereby, the structural error of the counter electrode can be reduced.

Further, when the first substrate is a silicon substrate, the following effects are obtained as compared with the case where the entire substrate is made of a material having better thermal conductivity than silicon. First, a control circuit using a semiconductor device such as a CMOS can be integrally formed on a silicon substrate by a semiconductor manufacturing technique. Therefore, a control circuit corresponding to a large number of large counter electrode arrays can be realized. Second, since the counter electrode can be formed using the MEMS manufacturing technology, a fine and highly accurate counter electrode array can be formed on a large scale.

Further, the counter electrode array of the charged particle optical system of the present embodiment can be configured such that the first substrate such as a silicon substrate is thinned only in the thickness of the region where the counter electrode is formed. Thereby, this embodiment can have the following three effects. First, a through hole for passing a charged particle beam can be formed in the substrate with high accuracy. If the through hole is deep (that is, the dimension in the thickness direction of the substrate is large), it becomes difficult to control the diameter of the through hole and the inclination of the center axis of the hole in processing. If such an error occurs, the charged particle beam may be blocked. Further, when the diameter of the through hole becomes large due to an error, the through hole may reach the counter electrode disposed close to the counter electrode, and the counter electrode may be damaged. Therefore, it is necessary to increase the hole diameter for the charged particle beam and increase the gap of the counter electrode with respect to the hole diameter in anticipation of the processing margin. And since the gap of a counter electrode becomes large, the voltage applied to a counter electrode will become high voltage. In the configuration in which only the counter electrode formation area is thin as in this embodiment, the processing depth of the through hole can be reduced and the processing accuracy of the through hole can be improved, so that the voltage applied to the counter electrode can be reduced. it can. If the voltage can be lowered, the heat generation of the circuit and wiring can be further reduced.

Second, it is possible to reduce the diameter and pitch of the through holes. Since the thickness of the region where the through hole is formed is thin, the ratio of the depth to the hole diameter (aspect ratio) can be reduced even if the through hole having a small hole diameter is formed. If the aspect ratio is small, through-hole processing can be performed even if the hole diameter is reduced. In particular, in the case of deep etching of silicon, the aspect ratio is in the range of about 1 to 100. More preferably, it may be about 1 to 5. In addition, since the hole is processed with high accuracy for the first reason, it is processed accurately even in a close layout. For this reason, the pitch can also be reduced. If the hole diameter and pitch can be reduced as described above, a counter electrode array with a higher degree of integration can be formed. Third, since the area where the counter electrode is not formed is kept thick, it can be kept high without reducing the rigidity of the entire device. Therefore, it is possible to prevent the device from being damaged or deformed in the manufacturing / assembling process.

In addition, the counter electrode array of the charged particle optical system according to the present embodiment can be made of a material having a thermal expansion coefficient larger than that of silicon. As a result, it is possible to increase the elongation on the second main surface side, which is the low temperature side, and to reduce the warpage of the entire substrate such as a silicon substrate. Further, even when a multilayer wiring of a semiconductor integrated circuit is used as the wiring connecting the control circuit formed on the substrate and the interface portion, the warpage of the substrate can be effectively reduced.

Further, the counter electrode array of the charged particle optical system according to the present embodiment can be configured such that a filling material is embedded in one or more columnar structures. In order to reduce the thermal resistance of the substrate over a wide area, a plurality of columnar structures are arranged. This makes it possible to reduce deformation even if there is residual stress in the filling material, compared to the case where the entire large area is not divided into columns. In addition, since the formation density of the columnar structure can be adjusted according to the heat generation location, the minimum necessary filling material can be disposed according to the required amount of reduction in thermal resistance. Therefore, even if there is a residual stress in the filling material, a configuration with little deformation can be achieved. In addition, when the filling material is embedded, the embedded through-wiring manufacturing technology used in the semiconductor integrated circuit can be applied, so that the embedded region can be manufactured with a high yield without degrading the operation characteristics of the control circuit integrated on the substrate. Become. In particular, even if the area of the region where it is desired to reduce the thermal resistance is changed by design, it can be dealt with by changing the number and pitch to be formed without changing the dimensions of the columnar structure. Therefore, the thermal resistance can be reduced for various areas by adjusting and applying the conditions of the manufacturing process of the columnar structure. Further, as the filling material, for example, copper, tungsten, or an alloy containing the same can be used.

In addition, the charged particle optical system of the present embodiment can be a unit that combines a counter electrode array and an aperture array having an aperture that restricts a charged particle beam incident on the array. In the aperture array, a through hole for allowing a charged particle beam to pass through is formed in a substrate such as a silicon substrate. Moreover, you may give a film with good electrical conductivity to the outermost surface. Specifically, platinum, molybdenum, or the like can be used. The aperture array has a third main surface that is a surface in thermal contact with the second main surface of the counter electrode array. And it has the 4th main surface on the opposite side of the 3rd main surface. The fourth main surface is a heat exhaust surface for releasing the heat of the counter electrode array and the aperture array to the outside. And the opening array of this embodiment has the area | region filled with the filling material whose heat conductivity is higher than silicon etc. As shown in FIG. This filled area reduces the thermal resistance of the substrate of the aperture array. In this way, even if heat is exhausted from the fourth main surface of the aperture array, the thermal resistance of the counter electrode array and the aperture array is reduced, so that thermal deformation of the entire unit can be reduced. . In particular, since the counter electrode array and the aperture array can be arranged close to each other, the optical axis alignment of the unit assembly becomes easy. Therefore, even a counter electrode array / opening array with a smaller pitch can be assembled with high precision positioning. As the filling material, copper, tungsten, or an alloy containing the same can be used.

In the combined unit, a region in which the substrate of the opening array is filled with the filling material can be a columnar structure. And it can be set as the structure where the columnar structure extended from the 3rd main surface to the 4th main surface. Since the filling material passes through the substrate of the aperture array, heat from the counter electrode array flowing into the third main surface can be effectively conducted to the fourth main surface. Further, when the thermal resistance is reduced over a wide area by using the columnar structure, a plurality of columnar structures can be arranged. Thereby, compared with the case where not all the large areas are divided | segmented into columnar shape, even if there exists a residual stress in a filling material, a deformation | transformation can be reduced. The effect here is substantially the same as that of the columnar structure filling material in the first substrate.

Further, an exposure apparatus that draws a pattern on a substrate with a plurality of charged particle beams can be configured using the charged particle optical system of the present embodiment. Since the thermal deformation of the optical system is reduced, accurate pattern drawing with little optical aberration can be performed. In addition, since the number and density of the counter electrode arrays can be increased, an exposure apparatus with improved drawing speed and high throughput can be realized.

Hereinafter, the present invention will be described in more detail with reference to more specific examples. However, the present invention is not limited to these examples.
Example 1
Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 2 shows a configuration of a charged particle drawing apparatus using the charged particle optical system of the present invention. Here, a case where the charged particles are electrons will be described. The charged particle drawing apparatus has a controller 101, and a circuit shown in FIG. 2 can control a charged particle optical system and a stage to form a desired pattern on a wafer.

A radiated electron beam is emitted from the electron source 107, converted into a parallel beam by the collimator lens 108, and irradiated onto the aperture array 109. The plurality of electron beams divided by the aperture array 109 are individually focused by the focusing lens array 110 controlled by the lens control circuit 105 and imaged on the counter electrode array 111. The counter electrode array 111 is a device having individual counter electrodes. The counter electrode array 111 individually turns on / off the beam according to the drawing pattern based on the blanking signal generated by the drawing pattern generation circuit 102, the bitmap conversion circuit 103, and the blanking command circuit 106.

When the beam is ON, no voltage is applied to the deflection electrode of the counter electrode array 111, and when the beam is OFF, a voltage is applied to the deflection electrode of the counter electrode array 111 to deflect the multi-electron beam. . The multi-electron beam deflected by the counter electrode array 111 is blocked by the stop aperture array 112 in the subsequent stage, and the beam is turned off. The electron beam that has passed through the stop aperture array 112 is deflected by the electrostatic deflector 113. The deflector 113 is formed by a counter electrode. Here, two electrostatic deflectors are arranged to perform two-stage deflection in the deflection direction. These electrostatic deflectors 113 are driven in accordance with signals from the deflector control circuit 104. Finally, the plurality of electron beams are reduced and imaged on the wafer 115 by the objective lens array 114 driven by the lens control circuit 105. During pattern drawing, the wafer 115 is continuously moved by the stage 116. Then, the counter electrode array 111 individually turns the beams on and off according to the drawing pattern. Thereby, a desired pattern can be drawn on the wafer 115 surface at high speed. The controller 101 controls the entire circuit.

Next, the counter electrode array 111 of this embodiment will be described in more detail.
FIGS. 1A and 1B and FIGS. 3A and 3B are diagrams showing the counter electrode array 111 of this embodiment. FIG. 1A is a top view, and FIG. 1B is a cross-sectional view taken along the line AA ′ of FIG. As shown in FIG. 1, the counter electrode array has a counter electrode formation region 9 and a control circuit formation region 10 on a silicon substrate 1. The counter electrode formation region 9 has a plurality of pairs of counter electrodes. On the other hand, a blanking command circuit 106 is formed in the control circuit formation region 10. As shown in FIG. 1B, the silicon substrate 1 has a first main surface 2 and a second main surface 3 which is the opposite surface. A control circuit 4 is formed as a blanking command circuit 106 in the control circuit formation region 10 on the first main surface. A multilayer wiring layer 6 and an interface unit 5 are formed on the control circuit 4 as shown in the figure. The multilayer wiring layer 6 has a structure in which insulator films including conductive interlayer vias and metal wiring films are alternately stacked (each layer is not shown). The multilayer wiring layer 6 electrically connects the interface unit 5 and the control circuit 4, and the control circuit 4 and the counter electrode 11. The multilayer wiring layer 6 can use, for example, aluminum or copper as a conductive material, and silicon oxide as an insulator film. In this embodiment, copper and silicon oxide are used as the conductive material and the insulating film, respectively. A signal from the bitmap conversion circuit 103 is guided to the interface unit 5 by light. Therefore, the interface unit includes a photodiode for performing photoelectric conversion. For this reason, the control circuit 4 includes a drive circuit for driving the photodiode.

Next, the counter electrode formation region 9 will be described in detail with reference to FIGS. 3A is a top view of the counter electrode formation region 9, and FIG. 3B is a cross-sectional view taken along line A-A 'of FIG. 3A. In the counter electrode forming region 9, 16 charged particle optical elements 13 each having a pair of two counter electrodes 11 and a through-hole 12 indicated by a circular broken line as one element are arranged in a total of 16 elements. As shown in FIG. 3B, the counter electrodes 11 </ b> A and 11 </ b> B are formed on the multilayer wiring layer 6. Both the counter electrodes 11A and 11B have a bump structure formed of gold. A through hole 12 is formed between the counter electrodes 11A and 11B. The through hole 12 is formed through the multilayer wiring layer 16 and the silicon substrate 1. The 16 elements are connected to four vertical and horizontal wirings, and each element is connected to a switch element and a memory element (not shown). The control circuit 4 performs active matrix driving to apply a voltage corresponding to the drawing pattern. Can be applied. Although the number of charged particle optical elements 13 arranged in one counter electrode formation region 9 is 16 elements in FIG. 3 for explanation, in the present embodiment, about 680 elements of 26 × 26 are formed. Moreover, if the MEMS manufacturing technique is used, it can be formed on a scale of several thousand to several tens of thousands.

The electrode 11A is kept at the ground potential, and a voltage higher than the ground potential is applied to the electrode 11B. The voltage applied to the electrode 11B is about 1-20V, More preferably, it is about 1-3V. In this embodiment, about 2V is applied. In FIG. 3B, the trajectory of a charged particle beam (here, an electron beam is assumed) when a voltage is applied is shown as a solid line D. The broken line C is the trajectory of the charged particle beam when no voltage is applied. In this way, when a voltage is applied to the electrode 11B, the charged particle beam can be deflected.

The charged particle optical element 13 is not limited to a pair or a set of counter electrodes shown in FIG. In addition, it is possible to increase the number of pairs or sets of counter electrodes. 4A and 4B are enlarged top views of one charged particle optical element 13. FIG. 4A shows an example in which a pair of counter electrodes 11A and 11B similar to those in FIG. 3 are formed. On the other hand, in FIG. 4B, two pairs of counter electrodes 11A and 11B and counter electrodes 11C and 11D are formed. In this way, a plurality of sets of counter electrodes may be formed in one charged particle optical element 13. In the case of FIG. 4B, for example, the counter electrodes 11A and 11B are operated at the same potential at a certain potential A, and the counter electrodes 11C and 11D are operated at the same potential at a potential B different from the potential A. If the control circuit and wiring are configured, it can also operate as an astigmatism corrector. If all the counter electrodes 11A, 11B, 11C, and 11D have the same potential, they can act as lenses. Further, if the above voltages are added, the function of the deflector, lens, and astigmatism corrector can be combined.

The control circuit 4 of this embodiment generates heat during driving and raises the temperature of the entire counter electrode array. The counter electrode formation region 9 as a whole also generates heat because it has the switch element and the wiring 6 although the amount of heat generation is smaller than that of the control circuit. In such a configuration, the second main surface 3 of the substrate 1 is fixed to the holder substrate 8 so that a charged particle beam (moving in the direction of the arrow α) can pass as shown in FIG. The holder substrate 8 has a cooling means (not shown), and heat can be discharged from the second main surface 3 to the holder substrate 8. The cooling means can be implemented by forming the holder substrate 8 itself with a material having good thermal conductivity, or by forming a flow path to flow a refrigerant. In the present embodiment, the holder substrate 8 has a flow path formed therein, and can be cooled using water as a refrigerant. The member of the holder substrate 8 is also formed of copper.

The silicon substrate 1 has a via 7 filled with a metal having higher thermal conductivity than silicon. Particularly in this embodiment, copper is embedded as a filling material. As shown in FIGS. 1A and 1B, the vias 7 have a columnar structure, and a plurality of vias are densely arranged in the lower region of the control circuit 4 and the counter electrode formation region 9. The heat of the control circuit 4 can be effectively conducted to the second main surface 3. The columnar cross-sectional shape is circular in the illustrated example, but may be any other shape such as a square, a rectangle, or a triangle. The via 7 may be formed by any method such as a method of opening a hole and filling the metal with electroplating. The thermal conductivity coefficient of copper is 398 W / (m · K), which is about 2.6 times higher than that of silicon (150 W / (m · K)). Therefore, the thermal resistance of this part can be reduced to half or less. In the present embodiment, the via 7 buried in this way is formed only immediately below the control circuit 4 and the counter electrode formation region 9 having a large calorific value. Thus, by lowering the thermal resistance of the substrate 1 at the location where the heat generation amount is large, the temperature rise of the control circuit 4 and the multilayer wiring layer 6 can be reduced.

Next, specific dimension examples will be described. The thickness of the silicon substrate 1 is 340 μm. The thickness of the multilayer wiring layer 6 is 10 μm. The counter electrode formation region 9 is formed in an area of 4 mm × 4 mm, and 26 × 26 charged particle optical elements 13 are formed in this area at a pitch of 150 μm. The through hole 12 typically has a diameter of about 10 μm to 30 μm, and in this embodiment, has a diameter of 15 μm. The counter electrodes 11A and 11B each have a width of 10 μm × length of 20 μm × height of 15 μm and are configured using gold bumps. On the other hand, the control circuit 4 is formed in an area of 6 mm × 1.5 mm with a distance of 0.1 mm from the counter electrode formation region 9. The copper vias 7 are formed immediately below the counter electrode formation region 9 in a region where the charged particle optical element 13 is not formed with a pitch of 150 μm and a diameter of 150 μm. Directly below the control circuit 4, the diameter is 300 μm and the pitch is 150 μm. All the vias 7 are formed in a region having a depth of 180 μm from the second main surface 3.

In such a configuration, one control circuit 4 and the counter electrode formation region 9 generate heat of about 6 W and 2 W, respectively. The second main surface 3 and the holder substrate 8 are not bonded in the counter electrode formation region 9 but bonded so that a good thermal connection can be obtained in other portions. The cooling means mounted on the holder substrate 8 is exhausted with a heat transfer coefficient of 10,000 W / (m ² · K). Accordingly, the first main surface 2 is at a higher temperature than the second main surface 3.

At this time, when driving is performed only by the substrate 1 without including all the vias 7, the translational displacement in the optical axis direction of the counter electrode formation region 9 due to heat deformation due to heat generation is an average displacement in the direction of arrow α in FIG. 62 nm. On the other hand, in this embodiment, it can be reduced by about 13%, which is 54 nm. Further, the deformation distribution in the counter electrode formation region 9 can also be reduced from 17 nm to 15 nm. As described above, in this embodiment, the thermal deformation of the counter electrode formation region 9 can be reduced by forming the via 7. Therefore, since the positional accuracy of the plurality of charged particle optical elements 13 formed in the counter electrode formation region 9 can be improved, a charged optical element with less aberration can be obtained. In addition, since the amount of change in the positional relationship with another optical element in the charged particle optical system before and after driving is reduced, assembly of the entire charged particle optical system can be simplified.

Further, copper used as a filling material in this example has a linear expansion coefficient 5 to 6 times higher than that of silicon. This has the following effects. The multilayer wiring layer 6 for electrically wiring to the control circuit 4 and the interface unit 5 has a structure in which silicon oxide films and copper are alternately stacked. Therefore, the linear expansion coefficient is higher than that of silicon. Since the multilayer wiring layer 6 generates heat and is close to the control circuit 4, the temperature rises. In such a situation, the first main surface 2 side receives stress due to the elongation of the multilayer wiring layer 6. Therefore, as in the present embodiment, the via embedding depth of copper in the via 7 is not stopped through the silicon substrate, but is stopped halfway, so that the extension on the second main surface 3 side is increased and the multilayer wiring layer 6 is used. The influence of thermal stress on deformation can be reduced. Alternatively, the silicon substrate 1 and the via 7 can be electrically connected. In that case, the via 7 can be used as power supply means for defining the potential of the silicon substrate 1. Thus, the potential can be regulated by reducing the potential distribution even when the silicon substrate 1 has a high resistance without providing a special power supply pad or the like to the substrate 1.

The manufacturing method of the counter electrode array of this example is as follows. A control circuit 4 and a multilayer wiring layer 6 are formed on a silicon substrate using a general semiconductor manufacturing technique, and then a photodiode is mounted. Thereafter, the through hole 12 is produced by a MEMS manufacturing technique, and the through hole 12 is backfilled and flattened. And the hole for via | veer 7 is formed from the 2nd main surface 3 side by a MEMS manufacturing technique, and the copper via | veer 7 is formed by electroplating. Thereafter, gold bumps are formed from the first main surface 2 side by electroplating to form counter electrodes 11A and 11B. Finally, the backfill material of the through holes 12 can be removed to form the counter electrode array. As described above, since the counter electrode array of this embodiment can be formed by combining the semiconductor manufacturing technology and the MEMS manufacturing technology, a high-density and large-scale counter electrode array can be formed with high accuracy.

(Example 2)
A second embodiment of the present invention will be described with reference to FIGS. 5 (a) and 5 (b). Note that portions having the same functions as those in the first embodiment are denoted by the same reference numerals, and the description is simplified, and the description of the same effect is also simplified or omitted. The thickness of the counter electrode formation region 9 of the silicon substrate 1 is different between the first embodiment and the present embodiment. In the present embodiment, the thickness of this region is thinner than the thickness of regions other than that region. FIG. 5A is a top view of the counter electrode array of this embodiment, and FIG. 5B is a cross-sectional view taken along the line AA ′ of FIG. The counter electrode formation region 9 indicated by a broken line in FIG. 5B is thinner than the other regions. Further, unlike the first embodiment, the via 7 is not formed in the counter electrode formation region 9.

Next, specific dimension examples will be described. The thickness of the counter electrode forming region 9 of the silicon substrate 1 is 40 μm. The other thickness is 340 μm. The diameter of the through-hole 12 is typically 0.5 μm to 20 μm, and in this embodiment is 1.5 μm. Due to the processing characteristics of deep dry etching on silicon, it is difficult to control the diameter and the inclination of the central axis when processing through holes with a high aspect ratio. If such an error occurs, the charged particle beam may be blocked. Further, when the diameter of the through hole becomes large due to an error, the through hole may reach the counter electrode arranged close to the counter electrode, and the counter electrode may be damaged. Therefore, it is necessary to increase the hole diameter for the charged particle beam and increase the gap of the counter electrode with respect to the hole diameter in anticipation of the processing margin. In this embodiment, by selecting the amount of thinning the substrate 1 according to the target through-hole diameter, a through-hole having a submicron order diameter can be formed between the counter electrodes. Furthermore, the pitch of the through holes 12 can be reduced, and the charged particle optical elements 13 can be arranged with high density.

The vias 7 are formed with a diameter of 300 μm and a pitch of 150 μm immediately below the control circuit 4. Each via 7 is formed in a region having a depth of 240 μm from the second main surface 3. In the present embodiment, only the control circuit 4 generates heat at 6 W. Other dimensions and the amount of exhaust heat are the same as in the first embodiment.

The silicon substrate 1 has a temperature gradient from the first main surface 2 to the second main surface 3, and a large thermal stress is generated on the first main surface side. Furthermore, since the multilayer wiring layer 6 has a larger linear expansion coefficient than silicon, this effect is increased. Since the counter electrode formation region 9 is formed in a thin film on the first main surface 2 side, the arrow in FIG. 5B is caused by the effect of the temperature increase and the temperature gradient in the thickness direction as described above. A translational displacement occurs in the β direction. At this time, this direction (Z direction) displacement of the upper surface of the counter electrode formation region 9 is shown in FIG. FIG. 6 shows the case where the hollow plot does not include the via 7 and only the silicon substrate 1 and the solid plot is the present embodiment. The horizontal axis indicates the position of the line segment OX shown in FIG. When the via 7 is not formed as shown, the maximum displacement is 0.15 μm. On the other hand, in this embodiment, the maximum displacement is 0.08 μm, and the maximum displacement can be reduced. Further, assuming that about 80% of the counter electrode formation region 9 having an overall width of 4 mm is actually used, the difference shown by the lines P and Q in FIG. 6 is an important displacement distribution. It can be seen that the displacement distribution of the prior art is about 80 nm, the displacement distribution of the present embodiment is about 15 nm, and the displacement distribution can also be reduced by the via 7.

As described above, even when only the counter electrode formation region 9 of the substrate 1 is thinned, the deformation due to heat generation of the control circuit 4 can be effectively reduced by forming the via 7. Further, in this embodiment, since it is not necessary to form the vias 7 in the counter electrode forming region 9, the counter electrode array can be formed with a very high density. And since the filling material is not formed in the counter electrode formation area 9, the deformation | transformation resulting from the residual stress of a filling material can be eliminated.

(Example 3)
Embodiment 3 of the present invention will be described with reference to FIGS. 7 (a) and 7 (b). Note that parts having the same functions as those of the first and second embodiments are denoted by the same reference numerals, and the description will be simplified, and the description of the same effect will be simplified or omitted. The present embodiment is different from the previous embodiment in that it is an integrated unit in which two devices of the counter electrode array and the aperture array are assembled on the holder substrate 8.

FIG. 7A shows a cross-sectional view of the unit of this embodiment. In the portion surrounded by the broken line R, the counter electrode array of Example 2 is joined to the third main surface 14 of the second substrate 16 with the second main surface 3 oriented as shown. In the present embodiment, the second main surface 3 and the third main surface 14 are bonded using an adhesive having good thermal conductivity. FIG. 7B is a top view seen from the direction of the arrow γ in FIG. As shown in the drawing, an opening 18 is formed in the second silicon substrate 16 at a position corresponding to the counter electrode. The charged particle beam enters from the direction of the arrow γ, is shaped into a desired shape by the opening 18 and enters the counter electrode. The opening 18 and the through hole 12 of the silicon substrate 1 are installed with their center axes aligned. By bonding the silicon substrate 1 and the second silicon substrate 16 without using another member as in this embodiment, the alignment between the two substrates can be improved. In addition, by joining at the wafer level and finally cutting to the device size, a highly aligned unit can be manufactured at low cost.

In the second silicon substrate 16, the region where the opening 18 is formed is thin. Therefore, similarly to the through-hole 12 of the second embodiment, it is possible to accurately process holes with a minute diameter and pitch. On the other hand, the thickness of the other portions is increased, and the rigidity of the entire second silicon substrate 16 is kept high. By adopting such a structure, the second silicon substrate 16 is prevented from being damaged or deformed due to external stress even if an aperture array having a minute diameter and pitch is formed. Can do. The non-thinned portion is fixed on the fourth main surface 15 so as to have a good thermal connection to the holder substrate 8. As described in the previous embodiment, heat can be discharged from the fourth main surface 15 to the outside by the cooling means mounted on the holder substrate 8.

The second silicon substrate 16 has a second via 17 so as to penetrate from the third main surface 14 to the fourth main surface 15 as shown in FIG. The second via 17 is formed at a position corresponding to the via 7 as shown in the figure so that it can be thermally connected to the via 7 formed in the counter electrode array. As with the via 7, a metal such as copper or tungsten can be used as the second filling material of the second via 17. In this embodiment, the filling material is copper. Heat from the control circuit 4, the interface unit 5, and the multilayer wiring layer 6 formed on the first main surface 2 side is discharged from the counter electrode array through the second main surface 3. Subsequently, since the second main surface 3 and the third main surface 14 are thermally well connected, heat is conducted from the third main surface 14 to the fourth main surface 15, and the holder substrate 8. Is discharged. At this time, since the thermal resistance in the thickness direction of the silicon substrate 1 and the second silicon substrate 16 is reduced by the via 7 and the second via 17, the heat from the first main surface 2 is effectively reduced. Can be discharged. And the temperature rise of the 1st main surface 2 can be reduced. In this manner, the structure in which the silicon substrate 1 and the second silicon substrate 16 are joined can be cooled well by the via 7 and the second via 17.

Alternatively, the silicon substrate 1 and the via 7 and the second silicon substrate 16 and the second via 17 may be electrically connected. In that case, the via 7 and the second via 17 can be used as power supply means for defining the potential of the silicon substrate 1 and the second silicon substrate 16. Without providing a special power supply pad or the like to the substrate, the potential can be regulated by reducing the potential distribution even when silicon has a high resistance.

1 ... Silicon substrate (first substrate) 2 ... First main surface 3 ... Second main surface 4 ... Control circuit 7 ... Via (first filling material region), 11A, 11B .. Counter electrode, 12 .. Through hole, 14 .. Third main surface, 15.. Fourth main surface, 16 .. Second silicon substrate (second substrate), 17. Second via (second filling material region), 18 .. opening

In the production of semiconductor devices, the electron beam exposure technique is a promising candidate for lithography that enables fine pattern exposure of 0.1 μm or less. In such an exposure apparatus, a charged particle optical element for controlling the optical characteristics of the electron beam is used. In the electron beam exposure technique, there has been proposed a multi-beam system that simultaneously draws a pattern with a plurality of electron beams without using a mask. In a multi-beam system, a charged particle optical element in which charged particle optical elements are arranged in a one-dimensional or two-dimensional array is used. In such a charged particle optical element array, a deflection electrode and a multipole lens can be formed by a microelectromechanical system (MEMS) manufacturing technique, and one element can be miniaturized and arranged at a high density to produce a large-scale array. . Furthermore, the control circuit is also integrated on the same substrate as the substrate on which the deflection electrode is formed, so that high speed and large scale array can be realized. (Refer to Patent Document 1 and Non-Patent Document 1) In addition, the astigmatism corrector can be downsized by using the MEMS manufacturing technique and using the facing electrode structure similar to the deflection electrode. (See Non-Patent Document 1)

In such charged particle optical element arrays, higher precision is required for alignment between optical element arrays as one element is reduced in size and density, and smaller optical aberrations are required as drawing patterns become finer. Or Therefore, it is important to realize a charged particle optical element array with small thermal deformation.

In a device in which the charged particle optical element array and the control circuit are integrated on the same substrate, there is a concern that heat generated by the control circuit causes the charged particle optical element array on the substrate to be thermally deformed. In particular, the control circuit also has an optical interface unit such as a photodiode for inputting a control signal to the device or an electrical interface unit such as a metal bump or a metal pad on the same surface side of the substrate. For this reason, it is difficult to say that it is easy to enlarge the exhaust heat exhaust area on this surface side. Therefore, there is a problem that thermal deformation cannot be sufficiently reduced. On the other hand, it is conceivable to cool from the back surface opposite to this surface. In this case, due to the thermal resistance of the substrate, it may not be possible to exhaust heat sufficiently, or a temperature gradient may occur in the thickness direction of the substrate, causing bending stress. Therefore, also in this case, there is a problem that thermal deformation cannot be sufficiently reduced.

The counter electrode array also releases heat to the outside of the device on the surface (second main surface) opposite to the surface (first main surface) on which the counter electrode, control circuit, and interface section are formed. It has a heat exhaust surface. Here, the optical axis of the charged particle beam is the normal line, the surface of the first substrate on which the counter electrode is formed is the first main surface, and the surface opposite to the first main surface is the second main surface. A surface is a thickness, and a dimension in a direction from the first main surface to the second main surface is a thickness. The cooling means can come into thermal contact with the heat removal surface to discharge the heat. As the cooling means, means capable of transporting heat to the outside of the system, for example, a heat sink, a cooling element using a refrigerant, a Peltier element, a heat pipe, or the like is used. Moreover, you may have a heating means in the said heat exhaust surface . In the manner of this, when installing the cooling means to the second principal surface side, as compared with the case of placing the cooling means to the first main surface, it can be increased formation area of the interface unit and the counter electrode of the control signal. That is, the number of counter electrode arrays can be increased with the same device size. Therefore, the device can be manufactured at a lower cost.

Claims (9)

A charged particle optical system having a first substrate provided with a counter electrode array including a plurality of counter electrodes that form electric fields that act on a plurality of charged particle beams in an optically charged particle manner, respectively.
The optical axis of the charged particle beam is a normal line, the surface of the first substrate on which the counter electrode is formed is a first main surface, and the surface opposite to the first main surface is a second main surface. The first substrate extends in the thickness direction from the second main surface, with the thickness in the direction from the first main surface to the second main surface as the thickness. A charged particle optical system having a region provided with a first filling material having higher thermal conductivity than a substrate. The first substrate is a silicon substrate;
The counter electrode array includes a control circuit on the silicon substrate, an interface unit that receives a control signal to the control circuit, and an electric field that acts on the plurality of charged particle beams optically based on the control signal. The charged particle optical system according to claim 1, further comprising: a plurality of counter electrodes that form a plurality of counter electrodes. The first substrate has a plurality of through holes that penetrate the first substrate in the thickness direction through which the plurality of charged particle beams respectively pass.
The thickness of the region of the first substrate on which the plurality of counter electrodes are formed is thinner than the thickness of a region other than the region on which the counter electrodes are formed. Charged particle optics. 4. The charged particle optical system according to claim 1, wherein the first filling material has a higher coefficient of thermal expansion than the material of the first substrate or silicon. 5. The charged particle optical system according to any one of claims 1 to 4, wherein the region filled with the first filling material is a region having one or more columnar structures. Further comprising an aperture array;
The aperture array has a plurality of apertures in the second substrate that respectively limit the charged particle beam incident on the counter electrode array;
The second substrate has the optical axis as a normal line, one surface as a third main surface, a surface opposite to the first main surface as a fourth main surface, and a third main surface. And a thickness in a direction between the fourth main surface and a region having a second filling material having a higher thermal conductivity than the second substrate in the thickness direction,
The charged particle according to any one of claims 1 to 5, wherein the third main surface is disposed in thermal contact with the second main surface of the counter electrode array. Optical system. The region filled with the second filling material is a region of one or more columnar structures, and penetrates from the third main surface to the fourth main surface. The charged particle optical system according to 1. An optical element array structure having a first substrate formed with a plurality of apertures through which a plurality of charged particle beams pass.
The optical axis of the charged particle beam is a normal line, one surface of the first substrate is a first main surface, a surface opposite to the first main surface is a second main surface, The thickness of the first substrate from the main surface to the second main surface is a thickness, and the first substrate extends in the thickness direction from the second main surface, and is more thermally conductive than the first substrate. An optical element array structure having a region provided with a high first filling material. The charged particle optical system or optical element array structure according to any one of claims 1 to 8,
An exposure apparatus that performs drawing on a substrate using a plurality of charged particle beams.

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