JP2013161959A - Semiconductor integrated circuit and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an LSI chip 10 in which inner I/O buffer cells Cec having bonding pads Pb which are positioned closer to an LSI internal circuit 10a and outer I/O buffer cells Cea having bonding pads Pa which are positioned farther from the LSI internal circuit 10a are arranged such that arrangements of the bonding pads of the I/O buffer cells are arranged in a zigzag arrangement, and which eliminate a difference in a signal delay amount and a difference in a voltage drop amount which are caused a difference in positions of the bonding pads between the inner I/O buffer cells and the outer I/O buffer cells.SOLUTION: A semiconductor integrated circuit comprises: an inner peripheral side region Rc in which bonding pads Pc of an inner I/O buffer cells Cec are arranged; an outer peripheral side area Ra in which bonding pads Pa of an outer I/O buffer cells Cea are arranged; and an intermediate region ensured between the inner peripheral side region Rc and the outer peripheral side region Ra in which interface circuits which compose signal I/O buffer cells are arranged and wiring Vw for a power source and wiring Gw for grounding are arranged.

Description

  The present invention relates to a semiconductor integrated circuit and an electronic apparatus, and more particularly to different types of I / O buffers in a semiconductor integrated circuit (LSI chip) having a plurality of types of I / O buffer cells having different bonding pad positions with respect to an LSI internal circuit. The present invention relates to a configuration capable of eliminating a difference in signal delay amount and voltage drop amount caused by which of the cells is used.

  Conventionally, in semiconductor integrated circuits (LSI chips), the layout area of LSI internal circuits that perform arithmetic processing is reduced by miniaturizing wiring and multilayering, and the number of electrodes suitable for the scale of LSI internal circuits is secured. For this reason, there is a staggered arrangement of electrodes arranged around the LSI internal circuit.

  FIG. 8 is a diagram for explaining a semiconductor chip disclosed in Patent Document 1 as an example of such a semiconductor chip, and FIG. 8A is a plan view showing a schematic configuration of this semiconductor chip. b) is a cross-sectional view showing a state in which the semiconductor chip is accommodated in a main body of a semiconductor package (hereinafter referred to as a package main body).

  The semiconductor chip 100 includes an internal circuit 102 that performs arithmetic processing, and a plurality of electrodes 103 that are arranged in two rows along the periphery of the internal circuit. Here, the internal circuit 102 includes a plurality of individual circuits (unit cells) 101. The individual circuit 101 is a circuit as a design unit including basic circuit elements such as transistors.

  Further, the arrangement pattern of the plurality of electrodes 103 arranged in two rows around the inner turning portion 102 is a staggered pattern. Specifically, the plurality of electrodes 103 are arranged in a row inside the chip. The signal input / output electrodes 103a are arranged, and the power supply electrodes 103b and the ground electrodes 103c are alternately arranged in a column outside the chip.

  Such a semiconductor chip 100 is accommodated in a package main body 110, electrodes of the semiconductor chip 100 are connected to terminals of the package main body 110, and the package main body is sealed with a package lid member, a sealing resin, or the like. Can be obtained.

  Here, the semiconductor chip 100 is disposed at the center of the package body 110, and a common power ring wiring 111 and a common ground ring wiring 112 are provided in the first wiring region around the region where the semiconductor chip is disposed. The common ground ring wiring 112 is formed outside the common power supply ring wiring 111. A second wiring region having a height higher than that of the first wiring region is formed on the outer peripheral side of the first wiring region around the region where the semiconductor chip is disposed. In the region, input / output inner lead terminals 113 are arranged.

  The signal input / output electrode 103 a disposed inside the semiconductor chip 100 is connected to the inner lead 113 by the wiring wire 121, and the power supply electrode 103 b disposed outside the semiconductor chip 100 is connected to the wiring wire 122. The ground electrode 103c connected to the common power supply ring wiring 111 disposed on the innermost side of the package body 110 and disposed outside the semiconductor chip 100 is connected to the common power supply ring wiring 111 by the wiring wire 123. It is connected to the common ground ring wiring 112 arranged outside.

  Further, as a semiconductor chip such as an LSI chip, in addition to the semiconductor chip disclosed in Patent Document 1, an input / output buffer cell including an electrode pad around the LSI internal circuit and separately from the unit cell constituting the LSI internal circuit. Some (I / O buffer cells) are arranged.

  Hereinafter, a semiconductor chip (LSI chip) having an I / O buffer cell will be described with reference to FIGS. In these figures, Cea1, Ceb2, Cea3, Ceb4, Cea5, Ceb6, Cea7, and Ceb8 are I / O buffer cells, and Pa1, Pb2, Pa3, Pb4, Pa5, Pb6, Pa7, and Pb8 are Although it is a bonding pad, for convenience of explanation, when I / O buffer cells are collectively described, it is referred to as I / O buffer cell Ce, and when outside I / O buffer cells are collectively described, outer I / O buffer cells are described. When the inner I / O buffer cells are collectively described as the buffer cell Cea, the inner I / O buffer cell Ceb is used. When the bonding pads of the outer I / O buffer cell are described together, the bonding pad Pa is used. When collectively describing the bonding pads of the inner I / O buffer cell, the bonding pads Pb and That.

  FIG. 9 is a plan view for explaining a semiconductor chip having such an I / O buffer cell, and shows a schematic configuration of the semiconductor chip.

  A semiconductor chip 200 shown in FIG. 9 is arranged around an internal circuit part (LSI internal circuit) 200a in which unit cells Uc serving as units constituting a logic circuit are arranged, and around the internal circuit part 200a. And a buffer unit 200b for exchanging signals with each other. The buffer unit 200b includes two types of I / O buffer cells Cea and Ceb as unit circuits of a design having bonding pads Pa and Pb that are located at different positions with respect to the internal circuit unit 200a. Here, the bonding pads Pa and Pb are electrode pads to which bonding wires (wiring wires) are fixed.

  Further, in the buffer arrangement region BR in which the I / O buffer cell Ce is arranged, bonding pads Pa and Pb are arranged in two rows for each I / O buffer cell Ce, and the outer I / O buffer cell Cea The bonding pad Pa is located on the outer peripheral side portion Ra of the buffer arrangement region BR, and the bonding pad Pb of the inner I / O buffer cell Ceb is between the outer peripheral side portion Ra and the inner peripheral side portion Rc of the buffer arrangement region BR. Located in the middle portion Rb, the bonding pads Pa and Pb are arranged in a staggered pattern.

  Further, between the arrangement area CR of the LSI internal circuit 200a and the buffer arrangement area BR, the power supply wiring Vw and the ground wiring Gw are arranged so as to surround the LSI internal circuit 200a.

  FIG. 10 is a diagram for explaining a detailed configuration of a part (B section) of the semiconductor chip 200 shown in FIG. 9, and shows the positional relationship between the I / O buffer cell and the bonding pad.

  In this semiconductor chip 200, the outer I / O buffer cell Cea and the inner I / O buffer cell Ceb arranged in the buffer arrangement region BR are provided with bonding pads Pa and Pb, respectively. Bonding pads Pa1, Pa3, Pa5, Pa7 corresponding to the cells Cea1, Cea3, Cea5, Cea7 are arranged on the outer peripheral portion Ra of the buffer arrangement area BR, and correspond to the inner I / O buffer cells Ceb2, Ceb4, Ceb6, Ceb8. The bonding pads Pb2, Pb4, Pb6, and Pb8 to be performed are arranged in the intermediate portion Rb of the buffer arrangement region BR.

  FIG. 11 is a diagram for explaining a detailed configuration of a part (B section) of the semiconductor chip 200 shown in FIG. 9, and shows the positional relationship between the power supply wiring and ground wiring and the bonding pads.

  In this semiconductor chip 200, the I / O buffer cells Cea1 and Ceb6 are power I / O buffer cells, the I / O buffer cells Cea3 and Ceb8 are ground I / O buffer cells, and the I / O buffer cell Cea1. The bonding pads Pa1 and Pb6 corresponding to Ceb6 are connected to the power supply wiring Vw, and the bonding pads Pa3 and Pb8 corresponding to the I / O buffer cells Cea3 and Ceb8 are connected to the ground wiring Gw.

  The other I / O buffer cells Ceb2, Ceb4, Cea5, and Cea7 are signal I / O buffer cells, and bonding pads Pb2, Pb4, Pa5, and Pa7 corresponding to these signal I / O buffer cells are LSIs. This is a bonding pad for transferring a signal between the internal circuit 200a and an external circuit.

  FIG. 12 is a diagram showing a detailed configuration of a part (part B) of the semiconductor chip 200 shown in FIG. 9, and positions of bonding pads and interface circuits (input / output circuits) in the signal I / O buffer cell. Showing the relationship. Accordingly, in FIG. 12, the power supply wiring and the ground wiring are shown for convenience in explaining the connection relation of the circuit, and do not show the actual positions. The actual positions are shown in FIG. As shown in

  In this semiconductor chip 200, signal I / O buffer cells Ceb2 and Cea5 are output I / O buffer cells for outputting signals obtained by the LSI internal circuit 200a of the semiconductor chip 200 to an external circuit. These output I / O buffer cells Ceb2 and Cea5 have interface circuits Fb2 and Fa5, respectively, for amplifying and converting signals from the LSI internal circuit 200a. The signal I / O buffer cells Ceb4 and Cea7 are input I / O buffer cells for inputting signals from external circuits to the LSI internal circuit 200a of the chip 200, and these input I / O buffer cells. Ceb4 and Cea7 have interface circuits Fb4 and Fa7, respectively, for amplifying and converting signals output to the outside of the LSI chip 200.

  In addition, each I / O buffer cell Cea1, Ceb2, Cea3, Ceb4, Cea5, Ceb6, Cea7, Ceb8 is electrostatically applied to the corresponding bonding pads Pa1, Pb2, Pa3, Pb4, Pa5, Pb6, Pa7, Pb8. The protection circuits Da1, Db2, Da3, Db4, Da5, Db6, Da7, Db8 are provided to prevent the noise from destroying the LSI internal circuit 200a. Each buffer cell is arranged at the outer peripheral side portion Ra of the buffer arrangement region BR and is connected to the bonding pad of the corresponding I / O buffer cell. These protection circuits are connected to the power supply wiring Vw and the ground wiring Gw.

  Also for the semiconductor chip 200 having such a configuration, like the semiconductor chip 100 shown in FIG. 8, the semiconductor chip 200 is accommodated in a package body as shown in FIG. 8B, for example, and each bonding pad is attached to the package body. A semiconductor package on which a semiconductor chip is mounted is obtained by connecting to wiring and terminals and sealing the package body.

  At this time, the bonding pads of the semiconductor chip and the terminals of the package body are connected as follows. For example, the bonding pads Pb2, Pb4, Pa5, Pa7 of the signal I / O buffer cells Ceb2, Ceb4, Cea5, Cea7 are connected to the input / output inner lead terminals 113 of the package body by bonding wires. Further, the bonding pads Pa1 and Pb6 of the power supply buffer cells Cea1 and Ceb6 are connected to the common power supply ring wiring 111 by bonding wires, and the bonding pads Pa3 and Pb8 of the grounding buffer cells Cea3 and Ceb8 are connected to the common ground by bonding wires. The ring wiring 112 is connected.

JP 11-87399 A

  However, in recent years, with the miniaturization and low power consumption of LSIs, and the increase in scale and speed of LSIs, circuit malfunction due to voltage drop (IR drop) caused by wiring resistance inside the LSI is prevented. Because of this, the design is becoming very difficult.

  For example, in the semiconductor integrated circuit (LSI chip) 200 shown in FIGS. 9 to 12, the bonding pads of the I / O buffer cell are divided into the outer peripheral side portion Ra and the intermediate portion Rb of the buffer arrangement region BR of the semiconductor chip 200. For this reason, the outer I / O buffer cells Cea1, Cea3, Cea5, Cea7 in which the bonding pads Pa1, Pa3, Pa5, Pa7 are arranged on the outer peripheral side portion Ra of the buffer arrangement region BR, and bonding In the inner I / O buffer cells Ceb2, Ceb4, Ceb6, and Ceb8 in which the pads Pb2, Pb4, Pb6, and Pb8 are arranged in the intermediate portion Rb of the buffer arrangement region BR, the corresponding bonding pads to the LSI internal circuit The distance is different.

  Therefore, when the I / O buffer cell is used as a signal I / O buffer cell, the bonding pad Pa is an outer I / O buffer cell Cea arranged in the outer peripheral portion Ra of the buffer arrangement region BR. There is a possibility that a difference in signal transmission time, rise time, and the like occurs in the case of the inner I / O buffer cell Ceb in which the bonding pad Pb is arranged in the intermediate portion Rb of the buffer arrangement region BR.

  Further, as a power I / O buffer cell, the outer I / O having a large distance (wiring resistance) from the corresponding bonding pad to the power wiring Vw and the ground wiring Gw provided around the LSI internal circuit 200a. When the buffer cell is used, the IR drop value becomes large, and there is a possibility that the circuit design satisfying the design constraint cannot be performed.

  The present invention has been made in order to solve such problems. Regardless of the position of the bonding pad in the I / O buffer cell to be used, that is, the position of the bonding pad is close to the LSI internal circuit. High-speed or large current that can supply stable power supply voltage and input / output signals even when using O-buffer cells or using I / O buffer cells whose bonding pads are far from the LSI internal circuit An object of the present invention is to obtain a semiconductor integrated circuit capable of operating in the above and an electronic device equipped with such a semiconductor integrated circuit.

  A semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit having an internal circuit section constituting a logic circuit, and a buffer section for transferring signals between the internal circuit section and an external circuit. The unit is designed as a unit circuit having an electrode pad, the inner buffer cell in which the electrode pad is disposed in the inner region near the inner circuit unit, and the electrode pad is disposed in the outer region far from the inner circuit unit. An input / output circuit for inputting a signal or outputting a signal is formed in an intermediate region between the inner region and the outer region. Thus, the above object can be achieved.

  In the semiconductor integrated circuit, the present invention further includes a power supply wiring and a grounding wiring arranged along the periphery of the internal circuit portion, and the power supply wiring and the grounding wiring are electrode pads of the inner buffer cell. It is preferable that it is arranged in the intermediate region so as to be located between the inner region which is the arrangement region of the outer buffer cell and the outer region which is the arrangement region of the electrode pads of the outer buffer cell.

  In the semiconductor integrated circuit according to the present invention, the power supply wiring and the grounding wiring are arranged along the periphery of the internal circuit portion, and the power supply wiring and the grounding wiring are arranged in the arrangement region of the internal circuit portion. And an inner region that is an arrangement region of the electrode pads of the inner buffer cell, and is preferably disposed in a region closer to the internal circuit portion than the inner region.

  In the semiconductor integrated circuit according to the present invention, it is preferable that the power supply wiring and the ground wiring are formed by patterning a single conductive layer and are arranged adjacent to each other.

  In the semiconductor integrated circuit according to the present invention, it is preferable that the power supply wiring and the ground wiring are three-dimensionally arranged so as to overlap each other by patterning two conductive layers.

  According to the present invention, in the semiconductor integrated circuit, each of the inner buffer cell and the outer buffer cell is formed in a region below a corresponding electrode pad, and the internal circuit portion is detected from electrostatic noise applied to the electrode pad. It is preferable to have a protection circuit that protects.

  In the semiconductor integrated circuit according to the aspect of the invention, it is preferable that the input / output circuit is connected to the power supply wiring and the ground wiring so that driving power is supplied to the wiring.

  In the semiconductor integrated circuit according to the present invention, the arrangement pattern of the electrode pads of the plurality of inner buffer cells arranged in the inner region and the electrode pads of the plurality of outer buffer cells arranged in the outer region is staggered. An array pattern is preferred.

  In the semiconductor integrated circuit according to the present invention, it is preferable that the internal circuit portion is formed by arranging basic cells that are unit circuits constituting the logic circuit.

  In the semiconductor integrated circuit according to the present invention, the signal wiring from the input / output circuit of the inner buffer cell to the internal circuit section is preferably formed so as to pass through the outer buffer cell adjacent to the inner buffer cell. .

  According to the present invention, in the semiconductor integrated circuit, a wiring from the power buffer cell that supplies power to the power wiring among the plurality of inner buffer cells to the power wiring is adjacent to the power buffer cell. The outer buffer cell is preferably formed so as to pass through.

  In the semiconductor integrated circuit according to the present invention, input / output of signals to / from the internal circuit unit is all performed by the outer buffer cell, and power supply to the power supply wiring and setting of a ground potential of the ground wiring are performed. Are preferably configured to be performed by the outer buffer cell.

  An electronic apparatus according to the present invention includes the above-described semiconductor integrated circuit according to the present invention, whereby the above-described object is achieved.

  Next, the operation will be described.

  In the present invention, in a semiconductor integrated circuit, as a unit circuit of a design having an electrode pad that constitutes a buffer portion between an internal circuit portion and an external circuit, the electrode pad is disposed in an inner region near the internal circuit portion. An inner buffer cell, and an outer buffer cell in which an electrode pad is disposed in an outer region far from the inner circuit portion. The inner buffer cell and the outer buffer cell are connected to each other for input of signals or output of signals. Since the output circuit is formed in an intermediate region between the inner region and the outer region, the distance from the input / output circuit to the internal circuit portion in the inner buffer cell and the outer buffer cell is substantially equal. The difference in signal delay due to the position of the bonding pad between the inner buffer cell and the outer buffer cell can be eliminated.

  This makes it possible to perform stable signal input / output regardless of the position of the bonding pad of the buffer cell to be used, and increases the degree of freedom in designing the buffer unit using the buffer cell.

  In the present invention, the input / output circuit for inputting or outputting signals is provided between the inner region where the electrode pads of the inner buffer cells are arranged and the outer region where the electrode pads of the outer buffer cells are arranged. Therefore, it is not necessary to consider much damage under the electrode pad by wafer test probing or wire bonding when a semiconductor chip is incorporated into a package.

  According to the present invention, in the semiconductor integrated circuit, the power supply wiring and the ground wiring are arranged in an inner region that is an electrode pad arrangement region of the inner buffer cell and an outer region that is an electrode pad arrangement region of the outer buffer cell. The distance from the electrode pad to the power supply wiring and the ground wiring in the inner buffer cell and the outer buffer cell is substantially equal, and the inner buffer cell and the outer buffer cell Differences in voltage drop due to different bonding pad positions can be eliminated.

  In particular, the wiring resistance when the inner buffer cell is used is substantially the same as the wiring resistance when the outer buffer cell is used. Increase in wiring resistance can be avoided, and avoidance of large differences in signal transmission time and rise time due to differences in wiring path between when many outer buffer cells are used and when many inner buffer cells are used it can.

  Accordingly, it is possible to supply a stable power supply voltage regardless of the position of the bonding pad of the buffer cell to be used, and the degree of freedom in designing the buffer unit using the buffer cell is increased.

  In the present invention, in the inner buffer cell and the outer buffer cell, a protection circuit that protects the internal circuit portion from electrostatic noise applied to the electrode pad is disposed in a region below the corresponding electrode pad. Therefore, when electrostatic noise or the like is applied from the outside, the protection circuit immediately below the electrode pad operates immediately, and it is possible to quickly prevent adverse effects on the internal circuit part, that is, destruction of the semiconductor elements constituting the internal circuit part. it can.

  Even if there is some damage under the electrode pad during probing or wire bonding during wafer test, this protection circuit is not related to the operation of the internal circuit part. Does not affect processing.

  In the present invention, the array pattern formed by the electrode pads of the plurality of inner buffer cells arranged in the inner region and the electrode pads of the plurality of outer buffer cells arranged in the outer region is a staggered arrangement pattern. By avoiding interference between the electrode pads of the inner buffer cell and the electrode pads of the outer buffer cell, the arrangement pitch of these electrode pads can be narrowed, thereby reducing the number of electrodes arranged around the internal circuit portion. Can be increased.

  As described above, according to the present invention, in a semiconductor integrated circuit, as a unit circuit of a design having an electrode pad that constitutes a buffer unit between an internal circuit unit and an external circuit, the electrode pad is formed in the internal circuit unit. An inner buffer cell disposed in a near inner region and an outer buffer cell in which an electrode pad is disposed in an outer region far from the internal circuit portion, and the inner buffer cell and the outer buffer cell are connected to the signal input or Since the input / output circuit for outputting a signal is formed in an intermediate region between the inner region and the outer region, regardless of the position of the electrode pad in the buffer cell to be used, that is, the bonding pad Even if the inner buffer cell is located close to the internal circuit, or the outer buffer cell where the bonding pad is far from the internal circuit is used. However, it is possible to realize a semiconductor integrated circuit capable of supplying a stable power supply voltage and inputting / outputting a signal and capable of operating at a high speed or a large current and an electronic device equipped with such a semiconductor integrated circuit. it can.

FIG. 1 is a plan view for explaining a semiconductor integrated circuit (semiconductor chip) according to Embodiment 1 of the present invention, and shows a schematic configuration of an LSI chip as the semiconductor chip. FIG. 2 is a diagram showing a part (part A of FIG. 1) of the semiconductor integrated circuit (semiconductor chip) according to Embodiment 1 of the present invention. In the I / O buffer cell of the semiconductor chip and the I / O buffer cell, The positional relationship with the bonding pad is shown. FIG. 3 is a diagram showing a part of the semiconductor integrated circuit (semiconductor chip) (part A of FIG. 1) according to Embodiment 1 of the present invention, and includes a power supply wiring, a ground wiring, and a bonding pad in the I / O buffer cell. The positional relationship is shown. FIG. 4 is a view showing a part of the semiconductor integrated circuit (semiconductor chip) (part A in FIG. 1) according to the first embodiment of the present invention, and shows the bonding pad and interface circuit in the signal I / O buffer cell. The positional relationship is shown. FIG. 5 is a plan view for explaining a semiconductor integrated circuit (semiconductor chip) according to Embodiment 2 of the present invention, and shows a schematic configuration of an LSI chip as the semiconductor chip. FIG. 6 is a view showing a part of the semiconductor integrated circuit (semiconductor chip) (part A1 in FIG. 5) according to Embodiment 2 of the present invention, and includes a power supply line, a ground line, and a bonding pad in the I / O buffer cell. The positional relationship is shown. FIG. 7 is a diagram for explaining an electronic apparatus according to Embodiment 3 of the present invention. FIG. 8 is a diagram for explaining a semiconductor chip disclosed in Patent Document 1. FIG. 8A is a plan view showing a schematic configuration of the semiconductor chip. FIG. 8B is a diagram illustrating the semiconductor chip. It is sectional drawing which shows the state accommodated in the package main body. FIG. 9 is a diagram for explaining a semiconductor chip having a conventional I / O buffer cell, and is a plan view showing a schematic configuration of the semiconductor chip. FIG. 10 is a diagram showing a detailed configuration of a part (B section) of the semiconductor chip 200 shown in FIG. 9, and shows the positional relationship between the I / O buffer cells and the bonding pads. FIG. 11 is a diagram showing a detailed configuration of a part (part B) of the semiconductor chip 200 shown in FIG. 9, and shows the positional relationship between the power supply wiring and ground wiring and the bonding pads. FIG. 12 is a diagram showing a detailed configuration of a part (B section) of the semiconductor chip 200 shown in FIG. 9, and shows the positional relationship between the bonding pad and the interface circuit in the signal I / O buffer cell. .

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
1 to 4 are diagrams for explaining a semiconductor integrated circuit according to Embodiment 1 of the present invention.

  In these drawings, Cea1, Cec2, Cea3, Cec4, Cea5, Cec6, Cea7, and Cec8 are I / O buffer cells, and Pa1, Pc2, Pa3, Pc4, Pa5, Pc6, Pa7, and Pc8 are Although it is a bonding pad, for convenience of explanation, when I / O buffer cells are collectively described, it is referred to as I / O buffer cell Ce, and when outside I / O buffer cells are collectively described, outer I / O buffer cells are described. When the inner I / O buffer cells are collectively described as the buffer cell Cea, the inner I / O buffer cell Cec is used. When the bonding pads of the outer I / O buffer cell are collectively described, the bonding pad Pa is used. When collectively describing the bonding pads of the inner I / O buffer cell, the bonding pads Pc and That.

  Hereinafter, the first embodiment will be described in detail.

  FIG. 1 is a plan view for explaining a semiconductor integrated circuit according to Embodiment 1 of the present invention, and shows a schematic structure of a semiconductor chip (LSI chip) which is the semiconductor integrated circuit. FIG. 2 is a diagram showing a detailed configuration of a part (part A) of the semiconductor chip 10 shown in FIG. 1, and shows the positional relationship between the I / O buffer cells and the bonding pads.

  The semiconductor chip (LSI chip) 10 according to the first embodiment includes an internal circuit unit (LSI internal circuit) 10a in which basic cells Uc serving as units constituting a logic circuit are arranged, and the LSI internal circuit 10a and external circuits. (Not shown) and a buffer unit 10b for exchanging signals with it.

  The buffer unit 10b is a unit circuit having an electrode pad (bonding pad) to which a bonding wire is connected, that is, an I / O buffer cell Ce, and the bonding pad Pc is disposed in the vicinity of the LSI internal circuit 10a. A plurality of inner I / O buffer cells Cec, and a plurality of outer I / O buffer cells Cea in which the bonding pad Pa is located far from the LSI internal circuit 10a.

  Referring to part A of FIG. 1 (see FIG. 2), for example, the I / O buffer cells Cea1, Cec2, Cea3, Cec4, Cea5 are arranged in the buffer arrangement region BR in which these I / O buffer cells are arranged. Bonding pads Pa1, Pc2, Pa3, Pc4, Pa5, Pc6, Pa7, and Pc8 are arranged in a staggered manner for each of Cec6, Cea7, and Cec8.

  That is, the I / O buffer cells Cea1, Ceb2, Cea3, Ceb4, Cea5, Ceb6, Cea7, and Ceb8 arranged in the buffer arrangement region BR of the semiconductor chip 10 have bonding pads Pa1, Pc2, Pa3, Pc4, Pa5, Pc6, Pa7, and Pc8 are provided, and bonding pads Pa1, Pa3, Pa5, and Pa7 corresponding to the outer I / O buffer cells Cea1, Cea3, Cea5, and Cea7 are outer peripheral side portions (outside of the buffer arrangement region BR). The bonding pads Pc2, Pc4, Pc6, and Pc8 corresponding to the inner I / O buffer cells Cec2, Cec4, Cec6, and Cec8 are arranged in the inner peripheral side portion (inner region) Rc of the buffer arrangement region BR. Has been.

  Further, as shown in FIG. 1, on the intermediate portion (intermediate region) RB which is a space secured between the outer peripheral portion Ra and the inner peripheral portion Rc of the buffer arrangement region BR, the power supply wiring Vw and the ground The wiring line Gw is annularly arranged so as to surround the LSI internal circuit 10a. In FIG. 2, the power supply wiring Vw and the ground wiring Gw are not shown.

  Here, the power supply wiring Vw and the ground wiring Gw are formed by patterning a single conductive layer, and are disposed adjacent to each other. However, the power supply wiring Vw and the ground wiring Gw may be formed by patterning two conductive layers, and three-dimensionally arranged so as to overlap each other.

  FIG. 3 is a diagram showing a detailed configuration of a part (part A) of the semiconductor chip 10 shown in FIG. 1, and shows the positional relationship between the power supply wiring and ground wiring and the bonding pads.

  In this semiconductor chip 10, for example, the outer I / O buffer cell Cea1 and the inner I / O buffer cell Cec6 are power supply buffer cells, and the outer I / O buffer cell Cea3 and the inner I / O buffer cell Cec8 are ground buffers. The bonding pads Pa1 and Pc6 corresponding to the I / O buffer cells Cea1 and Cec6 are connected to the power supply wiring Vw, and the bonding pads Pa3 and Pc8 corresponding to the I / O buffer cells Cea3 and Cec8 are connected to the ground wiring Gw. It is connected to the.

  The inner I / O buffer cells Cec2 and Cec4 and the outer I / O buffer cells Cea5 and Cea7 are signal I / O buffer cells, and bonding pads Pc2, Pc4, Pa5 and Pa7 are bonding pads for passing signals between the LSI internal circuit 10a and an external circuit (not shown).

  FIG. 4 is a diagram showing a detailed configuration of a part (part A) of the semiconductor chip 10 shown in FIG. 1, and shows the positional relationship between the bonding pad and the interface circuit in the signal I / O buffer cell. . Therefore, in FIG. 4, the power supply wiring and the ground wiring are shown for convenience in explaining the connection relation of the circuit, and do not show the actual positions. The actual positions are shown in FIG. As shown in

  In this semiconductor chip 10, for example, signal I / O buffer cells Cec4 and Cea7 are output I / O buffer cells for outputting signals obtained by the LSI internal circuit 10a of the semiconductor chip 10 to an external circuit. These output I / O buffer cells Ceb4 and Cea7 have interface circuits Fc4 and Fa7 for amplifying and converting signals from the LSI internal circuit 10a, respectively. The signal I / O buffer cells Cec2 and Cea5 are input I / O buffer cells for inputting a signal from an external circuit to the LSI internal circuit 10a of the chip 10, and these input I / O buffer cells. Each of Cec2 and Cea5 has interface circuits Fc2 and Fa5 for amplifying and converting a signal input to the LSI internal circuit 10a. These interface circuits Fc2, Fc4, Fa5, and Fa7 are connected to these wirings so that driving power is supplied by the power wiring Vw and the ground wiring Gw.

  Here, the signal wiring from the interface circuits Fc2 and Fc4 of the inner I / O buffer cells Cec2 and Cec4 to the LSI internal circuit 10a passes through the outer I / O buffer cells Cea1 and Cea3 adjacent to the inner I / O buffer cell. It is supposed to be. Further, signal wirings between the bonding pads Pa5 and Pa7 of the outer I / O buffer cells Cea5 and Cea7 and the LSI internal circuit 10a are arranged in these outer I / O buffer cells. Accordingly, all the wirings between the signal I / O buffer cells and the LSI internal circuit go through the outer I / O buffer cells.

  In addition, each I / O buffer cell Cea1, Cec2, Cea3, Cec4, Cea5, Cec6, Cea7, Cec8 is electrostatically applied to the corresponding bonding pads Pa1, Pc2, Pa3, Pc4, Pa5, Pc6, Pa7, Pc8. Protection circuits Da1, Dc2, Da3, Dc4, Da5, Dc6, Da7, and Dc8 are provided to prevent the noise from destroying the LSI internal circuit 10a. The O buffer cells Cea1, Cec2, Cea3, Cec4, Cea5, Cec6, Cea7, and Cec8 are arranged in regions immediately below the bonding pads of the corresponding I / O buffer cells. These protection circuits are connected to the power supply wiring Vw and the ground wiring Gw.

  For the semiconductor chip 10 having such a configuration, like the semiconductor chip 100 shown in FIG. 8, the semiconductor chip 10 is accommodated in, for example, a package body as shown in FIG. A semiconductor package on which a semiconductor chip is mounted can be obtained by connecting to wiring and terminals and sealing with a package lid member or a sealing resin.

  At this time, the bonding pads of the semiconductor chip and the terminals of the package body are connected as follows. For example, the bonding pads Pc2, Pc4, Pa5, and Pa7 of the signal I / O buffer cells Cec2, Cec4, Cea5, and Cea7 are connected to the input / output inner lead terminals 113 of the package main body by wiring wires. In addition, one or both of the bonding pads Pa1 and Pc6 of the power supply buffer cells Cea1 and Ceb6 are connected to the common power supply ring wiring 111 by wiring wires, and the bonding pads Pa3 and Pc8 of the grounding buffer cells Cea3 and Cec8 are connected. Either or both of these are connected to the common ground ring wiring 112 by a wiring wire.

  Next, the function and effect will be described.

  In the first embodiment, in the semiconductor integrated circuit 10, a bonding pad Pc is used as a unit circuit having a bonding pad that constitutes a buffer unit 10b between an internal circuit LSI (internal circuit unit) 10a and an external circuit. An inner I / O buffer cell Cec disposed in the inner peripheral portion Rc close to the LSI internal circuit 10a and an outer I / O buffer cell in which the bonding pad Pa is disposed in the outer peripheral portion Ra far from the LSI internal circuit 10a. And an interface circuit for inputting or outputting signals between the inner peripheral portion Rc and the outer peripheral portion Ra. The inner I / O buffer cell Cec and the outer I / O buffer cell Cea are secured between the inner peripheral portion Rc and the outer peripheral portion Ra. The intermediate I / O buffer cell Cec and the intermediate I / O buffer cell Signals resulting from the fact that the distance from the interface circuit to the LSI internal circuit in each of the outer I / O buffer cells Cea is substantially the same, and the bonding pad positions are different between the inner I / O buffer cell and the outer I / O buffer cell. The difference in delay amount can be eliminated.

  Further, the power supply wiring Vw and the ground wiring Gw are arranged with the inner peripheral portion Rc, which is the arrangement area of the bonding pad Pc of the inner I / O buffer cell Cec, and the arrangement area of the bonding pad Pa, of the outer I / O buffer cell Cea. Are arranged so as to be positioned between the outer peripheral side portion Ra and the power supply wiring Vw and grounding from the respective bonding pads Pc and Pa in the inner I / O buffer cell Cec and the outer I / O buffer cell Cea. The distances to the wiring Gw are substantially equal, and the difference in voltage drop due to the bonding pad position being different between the inner I / O buffer cell Cec and the outer I / O buffer cell Cea can be eliminated.

  This makes it possible to perform stable signal input / output and supply of a stable power supply voltage regardless of the position of the bonding pad of the buffer cell to be used, and the buffer unit 10b using the I / O buffer cell Ce. Increased design freedom.

  In the present embodiment, the interface circuits Fc2, Fc4, Fa5, and Fa7 for inputting or outputting signals are divided into an inner peripheral portion Rc where the bonding pad Pc of the inner I / O buffer cell Cec is disposed, and an outer portion. Since it is disposed between the I / O buffer cell Cea and the outer peripheral side portion Ra where the bonding pad Pa is disposed, the damage under the bonding pad is less caused by probing of the wafer test or wire bonding when incorporating into the package. No need to consider.

  In the present embodiment, in the inner I / O buffer cell Cec and the outer I / O buffer cell Cea, the LSI internal circuit 10a is formed in the region below the corresponding bonding pad from the electrostatic noise applied to the bonding pad. Since a protection circuit for protecting the circuit is arranged, when electrostatic noise or the like is applied from the outside, the protection circuit immediately below the bonding pad operates immediately, and adversely affects the LSI internal circuit 10a, that is, configures the LSI internal circuit 10a. It is possible to quickly prevent the destruction of the semiconductor element to be performed.

  Even if there is some damage under the electrode pad during probing or wire bonding during the wafer test, this protection circuit is not related to the operation of the LSI internal circuit 10a. Does not affect signal processing.

  In the present embodiment, the bonding pads Pc of the plurality of inner I / O buffer cells Cec disposed in the inner peripheral portion Rc and the bonding of the plurality of outer I / O buffer cells Cea disposed in the outer peripheral portion Ra. Since the arrangement pattern formed by the pads Pa is a staggered arrangement pattern, interference between the bonding pad Pc of the inner I / O buffer cell Cec and the bonding pad Pa of the outer I / O buffer cell Cea is avoided, and the bonding is performed. The arrangement pitch of the pads can be narrowed, whereby the number of electrodes (number of bonding pads) arranged around the LSI internal circuit 10a can be increased.

  Furthermore, in the LSI chip 10 of the first embodiment, the wiring resistance when the inner I / O buffer cell Cec is used and the wiring resistance when the outer I / O buffer cell Cea are used are substantially the same. Therefore, it is possible to avoid an increase in wiring resistance in the buffer unit 10b when many outside I / O buffer cells Cea are used, and when the outside I / O buffer cells Cea are used and inside I / O buffers. It is possible to avoid the occurrence of a difference in signal transmission time and rise time due to a difference in wiring path between the case where the cell Cec is used.

  In other words, conventionally, for the power I / O buffer cell, the wiring resistance is higher when the outer I / O buffer cell is used than when the inner I / O buffer cell is used. For this reason, when many outside I / O buffer cells are used, the resistance value in the buffer section becomes large, greatly affecting the IR drop of the entire LSI chip, and circuit design that satisfies the design constraints may not be possible. It was. As for the signal I / O buffer cell, there is a difference in the wiring path between the case where the outer I / O buffer cell is used and the case where the inner I / O buffer cell is used. However, in the LSI chip of the first embodiment, such a problem is solved because there is no difference in wiring resistance even if there is a difference in the wiring path as described above.

  As described above, in the semiconductor integrated circuit (semiconductor chip) 10 according to the first embodiment, the LSI internal circuit 10a constituting the logic circuit, and the buffer unit 10b for exchanging signals between the LSI internal circuit 10a and the external circuit. As the I / O buffer cell Ce constituting the buffer unit 10b, the position of the bonding pad Pc is close to the LSI internal circuit 10a, and the position of the bonding pad Pa is the LSI internal circuit 10a. The outer I / O buffer cell Cea far from the I / O buffer cell Cec, the bonding pads Pc, Pa of the Cea are arranged in a staggered arrangement, and the bonding pad arrangement region of the inner I / O buffer cell Cec And a space between the bonding pads of the outer I / O buffer cell Cea (Intermediate region) Rb is alternately arranged so as to be secured, and in the signal I / O buffer cell, since the interface circuit with the inside is arranged in the secured space, the inner I / O buffer cell Cec and the outer I / O Even when the bonding pads Pc and Pa of the buffer cell Cea are arranged in a staggered pattern, the terminals (package body) in the LSI chip can be used without worrying about the wiring resistance difference in the wiring path from the bonding pad to the LSI internal circuit 10a. The arrangement of the electrodes and leads) can be determined.

  Therefore, even when the terminal arrangement in the LSI chip is changed, there is no need to reexamine the change in the voltage drop amount in the buffer unit, and there is an effect of preventing the development period from being unnecessarily extended.

In the first embodiment, as the semiconductor integrated circuit, the power supply wiring Vw and the ground wiring Gw are arranged in the intermediate portion Rb in the buffer arrangement region BG. However, the power supply wiring Vw and the ground wiring Gw are shown. May be arranged between the buffer arrangement region BG and the LSI internal circuit 10a, and a semiconductor integrated circuit (LSI chip) having such a configuration will be described below as a second embodiment.
(Embodiment 2)
FIG. 5 is a plan view for explaining a semiconductor integrated circuit (semiconductor chip) according to Embodiment 2 of the present invention, and shows a schematic configuration of an LSI chip as the semiconductor chip.

  FIG. 6 is a view showing a part of the semiconductor integrated circuit (semiconductor chip) (part A1 in FIG. 5) according to Embodiment 2 of the present invention, and includes a power supply line, a ground line, and a bonding pad in the I / O buffer cell. The positional relationship is shown.

  In the semiconductor integrated circuit (LSI chip) 20 according to the second embodiment, the power supply wiring Vw and the ground wiring Gw in the semiconductor integrated circuit (LSI chip) 10 according to the first embodiment are arranged in the intermediate portion Rb in the buffer arrangement region BR. Instead of the configuration described above, the power supply wiring Vw and the grounding wiring Gw are provided between the buffer arrangement region BR and the arrangement region CR of the LSI internal circuit 10a. The outer I / O buffer cell Cea1 and the inner I / O buffer cell Cec2 are power I / O buffer cells, and the outer I / O buffer cell Cea7 and the inner I / O buffer cell Cec8 are ground I / O buffer cells. Yes.

  Accordingly, the bonding pad Pa1 of the outer I / O buffer cell Cea1 is connected to the power supply wiring Vw by the I / O buffer cell Cea1, and the bonding pad Pc2 of the inner I / O buffer cell Cec2 is connected to the outer I / O buffer cell Cec1. It is connected to the power supply wiring Vw via the O buffer cell Cea1.

  The bonding pad Pa7 of the outer I / O buffer cell Cea7 is connected to the ground wiring Gw by the I / O buffer cell Cea7, and the bonding pad Pc8 of the inner I / O buffer cell Cec8 is connected to the outer I / O buffer cell Cec7. It is connected to the ground wiring Gw via the O buffer cell Cea7.

  In the semiconductor integrated circuit (LSI chip) 20 of the second embodiment, the outer I / O buffer cells Cea3 and Cea5 and the inner I / O buffer cells Cec4 and Cec6 are signal I / O buffer cells. However, the interface circuit is not shown in FIG.

  As described above, in the second embodiment, power is supplied from the power I / O buffer cell to the power supply wiring Vw as shown in FIG. 6, as is the power supply from the inner I / O buffer cell Cec2. The power supply from the O buffer cell Cea1 is also performed via the outer I / O buffer cell.

  Other configurations of the semiconductor integrated circuit (LSI chip) 20 according to the second embodiment are the same as those of the semiconductor integrated circuit (LSI chip) 10 according to the first embodiment.

  Also in the second embodiment having such a configuration, the distances from the bonding pads to the power supply wiring Vw and the ground wiring Gw in the inner I / O buffer cell Cec and the outer I / O buffer cell Cea are substantially equal, It is possible to eliminate the difference in the amount of voltage drop caused by the bonding pad position being different between the I / O buffer cell Cec and the outer I / O buffer cell Cea.

Further, although not specifically described in the first and second embodiments, the semiconductor integrated circuit (LSI chip) of the first and second embodiments includes an electronic information device such as a mobile phone or a computer, and a microcomputer. The third embodiment will be described as an electronic device in which the semiconductor integrated circuit according to the first embodiment or the second embodiment is mounted as a semiconductor integrated circuit used in an electronic device such as a home appliance.
(Embodiment 3)
FIG. 7 is a diagram for explaining an electronic apparatus according to Embodiment 3 of the present invention.

  The electronic device 90 according to the third embodiment shown in FIG. 7 has at least one of the LSI chips 10 and 20 according to the first and second embodiments of the present invention mounted on at least one of the following components constituting the electronic device 90. It is a thing.

  Here, the electronic device 90 includes an input operation unit 90a for inputting information by the operator, a memory unit 92 such as a recording medium for recording the input information input from the input operation unit 90a, and the input information as liquid crystal. A display unit 93 such as a liquid crystal display device that is displayed on a display screen such as a display screen, a communication unit 94 such as a transmission / reception device that performs communication processing using the input information, and prints and outputs the input information. It has at least one of the image output part 95 to (print out).

  In addition, the electronic information device 90 may include an imaging unit 91 that captures an image of a subject. In this case, a memory unit 92 such as a recording medium records image data obtained by the imaging unit 91 for recording. Data is recorded after predetermined signal processing, and the display unit 93 performs predetermined signal processing for display on the image data and displays it on a display screen such as a liquid crystal display screen. Then, after performing predetermined signal processing for communication on the image data, communication processing is performed on the image data, and the image output unit 95 prints (prints) and outputs (prints out) the image data. May be.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention includes a semiconductor having an I / O buffer cell including an active circuit and bonding pads as a unit design circuit constituting a buffer section of an LSI internal circuit, and the bonding pads of the I / O buffer cells being arranged in a staggered arrangement. In the field of integrated circuits and electronic devices equipped with such semiconductor integrated circuits, stable power supply voltage supply and signal input / output are possible regardless of the position of the bonding pad used, that is, the I / O buffer cell used. Therefore, it is possible to realize a semiconductor integrated circuit that is required to operate at a high speed or with a large current and an electronic device equipped with such a semiconductor integrated circuit.

10, 20 Semiconductor integrated circuit (LSI chip)
10a LSI internal circuit 10b Buffer unit 90 Electronic information device 91 Imaging unit 92 Memory unit 93 Display unit 94 Communication unit 95 Image output unit BR buffer arrangement area Ce I / O buffer cells Cea, Cea1, Cea3, Cea5, Cea7 Outer I / O Buffer cell Cec, Cec2, Cec4, Cec6, Cec8 Inside I / O buffer cell CR Internal circuit layout area Da1, Db2, Da3, Db4, Da5, Db6, Da7, Db8 protection circuit Fa5, Fa7, Fb2, Fb4 interface circuit (input Output circuit)
Gw Grounding wiring Pa, Pb, Pa1, Pb2, Pa3, Pb4, Pa5, Pb6, Pa7, Pb8 Bonding pads (electrode pads)
Ra Outer peripheral part (outer area)
Rb middle part (middle region)
Rc Inner peripheral part (inner area)
Uc Basic cell Vw Power supply wiring

Claims (13)

A semiconductor integrated circuit having an internal circuit part constituting a logic circuit and a buffer part for transferring a signal between the internal circuit part and an external circuit,
The buffer unit is designed as a unit circuit having an electrode pad, an inner buffer cell in which the electrode pad is disposed in an inner region near the internal circuit unit, and an outer region in which the electrode pad is far from the internal circuit unit. An outer buffer cell being disposed,
The inner buffer cell and the outer buffer cell are configured such that an input / output circuit for inputting or outputting a signal is formed in an intermediate region between the inner region and the outer region. circuit. The semiconductor integrated circuit according to claim 1,
Power supply wiring and grounding wiring arranged along the periphery of the internal circuit section,
The power supply wiring and the grounding wiring are:
A semiconductor integrated circuit disposed in the intermediate region so as to be positioned between an inner region that is an electrode pad region of the inner buffer cell and an outer region that is an electrode pad region of the outer buffer cell. circuit. The semiconductor integrated circuit according to claim 1,
Power supply wiring and grounding wiring arranged along the periphery of the internal circuit section,
The power supply wiring and the grounding wiring are:
Semiconductor integrated circuit disposed in a region closer to the internal circuit portion than the inner region so as to be positioned between the inner circuit region and the inner region that is the electrode pad arrangement region of the inner buffer cell circuit. The semiconductor integrated circuit according to claim 2 or claim 3,
The power supply wiring and the ground wiring are formed by patterning a single conductive layer, and are disposed adjacent to each other. The semiconductor integrated circuit according to claim 2 or claim 3,
The power supply wiring and the ground wiring are formed by patterning two conductive layers, and are three-dimensionally arranged so as to overlap each other. The semiconductor integrated circuit according to any one of claims 1 to 5,
Each of the inner buffer cell and the outer buffer cell is formed in a region below the corresponding electrode pad, and includes a protection circuit that protects the internal circuit portion from electrostatic noise applied to the electrode pad. circuit. The semiconductor integrated circuit according to any one of claims 2 to 6,
The input / output circuit is a semiconductor integrated circuit connected to these wirings so that driving power is supplied by the power wiring and the ground wiring. The semiconductor integrated circuit according to any one of claims 1 to 7,
A semiconductor integrated circuit in which an arrangement pattern of electrode pads of a plurality of inner buffer cells arranged in the inner area and an electrode pad of a plurality of outer buffer cells arranged in the outer area is a staggered arrangement pattern . The semiconductor integrated circuit according to any one of claims 1 to 8,
The internal circuit unit is a semiconductor integrated circuit formed by arranging basic cells that are unit circuits constituting the logic circuit. The semiconductor integrated circuit according to any one of claims 1 to 8,
The signal wiring from the input / output circuit of the inner buffer cell to the internal circuit unit is formed so as to pass through the outer buffer cell adjacent to the inner buffer cell. The semiconductor integrated circuit according to claim 3,
Of the plurality of inner buffer cells, the wiring from the power supply buffer cell that supplies power to the power supply wiring to the power supply wiring is formed so as to pass through the outer buffer cell adjacent to the power supply buffer cell. A semiconductor integrated circuit. The semiconductor integrated circuit according to any one of claims 1 to 9 and claim 11,
Input / output of signals to / from the internal circuit unit is all performed by the outer buffer cell,
A semiconductor integrated circuit configured such that the supply of power to the power wiring and the setting of the ground potential of the ground wiring are all performed by the outer buffer cell.   An electronic apparatus comprising the semiconductor integrated circuit according to any one of claims 1 to 12.

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