JP2013158140A - Semiconductor device - Google Patents

Abstract

A conventional switching power supply circuit has a problem that output current capability is reduced at a high temperature.
A semiconductor device including a duty control circuit for generating a switching control signal for controlling the switching element in a voltage conversion circuit for controlling the switching element to convert an input voltage to generate an output voltage. The duty control circuit 2 detects that the output voltage Vout has fallen below the target voltage, and switches the output voltage detection circuit 11 to enable the gating signal CMPOUT and the gating signal CMPOUT in the enable state. An on-time control circuit 10 that outputs a control signal PFMOUT, and the on-time control circuit 10 increases the pulse width of the switching control signal so that the pulse width of the switching control signal PFMOUT increases as the environmental temperature increases. to correct.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device, for example, a semiconductor device including a circuit that generates a switching control signal for controlling a conduction state of a switching element of a power supply circuit.

  A switching power supply circuit is often used as a power supply circuit for supplying power to other circuits. The switching power supply circuit switches on and off of the switching element by a pulse signal, and controls the voltage by controlling the switching timing and the on-time of the switching element. Therefore, the switching power supply circuit has an advantage of high power efficiency.

  An example of this switching power supply circuit is disclosed in Patent Documents 1 and 2. The DC-DC converter disclosed in Patent Document 1 generates a pulse signal that controls the conduction state of a switching element based on a clock signal whose frequency changes according to the output voltage of the DC-DC converter, and the pulse signal The pulse width is linked to a change in at least one of the input voltage and the output voltage. Patent Document 2 relates to a switching power supply device and lowers the switching frequency when the temperature of the switching element is high.

JP 2008-29159 A JP 2008-259309 A

  A switching power supply circuit generally has a switching element, a backflow prevention diode, an inductor, and a smoothing capacitor as an output stage circuit. The switching element and the backflow prevention diode are connected in series between an input terminal to which an input voltage is input and a ground terminal. One end of the inductor is connected to a node between the switching element and the backflow prevention diode. The smoothing capacitor is connected between the other end of the inductor and the ground terminal. The switching power supply circuit outputs an output voltage from a node between the inductor and the smoothing capacitor.

  Here, in the backflow prevention diode, a leak current flows from the cathode side (terminal on the switching element side) toward the anode side (terminal on the ground terminal side). This leakage current has a characteristic that it increases as the temperature of the backflow prevention diode increases. That is, in the switching power supply circuit, when the environmental temperature such as the temperature of the backflow prevention diode increases, the amount of charge charged in the smoothing capacitor decreases due to the leak current flowing through the backflow prevention diode. As a result, the switching power supply circuit has a problem that the output current capability decreases at high temperatures. In Patent Documents 1 and 2, since the output current capability cannot be improved when the environmental temperature becomes high, the above problem cannot be solved.

  A semiconductor device according to an embodiment includes a duty control circuit that generates a switching control signal for controlling the switching element in a voltage conversion circuit that controls the switching element to convert an input voltage to generate an output voltage. A semiconductor device, wherein the duty control circuit detects that the output voltage has fallen below a target voltage and enables a gating signal, and a period in which the gating signal is in an enabled state An on-time control circuit that outputs the switching control signal, and the on-time control circuit is configured to output the switching control signal so that a pulse width of the switching control signal increases as the environmental temperature increases. Correct the pulse width.

  According to the semiconductor device according to the embodiment, the on-time control circuit corrects the pulse width of the switching control signal so that the pulse width of the switching control signal increases as the environmental temperature increases. Thereby, the semiconductor device according to the embodiment can prevent the output current capability from being lowered by increasing the amount of current output from the switching element when the environmental temperature becomes high.

  According to the semiconductor device according to one embodiment, it is possible to prevent a decrease in output current capability at a high temperature in the switching power supply circuit.

1 is a block diagram of a switching power supply circuit according to a first embodiment; 3 is a block diagram of an on-time control circuit according to the first exemplary embodiment; FIG. FIG. 3 is a block diagram of an adjustment current source according to the first exemplary embodiment. 3 is a timing chart illustrating an operation at a high temperature of the on-time control circuit according to the first embodiment; 3 is a timing chart showing an operation at a low temperature of the on-time control circuit according to the first exemplary embodiment; 3 is a timing chart showing an operation of the switching power supply circuit according to the first exemplary embodiment; It is a graph which shows the temperature characteristic of the leakage current of a backflow prevention diode. 3 is a graph showing output characteristics of the switching power supply circuit according to the first exemplary embodiment; FIG. 6 is a block diagram of an on-time control circuit according to a second exemplary embodiment. FIG. 6 is a block diagram of an on-time control circuit according to a third exemplary embodiment. FIG. 6 is a block diagram of an on-time control circuit according to a fourth exemplary embodiment. FIG. 10 is a block diagram of an on-time control circuit according to a fifth embodiment; 10 is a timing chart showing an operation during normal operation of the on-time control circuit according to the fifth embodiment; FIG. 10 is a timing chart illustrating an operation of the on-time control circuit according to the fifth embodiment when abnormal heat is generated.

Embodiment 1
Hereinafter, embodiments will be described with reference to the drawings. First, in the semiconductor device 1 according to the first embodiment, the pulse width of the switching control signal for switching the switching element is varied according to the environmental temperature. The environmental temperature is a temperature inside the device on which the semiconductor device 1 is mounted, a temperature of an element mounted on the mounting substrate together with the semiconductor device 1, a temperature of a semiconductor substrate constituting the semiconductor device 1, and the like. It is the temperature of the element and board | substrate regarding the voltage conversion circuit containing this.

  FIG. 1 is a block diagram of a voltage conversion circuit (for example, a switching power supply circuit) according to the first embodiment. As shown in FIG. 1, the switching power supply circuit according to the first embodiment includes a semiconductor device 1 and an output stage circuit PWC. This switching power supply circuit controls the switching element SWTr of the output stage circuit PWC to convert the voltage of the input voltage Vin to generate the output voltage Vout. The switching power supply circuit according to the first embodiment applies the output voltage Vout generated in the output stage circuit PWC to the load circuit LD. Further, the switching power supply circuit according to the first embodiment drives a switching element by a PFM (Pulse Frequency Modulation) method.

  The semiconductor device 1 includes a duty control circuit 2 that generates a switching control signal for controlling the switching element. The output stage circuit PWC includes a switching element SWTr, a backflow prevention diode D1, an inductor L1, and a smoothing capacitor C1. The switching element SWTr and the backflow prevention diode D1 are connected in series between an input terminal to which the input voltage Vin is input and a ground terminal to which the ground voltage GND is supplied. One end of the inductor L1 is connected to a node between the switching element SWTr and the backflow prevention diode D1. The smoothing capacitor C1 is connected between the other end of the inductor L1 and the ground terminal. The switching power supply circuit outputs the output voltage Vout from a node between the inductor L1 and the smoothing capacitor C1. Here, the switching element SWTr is formed of, for example, an NMOS transistor. Further, the switching element SWTr can be formed on the semiconductor substrate of the semiconductor device 1. In this case, the switching element SWTr of the output stage circuit PWC is built in the semiconductor device 1.

  The duty control circuit 2 includes an on-time control circuit 10 and an output voltage detection circuit 11. The output voltage detection circuit 11 detects that the output voltage Vout has fallen below the target voltage (for example, the reference voltage VREF), and enables the gating signal CMPOUT (for example, high level). In the example shown in FIG. 1, the output voltage detection circuit 11 is configured by a hysteresis comparator CMP0. The hysteresis comparator CMP0 sets the reference voltage VREF as the target lower limit voltage VREFL, and sets a voltage higher than the reference voltage VREF as the target upper limit voltage VREFH. The hysteresis comparator CMP0 enables the gating signal CMPOUT in response to the output voltage Vout falling below the target lower limit voltage VREFL, and the gating signal CMPOUT in response to the output voltage Vout exceeding the target upper limit voltage VREFH. Is disabled. Thereby, in the semiconductor device 1, the fluctuation range of the output voltage Vout is maintained within a predetermined range.

  The semiconductor device 1 has external terminals TM0 and TM1. Then, the semiconductor device 1 outputs the switching control signal PFMOUT through the external terminal TM0, and acquires the output voltage Vout through the external terminal TM1.

  The on-time control circuit 10 outputs the switching control signal PFMOUT during a period in which the gating signal CMPOUT is enabled. In addition, the on-time control circuit 10 corrects the pulse width of the switching control signal PFMOUT so that the pulse width of the switching control signal PFMOUT increases as the environmental temperature increases. The on-time control circuit 10 acquires information on the environmental temperature based on the temperature information TI acquired from the external or internal temperature detection element. The on-time control circuit 10 controls the pulse width of the switching control signal PFMOUT so as to follow at least one of the input voltage Vin and the output voltage Vout. Therefore, a specific configuration of the on-time control circuit 10 will be described below.

  FIG. 2 shows a detailed block diagram of the on-time control circuit 10. As shown in FIG. 2, the on-time control circuit 10 includes a pulse width correction circuit 20 and a control pulse generation circuit 21. The pulse width correction circuit 20 generates a temperature correction current Itemp that increases as the environmental temperature increases. The control pulse generation circuit 21 includes a first current source (for example, an adjustment current source 22) that generates a first pulse width setting current IREF0 that sets the pulse width of the switching control signal PFMOUT before correction. The on-time control circuit 10 determines the pulse width of the switching control signal PFMOUT in accordance with the magnitude of the second pulse width setting current IREF1 obtained by correcting the first pulse width setting current IREF0 with the temperature correction current Itemp.

  Further, the on-time control circuit 10 gives information related to the environmental temperature (for example, temperature information TI) to the pulse width correction circuit 20. The on-time control circuit 10 acquires temperature information TI from a temperature detection element provided on a mounting substrate on which the semiconductor device 1 is mounted. In the example shown in FIG. 2, the temperature detection diode D21 is shown as the temperature detection element. The temperature detection diode D21 simulates the temperature characteristics of the leakage current of the backflow prevention diode D1 of the switching power supply circuit. The pulse width correction circuit 20 of the on-time control circuit 10 acquires the leak current Iti flowing through the temperature detection diode D21 as temperature information TI. The pulse width correction circuit 20 gives the output voltage Vout of the switching power supply circuit to the external terminal TM2. Thereby, the voltage value of the output voltage Vout is reflected in the voltage difference between the cathode terminal and the anode terminal of the temperature detection diode D21, and the fluctuation of the leakage current of the backflow prevention diode D1 according to the magnitude of the output voltage Vout is reflected. Leak current Iti can be generated.

  The circuit configuration of the on-time control circuit 10 shown in FIG. It is an embodiment for realizing the above characteristics. In the example shown in FIG. 2, the pulse width correction circuit 20 includes an error amplifier AMP1, PMOS transistors MP21 and MP22, NMOS transistors MN21 and MN22, and an external terminal TM2.

  The inverting input terminal of the error amplifier AMP1 is supplied with the output voltage Vout as the reference voltage Vref1. The non-inverting input terminal of the error amplifier AMP1 is connected to a node connecting the external terminal TM2 and the drain of the PMOS transistor MP21. The output terminal of the error amplifier AMP1 is connected to the gate of the PMOS transistor MP21. The source of the PMOS transistor MP21 is connected to a power supply terminal to which the power supply voltage VDD is supplied. That is, the error amplifier AMP1 and the PMOS transistor MP21 constitute a regulator circuit, and supplies the output voltage Vout to the external terminal TM2 in a state where the leakage current Iti flows through the PMOS transistor MP21.

  The source of the PMOS transistor MP22 is connected to a power supply terminal to which the power supply voltage VDD is supplied. The gate of the PMOS transistor MP22 is connected to the output terminal of the error amplifier AMP1. The source of the PMOS transistor MP22 is connected to the drain of the NMOS transistor MN21. That is, the PMOS transistor MP22 forms a current mirror circuit with the PMOS transistor MP21, and outputs a current I21 corresponding to the leakage current Iti. For example, when the transistor size of the PMOS transistor MP21 and the transistor size of the PMOS transistor MP22 are set to the same value, the current I21 is the same as the leakage current Iti. Here, the transistor size is a value determined by the ratio between the gate width and the gate length of the transistor.

  The source of the NMOS transistor MN21 is connected to the ground terminal. The gate of the NMOS transistor MN21 is connected to the drain. The source of the NMOS transistor MN22 is connected to the ground terminal. The gate of the NMOS transistor MN22 is connected in common with the gate of the NMOS transistor MN21. That is, the NMOS transistors MN21 and MN22 form a current mirror, and output a current corresponding to the current I21 input to the drain of the NMOS transistor MN21 from the drain of the NMOS transistor MN22 as the temperature correction current Itemp. For example, when the transistor size of the NMOS transistor MN21 and the transistor size of the NMOS transistor MN22 are the same, the current I21 and the temperature correction current Itemp have the same current amount. The drain of the NMOS transistor MN22 is connected to a node to which the adjustment current source 22 of the control pulse generation circuit 21 and the drain of the NMOS transistor MN23 are connected.

  The control pulse generation circuit 21 includes a first current source (for example, an adjustment current source 22), AND circuits 23 and 24, a comparator CMP1, NMOS transistors MN23 to MN25, a PMOS transistor MP23, and a capacitor C21.

  The adjustment current source 22 generates a first pulse width setting current IREF0 that sets the pulse width of the switching control signal PFMOUT before correction. Then, the control pulse generation circuit 21 determines the pulse width of the switching control signal FPMOUT according to the magnitude of the second pulse width setting current IREF1 obtained by correcting the first pulse width setting current IREF0 with the temperature correction current Itemp. The adjustment current source 22 receives the input voltage Vin and the output voltage Vout. The adjustment current source 22 increases the first pulse width setting current IREF0 in accordance with the increase of the input voltage Vin. In addition, the adjustment current source 22 decreases the first pulse width setting current IREF0 in accordance with the increase in the output voltage Vout.

  A detailed circuit diagram of the adjustment current source 22 is shown in FIG. As shown in FIG. 3, the adjustment current source 22 includes NMOS transistors MN31 to MN34, PMOS transistors MP31 and MP32, and resistors R32 and R33.

  The source of the NMOS transistor MN31 is connected to the ground terminal. The gate of the NMOS transistor MN31 is connected to the drain of the NMOS transistor MN31. The drain of the NMOS transistor MN31 is connected to a terminal to which an input voltage Vin is applied via a resistor R31. The source of the NMOS transistor MN32 is connected to the ground terminal. The gate of the NMOS transistor MN32 is commonly connected to the gate of the NMOS transistor MN31. The drain of the NMOS transistor MN32 is connected to the drain of the PMOS transistor MP31.

  That is, the NMOS transistors MN31 and MN32 constitute a current mirror circuit. A current I31 having a value obtained by dividing a voltage value obtained by subtracting the threshold voltage of the NMOS transistor MN31 from the input voltage Vin by the resistance value of the resistor R31 is input to the drain of the NMOS transistor MN31. That is, the current I31 has a current amount proportional to the magnitude of the input voltage Vin. In the current mirror circuit, the current I32 corresponding to the current I31 is output from the NMOS transistor MN32. Specifically, the ratio of the current value of the current I32 to the current I31 is determined in accordance with the transistor size ratio between the NMOS transistor MN31 and the NMOS transistor MN32. When the transistor size ratio of the NMOS transistors MN31 and MN32 is 1: 1, the current values of the currents I31 and I32 are approximately equal.

  The source of the NMOS transistor MN33 is connected to the ground terminal. The gate of the NMOS transistor MN33 is connected to the drain of the NMOS transistor MN33. The drain of the NMOS transistor MN33 is connected to a terminal to which an output voltage Vout is applied via a resistor R32. The source of the NMOS transistor MN34 is connected to the ground terminal. The gate of the NMOS transistor MN34 is commonly connected to the gate of the NMOS transistor MN33. The drain of the NMOS transistor MN34 is connected to the drain of the PMOS transistor MP32.

  That is, the NMOS transistors MN33 and MN34 constitute a current mirror circuit. A current I33 having a value obtained by dividing a voltage value obtained by subtracting the threshold voltage of the NMOS transistor MN33 from the output voltage Vout by the resistance value of the resistor R32 is input to the drain of the NMOS transistor MN33. That is, the current I34 has a current amount proportional to the magnitude of the output voltage Vout. In the current mirror circuit, the current I34 corresponding to the current I33 is output from the NMOS transistor MN34. Specifically, the ratio of the current value of the current I34 to the current I33 is determined according to the transistor size ratio between the NMOS transistor MN33 and the NMOS transistor MN34. When the transistor size ratio of the NMOS transistors MN33 and MN34 is 1: 1, the current values of the currents I33 and I34 are approximately equal.

  The source of the PMOS transistor MP31 is connected to the power supply terminal. The gate of the PMOS transistor MP31 is connected to the drain of the PMOS transistor MP31. The drain of the PMOS transistor MP31 is connected to the drain of the NMOS transistor MN32. The source of the PMOS transistor MP32 is connected to the power supply terminal. The gate of the PMOS transistor MN32 is commonly connected to the gate of the PMOS transistor MP31. The drain of the PMOS transistor MP32 serves as the output terminal of the adjustment current source 22.

  That is, the PMOS transistors MP31 and MP32 constitute a current mirror circuit. In the current mirror circuit, a current I35 corresponding to the current I32 is output from the drain of the NMOS transistor MP32. Specifically, the current value of the current I35 relative to the current I32 is determined according to the transistor size ratio between the PMOS transistor MP31 and the PMOS transistor MP32. When the transistor size ratio of the PMOS transistors MP31 and MP32 is 1: 1, the current values of the currents I32 and I35 are substantially equal. The drain of the NMOS transistor MN34 is connected to the drain of the PMOS transistor MP31. That is, the current I35 and the current I34 are combined at the drain of the PMOS transistor MP32. This combined current becomes the first pulse width setting current IREF0, and the current value is a value obtained by subtracting the current I34 from the current I35. That is, the first pulse width setting current IREF0 includes a component that increases when the input voltage Vin increases and decreases when the output voltage Vout increases.

  Next, the configuration of the control pulse generation circuit 21 other than the adjustment current source 22 will be described. The source of the NMOS transistor MN23 is connected to the ground terminal. The gate of the NMOS transistor MN23 is connected to the drain of the NMOS transistor MN23. The drain of the NMOS transistor MN23 is connected to the drain of the PMOS transistor MP31 of the adjustment current source 22. Here, the drain of the NMOS transistor MN22 of the pulse width correction circuit 20 is connected to a node to which the drain of the NMOS transistor MN23 and the adjustment current source 22 are connected. Then, at the node, a second pulse width setting current IREF1 obtained by combining the first pulse width setting current IREF0 and the temperature correction current Itemp is generated. Specifically, the second pulse width setting current IREF1 has a current value obtained by subtracting the temperature correction current Itemp from the first pulse width setting current IREF0. That is, in the semiconductor device 1 according to the first embodiment, the second pulse width setting current obtained by correcting the first pulse width setting current with the temperature correction current is generated at the node. The gate of the NMOS transistor MN24 is commonly connected to the gate of the NMOS transistor MN23. The drain of the NMOS transistor MN24 is connected to the source of the NMOS transistor MN25.

  That is, the NMOS transistors MN23 and MN24 constitute a current mirror circuit. The second pulse width setting current IREF1 is input to the drain of the NMOS transistor MN23. In the current mirror circuit, the current I22 corresponding to the second pulse width setting current IREF1 is output from the NMOS transistor MN24. Specifically, the ratio of the current value of the current I22 to the second pulse width setting current IREF1 is determined according to the transistor size ratio between the NMOS transistor MN23 and the NMOS transistor MN24. When the transistor size ratio of the NMOS transistors MN23 and MN24 is 1: 1, the current values of the second pulse width setting current IREF1 and the current I22 are approximately equal.

  The source of the NMOS transistor MN25 is connected to the drain of the NMOS transistor MN24. The drain of the NMOS transistor MN25 is connected to the drain of the PMOS transistor MP24. The drain of the PMOS transistor MP23 is connected to the power supply terminal. The gate of the NMOS transistor MN25 and the gate of the PMOS transistor MP23 are connected to each other. The clock signal CLK is input to the gate of the NMOS transistor MN25 and the gate of the PMOS transistor MP23. A node connecting the drain of the NMOS transistor MN25 and the drain of the PMOS transistor MP23 is connected to the non-inverting input terminal of the comparator CMP1. A capacitor C21 is connected between the node connecting the drain of the NMOS transistor MN25 and the drain of the PMOS transistor MP23 and the ground terminal.

  A signal output from a node connecting the drain of the NMOS transistor MN25 and the drain of the PMOS transistor MP23 is hereinafter referred to as a duty control voltage CLKDLY. The duty control voltage CLKDLY is at a high level (for example, the power supply voltage VDD) while the clock signal CLK is at a low level, and is a time constant determined by the current I22 and the capacitance value of the capacitor C21 when the clock signal CLK is at a high level. As the voltage level decreases.

  In the comparator CMP1, the duty control voltage CLKDLY is input to the non-inverting input terminal, and the reference voltage Vref2 is input to the inverting input terminal. The reference voltage Vref2 is a constant voltage having a stable voltage value against temperature fluctuations and power supply voltage fluctuations, and is generated by a constant voltage source (not shown). The comparator CMP1 compares the voltage level of the duty control voltage CLKDLY with the reference voltage Vref2, and switches the logic level of the digital output signal DOUT. Specifically, the comparator CMP1 sets the digital output signal DOUT to a high level during a period in which the voltage level of the duty control voltage CLKDLY is higher than the reference voltage Vref2. On the other hand, the comparator CMP1 sets the digital output signal DOUT to a low level during a period in which the voltage level of the duty control voltage CLKDLY is lower than the reference voltage Vref2.

  The AND circuit 23 gates the digital output signal DOUT with the clock signal CLK. Hereinafter, a signal output from the AND circuit 23 is referred to as a PFM clock signal PFMCLK. The PFM clock signal PFMCLK is at a low level when the clock signal CLK is at a low level, and is at a logic level according to the logic level of the digital output signal DOUT when the clock signal CLK is at a high level. The AND circuit 24 gates the PFM clock signal PFMCLK by the gating signal CMPOUT. The signal output from the AND circuit 24 is the switching control signal PFMOUT. Specifically, the PFM clock signal PFMCLK is output as the switching control signal PFMOUT while the gating signal CMPOUT is in an enabled state (for example, high level). A low level signal is output as the switching control signal PFMOUT while the gating signal CMPOUT is disabled (for example, low level).

  Subsequently, the operation of the on-time control circuit 10 will be described. First, the PFM clock signal PFMCLK generated by the control pulse generation circuit 21 of the on-time control circuit 10 will be described.

  FIG. 4 is a timing chart showing the operation at a high temperature of the on-time control circuit 10 according to the first embodiment. As shown in FIG. 4, in the on-time control circuit 10, when the clock signal CLK rises at the timing T10, the voltage level of the duty control voltage CLKDLY starts decreasing accordingly. At timing T11, when the voltage level of the duty control voltage CLKDLY falls below the reference voltage Vref2, the digital output signal DOUT falls. Thereafter, when the clock signal CLK falls at the timing T12, the duty control voltage CLKDLY is reset to a high level accordingly.

  The PFM clock signal PFMCLK is at a low level while the clock signal CLK is at a low level. The PFM clock signal PFMCLK is at a high level when the clock signal CLK is at a high level while the digital output signal DOUT is at a high level, and is at a low level when the digital output signal DOUT is at a low level.

  FIG. 5 is a timing chart showing the operation at low temperature of the on-time control circuit 10 according to the first embodiment. As shown in FIG. 5, when the temperature is low, the operation is practically the same as that when the temperature is high. Therefore, the pulse width of the PFM clock signal PFMCLK is smaller at low temperatures than at high temperatures.

  The leakage current Iti given to the on-time control circuit 10 as temperature information TI increases as the temperature increases. Therefore, the on-time control circuit 10 has a feature that the temperature correction current Itemp increases as the environmental temperature increases, and the second pulse width setting current IREF1 decreases. Therefore, in the on-time control circuit 10, the magnitude of the current I22 that draws charges from the capacitor C21 during a period when the clock signal CLK is at a high level decreases at a high temperature, and the pulse width of the PFM clock signal PFMCLK at a high temperature increases.

  Next, the switching control signal PFMOUT generated by the on-time control circuit 10 will be described. FIG. 6 is a timing chart showing the operation of the switching power supply circuit according to the first embodiment. As shown in FIG. 6, in the switching power supply circuit according to the first embodiment, the output voltage detection circuit 11 enables the gating signal CMPOUT in response to the output voltage Vout falling below the target lower limit voltage VREFL (for example, , T31, T33, T35). The gating signal CMPOUT is switched to a disabled state in response to the output voltage Vout exceeding the target upper limit voltage VREFH (for example, timings T32 and T34).

  The on-time control circuit 10 supplies the PFM clock signal PFMCLK to the switching element SWTr while the gating signal CMPOUT is enabled, and maintains the switching element SWTr in the off state when the gating signal CMPOUT is disabled. To do. In the switching power supply circuit according to the first embodiment, the frequency at which the state of the gating signal CMPOUT switches (for example, the length of the periods TE1 and TE2) changes according to the magnitude of the load current flowing through the load circuit LD.

  Next, a change in operating characteristics due to temperature of the switching power supply circuit according to the first embodiment will be described. First, FIG. 7 shows a graph showing the temperature characteristics of the leakage current of the backflow prevention diode D1 of the output stage circuit PWC.

  As shown in FIG. 7, the backflow prevention diode D1 has a characteristic that the leakage current increases as the junction temperature (for example, the temperature of the semiconductor substrate) becomes higher. This increase in leakage current increases exponentially with respect to temperature fluctuations.

  Next, FIG. 8 shows output characteristics of the switching power supply circuit according to the first embodiment. The output characteristics shown in FIG. 8 indicate the output current capability of the switching power supply circuit at high temperature and low temperature. In FIG. 8, the load current Iload increases with time. In the switching power supply circuit according to the first embodiment, the output current capability IH at the high temperature is higher than the output current capability IL at the low temperature.

  When the pulse width of the PFM clock signal PFMCLK is maintained constant regardless of the environmental temperature without using the on-time control circuit 10 according to the first embodiment, as shown in FIG. 7, the leakage current flowing through the backflow prevention diode D1 Increases, and the ability of the switching power supply circuit to output the load current Iload decreases. However, as shown in FIG. 8, in the semiconductor device 1 according to the first embodiment, the output current capability of the switching power supply circuit increases at a high temperature.

  As described above, in the semiconductor device 1 according to the first embodiment, the on-time control circuit 10 corrects the pulse width so that the pulse width of the switching control signal for controlling the switching element is increased according to the environmental temperature. . Thereby, in the switching power supply circuit including the semiconductor device 1, even if the leakage current of the backflow prevention diode D1 increases at a high temperature, it is possible to prevent a decrease in output current capability due to the increased leakage current.

  Further, according to the semiconductor device 1 according to the first embodiment, even when a protection operation is performed in response to an increase in the temperature of the operating environment of the switching power supply circuit, it is normal without causing a shortage of output current capability. The operation can be continued.

  Further, in the semiconductor device 1 according to the first embodiment, when the input voltage Vin increases or when the output voltage Vout decreases, the pulse width of the switching control signal PFMOUT can be reduced according to the fluctuation of the voltage. it can. Thus, the semiconductor device 1 can generate the switching control signal PFMOUT having a pulse width that matches the magnitude of the input voltage Vin or the output voltage Vout.

Embodiment 2
In the second embodiment, an on-time control circuit 10a which is another form of the on-time control circuit 10 will be described. A block diagram of the on-time control circuit 10a is shown in FIG. As illustrated in FIG. 9, the on-time control circuit 10 a according to the second embodiment includes a pulse width correction circuit 40 that is another form of the pulse width correction circuit 20. In the description of the second embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and the description thereof is omitted.

  The pulse width correction circuit 40 has a temperature detection diode D41 formed on a semiconductor substrate on which the semiconductor device 1 is formed as a temperature detection element. The temperature detection diode D41 generates a forward voltage (for example, a diode voltage Vtemp) of the temperature detection diode D41 as the temperature information TI. The diode voltage Vtemp has a feature that the voltage value decreases as the substrate temperature rises. The pulse width correction circuit 40 includes an error amplifier AMP2, PMOS transistors MP41 and MP42, a resistor R41, and a second current source (for example, a current source IS41).

  The cathode of the temperature detection diode D41 is connected to the ground terminal. A current source IS41 is connected between the anode of the temperature detection diode D41 and the power supply terminal. The current source IS41 flows a current I41 having a stable current value against power supply voltage fluctuations and temperature fluctuations. This current I41 is applied to the temperature detection diode D41. Then, the temperature detection diode D41 generates the diode voltage Vtemp when the current I41 flows.

  The temperature information TI is supplied as the reference voltage Vref1 to the inverting input terminal of the error amplifier AMP1. In the on-time control circuit 10a according to the second embodiment, the temperature information TI is the diode voltage Vtemp generated by the temperature detection diode D41. The non-inverting input terminal of the error amplifier AMP2 is connected to one end of the resistor R41 and the drain of the PMOS transistor MP41. The output terminal of the error amplifier AMP2 is connected to the gate of the PMOS transistor MP41. The source of the PMOS transistor MP41 is connected to a power supply terminal to which the power supply voltage VDD is supplied. The other end of the resistor R41 is connected to the ground terminal. That is, the error amplifier AMP2 and the PMOS transistor MP41 constitute a regulator circuit, and the diode voltage Vtemp is given to the resistor R41, and the current I42 calculated by dividing the voltage value of the diode voltage Vtemp by the resistor R41 is supplied to the PMOS transistor MP41. Shed. That is, the amount of current I42 changes in proportion to the temperature fluctuation of the diode voltage Vtemp.

  The source of the PMOS transistor MP42 is connected to a power supply terminal to which the power supply voltage VDD is supplied. The gate of the PMOS transistor MP42 is connected to the output terminal of the error amplifier AMP2. The drain of the PMOS transistor MP42 is connected to a node to which the adjustment current source 22 of the control pulse generation circuit 21 and the drain of the NMOS transistor MN23 are connected. That is, the PMOS transistor MP42 forms a current mirror circuit with the PMOS transistor MP41, and outputs a current Itemp corresponding to the current I42. For example, when the transistor size of the PMOS transistor MP41 and the transistor size of the PMOS transistor MP42 are set to the same value, the current Itemp is the same as the current I41. Here, the transistor size is a value determined by the ratio between the gate width and the gate length of the transistor.

  In addition, the control pulse generation circuit 21 according to the second embodiment generates the second pulse width setting current IREF1 by adding a current obtained by adding the temperature correction current Itemp to the first pulse width setting current IREF0. That is, also in the second embodiment, the second pulse width setting current IREF1 includes a temperature fluctuation component that decreases as the environmental temperature rises, like the second pulse width setting current IREF1 according to the first embodiment. . In the control pulse generation circuit 21 according to the second embodiment, the pulse width of the PFM clock signal PFMCLK is varied based on the second pulse width setting current IREF1. At this time, the control pulse generation circuit 21 according to the second embodiment generates the PFM clock signal PFMCLK by the same operation as the control pulse generation circuit 21 according to the first embodiment.

  From the above description, in the second embodiment, the diode voltage Vtemp of the temperature detection diode D41 formed on the semiconductor substrate on which the semiconductor device 1 is formed is used as temperature information. Thereby, in the semiconductor device 1 according to the second embodiment, since it is not necessary to provide the external terminal TM2, the package size and chip size of the semiconductor device can be made smaller than those of the semiconductor device according to the first embodiment.

Embodiment 3
In the third embodiment, an on-time control circuit 10b which is another form of the on-time control circuit 10a will be described. A block diagram of the on-time control circuit 10b is shown in FIG. As illustrated in FIG. 10, the on-time control circuit 10 b according to the third embodiment includes a pulse width correction circuit 50 that is another form of the pulse width correction circuit 40. In the description of the third embodiment, the same components as those described in the first and second embodiments are denoted by the same reference numerals as those in the first and second embodiments, and the description thereof is omitted.

  As shown in FIG. 10, the pulse width correction circuit 50 uses a thermistor R51 as a temperature detection element instead of the temperature detection diode D41. The thermistor R51 is provided on the mounting substrate, and the resistance value varies depending on the temperature. More specifically, the thermistor R51 has a resistance value that decreases as the temperature increases. The thermistor R51 is connected to the pulse width correction circuit 50 via the external terminal TM3. In the thermistor R51 and the pulse width correction circuit 50, the voltage Vtemp generated by flowing the current I41 through the thermistor R51 is used as the reference voltage Vref1.

  From the above description, in the third embodiment, the thermistor R51 is used as the temperature detection element. The thermistor R51 is an element that can be installed in various places. Therefore, by using the thermistor R51, for example, the temperature of the backflow prevention diode D1 can be directly monitored, and the monitoring result can be reflected in the voltage Vtemp. Then, by causing the voltage Vtemp to accurately follow the temperature of the backflow prevention diode D1, the switching power supply circuit including the semiconductor device according to the third embodiment can further improve the temperature followability of the output current capability.

Embodiment 4
In the fourth embodiment, an on-time control circuit 10c, which is another form of the on-time control circuit 10, will be described. A block diagram of the on-time control circuit 10c is shown in FIG. As shown in FIG. 11, the on-time control circuit 10 c according to the fourth embodiment is obtained by replacing the current mirror circuit configured by the NMOS transistors MN <b> 23 and MN <b> 24 in the control pulse generation circuit 21 with a pulse width correction circuit 60. . In the description of the fourth embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and description thereof is omitted.

  The pulse width correction circuit 60 generates a second pulse width setting current IREF1 that increases or decreases in response to the environmental temperature changing up and down from the first pulse width setting current IREF0. The pulse width correction circuit 60 includes a first transistor (for example, NMOS transistor MN61) and a second transistor (for example, NMOS transistor MN62). The first pulse width setting current is input to the drain of the NMOS transistor MN61. The NMOS transistor MN62 constitutes a current mirror circuit together with the NMOS transistor MN61, and differs from the NMOS transistor MN61 in the transistor size determined by the ratio between the gate width and the gate length, and outputs the second pulse width setting current IREF1. In the example shown in FIG. 11, the transistor size ratio of the NMOS transistors MN61 and MN62 is N: M.

  As described above, when the current mirror circuit is configured by transistors having different transistor sizes, the second pulse width setting current IREF1 can be reduced as the temperature of the semiconductor substrate increases. That is, by using the pulse width correction circuit 60, the second pulse width setting current IREF1 whose current value decreases as the semiconductor substrate rises can be generated as in the first embodiment. Further, the on-time control circuit 10c can generate the switching control signal PFMOUT whose pulse width becomes smaller as the semiconductor substrate rises in accordance with the second pulse width setting current IREF1.

  From the above description, the on-time control circuit 10 c according to the third embodiment uses the part corresponding to the current mirror circuit configured by the NMOS transistors MN 23 and MN 24 of the control pulse generation circuit 21 as the pulse width correction circuit 60. Thus, the on-time control circuit 10c according to the third embodiment can configure the pulse width correction circuit 60 without using an error amplifier or the like, and thus is smaller than the on-time control circuit 10 according to the first embodiment. Similar functions can be realized with a circuit scale.

Embodiment 5
In the fifth embodiment, an on-time control circuit 10d which is another form of the on-time control circuit 10 will be described. A block diagram of the on-time control circuit 10d is shown in FIG. As illustrated in FIG. 12, the on-time control circuit 10 d according to the fifth embodiment includes a control pulse generation circuit 70 in which a one-shot pulse signal 71 is added to the control pulse generation circuit 21. In the description of the fifth embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and the description thereof is omitted.

  The one-shot pulse signal 71 generates a pulse signal PCLK having a pulse width smaller than that of the clock signal CLK every time a pulse of the clock signal CLK is input. The on-time control circuit 10d controls the pulse width of the switching control signal PFMOUT with the pulse width of the pulse signal PCLK as the maximum pulse width regardless of the environmental temperature.

  In the on-time control circuit 10d, the pulse signal PCLK is input to the NMOS transistor MN25, the PMOS transistor MP23, and the AND circuit 23.

  Therefore, the operation of the on-time control circuit 10d will be described. FIG. 13 is a timing chart showing an operation during normal operation of the on-time control circuit according to the fifth embodiment. As shown in FIG. 13, the one-shot pulse signal 71 generates a pulse signal PCLK having a pulse width PW2 smaller than the pulse width PW1, where the pulse width of the clock signal CLK is PW1. During normal operation, the on-time control circuit 10d generates a PFM clock signal PFMCLK having a pulse width corresponding to the time constant of the duty control voltage CLKDLY (timing T41).

  FIG. 14 is a timing chart showing the operation of the on-time control circuit according to the fifth embodiment at the time of abnormal heat generation. As shown in FIG. 14, when the abnormal heat generation occurs, the temperature correction current Itemp increases and the second pulse width setting current IREF1 that decreases the voltage level of the duty control voltage CLKDLY decreases. Therefore, the duty control voltage CLKDLY does not fall below the reference voltage Vref2 during the period when the clock signal CLK is at the high level. However, in the on-time control circuit 10d according to the second embodiment, the digital output signal DOUT is gated by the pulse signal PCLK. Therefore, in the on-time control circuit 10d, the pulse width of the PFM clock signal PFMCLK is limited to the same width as the pulse width PW2 of the pulse signal PCLK regardless of the environmental temperature (timing T51).

  From the above description, according to the on-time control circuit 10d according to the second embodiment, the maximum value of the pulse width of the switching control signal PFMOUT is limited by the pulse width of the pulse signal PCLK generated by the one-shot pulse signal 71. As a result, abnormal heat generation can be prevented and the pulse width of the switching control signal PFMOUT can be prevented from becoming larger than expected, and failure due to heat generation of the switching element SWTr can be prevented.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Duty control circuit 10, 10a, 10b, 10c, 10d ON time control circuit 11 Output voltage detection circuit 20, 40, 50, 60 Pulse width correction circuit 21, 70 Control pulse generation circuit 22 Adjustment current source 23, 24 AND circuit 71 One shot pulse signal IS41 Current source CMP0 Hysteresis comparator AMP1, AMP2 Error amplifier CMP1 Comparator PWC Output stage circuit SWTr Switching element D1 Backflow prevention diode D21, D41 Temperature detection diode L1 Inductor C1 Smoothing capacitor C21 Capacitor R31, R32, R41 Resistor R51 thermistor IREF0 first pulse width setting current IREF1 second pulse width setting current Itemp temperature correction current VREF reference voltage CMPOUT gate Ingu signal PFMOUT switching control signals Vref1, Vref2 reference voltage Vin input voltage Vout output voltage CLK reference clock signal CLKDLY duty control voltage DOUT digital output signal PFMCLK PFM clock signal PCLK pulse signal LD load VREFL target lower limit voltage VREFH target upper limit voltage

Claims (12)

A semiconductor device including a duty control circuit that generates a switching control signal that controls the switching element in a voltage conversion circuit that controls the switching element to convert an input voltage to generate an output voltage,
The duty control circuit includes:
An output voltage detection circuit for detecting that the output voltage has fallen below a target voltage and enabling a gating signal;
An on-time control circuit that outputs the switching control signal during a period in which the gating signal is enabled,
The on-time control circuit is a semiconductor device that corrects the pulse width of the switching control signal so that the pulse width of the switching control signal increases as the environmental temperature increases. The on-time control circuit includes:
A control pulse generation circuit comprising a first current source for generating a first pulse width setting current for setting a pulse width of the switching control signal before correction;
A pulse width correction circuit that generates a temperature correction current that increases as the environmental temperature increases, and
The control pulse generation circuit determines a pulse width of the switching control signal according to a magnitude of a second pulse width setting current obtained by correcting the first pulse width setting current with the temperature correction current. The semiconductor device described.   3. The semiconductor device according to claim 2, wherein the control pulse generation circuit generates the second pulse width setting current by adding or subtracting the temperature correction current with respect to the first pulse width setting current.   4. The semiconductor device according to claim 3, wherein the first current source increases the first pulse width setting current in accordance with a voltage variation of at least one of an increase in the input voltage and a decrease in the output voltage.   5. The semiconductor device according to claim 2, wherein the on-time control circuit acquires information related to the environmental temperature from a temperature detection element provided on a mounting substrate on which the semiconductor device is mounted. The temperature detection element is a temperature detection diode that artificially reproduces the temperature characteristic of the leakage current of the backflow prevention diode of the voltage conversion circuit,
The semiconductor device according to claim 5, wherein the on-time control circuit acquires a leakage current flowing through the temperature detection diode as information related to the environmental temperature, and increases or decreases the temperature correction current based on the acquired information. The temperature detection element is a thermistor provided on the mounting substrate, the resistance value of which varies with temperature.
The on-time control circuit relates to a voltage generated based on a current generated by a second current source formed on a semiconductor substrate on which the on-time control circuit is formed and a resistance value of the thermistor. The semiconductor device according to claim 5, acquired as information, and increasing or decreasing the temperature correction current based on the acquired information.   The on-time control circuit acquires a forward voltage of a diode formed on a semiconductor substrate on which the on-time control circuit is formed as information on the environmental temperature, and increases or decreases the temperature correction current based on the acquired information. The semiconductor device according to claim 2. The on-time control circuit includes:
A control pulse generation circuit comprising a first current source for generating a first pulse width setting current for setting a pulse width of the switching control signal before correction;
A pulse width correction circuit that generates a second pulse width setting current that increases or decreases in response to the environmental temperature fluctuating up and down from the first pulse width setting current;
The semiconductor device according to claim 1, wherein the control pulse generation circuit determines a pulse width of the switching control signal in accordance with a magnitude of the second pulse width setting current. The pulse width correction circuit includes:
A first transistor to which the first pulse width setting current is input;
A current mirror circuit is formed together with the first transistor, and a transistor size determined by a ratio of a gate width to a gate length is different from the first transistor, and a second transistor that outputs the second pulse width setting current ,
The semiconductor device according to claim 9.   The semiconductor device according to claim 1, wherein the on-time control circuit includes a pulse width limiting circuit that limits a maximum value of a pulse width of the switching control signal. The pulse width limiting circuit is
A one-shot pulse signal that generates a pulse signal having a pulse width smaller than the pulse width of the clock signal each time a clock signal pulse is input;
The semiconductor device according to claim 11, wherein the pulse width of the switching control signal is controlled using the pulse width of the pulse signal as a maximum pulse width regardless of the environmental temperature.

Images