JP2013157932A - Imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an imaging apparatus capable of imaging a subject at high speed and with high precision.SOLUTION: A control circuit of the imaging apparatus determines video signal intensity, repeats operations of fifth to ninth periods without turning on a reset switch Sw 2 when the video signal intensity is less than a predetermined value, and stops electric charge accumulation to a capacitor from a photodiode PD and performs the operations of the fifth to ninth periods when the video signal intensity is a predetermined value or larger, to output the video signal from a differential amplifier. The imaging apparatus is equipped with two-stage memories M3 to M6, which remove a noise component in a differential amplifier AMP 2. When the video signal intensity is less than a predetermined value, the reset switch is turned on again and the operations of the fifth periods and later are performed without resetting an integration circuit ITG, thereby achieving a highly precise imaging while shortening time required for electric charge accumulation.

Description

  The present invention relates to an imaging device including a photodiode array.

  Conventionally, several control methods are known in an imaging apparatus including a photodiode array.

  In the imaging device described in Patent Document 1, a connection switch is provided between a photodiode and an integration circuit, and the switch is turned off after the charge accumulation operation in the integration circuit is completed.

  Furthermore, in the imaging apparatus described in Patent Document 2, a connection switch is provided between the photodiode and the integration circuit, and the connection switch is disconnected when the output from the integration circuit is excessive. This prevents excess charge from flowing into the integrating circuit.

  In addition, in the imaging device described in Patent Document 3, a configuration (AE: automatic exposure) is shown in which a mechanical shutter is automatically closed when the exposure amount of a photodiode reaches a predetermined value in a digital camera. .

Japanese Patent Laid-Open No. 6-178046 JP 11-252305 A JP 2000-78484 A

  However, in recent years, an imaging apparatus that can perform imaging at higher speed and higher accuracy than the prior art is expected. In particular, high-speed and high-precision imaging devices are expected to be applied to various fields such as electronic information devices such as printers and scanners, mobile tracking devices, and industrial inspection devices.

  The present invention has been made in view of such a problem, and an object thereof is to provide an imaging apparatus capable of performing high-speed and high-accuracy imaging.

  In order to solve the above-described problem, an imaging apparatus according to the present invention is an imaging apparatus having a plurality of aligned pixels, wherein each of the pixels includes a photodiode, a capacitor connected between input / output terminals of an amplifier, and the pixel An integration circuit having a reset switch for short-circuiting the capacitor; a first noise memory connected to the output terminal of the integration circuit via a first transfer switch; and a first noise memory connected to the first noise memory via a second transfer switch. A second noise memory; a first signal memory connected to the output terminal of the integrating circuit via a third transfer switch; and a second signal memory connected to the first signal memory via a fourth transfer switch. A differential amplifier that outputs a difference between outputs of the second noise memory and the second signal memory, and a video signal output from the differential amplifier, And a, and a control circuit for controlling the charge accumulation period of the serial capacitors.

  Here, the control circuit executes the period of the following states (1) to (9) in order so that the reset switch, the first transfer switch, the second transfer switch, and the third transfer switch And the fourth transfer switch.

(1) A first period in an initial state in which the reset switch, the first transfer switch, the second transfer switch, the third transfer switch, and the fourth transfer switch are OFF.
(2) A second period in which the reset switch and the first transfer switch are turned on and the output terminal of the integrating circuit is connected to the first noise memory.
(3) A third period in which the first transfer switch is turned off before the reset switch is turned off.
(4) A fourth period in which the reset switch is turned off and electric charge is accumulated in the capacitor from the photodiode.
(5) A fifth period in which the third transfer switch and the fourth transfer switch are turned on, and the output terminal of the integration circuit is connected to the second signal memory via the first signal memory.
(6) A sixth period in which the third transfer switch and the fourth transfer switch are turned off.
(7) A seventh period in which the second transfer switch is turned on to transfer the data stored in the first noise memory to the second noise memory.
(8) An eighth period in which the second transfer switch is turned off.
(9) A ninth period in which a video signal is output from the differential amplifier.

  The control circuit determines the magnitude of the video signal. If the magnitude of the video signal is less than a predetermined value, the control circuit does not turn on the reset switch and the fifth period to the ninth period. When the magnitude of the video signal is equal to or greater than the predetermined value, the accumulation of charge from the photodiode to the capacitor is stopped, and the operation from the fifth period to the ninth period is performed. The video signal is output from the differential amplifier.

  According to the image pickup apparatus of the present invention, by providing a two-stage memory, when the magnitude of the video signal is less than a predetermined value while removing the noise component by the differential amplifier, the reset switch is turned on again. Then, since the operation after the fifth period is executed without resetting the integration circuit, it is possible to perform high-accuracy imaging while shortening the time required for charge accumulation.

  According to the imaging apparatus of the present invention, high-speed and high-accuracy imaging can be performed.

FIG. 1 is a block diagram of an imaging apparatus according to an embodiment (FIG. 1A) and a block diagram of a displacement sensor using the imaging apparatus (FIG. 1B). FIG. 2 is a block diagram of an exposure time control circuit (FIG. 2A) and a table (FIG. 2B) showing a relationship between input / output and control output. FIG. 3 is a block diagram (FIG. 3A) showing a circuit configuration around one pixel and a table (FIG. 3B) showing ON / OFF states of each switch. It is a timing chart of each switch. FIG. 5 is a diagram showing an example of a square wave generation circuit (FIG. 5A), and an example of a square wave generation element (FIG. 5B).

  Hereinafter, the imaging apparatus according to the embodiment will be described. In addition, the same code | symbol is used for the same element and the overlapping description is abbreviate | omitted.

  FIG. 1 is a block diagram (FIG. 1A) of an imaging apparatus according to the embodiment and a block diagram (FIG. 1B) of a displacement sensor using the imaging apparatus.

  As shown in FIG. 1A, the imaging device 1 is a line sensor, and includes a plurality of pixels P (1) to P (N) arranged in a one-dimensional manner (N is 2 or more). Integer). These pixel groups can be arranged two-dimensionally. Signals from the pixels P (1) to P (N) are sequentially read out via the switch Sw9 and the amplifier AMP3. The output of the switch Sw9 is output as a video signal to the outside of the imaging device 1 via the amplifier AMP3. This video signal is A / D converted as necessary.

  Each switch Sw9 is sequentially turned on in synchronization with the charge transfer instruction signal from the shift register 1S. The shift register 1S receives a clock signal CLK and a start signal or trigger signal Trig that instructs the start of charge transfer. When the trigger signal Trig is input, the shift register 1S sequentially turns on the transfer switch Sw9 for each pixel arranged in a one-dimensional manner to start charge transfer. As the shift register 1S, a MOS shift register can be used. The clock signal determines the operation timing in the shift register 1S.

  The exposure time (integrated value of a plurality of charge accumulation times) in each pixel P (1) to P (N) is controlled by the exposure time control circuit 1E. The exposure time control circuit 1E can be incorporated in the imaging device 1 as an imaging chip, but can also be incorporated in another device, for example, a control computer. A video signal is input to the exposure time control device 1E. An exposure time for each pixel is set according to the input video signal. The exposure time control circuit 1E functions as a control circuit that controls the switch group of the imaging apparatus together with the shift register 1S.

  The exposure time control circuit 1E receives a clock signal CLK used for exposure time measurement and the like, and a trigger signal Trig for informing the timing at the time of signal reading. When the magnitude (intensity) of the video signal is less than a predetermined value, the exposure time control circuit 1E lengthens the exposure time (integrated value of a plurality of charge accumulation times), and when the video signal is greater than the predetermined value, Accumulation of charge from the photodiode in the pixel to the capacitor C1 (see FIG. 3A) of the integration circuit is stopped. This exposure time can be performed by turning on / off a switch in each pixel.

  As shown in FIG. 1B, the displacement sensor includes the above-described imaging device 1, the light projecting device 2, and the control device 3 that controls them, and determines the distance to the object to be measured OBJ. It can be measured. When scanning the irradiation position on the object OBJ, a set of distance information, that is, surface irregularities can be obtained. When the trigger signal Trig is input from the control device 3 to the light projecting device 2, the light projecting device 2 emits light toward the object OBJ. The wavelength of this light is selected according to the sensitivity wavelength region of the pixel in the imaging device 1. For example, when the pixel is made of Si, infrared rays can be used as the emitted light. The light projecting device 2 also receives the clock signal CLK, and the light projection time can be determined by counting the input clock signal CLK. Since the clock signal CLK is a pulse signal, pulse light can be emitted by supplying a driving current synchronized with the pulse signal to a light emitting element (laser diode or light emitting diode) in the light projecting device 2.

  The trigger signal for light emission input to the light projecting device 2 and the clock signal CLK are also input to the imaging device 1. This is to synchronize the light projecting operation and the imaging operation. When light is emitted from the light projecting device 2 to the object OBJ, the irradiated light is reflected on the surface of the object. The reflected light is incident on the pixel group in the imaging device 1. In this case, the incident position (spot) of the reflected light within the pixel group corresponds to the distance (displacement) to the object OBJ based on the principle of triangulation. That is, when there is an incident light peak in the pixel group, the position corresponds to the distance from the light projecting device 2 to the object OBJ. The imaging device 1 includes a condenser lens that condenses the reflected light on the pixel group. Since a video signal is output from the imaging apparatus 1, the video signal may be input to a processing circuit such as a computer to determine the incident position. Therefore, such a system can also be used as a displacement sensor.

  FIG. 2 is a block diagram (FIG. 2A) of the exposure time control circuit according to the first embodiment, and a chart (FIG. 2B) showing the relationship between input / output and control output.

  The video signal (Vout) is output from the amplifier AMP3 (see FIG. 1) in the imaging apparatus 1, and this video signal (Vout) is fed back to the exposure time control circuit 1E. The exposure time control circuit 1E adjusts the exposure time (charge accumulation time) based on the determination circuit 1Ea that determines the magnitude of the output (video signal (Vout)) of the integration circuit ITG in the imaging device 1, and the output of the determination circuit 1Ea. An exposure time adjusting circuit 1Eb for generating a control output to be generated, and a square wave generating circuit 1Ec for generating a square wave for controlling various switches based on the control output.

  The determination circuit 1Ea includes a comparator COMP1. In the comparator COMP1, a voltage Vlow having a predetermined value, which is a lower limit value, is input to the inverting input terminal (−), and a video signal (Vout) is input to the non-inverting input terminal (+), and an output 1 is generated.

  As shown in the upper column of FIG. 2B, when the magnitude of the input video signal (Vout) is equal to or higher than the lower limit value Vlow, that is, when the input voltage is appropriate, the output 1 of the comparator COMP1 is H The exposure time adjustment circuit 1Eb generates a control output that prompts the end of the exposure time.

  As shown in the lower column of FIG. 2B, when the input video signal (Vout) is lower than the lower limit value Vlow, that is, when the input voltage is too low, the output 1 and output 2 of the comparator COMP1 are L (low level), and the exposure time adjustment circuit 1Eb generates a control output that prompts the exposure time to be extended.

  Here, the video signal whose size is determined includes an integrated output from each of the pixels P (1) to P (N) transferred in time series. It is possible to control the switch in the pixel with the integral output corresponding to each pixel as a reference, and to individually control the exposure time in each pixel, but here, the average value or the integrated value of the entire pixel output is used. Based on this, the exposure time of all pixels is controlled simultaneously.

  That is, the video signal whose size is determined is an integrated value for one frame of the integrated output from each pixel P (1) to P (N) transferred in time series, and the switches in all the pixels are simultaneously set. And control the exposure time in all pixels simultaneously.

  Although the output video signal is determined by the determination circuit 1Ea, the exposure time adjustment circuit 1Eb feedback-controls the pixel exposure time ((integrated value of a plurality of charge accumulation times) based on the determination result of the determination circuit 1Ea. Here, the exposure time (the integrated value of the charge accumulation time in the integration circuit) is a plurality of charge accumulations from when the reset switch Sw2 (see FIG. 3) is turned OFF until the exposure is completed. This exposure is terminated by stopping the flow of charge from the photodiode to the capacitor C1 of the integration circuit, as a specific example, the integration circuit and the photodiode PD. The connection switch Sw1 between the two is turned off.

  When the determination circuit 1Ea determines that the video signal (Vout), which is the output of the integration circuit, is smaller than the lower limit value Vlow, the exposure time adjustment circuit 1Eb outputs to increase the number of extension of the charge accumulation period, that is, Then, an instruction signal for prohibiting the end of exposure (inhibiting turning off of the connection switch Sw1 (see FIG. 3)) is input to the square wave generating circuit 1Ec, whereby the square wave generating circuit 1Ec is prohibited from completing the exposure. In the state, a square wave is generated so that the next charge accumulation operation is repeated, and the generated square wave is input to the corresponding switch. When the video signal is equal to or higher than the lower limit value Vlow, the end of exposure is not prohibited, so that the connection switch Sw1 is turned OFF and the exposure ends.

  As described above, the exposure time control circuit 1E controls the total number of charges in the integration circuit by controlling the number of extension of the non-destructive charge accumulation period based on the video signal periodically read based on the output of the integration circuit. The accumulation period is controlled.

  Next, control of the number of times of accumulation (extended number) of the charge accumulation period will be described.

  FIG. 3 is a block diagram (FIG. 3A) showing a circuit configuration around one pixel according to the embodiment, and a chart (FIG. 3B) showing ON / OFF states of each switch according to the embodiment. is there.

  As shown in FIG. 3A, each pixel P included in the imaging device described above includes a photodiode PD, an integration circuit ITG including an amplifier AMP1, an input terminal of the integration circuit ITG, and a cathode of the photodiode PD. And a switch Sw1 for connecting the two. The anode of the photodiode PD is grounded.

  The pixel P includes a first noise memory M3 connected to the output terminal of the integration circuit ITG via the first transfer switch Sw3, and a second noise memory connected to the first noise memory M3 via the second transfer switch Sw5. M5, a first signal memory M4 connected to the output terminal of the integration circuit ITG via a third transfer switch Sw4, and a second signal memory M6 connected to the first signal memory M4 via a fourth transfer switch Sw6. And the differential amplifier AMP2 that outputs the difference between the outputs of the second noise memory M5 and the second signal memory M6, and the video signal output from the differential amplifier AMP2 to control the charge accumulation period in the capacitor C1. A control circuit (exposure time control circuit and shift register (see FIG. 2)) is provided.

  The integration circuit ITG is connected in parallel with the capacitor C1 interposed between the input terminal and the output terminal of the amplifier AMP1 and the capacitor C1, and similarly reset between the input terminal and the output terminal of the amplifier AMP1. And a switch Sw2. The reset switch Sw2 can short-circuit the capacitor C1.

  A differential amplifier AMP2 is connected to the output terminals of the subsequent stage noise memory M5 and signal memory M6 via transfer switches Sw7 and Sw8, and an output terminal of the differential amplifier AMP2 is connected to a video signal read switch Sw9. An output amplifier AMP3 is connected. A parasitic capacitor Cpd is connected to the photodiode PD in parallel with the ground.

  Here, in order to store electric charge in the capacitor C1 of the integration circuit ITG, (1) the reset switch Sw2 is opened (OFF), and (2) the connection switch Sw1 is connected (ON). (Hereinafter, charge accumulation conditions). When these two conditions are satisfied, charge is accumulated in the capacitor C1 of the integration circuit ITG. On the other hand, in order to stop the charge accumulation operation in the capacitor C1 of the integration circuit ITG, one or both of the above two conditions (1) and (2) may not be satisfied.

  FIG. 3B illustrates control of each switch from time t1 to t11 and control from time tA to tI. FIG. 4 is a timing chart of each switch according to the embodiment.

  Here, the control circuit executes the connection periods Sw1, the reset switch Sw2, the first transfer switch Sw3, and the second transfer switch so as to sequentially execute the periods T1 to T10 in the following states (1) to (10). Sw5, the third transfer switch Sw4, the fourth transfer switch Sw6, and the other transfer switches Sw6 to Sw9 are controlled.

  (First Period T1) The first period T1 defined by the times t1 to t2 includes the reset switch Sw2, the first transfer switch M3, the second transfer switch M5, the third transfer switch Sw4, and the fourth transfer switch Sw6. This is a period of an initial state in which all the switches Sw1 to Sw9 are OFF. In the first period T1, only one charge accumulation condition (the above condition (1)) is satisfied, but since not all the charge accumulation conditions are satisfied, no charge is accumulated.

  (Second period T2) In the second period T2 defined by the times t2 to t3, the connection switch Sw1, the reset switch Sw2, and the first transfer switch Sw3 are turned on, and the output terminal of the integration circuit ITG is connected to the first noise memory M3. This is a period for connection, and the other switches Sw4 to Sw9 are OFF. In the second period T2, only one charge accumulation condition (the above condition (2)) is satisfied, but since not all the charge accumulation conditions are satisfied, no charge is accumulated. When the reset switch Sw2 is turned on, the charge accumulated in the capacitor C1 is reset, and when the connection switch Sw1 is turned on, preparation for charge accumulation is completed.

  (Third period T3) A third period T3 defined by times t3 to t4 is a period in which the first transfer switch Sw3 is turned off before the reset switch Sw2 is turned off. In the third period T2, only one charge accumulation condition (the above condition (2)) is satisfied, but since not all the charge accumulation conditions are satisfied, no charge is accumulated.

  (Fourth Period T4) The fourth period T4 defined by times t4 to t5 is a period in which the reset switch Sw4 is turned off and electric charges are accumulated from the photodiode PD to the capacitor C1. This time t4 is the exposure start time (charge accumulation start time). The charge generated by the incidence of light on the photodiode PF is accumulated in the capacitor C1 through the connection switch Sw1. In the second period T4, since both charge accumulation conditions (the above conditions (1) and (2)) are satisfied, charges are accumulated. Thereafter, charge accumulation is performed until one of the conditions is not satisfied.

  (Fifth Period T5) In the fifth period T5 defined by the times t5 to t6, the third transfer switch Sw4 and the fourth transfer switch Sw6 are turned on, and the output terminal of the integration circuit ITG is connected to the first signal memory M4. Through the second signal memory M6. This time t6 is the first charge accumulation period end time.

  (Sixth period T6) A sixth period T6 defined by times t6 to t7 is a period in which the third transfer switch Sw4 and the fourth transfer switch Sw6 are turned off.

  (Seventh Period T7) In a seventh period T7 defined by times t7 to t8, the second transfer switch Sw5 is turned on to transfer the data stored in the first noise memory M3 to the second noise memory M5. It is a period.

  (Eighth period T8) An eighth period T8 defined by times t8 to t9 is a period in which the second transfer switch Sw5 is turned off.

  (9th period T9) 9th period T9 prescribed | regulated by the time t9-t10 is a period which outputs a video signal from differential amplifier AMP2. That is, the transfer switches Sw7, Sw8, and Sw9 are turned on, and the video signal is output from the output amplifier AMP3.

  (Tenth period T10) A tenth period T10 defined by times t10 to t11 is a period in which the transfer switches Sw7, Sw8, and Sw9 are turned off and the switches Sw2 to Sw9 other than the connection switch Sw1 are turned off.

  Referring to the timing chart of FIG. 4, in the second period T2, the noise component generated when the reset switch Sw2 is turned from OFF to ON is accumulated in the first noise memory M3. Further, a period from time t4 to time t5 including the fourth period T4 is a first charge accumulation period (integration period) Integr1. The charge (data) accumulated in the capacitor C1 during this period is stored (transferred) in the second signal memory M5. Subsequently, by turning on the transfer switch Sw5, the data stored in the first noise memory M3 is transferred to the second noise memory M5, and in the subsequent ninth period (time t9 to t10) T9, The difference is read out as a video signal (Video). When 256 photodiodes are arranged one-dimensionally, 256-channel signals are sequentially read out in time series within the ninth period T9.

  Here, a determination is made as to whether the size of the video signal is sufficient. The control circuit determines the magnitude of the video signal, and if the magnitude of the video signal is less than a predetermined value (Vlow), the fifth switch from the fifth period T5 to the ninth period T9 (without turning on the reset switch Sw2). The operation from time t5 to time t10) is repeated. That is, after the time t10, the fifth period T5 to the ninth period T9 correspond to the times t11 to 16 in FIG. In this case, the entire charge accumulation period (integration period) is a period (Integ2) from time t4 to time t12. This time t12 is the end time of the second charge accumulation period.

  The second integration period Ineg2 is set to k times (k = 2) the first integration period integ1. Similarly, if the size of the video signal is not sufficient even after the second integration period 2, the charge accumulation time is further extended. The third integration period integ4 is from time t4 to time tA. This time tA is the end time of the third charge accumulation period. The third integration period Ineg3 is set to 2 × k times (four times) the first integration period integ1. By increasing the charge accumulation time in a geometric sequence, the number of processes on the circuit until the video signal reaches a target level or more can be reduced.

  When the magnitude of the video signal is equal to or greater than a predetermined value (Vlow), the accumulation of charges from the photodiode PD to the capacitor C1 is stopped. That is, the connection switch Sw2 is turned off. Subsequently, the operation of the fifth period T5 to the ninth period T9 is performed, and the video signal is output from the differential amplifier AMP2 and the output amplifier AMP3 (time tG to time tH).

  The operation in the fifth period T5 to the ninth period T9 (time t5 to time t10) corresponds to the operation from time tA to time tH in FIG. 4, but for the next imaging, from time tF to tG, At the same time when the connection switch Sw1 and the reset switch Sw2 are turned on, the noise transfer switch Sw3 is also turned on, so that noise generated on the output side of the integration circuit ITG is accumulated in the noise memory M3. The operations of the other switches Sw4, Sw6, Sw3, and Sw5 are the same as those at time t5 to time t10 from time tA to tI. Note that the connection switch Sw1 and the reset switch Sw2 are OFF between time tA and time tF.

  According to the imaging apparatus of the present invention, by providing the two-stage memories M3 to M6 for each of the noise component and the signal component, the size of the video signal is reduced while removing the noise component by the differential amplifier AMP2. If it is less than the predetermined value, the reset switch Sw2 is turned on again, and the operation after the fifth period T5 is repeatedly executed without resetting the integration circuit ITG (not reset from time t4 to time tG). High-accuracy imaging can be performed while shortening the time required for charge accumulation.

  Each of the memories M3 to M6 can be composed of a capacitor capable of storing a charge, but can also be composed of a sample and hold circuit capable of holding an input voltage.

  Note that, after the switches Sw7 and Sw8 of all the pixels are simultaneously turned on, the switches Sw9 corresponding to the pixels necessary for reading are sequentially turned on, whereby the data of each pixel can be read in time series. That is, the switches Sw7 and Sw8 are always turned on during the signal readout period (t9 to t10, t15 to t16, tG to tH), but the switch Sw9 is sequentially turned on for each pixel.

  When the number of pixels is 256 and the pixels of these 256 channels are aligned in a one-dimensional manner, these pixel data are read by sequentially turning on the switch Sw9 within the signal reading period. If the memory is disconnected from the previous circuit (the switches Sw5 and Sw6 are OFF), there is no problem even if the readout period is set within the reset period (tF to tI) of the next imaging cycle by the reset switch Sw2. Pixel data can be read out.

  Note that the switch Sw9 is sequentially turned on for each pixel, but the remaining switches can perform the same operation (global shutter) in all the pixels. In other words, the exposure time control circuit 1E sets the charge accumulation state in the integration circuit ITG of all the pixels P within the same period. In this case, since the exposure time in each pixel P is the same, the same image as the actual image can be taken. In addition, the time cycle required for charge accumulation or exposure can be shortened, and high-speed imaging is possible.

  Next, with reference to FIG. 1B again, the relationship with the light projecting device will be supplementarily described.

  When the trigger signal Trig for projecting light is input to the light projecting device 2, the light projecting device 2 starts projecting toward the object OBJ at the time t1 described above, and at the same time, the trigger signal Trig In the input imaging device 1, an imaging cycle starting from time t1 starts. The light projection period includes a charge accumulation period (time t4 to time tA), and is set longer than this. In a video signal output period other than the light projection period including the charge accumulation period (time t4 to time tA), the light projection is stopped from the viewpoint of low power consumption. Even if the light is always emitted, the device operates. The projected light can be continuous light, but can be pulsed light synchronized with the input clock signal CLK.

  In the above description, the imaging device 1 recognizes the start of light projection by open loop control (control that operates in synchronization with the input of the trigger signal Trig). However, the imaging device 1 is configured to recognize the trigger signal Trig. In addition to the input, the reflected light from the object is monitored using a monitor photodiode or a part of the pixel, and when the reflected light is incident, the input of the trigger signal is recognized as an effective value, and the imaging cycle is It is good also as performing feedback control to start.

  The accumulation start time t4 is set to a time when a predetermined time has elapsed from the light projection start time t1. The predetermined time is set to a period from the start of light projection until the light intensity is stabilized. In the case of open loop control, the predetermined time can be set in advance in the imaging apparatus 1, but in the case of feedback control, the predetermined time is determined when the intensity of reflected light to be monitored exceeds a predetermined value. Can be recognized when finished.

  Note that when the trigger signal Trig for ending projection is input from the control device 3 to the projector 2, the light emission from the projector 2 is stopped, but even after the trigger signal Trig for ending projection is input. Light emission continues for a short time as a transient phenomenon. Since this continuation period is a period in which light emission is unstable, the end time of light projection is set after the charge accumulation period has elapsed (after time tA). Thereby, it is possible to avoid imaging during unstable light projection.

  The trigger signal Trig at the start and end of projection can be set according to the rise and fall timing of one square wave, but the pulse wave that generates the rise time of this square wave, The trigger signal Trig can be easily generated by inputting a pulse wave for generating a down time to a bistable multivibrator (latch flip-flop) or the like.

  FIG. 5 is a diagram illustrating an example of a square wave generating circuit (FIG. 5A), and FIG. 5B is a diagram illustrating an example of a square wave generating element (FIG. 5B).

  Other square waves necessary for the operation in the circuit can be generated using a bistable multivibrator in the same manner as described above, and the square wave generation circuit 1Ec in FIG. Based on the Trig and the clock signal CLK, a plurality of square wave generating elements WG for generating square waves for controlling various switches are provided. The square wave generating element WG generates control signals for various switches having the above-described ON / OFF timing based on the input control output. In the figure, an example is shown in which control signals for eight switches are output. However, when the number of switches to be controlled differs from this due to circuit deformation, the number of square wave generation elements WG is changed to the number of control objects. The number of switches may be used.

  The rising and falling times of the square wave are configured such that the input clock signal is counted by a counter and the clock is used when the count value reaches a desired value. It can be. In other words, the rising and falling times of any square wave can be easily controlled. The start and end times of a series of imaging cycles can be determined by the trigger signal Trig input to the square wave generation circuit 1Ec. That is, it is only necessary to start the operation of the square wave generation circuit 1Ec when the trigger signal Trig is input.

  As the counter, a programmable counter PC (FIG. 5B) that generates an output when the count value reaches a desired value can be used. The desired value is a control output from the exposure time adjustment circuit. Can be changed. If the programmable counter PC counts the desired number of clocks and then inputs it to the latch flip-flop FF, the latch flip-flop FF generates a rising or falling portion of a square wave at the time of input. In the figure, one square wave generation element WG includes one programmable counter PC. However, if this includes two or more programmable counters, it is possible to freely generate clock pulses for generating various waveforms. It is.

  When the control output of the exposure time control circuit 1E prompts to extend the exposure time (integrated time), a counter that measures the time until the connection switch Sw1 is turned off may be reset after the video signal is determined.

  Note that the timing of switching the reset switch Sw2 from OFF to ON is preferably set to an intermediate position of a pulse square wave included in the clock signal CLK (a time between the rise time and the fall time of the pulse). That is, since the square wave signal for controlling ON / OFF of the connection switch Sw1 is generated from the clock signal CLK, noise is superimposed on the input signal to the connection switch Sw1 at the clock rise time and fall time. When the reset switch Sw2 is switched from ON to OFF simultaneously with the generation of the noise, the noise is taken into the capacitor C1. Therefore, in order to avoid accumulation of noise components, switching of the reset switch Sw2 is avoided at the edge of the clock signal.

  In the displacement sensor, when the imaging device 1 is a line sensor, the incident position of the reflected light corresponds to the distance to the object. That is, the light incident intensity at a specific pixel arranged in a one-dimensional manner is higher than the light incident intensity at the surrounding pixels. That is, the video signal output from the imaging device 1 has an intensity peak in one frame. More specifically, the intensity peak in the video signal is set to exceed the lower limit value Vlow, and the charge accumulation time is set accordingly.

  When the reflectance of the object is high, the reflected light intensity is high, so that the total charge accumulation time is shortened. When the reflectance is low, the reflected light intensity is low, so that the total charge accumulation is Time is shortened.

  The exposure time adjustment circuit 1Eb can generate a control output as shown in FIG. 2B according to the input levels L and H. Since two states are shown in FIG. 2B, all states can be expressed by a 1-bit digital output. When one state is input, the exposure time adjustment circuit 1Eb generates ON / OFF timings of the various switches described above. This function can be configured by a logic circuit, but it may be configured by incorporating a program for generating the above-mentioned ON / OFF timing in accordance with the input state into a microcomputer.

  Further, the exposure time control circuit 1E preferably sets the charge accumulation period in all the pixels P within the same period. In this case, since the exposure time is simultaneous, the same image as the actual image is displayed. An image can be taken.

  In the above-described embodiment, when the switch Sw4 is turned on, the connection switch Sw1 may be turned off (period T5). Thereby, the influence of the parasitic capacitor Cpd of the photodiode PD can be suppressed, and the load on the amplifier in the integration circuit ITG can be reduced. Therefore, the data transfer time when the switch Sw4 is turned on can be shortened, and high-speed imaging can be performed.

  As described above, in the imaging device according to the above-described embodiment, the magnitude of the video signal is determined, and when the magnitude of the video signal is less than a predetermined value, the reset switch Sw2 is not turned on. When the operation of the fifth period T5 to the ninth period T9 is repeated and the magnitude of the video signal is equal to or greater than a predetermined value, the accumulation of charge from the photodiode PD to the capacitor is stopped, and the fifth period T5 to the ninth period The operation of T9 is performed to output a video signal from the differential amplifier AMP2. In this apparatus, by providing the two-stage memories M3 to M6, the noise component is removed by the differential amplifier AMP2 by the CDS (correlated double sampling) circuit, and the size of the video signal is less than a predetermined value. Since the operation after the fifth period T5 is executed without resetting the reset switch and resetting the integration circuit ITG, it is possible to perform high-accuracy imaging while reducing the time required for charge accumulation. it can.

DESCRIPTION OF SYMBOLS 1 ... Imaging device, 2 ... Projection device, 3 ... Control device, OBJ ... Object, 1E ... Exposure time control circuit, 1S ... Shift register, P ... Pixel, ITG ... Integration circuit, C1 ... Capacitor, PD ... Photodiode M1 to M6 memory, Sw1 connection switch, Sw2 reset switch, Sw3 to Sw6 transfer switch.

Claims (1)

In an imaging device having a plurality of aligned pixels,
Each said pixel is
A photodiode;
An integrating circuit having a capacitor connected between the input and output terminals of the amplifier and a reset switch for short-circuiting the capacitor;
A first noise memory connected to an output terminal of the integrating circuit via a first transfer switch;
A second noise memory connected to the first noise memory via a second transfer switch;
A first signal memory connected to an output terminal of the integrating circuit via a third transfer switch;
A second signal memory connected to the first signal memory via a fourth transfer switch;
A differential amplifier that outputs a difference between outputs of the second noise memory and the second signal memory;
A control circuit for controlling a charge accumulation period in the capacitor based on a video signal output from the differential amplifier;
With
The control circuit includes:
Periods of the following states (1) to (9):
(1) a first period of an initial state in which the reset switch, the first transfer switch, the second transfer switch, the third transfer switch, and the fourth transfer switch are OFF,
(2) a second period in which the reset switch and the first transfer switch are turned on and an output terminal of the integrating circuit is connected to the first noise memory;
(3) a third period in which the first transfer switch is turned off before the reset switch is turned off;
(4) a fourth period in which the reset switch is turned off and electric charge is accumulated in the capacitor from the photodiode;
(5) A fifth period in which the third transfer switch and the fourth transfer switch are turned on and the output terminal of the integrating circuit is connected to the second signal memory via the first signal memory;
(6) A sixth period in which the third transfer switch and the fourth transfer switch are turned off,
(7) A seventh period in which the second transfer switch is turned on to transfer the data stored in the first noise memory to the second noise memory;
(8) an eighth period in which the second transfer switch is turned off; and
(9) a ninth period in which a video signal is output from the differential amplifier;
To control the reset switch, the first transfer switch, the second transfer switch, the third transfer switch, and the fourth transfer switch so that
Determining the magnitude of the video signal;
When the magnitude of the video signal is less than a predetermined value, the operation from the fifth period to the ninth period is repeated without turning on the reset switch,
When the magnitude of the video signal is greater than or equal to the predetermined value, the accumulation of electric charge from the photodiode to the capacitor is stopped, and the operation of the fifth period to the ninth period is performed, and the video signal is Output from the differential amplifier,
An imaging apparatus characterized by that.

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