JP2013141144A - A/d conversion circuit, imaging device, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain satisfactory signal characteristics by a simpler constitution.SOLUTION: An A/D conversion circuit comprises: a lamp generation unit which generates a gradient lamp signal to be referred to when an analog signal is converted to a digital signal; a comparator which compares the analog signal with the lamp signal and outputs the result of the comparison; and a counter which outputs a count value based on the result of the comparison by the comparator. The lamp generation unit is constituted by arranging plural capacitor elements in parallel. This technique can be applied to a CMOS image sensor, for example.

Description

  The present disclosure relates to an A / D conversion circuit, an imaging device, and an electronic device, and particularly to an A / D conversion circuit, an imaging device, and an electronic device that can obtain good signal characteristics with a simpler configuration.

  In recent years, solid-state imaging devices such as CMOS (Complementary Metal Oxide Semiconductor) image sensors and CCDs (Charge Coupled Devices) are widely used in digital still cameras, digital video cameras, and the like. In general, a solid-state imaging device has a pixel array unit in which a plurality of pixels each having a photodiode serving as a photoelectric conversion unit are arranged in a two-dimensional manner, or an analog pixel signal output from the pixel array unit. (Analog / Digital) It is configured with A / D conversion circuit to convert.

  For example, the applicant of the present application has proposed a CMOS image sensor that performs digital CDS (Correlated Double Sampling) processing on a pixel signal output from a pixel (see, for example, Patent Document 1).

  In the digital CDS processing, for example, a ramp waveform signal (hereinafter, referred to as a ramp signal as appropriate) in which a slope in which the voltage drops with a constant gradient appears repeatedly, such as a saw shape, is used as a reference signal. For example, a pixel signal that is A / D converted by comparing the pixel signal at the reset level of the pixel and the ramp signal, and an A / D conversion that compares the pixel signal at a level corresponding to the amount of light received by the pixel and the ramp signal By outputting a difference from the pixel signal, noise included in the pixel signal is removed.

  The A / D conversion circuit used for such digital CDS processing is a combination of a ramp generator that generates a ramp signal from a plurality of constant current sources and a comparator that compares the voltage of the pixel signal and the voltage of the ramp signal. Configured.

JP 2010-022063 A

  By the way, in general, in an A / D conversion circuit, it is necessary to remove the offset of the comparator before performing A / D conversion in order to obtain good signal characteristics. In the meantime, it was necessary to provide a capacitive element. On the other hand, from the viewpoint of downsizing the solid-state imaging device, etc., A / D can obtain good signal characteristics with a simple configuration without providing such a capacitive element, with the comparator offset removed. There is a need for a conversion circuit.

  The present disclosure has been made in view of such a situation, and makes it possible to obtain good signal characteristics with a simpler configuration.

  An A / D conversion circuit according to one aspect of the present disclosure includes a signal generation unit that generates a reference signal having a slope that is referred to when an analog signal is converted into a digital signal, and compares the analog signal with the reference signal. A comparison unit that outputs the comparison result and a count unit that outputs a count value based on the comparison result by the comparison unit, and the signal generation unit is configured by arranging a plurality of capacitive elements in parallel. Is done.

  The imaging device according to one aspect of the present disclosure includes a pixel array unit in which a plurality of pixels are arranged in an array and a pixel signal is output from the pixels, and an A / D conversion circuit corresponding to the number of columns of the pixels in parallel. An A / D conversion processing unit disposed in the A / D conversion circuit, wherein the A / D conversion circuit generates a reference signal having a slope referred to when an analog signal is converted into a digital signal, and the pixel Comparing a signal with the reference signal and outputting a comparison result; and a count unit outputting a count value based on the comparison result by the comparison unit, and the signal generator includes a plurality of Capacitance elements are arranged in parallel.

  An electronic device according to an aspect of the present disclosure includes a pixel array unit in which a plurality of pixels are arranged in an array and a pixel signal is output from the pixels, and an A / D conversion circuit corresponding to the number of columns of the pixels in parallel. And an A / D conversion processing unit disposed in the A / D conversion circuit, wherein the A / D conversion circuit generates a reference signal having a slope that is referred to when an analog signal is converted into a digital signal. The signal generation unit, a comparison unit that compares the pixel signal with the reference signal and outputs the comparison result, and a count unit that outputs a count value based on the comparison result of the comparison unit. The unit is configured by arranging a plurality of capacitive elements in parallel.

  In one aspect of the present disclosure, a plurality of capacitive elements are arranged in parallel to form a signal generation unit.

  According to one aspect of the present disclosure, good signal characteristics can be obtained with a simpler configuration.

It is a circuit diagram showing an example of composition of an embodiment of an A / D conversion circuit to which this art is applied. It is a figure which shows the waveform of a ramp signal. It is a figure which shows the A / D conversion circuit of an auto zero state. It is a figure which shows the A / D conversion circuit from which the auto zero state was cancelled | released. It is a figure which shows the A / D conversion circuit in the state where the ramp signal was reset. It is a figure which shows the A / D conversion circuit of the state which is outputting the ramp signal. It is a figure explaining the conventional A / D conversion circuit. It is a circuit diagram which shows the structural example of a CMOS image sensor. It is a figure which shows the waveform of the ramp signal at the time of applying digital CDS processing. It is a figure which shows the waveform of a nonlinear ramp signal. It is a block diagram which shows the structural example of the imaging device mounted in an electronic device.

  Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to the drawings.

  FIG. 1 is a circuit diagram illustrating a configuration example of an embodiment of an A / D conversion circuit to which the present technology is applied.

  In FIG. 1, the A / D conversion circuit 11 includes an A / D conversion unit 12 and a ramp generation unit 13, A / D converts a signal input to the input terminal 14, and outputs an output terminal 15. Output from.

  The A / D conversion unit 12 includes a comparator 21, a capacitive element 22, switches 23 and 24, and a counter 25, and the ramp generation unit 13 includes N capacitive elements 31-1 to 31-N. Configured.

  In the A / D conversion circuit 11, the wiring from which the ramp signal (reference signal) is output from the ramp generation unit 13 is connected to the non-inverting input terminal (+) of the comparator 21, and the non-inverting input terminal and the inverting terminal of the comparator 21. The output terminal (−) is connected via the switch 23. The input terminal 14 is connected to the inverting input terminal (−) of the comparator 21 via the capacitive element 22, and the inverting input terminal and the non-inverting output terminal (+) of the comparator 21 are connected via the switch 24. Connected. The non-inverting output terminal of the comparator 21 is connected to the input terminal of the counter 25, and the output terminal of the counter 25 is connected to the output terminal 15.

  A ramp signal output from the ramp generator 13 is input to the non-inverting input terminal of the comparator 21, and an analog signal input to the input terminal 14 is input to the inverting input terminal of the comparator 21 via the capacitive element 22. Is done. Then, the comparator 21 compares the voltage value of the ramp signal with the voltage value of the analog signal. For example, when the voltage value of the ramp signal is higher than the voltage value of the analog signal, the comparator 21 outputs a high level signal from the non-inverting output terminal and outputs a low level signal from the inverting output terminal. On the other hand, when the voltage value of the ramp signal is lower than the voltage value of the analog signal, the comparator 21 outputs a Low level signal from the non-inverting output terminal and outputs a High level signal from the inverting output terminal.

  The capacitor 22 stores an analog signal input from the input terminal 14, and the voltage of the analog signal stored in the capacitor 22 is input to the inverting input terminal of the comparator 21.

  The switches 23 and 24 execute an auto zero function for removing the offset of the comparator 21. For example, when A / D conversion is started in the A / D conversion unit 12, the switches 23 and 24 are short-circuited together, whereby the offset of the comparator 21 is removed.

  A predetermined clock signal is supplied to the counter 25 from a clock circuit (not shown), and the counter 25 starts counting the clock signal, for example, at the timing when the ramp signal starts to drop. Then, the counter 25 outputs a signal indicating the count value at the timing when the signal output from the non-inverting output terminal of the comparator 21 changes from the High level to the Low level to the output terminal 15. The comparator 21 switches the signal output from the non-inverting output terminal from the high level to the low level when the voltage value of the ramp signal becomes lower than the voltage value of the analog signal. The analog signal input to the terminal 14 is A / D converted.

  In the ramp generation unit 13, one end of each of the capacitive elements 31-1 to 31-N is made common (connected) and connected to the non-inverting output terminal of the comparator 21, and the other end of each of the capacitive elements 31-1 to 31-N. Are connected to the respective control terminals V [1] to V [N]. For example, a control signal for generating a ramp signal is supplied to the control terminals V [1] to V [N] from a logic control circuit 57 (FIG. 8) described later.

  The control terminals V [1] to V [N] are supplied with a high level or low level control signal, and the level of the ramp signal output from the ramp generation unit 13 is, for example, a high level control signal. It depends on the number. Accordingly, all the control signals are set to the high level, and the control signals are switched to the low level one by one according to the predetermined clock signal, so that the level of the ramp signal output from the ramp generation unit 13 is a slope with a predetermined slope ( Descent with a slope.

  Next, an example of an operation sequence of the A / D conversion circuit 11 when using the descending slope will be described with reference to FIGS.

  FIG. 2 shows the waveform of the ramp signal output from the ramp generator 13, the vertical axis shows the voltage Vramp of the ramp signal, and the horizontal axis shows time T. 3 to 6 show the state of the A / D conversion circuit 11 in each period of the ramp signal shown in FIG. 3 to 6, the illustration of the counter 25 is omitted.

  3 to 6 show that the capacitive element 31 is driven via inverters 32 and 33 connected in series in order to clarify that the control of the ramp generation unit 13 is digital control. Has been. That is, a control signal is input to the capacitive element 31-1 from the control terminal V [1] via the inverters 32-1 and 33-1, and the inverters 32-2 and 33-2 are input to the capacitive element 31-2. Then, a control signal is input from the control terminal V [2] via the control terminal V. Similarly, the control signal from the control terminal V [N] is supplied to the capacitive element 31-N via the inverters 32-N and 33-N. Entered. Instead of the inverters 32 and 33, for example, an arbitrary logic gate may be adopted.

  First, until time t1, the A / D conversion circuit 11 is set to the auto-zero state. At this time, in order to output a predetermined auto-zero voltage V0, as shown in FIG. 3, the ramp generator 13 has a predetermined number of control signals input to the control terminals V [1] to V [N]. These control signals are set to low level, and the remaining control signals are set to high level. In this state, in the A / D converter 12, the switches 23 and 24 are short-circuited.

  Next, in the period from time t1 to time t2, the auto-zero state of the A / D conversion circuit 11 is canceled. As shown in FIG. 4, the ramp generator 13 maintains switches 23 and 24 in the A / D converter 12 while maintaining the state of the control signal input to the control terminals V [1] to V [N]. Is released. Thereby, the offset of the comparator 21 is removed, and auto zero is completed.

  Thereafter, during the period from time t2 to time t3, the ramp generation unit 13 is reset. At this time, the predetermined number of control signals that have been set to the low level are switched to the high level, and all the control signals are set to the high level as shown in FIG. As a result, the ramp signal output from the ramp generator 13 rises from the auto-zero voltage V0 by a constant voltage, and the ramp generator 13 enters a state where it can output a descending slope.

  Then, during the period from time t3 to time t4, a descending slope in which the voltage drops with a constant gradient is output. At time t3, as shown in FIG. 6, in the ramp generation unit 13, the control signal input to the control terminal V [1] is switched from the high level to the low level. Thereafter, until time t4, the control signals input to the control terminals V [2] to V [N] are sequentially switched from the high level to the low level one by one according to a predetermined clock. As a result, the ramp signal output from the ramp generator 13 has a waveform in which the voltage drops at a constant gradient.

  In this way, the A / D conversion circuit 11 removes the offset of the comparator 21 by supplying the ramp signal as shown in FIG. 2 from the ramp generation unit 13 to the comparator 21 and short-circuiting the switches 23 and 24. Auto zero function can be realized. Thereby, the adverse effect due to the offset can be eliminated, and the A / D conversion circuit 11 can output a signal with better characteristics.

  In addition, the A / D conversion circuit 11 includes the ramp generating unit 13 including the capacitive elements 31-1 to 31-N. For example, in the conventional A / D conversion circuit, to realize the auto-zero function. It is possible to configure without including the necessary capacitive element.

  Here, a conventional A / D conversion circuit will be described with reference to FIG. In FIG. 7, the same reference numerals are given to components common to the A / D conversion circuit 11 of FIG. 1, and detailed description thereof is omitted.

  As shown in FIG. 7, the ramp generator 13 ′ of the conventional A / D conversion circuit 11 ′ has N constant current sources 41-1 to 41-N, and the constant current source 41-1. The current output from 41 to N is configured to flow into the resistor 42. A ramp signal is generated by controlling on / off of the constant current sources 41-1 to 41-N, and is connected to a connection point between the constant current sources 41-1 to 41-N and the resistor 42. A voltage corresponding to the ramp signal is accumulated in the capacitive element 43 and input to the non-inverting input terminal of the comparator 21.

  As described above, in the A / D conversion circuit 11 ′, the ramp generator 13 ′ is configured to generate the ramp signal using the constant current sources 41-1 to 41-N. It was necessary.

  On the other hand, in the A / D conversion circuit 11 of FIG. 1, by using the ramp generation unit 13 configured to generate a ramp signal using the capacitive elements 31-1 to 31-N, the capacitive element 43 is provided. There is no need to provide a simpler configuration. In addition, the area occupied by the A / D conversion circuit 11 can be reduced by the amount that the capacitive element 43 is unnecessary.

  The ramp generator 13 of the A / D conversion circuit 11 can generate a ramp signal by charging and discharging the capacitive elements 31-1 to 31-N. Generation of a current that constantly flows can be avoided by the current sources 41-1 to 41-N. Therefore, the A / D conversion circuit 11 can employ the ramp generator 13 so that the required current consumption is only the dynamic current used for charging the capacitive elements 31-1 to 31-N. Power consumption can be greatly reduced. Furthermore, the A / D conversion circuit 11 can reduce power consumption in proportion to a decrease in operating speed.

  Further, since the ramp generation unit 13 of the A / D conversion circuit 11 is configured without including a resistance element and a constant current source (an active element that outputs current), the stationary noise source can be greatly reduced. And a signal with very little noise can be output.

  Next, a CMOS image sensor including an A / D conversion circuit configured to include the A / D conversion unit 12 and the ramp generation unit 13 will be described with reference to FIG.

  As shown in FIG. 8, the CMOS image sensor 51 includes a ramp generation unit 13, a pixel array unit 52, a vertical drive unit 53, a column processing unit 54, a horizontal drive unit 55, an amplifier circuit 56, and a logic control circuit 57. Composed.

  The pixel array unit 52 includes a plurality of pixels 58 arranged in an array, and is connected to the vertical drive unit 53 via a plurality of horizontal signal lines H corresponding to the number of rows of the pixels 58. The column processing unit 54 is connected via a plurality of vertical signal lines V corresponding to the number of columns. That is, the plurality of pixels 58 included in the pixel array unit 52 are respectively arranged at points where the horizontal signal lines H and the vertical signal lines V intersect, and are driven according to the drive signal supplied via the horizontal signal lines H. The pixel signal is output to the vertical signal line V.

  The vertical drive unit 53 generates a drive signal (transfer signal, selection signal, reset signal, etc.) for driving each pixel 58 for each row of the plurality of pixels 58 included in the pixel array unit 52 and the horizontal signal line H. To supply sequentially.

  The column processing unit 54 includes a plurality of A / D conversion units 12 arranged in parallel according to the number of rows of the pixels 58, and performs A / D conversion on pixel signals output from the pixels 58. Output. At this time, the column processing unit 54 performs digital CDS processing as described later with reference to FIG. 9 on the pixel signal. In the plurality of A / D conversion units 12 included in the column processing unit 54, the non-inverting input terminal of the comparator 21 is shared and connected to the ramp generating unit 13, and the inverting input terminal of the comparator 21 is connected to the capacitive element 22. To the vertical signal line V. The output terminal of the counter 25 is shared and connected to the amplifier circuit 56.

  For each column of the plurality of pixels 58 included in the pixel array unit 52, the horizontal driving unit 55 sequentially outputs the pixel signals A / D converted by the A / D conversion unit 12 corresponding to each pixel 58 from the column processing unit 54. A drive signal for outputting to the A / D converter 12 is sequentially supplied.

  A pixel signal is supplied from the column processing unit 54 to the amplifier circuit 56 at a timing according to the drive signal of the horizontal drive unit 55, and the amplifier circuit 56 amplifies the pixel signal with a predetermined amplification factor, for example, in the subsequent stage Output to the image processing circuit.

  The logic control circuit 57 outputs a signal necessary for driving each block according to the drive cycle of each block inside the CMOS image sensor 51. For example, the logic control circuit 57 outputs a control signal to the control terminals V [1] to V [N] of the ramp generation unit 13 and causes the ramp generation unit 13 to output a ramp signal. Further, the logic control circuit 57 outputs a signal for controlling the opening and closing of the switches 23 and 24 to the A / D conversion unit 12 of the column processing unit 54 to execute the auto zero function of the A / D conversion unit 12.

  In the CMOS image sensor 51 thus configured, a so-called column / parallel A / D converter is configured by the ramp generation unit 13 and the column processing unit 54 having the plurality of A / D conversion units 12, and the pixel 58 The pixel signals output from are A / D converted in parallel for each row.

  With reference to FIG. 9, operations of the ramp generation unit 13 and the A / D conversion unit 12 when the digital CDS process is performed will be described.

  FIG. 9 shows the waveform of the ramp signal output from the ramp generator 13 when the digital CDS processing is applied, the vertical axis shows the voltage Vramp of the ramp signal, and the horizontal axis shows the time T. ing. When the digital CDS processing is applied, as shown in FIG. 9, a falling slope in which the voltage drops at a constant gradient is output twice.

  First, until time t11, the A / D converter 12 is set to the auto-zero state. In other words, the logic control circuit 57 outputs a predetermined number of control signals among the control signals input to the control terminals V [1] to V [N] of the ramp generator 13 in order to output a predetermined auto-zero voltage V0. Is set to low level, and the remaining control signals are set to high level. At this time, the logic control circuit 57 controls the A / D converter 12 so as to short-circuit the switches 23 and 24.

  Next, in the period from time t11 to time t12, the auto-zero state of the A / D conversion unit 12 is released. That is, the logic control circuit 57 opens the switches 23 and 24 of the A / D conversion unit 12 while maintaining the state of the control signal input to the control terminals V [1] to V [N] of the ramp generation unit 13. Control as follows. Thereby, the offset of the comparator 21 is removed, and auto zero is completed.

  Thereafter, during the period from time t12 to time t13, the ramp generation unit 13 is reset. In other words, the logic control circuit 57 switches the predetermined number of control signals that have been set to the Low level to the High level, and sets all the control signals supplied to the lamp generating unit 13 to the High level. As a result, the ramp signal output from the ramp generator 13 rises by a constant voltage from the auto-zero voltage V0, and the ramp generator 13 enters a state where it can output the first descending slope.

  Then, during the period from time t13 to time t14, a drop slope in which the voltage drops with a constant gradient is output. That is, the logic control circuit 57 switches the control signal input to the control terminal V [1] from the high level to the low level at time t13. Then, the logic control circuit 57 sequentially switches the control signals input to the control terminals V [2] to V [N] from the high level to the low level one by one according to a predetermined clock until time t14. . Thereby, the ramp generating unit 13 outputs a descending slope in which the voltage drops with a constant gradient.

  At this time, a pixel signal at a reset level is output from the pixel 58 via the vertical signal line V and accumulated in the capacitor 22. The comparator 21 outputs a signal output from the non-inverting output terminal at a timing when the voltage of the ramp signal output from the ramp generation unit 13 becomes lower than the voltage of the pixel signal accumulated in the capacitor 22. Switch from level to low level. On the other hand, under the control of the logic control circuit 57, the counter 25 outputs a signal indicating a count value from the timing (t13) at which the ramp signal starts dropping to the timing at which the signal from the comparator 21 changes from the high level to the low level. Output. This signal is held as a reset level pixel signal.

  Next, in the period from time t14 to time t15, the ramp generating unit 13 is reset. In other words, the logic control circuit 57 switches all control signals supplied to the ramp generator 13 from the low level to the high level. As a result, the ramp generating unit 13 is in a state where it can output the second descending slope.

  Then, during the period from time t15 to time t16, as in the period from time t13 to time t14, a descending slope in which the voltage drops with a constant gradient is output.

  At this time, a pixel signal having a level corresponding to the light received by the pixel 58 is output from the pixel 58 via the vertical signal line V and accumulated in the capacitor 22. The comparator 21 outputs a signal output from the non-inverting output terminal at a timing when the voltage of the ramp signal output from the ramp generation unit 13 becomes lower than the voltage of the pixel signal accumulated in the capacitor 22. Switch from level to low level. On the other hand, under the control of the logic control circuit 57, the counter 25 outputs a signal indicating the count value from the timing (t15) when the ramp signal starts to drop to the timing when the signal from the comparator 21 changes from the high level to the low level. Output. This signal is held as a pixel signal at the light receiving level.

  After that, a signal indicating a value obtained by calculating a difference between the pixel signal of the reset level and the pixel signal of the light receiving level that is held is an A / D converted signal obtained by A / D converting the analog pixel signal output from the pixel 58. Output from the converter 12.

  In this manner, the CMOS image sensor 51 employs digital CDS processing that calculates and outputs the difference between the reset level pixel signal output from the pixel 58 and the light reception level pixel signal. Thereby, noise specific to the pixel 58 included in the pixel signal output from the pixel 58 can be removed.

  Further, as described above, the A / D conversion circuit 11 can significantly reduce the stationary noise source, and, for example, cancels auto-zero for the pixel signal output from the A / D conversion circuit 11. Only so-called kTC noise that is sampled by the capacitive element 22 is included. The kTC noise can be removed by calculating the difference in the digital CDS process, and the kTC noise is prevented from being output from the A / D converter 12. Accordingly, the CMOS image sensor 51 can output a pixel signal having a simple characteristic, low power consumption, and good characteristics free from noise.

  The ramp generator 13 can generate a ramp waveform having a non-constant non-linear slope in addition to a ramp waveform having a slope in which the voltage drops linearly as shown in FIGS. .

  For example, by adjusting the number of control signals that can be switched from the High level to the Low level, the capacitance value of the capacitive element 31 included in the ramp generation unit 13, the time interval for switching the control signal from the High level to the Low level, etc. The slope of can be changed. Further, the number of control signals that can be switched from the High level to the Low level, the capacitance value of the capacitive element 31 included in the ramp generation unit 13, and the time interval for switching the control signal from the High level to the Low level are finely adjusted. This makes it possible to correct distortion that appears in the ramp signal.

  As a result, a ramp waveform whose slope of the descending slope is not constant, for example, as shown in FIG. 10, during the period from time t3 to time t4, the voltage first drops with a gentle slope, and the slope changes sharply. Such a ramp waveform can be generated.

  In this embodiment, the operation sequence using the ramp signal having the descending slope has been described. However, the ramp generator 13 has the ascending slope by inverting all of the high level and the low level of the control signal. A ramp signal can be generated, and an operation sequence using a ramp signal having a rising slope can be applied.

  The CMOS image sensor 51 as described above is used in various electronic devices such as an imaging system such as a digital still camera and a digital video camera, a mobile phone having an imaging function, or other devices having an imaging function. Can be applied.

  FIG. 11 is a block diagram illustrating a configuration example of an imaging device mounted on an electronic device.

  As illustrated in FIG. 11, the imaging apparatus 101 includes an optical system 102, an imaging element 103, a signal processing circuit 104, a monitor 105, and a memory 106, and can capture still images and moving images.

  The optical system 102 includes one or more lenses, guides image light (incident light) from the subject to the image sensor 103, and forms an image on the light receiving surface (sensor unit) of the image sensor 103.

  As the image sensor 103, the CMOS image sensor 51 having the above-described configuration example is applied. Charges are accumulated in the image sensor 103 for a certain period according to an image formed on the light receiving surface via the optical system 102. Then, a signal corresponding to the charge accumulated in the image sensor 103 is supplied to the signal processing circuit 104.

  The signal processing circuit 104 performs various types of signal processing on the signal charges output from the image sensor 103. An image (image data) obtained by performing signal processing by the signal processing circuit 104 is supplied to the monitor 105 and displayed, or supplied to the memory 106 and stored (recorded).

  In the imaging apparatus 101 configured as described above, by applying the CMOS image sensor 51 having the above-described configuration example as the imaging element 103, it is possible to obtain better image quality with less noise.

In addition, this technique can also take the following structures.
(1)
A plurality of pixels arranged in an array, and a pixel array unit from which pixel signals are output;
An A / D conversion processing unit in which A / D conversion circuits according to the number of columns of the pixels are arranged in parallel,
The A / D converter circuit is
A signal generator for generating a reference signal having a slope referred to when converting an analog signal into a digital signal;
A comparison unit that compares the pixel signal with the reference signal and outputs a comparison result;
A count unit that outputs a count value based on a comparison result by the comparison unit, and
The signal generation unit is configured by arranging a plurality of capacitive elements in parallel.
(2)
One terminal of the plurality of capacitive elements is shared and directly connected to the comparison unit,
The imaging device according to (1), wherein the reference signal is generated by switching a level of a control signal input to the other terminal of the plurality of capacitive elements.
(3)
The pixel outputs a pixel signal at a reset level and a pixel signal at a level corresponding to the amount of received light,
The image sensor according to (1) or (2), wherein the signal generation unit outputs the reference signal having two inclinations.

  Note that the present embodiment is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present disclosure.

  11 A / D conversion circuit, 12 A / D conversion unit, 13 ramp generation unit, 14 input terminal, 15 output terminal, 21 comparator, 22 capacitive element, 23 and 24 switch, 25 counter, 31 capacitive element, 32 and 33 inverter , 51 CMOS image sensor, 52 pixel array unit, 53 vertical drive unit, 54 column processing unit, 55 horizontal drive unit, 56 amplifier circuit, 57 logic control circuit, 58 pixel

Claims (6)

A signal generator for generating a reference signal having a slope referred to when converting an analog signal into a digital signal;
A comparator that compares the analog signal with the reference signal and outputs a comparison result;
A count unit that outputs a count value based on a comparison result by the comparison unit, and
The signal generator is configured by arranging a plurality of capacitive elements in parallel.
A / D (Analog / Digital) conversion circuit. One terminal of the plurality of capacitive elements is shared and directly connected to the comparison unit,
The A / D conversion circuit according to claim 1, wherein the reference signal is generated by switching a level of a control signal input to the other terminal of the plurality of capacitive elements. A plurality of pixels arranged in an array, and a pixel array unit from which pixel signals are output;
An A / D conversion processing unit in which A / D conversion circuits according to the number of columns of the pixels are arranged in parallel,
The A / D converter circuit is
A signal generator for generating a reference signal having a slope referred to when converting an analog signal into a digital signal;
A comparison unit that compares the pixel signal with the reference signal and outputs a comparison result;
A count unit that outputs a count value based on a comparison result by the comparison unit, and
The signal generation unit is configured by arranging a plurality of capacitive elements in parallel. One terminal of the plurality of capacitive elements is shared and directly connected to the comparison unit,
The imaging device according to claim 3, wherein the reference signal is generated by switching a level of a control signal input to the other terminal of the plurality of capacitive elements. The pixel outputs a pixel signal at a reset level and a pixel signal at a level corresponding to the amount of received light,
The imaging device according to claim 3, wherein the signal generation unit outputs the reference signal having two slopes. A plurality of pixels arranged in an array, and a pixel array unit from which pixel signals are output;
An A / D conversion processing unit in which A / D conversion circuits according to the number of columns of the pixels are arranged in parallel,
The A / D converter circuit is
A signal generator for generating a reference signal having a slope referred to when converting an analog signal into a digital signal;
A comparison unit that compares the pixel signal with the reference signal and outputs a comparison result;
A count unit that outputs a count value based on a comparison result by the comparison unit, and
The signal generating unit is an electronic device configured by arranging a plurality of capacitive elements in parallel.

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