JP2013118207A - Semiconductor integrated circuit - Google Patents

Abstract

In a memory equipped with an internal power supply circuit, when an internal power supply is generated based on an external power supply and supplied to the memory, the circuit area is reduced and the increase in power consumption is suppressed, and the internal power supply is stabilized. Realization of the supply.
In an area where the external power supply is at a normal voltage, the internal power supply is generated using only the internal step-down power supply block. In an area where the external power supply is at a low voltage, the internal power supply is reduced. In addition, the internal power supply 103 is generated using the internal boost power supply block 112.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a memory.

  As semiconductor manufacturing technology has advanced in recent years, devices have become increasingly finer and are typified by dynamic random access memory (hereinafter referred to as DRAM) and static random access memory (hereinafter referred to as SRAM). Memory integration has been improved. In addition, with the miniaturization of semiconductor manufacturing technology, the power supply voltage supplied to one semiconductor chip, for example, a system-on-chip (hereinafter referred to as SoC) has been lowered, and the SoC that operates at a lower power supply voltage. Is required.

  As an SoC equipped with a memory, an internal power supply circuit in which an internal power supply voltage that is lower or higher than the external power supply voltage based on an external power supply is installed in the memory, more specifically, an internal step-down power supply block It is widely known that the voltage is generated by an internal boost power supply block and supplied to a memory. This is because it is difficult to directly supply the high voltage required inside the memory from the outside as the external power supply voltage is lowered, and the resistance to fluctuations in the power supply voltage inside and outside the SoC is improved. It is aimed.

  As a publicly known example in which an internal power supply circuit is mounted in a memory, for example, according to Patent Document 1, there is a semiconductor integrated circuit in which a plurality of internal boost power supply blocks are mounted. An example is disclosed that realizes stable supply of the internal power supply voltage even when the external power supply voltage is lowered by selectively operating.

  FIG. 5 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit having a conventional internal power supply circuit. The configuration and operation of the memory internal power supply circuit will be described below with reference to FIG.

  5, the conventional internal power supply circuit includes an external power supply 501, an internal power supply 502, an internal step-down power supply 503, a first internal boost power supply block 504, a second internal boost power supply block 505, and an internal step-down power supply. The block 506 includes a control signal generation circuit 507, a first internal boost power supply control circuit 508, and a second internal boost power supply control circuit 509.

  The first internal boost power supply block 504 performs a boost operation based on the external power supply 501 and outputs the internal power supply 502. The second internal boost power supply block 505 performs a boost operation based on the internal step-down power supply 503 and outputs the internal power supply 502.

  From the control signal generation circuit 507, when the external power source 501 is in the normal voltage region of about 3.3V, the control signal generation circuit 507 is at the L level. When the external power source 501 is in the low voltage region of about 2.3V, for example. 1 logic signal 510 is output and input to the first internal boost power supply control circuit 508 and the second internal boost power supply control circuit 509. The first internal boost power supply control circuit 508 is composed of a two-input NOR circuit, and the first logic signal 510 is input to one input, and the ground is input to the other input. The second internal boost power supply control circuit 509 includes a two-input NAND circuit and an inverter circuit. The first logic signal 510 is input to one of the two inputs of the NAND circuit, and the other input. The external power source 501 is input to each. The second logic signal 511 is sent from the first internal boost power supply control circuit 508 to the first internal boost power supply block 504, and the third logic signal is sent from the second internal boost power supply control circuit 509 to the second internal boost power supply block 505. The logic signals 512 are respectively input. Both the first internal boost power supply block 504 and the second internal boost power supply block 505 are configured to perform a boost operation when the second logic signal 511 and the third logic signal 512 that are inputs are at the H level. .

  The external power supply 501 is, for example, a voltage of 3.3 V, and the internal power supply 502 supplied to the memory (not shown) is supplied to a row decoder (not shown) or a word driver (not shown) in the memory. The supplied voltage is, for example, 3.6 V, and the internal step-down power supply 503 is, for example, 2.3 V.

  First, when the external power supply 501 holds a voltage of a normal voltage region, for example, 3.3 V, an L level signal is output from the control signal generation circuit 507 to the first logic signal 510. In response to the first logic signal 510 becoming L level, the first internal boost power supply control circuit 508 and the second internal boost power supply control circuit 509 respectively send an H level signal to the second logic signal 511. Then, an L level signal is output as the third logic signal 512. In response to this, the first internal boost power supply block 504 starts the boost operation based on the external power supply 501 and outputs the internal power supply 502. On the other hand, the second internal boost power supply block 505 does not perform the boost operation based on the internal step-down power supply 503 because the third logic signal 512 that is the input signal from the previous stage is at the L level.

  As described above, when the external power source 501 is in the normal voltage region, the first internal boost power source block 504 performs a boost operation to supply the internal power source 502 to the memory, and the second internal boost power source block 505 boosts the voltage. Operation and current supply to the internal power supply 502 are not performed.

  On the other hand, when the external power source 501 is in a low voltage region, for example, a voltage of about 2.3 V, an H level signal is output from the control signal generation circuit 507 to the first logic signal 510. In response to the first logic signal 510 becoming H level, the first internal boost power supply control circuit 508 and the second internal boost power supply control circuit 509 respectively send an L level signal to the second logic signal 511. Then, an H level signal is output to the third logic signal 512. In response to this, the second internal boost power supply block 505 starts the boost operation based on the internal step-down power supply 503 and outputs the internal power supply 502. On the other hand, the first internal boost power supply block 504 does not perform the boost operation because the second logic signal 511 that is the input signal from the previous stage is at the L level.

  Thus, when the external power supply 501 is in the low voltage region, the second internal boost power supply block 505 performs a boost operation to supply the internal power supply 502 to the memory, and the first internal boost power supply block 504 boosts the voltage. Operation and current supply to the internal power supply 502 are not performed.

JP 2000-057765 A

  As a problem associated with the recent decrease in the voltage of the external power supply and the fluctuation of the power supply of the entire SoC, first of all, direct supply to the memory of the external power supply has become difficult due to a reduction in voltage and a reduction in the number of pins. If the voltage between the external power supply and the internal power supply to be supplied to the memory is reversed (the internal power supply becomes higher) due to the low voltage of the external power supply, use the internal step-down power supply block. There is a background that it is impossible to generate an internal power supply by stepping down the external power supply. Even if the external power supply is higher than the voltage of the internal power supply, the voltage difference between the two is getting smaller, so even if the internal step-down power supply block is used, sufficient current cannot be supplied. There may be situations where efficiency is poor or internal power generation is insufficient, resulting in failure to supply stable internal power. In addition to this, the power supply fluctuates due to some factor in the external power supply (for example, a voltage drop due to the power supply wiring impedance inside the SoC, a voltage drop due to instantaneous transient current generation in the SoC internal circuit, etc.) If this happens, the effect becomes even more pronounced. For this reason, it is common to use an internal boost power supply block instead of the internal step-down power supply block to generate an internal power supply that is higher in voltage than the external power supply. There are problems in that the power efficiency is lower than that of the power supply block, and the number of circuit elements and the circuit area required are increased.

  Further, according to the above-described conventional example and Patent Document 1, in a normal state where the external power supply holds a sufficient voltage, a part of the plurality of internal boost power supply blocks mounted is operated to operate the external power supply. Is boosted internally and supplied to the memory as an internal power supply. If the external power supply drops below a specified voltage, the external power supply is input to the internal step-down power supply block and the internal power supply is temporarily A step-down power supply is generated, and the internal step-down power supply block is supplied to another internal step-up power supply block that is different from the above-described internal step-up power supply block among the plurality of internal step-up power supply blocks that are mounted. A configuration for supplying an internal power source is disclosed. In this configuration, it is possible to supply a stable internal power supply to the memory even when the voltage of the external power supply drops, but on the other hand, the internal boost power supply block according to the voltage level of the original power supply that performs the boost operation If the external power supply is lowered to a predetermined voltage or lower and the internal step-down power supply block is used, the internal power generation is performed in two stages by stepping down the external power supply and then boosting it again Action is required.

  Since the internal boost power supply block is generally equipped with an oscillator circuit or a pump circuit, as described above, it requires a very large circuit area as compared with the internal step-down power supply block. However, since a plurality of types of internal boosting power supply blocks are mounted, the required circuit area is greatly increased, which greatly affects the increase in the chip area of the SoC as a whole. In addition, when performing a two-stage internal power generation operation in which the external power supply is stepped down and then boosted again, the power consumed is smaller than when the internal power supply is generated only with the internal step-down power supply block. As the power consumption of the entire SoC increases as a result, the concern that the desired power reduction effect cannot be obtained as the SoC even if the external power supply voltage is lowered can be easily assumed. Therefore, as a semiconductor integrated circuit having an internal power supply circuit, even when the external power supply voltage is lowered, it is very difficult to supply a stable internal power supply to the memory while suppressing an increase in area and power consumption. Met.

  The present invention has been made in view of such problems, and reduces the chip area and consumes power when generating internal power by an internal power supply circuit based on the external power and supplying the internal power to the memory. An object of the present invention is to supply a stable internal power supply to a memory while suppressing an increase in power.

  In order to solve the above problem, a first semiconductor integrated circuit according to the present invention includes an internal step-down power supply block that performs a step-down operation based on an external power supply, and an internal step-up operation that performs a step-up operation based on the external power supply. In the region where the external power supply is a normal voltage, the internal power supply of a desired voltage is generated using only the internal step-down power supply block, and in the region where the external power supply is a low voltage, In addition to the internal step-down power supply block or in place of the internal step-down power supply block, the internal step-up power supply block is used to generate an internal power supply having the desired voltage.

  The second semiconductor integrated circuit of the present invention includes an internal step-down power supply block that performs a step-down operation based on a selected power supply, and an internal step-up power supply block that generates an internal boost power supply based on an external power supply. The internal step-down power supply block generates an internal power supply of a desired voltage from the external power supply in a region where the external power supply is a normal voltage, and the internal boosting power supply block in a region where the external power supply is a low voltage. The internal step-down power supply block generates the internal power supply of the desired voltage from the internal boosted power supply generated by

  The present invention is an effective technique for a semiconductor integrated circuit that generates an internal power supply using an internal power supply circuit mounted inside based on an external power supply, while reducing the chip area and suppressing an increase in power consumption. It makes it possible to generate a stable internal power supply. Furthermore, the chip area can be further reduced by sharing a circuit to be used by a plurality of internal power supply blocks.

1 is a block diagram of a semiconductor integrated circuit according to a first embodiment of the present invention. FIG. 5 is a block diagram of a semiconductor integrated circuit according to a second embodiment of the present invention. FIG. 6 is a block diagram of a semiconductor integrated circuit according to a third embodiment of the present invention. It is a block diagram of the semiconductor integrated circuit which concerns on the 4th Embodiment of this invention. It is a block diagram of the conventional semiconductor integrated circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<< First Embodiment >>
FIG. 1 is a diagram showing a schematic configuration of a semiconductor integrated circuit including an internal power supply circuit according to the first embodiment of the present invention. Embodiments of the present invention in a typical internal power generation operation of a semiconductor integrated circuit including an internal power supply circuit will be described below.

  The semiconductor integrated circuit according to the first embodiment of the present invention includes an internal step-down power supply block 101, an internal step-up power supply block 112, and a reference generation circuit 104.

  The internal step-down power supply block 101 includes a 3.3V external power supply 102, an internal power supply 103 that requires 2.6V, a reference voltage 105 that is a 1.3V constant voltage generated from a constant voltage source or the like in the reference circuit 104, A first amplifier circuit 106 and a first amplifier circuit which output a detection signal L level when a reference voltage 105 and an internal power supply feedback voltage 111 described later are input and the internal power supply feedback voltage 111 becomes lower than the reference voltage 105. The first detection signal 107 that is a detection signal generated at 106, the step-down PMOS transistor 108 for generating the internal power supply 103 from the external power supply 102, and the voltage of the internal power supply 103, which is half of the internal power supply 103 The same as the first resistance element 109 and the first resistance element 109 for outputting 1 voltage The second resistor 110 having a resistance value, and an internal power-supply feedback voltage 111 is output as a voltage value of one-half of the internal power supply 103 from the internal power source 103 through the first resistor 109.

  The internal boost power supply block 112 is automatically boosted when an external power supply 102 that requires 3.3V, an internal power supply 103 that requires 2.6V, a pump circuit 113 that boosts the external power supply 102, and the external power supply 102 are supplied. An oscillator circuit 114 that generates a reference signal for operation and controls whether or not to output this reference signal according to the level of the input control signal, and a half of the external power supply 102 based on the external power supply 102 The third resistance element 115 for outputting the voltage of the second power source, the fourth resistance element 116 having the same resistance value as the third resistance element 115, and the half of the external power supply 102 via the third resistance element 115. The external power supply feedback voltage 117, the reference voltage 105, and the external power supply feedback voltage 117 that are output as the voltage values of the external power supply feedback voltage 11 are input. When the signal becomes lower than the reference voltage 105, the second amplifier circuit 118 that outputs the detection signal H level, the second detection signal 119 that is the detection signal generated by the second amplifier circuit 118, and the first detection signal A first logic circuit 120 which is an inverter circuit for inverting the signal polarity of 107, a third detection signal 121 obtained by inverting the signal polarity of the first detection signal 107 via the first logic circuit 120, The second detection signal 119 and the third detection signal 121 are input and output from the second logic circuit 122 and the second logic circuit 122 for taking a NAND (NAND) and input to the oscillator circuit 114. The first logic signal 123 for controlling whether or not the reference signal generated by the oscillator circuit 114 is output is output from the oscillator circuit 114 and the pump circuit 11 It is input to, and a second logic signal 124 is oscillator signal for carrying out an internal step-up operation.

  In the internal step-down power supply block 101, current is supplied from the external power supply 102 to the internal power supply 103 via the step-down PMOS transistor 108, thereby supplying current to the memory (not shown) as the internal power supply 103.

  On the other hand, in the internal boost power supply block 112, when the external power supply 102 is supplied to the pump circuit 113 and the second logic signal 124 for operating the pump circuit 113 is input from the oscillator circuit 114, the external power supply 102 is boosted. Then, the internal power supply 103 is generated and supplied to a memory (not shown). The oscillator circuit 114 outputs a reference signal that is automatically generated internally with the supply of the external power supply 102 as the second logic signal 124 when the input first logic signal 123 is at the L level. The circuit configuration is such that nothing is output when the logic signal 123 is at the H level.

  Regarding the first embodiment of the present invention configured as described above, first, an example in which the external power supply 102 is in a normal voltage region, for example, the external power supply 102 is 3.3V and the internal power supply 103 is 2.6V is taken as an example. Will be described.

  First, in the internal step-down power supply block 101, when the internal power supply 103 falls below a desired voltage of 2.6 V, the internal power supply 103 is divided into two minutes through the first resistance element 109 and the second resistance element 110. 1 (<1.3 V) is input to the first amplifier circuit 106 as the internal power supply feedback voltage 111. On the other hand, the reference voltage 105, which is a constant voltage of 1.3 V generated by the reference generation circuit 104, is also input to the first amplifier circuit 106, and voltage comparison is performed between the two. In this case, since the internal power supply feedback voltage 111 (<1.3 V) is lower than the reference voltage 105 (= 1.3 V), the first amplifier circuit 106 outputs the first detection signal 107 as a detection signal. An L level signal is output. In response to this, the gate input of the step-down PMOS transistor 108 becomes L level, the step-down PMOS transistor 108 is turned on to supply current from the external power supply 102 to the internal power supply 103, and the internal power supply 103 has a desired voltage of 2 Raise to 6V. When a sufficient current is supplied to the internal power supply 103 and reaches the desired voltage of 2.6 V, the internal power supply feedback voltage 111 is set to a voltage half that of the internal power supply 103 and is thus set to 1.3 V. In the first amplifier circuit 106, since the internal power supply feedback voltage 111 becomes higher than the reference voltage 105, the first detection signal 107 is switched from the L level to the H level. In response to this, the gate input of the step-down PMOS transistor 108 is switched from the L level to the H level, so that the step-down PMOS transistor 108 is turned off and the current supply from the external power supply 102 to the internal power supply 103 is stopped.

  In this way, when the internal power supply 103 falls below the desired voltage of 2.6 V, the internal step-down power supply block 101 performs a step-down operation and supplies current from the external power supply 102 to the internal power supply 103. Operates to maintain 2.6V.

  On the other hand, at this time, the internal boost power supply block 112 has an external voltage that is half the voltage of the external power supply 102 by the third resistance element 115 and the fourth resistance element 116 in order to monitor the voltage of the external power supply 102. The power supply feedback voltage 117 is always generated. The external power supply feedback voltage 117 and the reference voltage 105 that is the constant voltage 1.3 V generated by the reference generation circuit 104 are input to the second amplifier circuit 118. Since the external power supply 102 is a normal voltage region and holds a voltage of 3.3 V, the external power supply feedback voltage 117 (= 1.65 V) exceeds the reference voltage 105 (= 1.3 V), and the two are compared. Then, the second amplifier circuit 118 outputs an L level signal as the second detection signal 119. Next, when the internal power supply 103 is lower than 2.6V, an operation of the internal step-down power supply block 101 causes an L level signal from the first amplifier circuit 106, and the internal power supply 103 decreases 2.6V. In the case where it exceeds the upper limit, an H level signal is output as the first detection signal 107, respectively. The first detection signal 107 is input to the gate of the step-down PMOS transistor 108 and simultaneously to the internal boost power supply block 112, more specifically, the first logic circuit 120 that is an inverter circuit. The first detection signal 107 is inverted through the first logic circuit 120 to be the third detection signal 121. When the internal power supply 103 is lower than 2.6V, the first detection signal 107 is H level, and the internal power supply 103 is 2 When it exceeds .6V, it is inputted to the second logic circuit 122 which is a NAND circuit as an L level logic signal. In the second logic circuit 122, when the internal power supply 103 is lower than 2.6V, the second detection signal 119 at L level and the third detection signal 121 at H level are set to 2. When the voltage exceeds 6 V, the L-level second detection signal 119 and the L-level third detection signal 121 are input, and the third detection signal 121 is either the H level or the L level. Also, since the second detection signal 119 is at the L level, the first logic signal 123 that is an H level logic signal is output. The oscillator circuit 114 does not output a reference signal generated internally because the first logic signal 123 that is an input is at an H level, and nothing is input to the pump circuit 113 in the subsequent stage. Not implemented.

  Therefore, the internal boost power supply block 112 does not perform the boost operation regardless of the voltage level of the internal power supply 103 when the external power supply 102 holds a voltage of 3.3 V, which is a normal voltage region.

  Therefore, when the external power supply 102 is in a normal voltage region, when the voltage level of the internal power supply 103 decreases, current is supplied only from the internal step-down power supply block 101 and the voltage of the internal power supply 103 is maintained at 2.6V. To work.

  Next, a region where the external power supply 102 is at a low voltage, for example, a case where the external power supply 102 is 2.5 V and the internal power supply 103 is 2.6 V will be described as an example.

  First, in the internal step-down power supply block 101, when the internal power supply 103 falls below a desired voltage of 2.6 V, the internal power supply 103 is divided into two minutes through the first resistance element 109 and the second resistance element 110. 1 (<1.3 V) is input to the first amplifier circuit 106 as the internal power supply feedback voltage 111. On the other hand, the reference voltage 105, which is a constant voltage of 1.3 V generated by the reference generation circuit 104, is also input to the first amplifier circuit 106, and voltage comparison is performed between the two. In this case, since the internal power supply feedback voltage 111 (<1.3 V) is lower than the reference voltage 105 (= 1.3 V), the first amplifier circuit 106 outputs the first detection signal 107 as a detection signal. An L level signal is output. In response to this, the gate input of the step-down PMOS transistor 108 becomes L level, the step-down PMOS transistor 108 is turned on to supply current from the external power supply 102 to the internal power supply 103, and the internal power supply 103 has a desired voltage of 2 It operates to increase to .6V, but since the voltage 2.5V of the external power supply 102 is lower than the desired voltage 2.6V of the internal power supply 103, the internal power supply 103 is increased only to 2.5V at the maximum. I can't. Since the internal power supply feedback voltage 111 is set to a half voltage of the internal power supply 103, the internal power supply feedback voltage 111 rises only to a maximum of 1.25V. In the first amplifier circuit 106, the internal power supply feedback voltage 111 is the reference voltage 105, and the reference voltage 105 is always higher, so the first detection signal 107, which is the output of the first amplifier circuit 106, remains at the L level, and the gate of the step-down PMOS transistor 108 Since the input also remains at the L level, the internal step-down power supply block 101 continues to operate and continues to supply current from the external power supply 102 to the internal power supply 103. Here, the other internal booster power supply block 112 operates simultaneously (described later) and supplies current to the internal power supply 103 so that the internal power supply 103 can maintain 2.6 V. When the voltage reaches 6V, the internal power supply feedback voltage 111 is set to a voltage half that of the internal power supply 103 and thus reaches 1.3V. In the first amplifier circuit 106, the internal power supply feedback voltage 111 is set to the reference voltage. Since the voltage is higher than the voltage 105, the first detection signal 107 is switched from the L level to the H level. In response to this, the gate input of the step-down PMOS transistor 108 is switched from the L level to the H level, so that the step-down PMOS transistor 108 is turned off and the current supply from the external power supply 102 to the internal power supply 103 is stopped.

  On the other hand, at this time, the internal boost power supply block 112 has an external voltage that is half the voltage of the external power supply 102 by the third resistance element 115 and the fourth resistance element 116 in order to monitor the voltage of the external power supply 102. The power supply feedback voltage 117 is always generated. The external power supply feedback voltage 117 and the reference voltage 105 that is the constant voltage 1.3 V generated by the reference generation circuit 104 are input to the second amplifier circuit 118. Since the external power supply 102 is a low voltage region and is a voltage of 2.5 V, the external power supply feedback voltage 117 (= 1.25 V) is lower than the reference voltage 105 (= 1.3 V). The second amplifier circuit 118 outputs an H level signal as the second detection signal 119. Next, when the internal power supply 103 is lower than 2.6V, an operation of the internal step-down power supply block 101 causes an L level signal from the first amplifier circuit 106, and the internal power supply 103 decreases 2.6V. In the case where it exceeds the upper limit, an H level signal is output as the first detection signal 107, respectively. The first detection signal 107 is input to the gate of the step-down PMOS transistor 108 and simultaneously to the internal boost power supply block 112, more specifically, the first logic circuit 120 that is an inverter circuit. The first detection signal 107 is inverted through the first logic circuit 120 to be the third detection signal 121. When the internal power supply 103 is lower than 2.6V, the first detection signal 107 is H level, and the internal power supply 103 is 2 When it exceeds .6V, it is inputted to the second logic circuit 122 which is a NAND circuit as an L level logic signal. In the second logic circuit 122, when the internal power supply 103 is lower than 2.6V, the second detection signal 119 at H level and the third detection signal 121 at H level are set to 2. When the voltage exceeds 6 V, an H level second detection signal 119 and an L level third detection signal 121 are input. When the internal power supply 103 is less than 2.6 V, that is, in a state where current supply is necessary, the second logic circuit 122 is generated from the second detection signal 119 at H level and the third detection signal 121 at H level. Outputs an L level signal to the first logic signal 123, and the oscillator circuit 114 outputs an internally generated reference signal to the pump circuit 113 as the second logic signal 124. Since the second logic signal 124 is input, the pump circuit 113 performs a boost operation, boosts the external power supply 102, supplies current to the internal power supply 103, and operates until the internal power supply 103 reaches 2.6V. . Then, after the internal power supply 103 reaches 2.6V or when the internal power supply 103 originally exceeds 2.6V, that is, in a state where no current supply is required, the third detection signal 121 is at the L level. Therefore, from the second detection signal 119 at the H level, the second logic circuit 122 outputs an H level signal to the first logic signal 123, and the oscillator circuit 114 outputs an internally generated reference signal. do not do. The pump circuit 113 does not perform the boosting operation because the second logic signal 124 is not input.

  As described above, when the external power supply 102 is in the low voltage region, the internal boost power supply block 112 is controlled to perform the boost operation according to the voltage level of the internal power supply 103, and the internal power supply 103 is set to a desired voltage. When the voltage of 2.6V is satisfied, the voltage boosting operation is not performed. When the internal power supply 103 is lower than 2.6V, the voltage boosting operation is performed until the voltage reaches 2.6V, and when the voltage reaches 2.6V, the voltage boosting operation is performed. Take action to stop.

  Therefore, when the external power supply 102 is in the low voltage region, when the voltage level of the internal power supply 103 decreases, current supply is performed from the internal step-down power supply block 101 to increase the voltage of the internal power supply 103 to 2.6V. However, when sufficient current cannot be supplied only by the operation of the internal step-down power supply block 101 (the voltage cannot be increased to 2.6 V), the internal step-up power supply block 112 is also operated to connect the external power supply 102. Then, the boosting operation is performed to maintain the internal power supply 103 at 2.6V.

  According to the configuration as described above, even when the voltage of the external power supply 102 falls below the voltage of the internal power supply 103 supplied to the memory, that is, even when the voltage of the external power supply 102 becomes low, the internal step-down power supply block 101 In addition to the current supply, the internal power supply 103 can be stably supplied to the memory by performing the current supply by the operation of the internal boosting power supply block 112. From the viewpoint of circuit area and power efficiency, Compared to the case where a plurality of internal booster circuits are mounted as in the conventional example, a large area reduction and power reduction can be realized simultaneously.

  In general, in a boost power supply circuit such as the internal boost power supply block 112, the voltage fluctuation noise of the internal power supply 103 due to the boost pump operation becomes large, and the power supply supplied to the memory varies. According to the configuration as described above, the voltage fluctuation noise of the internal power supply 103 due to the pump operation in the internal boost power supply block 112 performs voltage feedback in the internal buck power supply block 101, and the current from the internal buck power supply block 101 is also current. It is suppressed by taking the structure which supplies.

  Further, by sharing the reference generation circuit 104, the reference voltage 105, and the first detection signal 107 between the internal step-down power supply block 101 and the internal step-up power supply block 112, the circuit area can be reduced as compared with the case where each circuit is configured individually. Can be greatly reduced.

  In addition, an internal power supply feedback voltage 111 for detecting whether or not the internal power supply 103 is lowered, and an external power supply feedback voltage 117 for detecting whether or not the external power supply 102 is lowered are respectively connected to the first resistance elements. 109, the second resistance element 110, the third resistance element 115, and the fourth resistance element 116 are used to detect the voltage after being converted to a half voltage, so that the external power supply 102 is lower than the internal power supply 103. Even in this case, since the same level of voltage (about 1.3 V) as the internal power supply feedback voltage 111 can be supplied to the first amplifier circuit 106 and the second amplifier circuit 118, a stable detection operation can be realized. In this case, for example, the reference voltage 105 generated by the reference generation circuit 104 is 2.6 V, and the internal power supply 103 is input to the first amplifier circuit 106 as it is without voltage conversion and is detected. When the external power supply 102 drops to 2.5V, that is, when the voltage falls below 2.6V, which is the desired voltage of the internal power supply 103, the reference generation circuit 104 has a reference voltage 105 up to 2.5V. Therefore, even if the internal step-down power supply block 101 and the internal step-up power supply block 112 operate, the problem that the internal power supply 103 can only be raised to 2.5V can be solved. The external power supply feedback voltage 117 is also set to a half voltage of the external power supply 102 in accordance with the generation of the reference voltage 105 at a constant voltage of 1.3V.

  In this embodiment, the internal power supply feedback voltage 111 is set to a half voltage of the internal power supply 103, the external power supply feedback voltage 117 is set to a half voltage of the external power supply 102, and the reference voltage 105 is set to 1.3V. However, the present invention is not limited to this, and the same effect can be obtained if the internal power supply feedback voltage 111, the external power supply feedback voltage 117, and the reference voltage 105 are lower than the internal power supply 103. realizable.

  In this embodiment, an example in which the internal power supply feedback voltage 111, the external power supply feedback voltage 117, and the reference voltage 105 are set to voltages lower than the internal power supply 103 is shown. However, the present invention is not limited to this, and is shown as an example. Even if a higher voltage is set using a voltage conversion circuit such as a resistance element or a booster circuit, the reference voltage 105 can be externally supplied as a higher voltage using a voltage conversion circuit such as a resistance element or a booster circuit. Even when the power supply 102 has a low voltage, a sufficient operation as a power supply circuit can be realized, so that the same effect can be realized.

  In the present embodiment, an example in which a resistance element is used to generate the internal power supply feedback voltage 111 and the external power supply feedback voltage 117 has been described. However, the present invention is not limited to this, and another means for converting the voltage is used. However, the same effect can be realized.

  In the present embodiment, an example is shown in which both the internal step-down power supply block 101 and the internal step-up power supply block 112 are operated in a region where the external power supply 102 is at a low voltage. However, the present invention is not limited to this. In the low voltage region, it is possible to stop the operation of the internal step-down power supply block 101 and operate only the internal step-up power supply block 112 to supply the internal power supply 103. In this case, a logic circuit in which the first detection signal 107 and the second detection signal 119 are input to the gate input of the step-down PMOS transistor 108 in the internal step-down power supply block 101, more specifically an OR circuit or the like. When the external power supply 102 is in the low voltage region, that is, when the second detection signal 119 is at the H level, the gate input of the step-down PMOS transistor 108 may be set to the H level.

  In the present embodiment, an example in which the reference voltage 105 is set to a constant voltage of 1.3 V has been described. However, the present invention is not limited to this, and the same voltage may be set in the reference generation circuit 104. The effect can be realized. By setting the internal power supply feedback voltage 111 to an arbitrary voltage, the voltage of the internal power supply 103 supplied to the memory can be freely set. Therefore, the memory requires the internal power supply 103 having a plurality of voltages. It is possible to cope with even cases.

  In the present embodiment, an example is shown in which the internal boost power supply block 112 is operated when the external power supply 102 falls below 2.6 V, which is the voltage of the internal power supply 103. However, the present invention is not limited to this. For example, when the voltage difference between the internal power supply 103 and the internal power supply 103 becomes small, even if the internal boost power supply block 112 is operated when the external power supply 102 drops to a voltage of about 2.7 V, for example, the same effect can be obtained. realizable. In this case, the voltage difference between the external power supply 102 and the internal power supply 103 is reduced before power efficiency when current is supplied from the external power supply 102 to the internal power supply 103 via the step-down PMOS transistor 108 is reduced. By operating the internal boost power supply block 112 at the same time, it is possible to suppress a reduction in power efficiency when the internal power supply 103 is supplied.

<< Second Embodiment >>
FIG. 2 is a diagram showing a schematic configuration of a semiconductor integrated circuit including an internal power supply circuit according to the second embodiment of the present invention. Embodiments of the present invention in a typical internal power generation operation of a semiconductor integrated circuit including an internal power supply circuit will be described below.

  In addition, the same code | symbol is provided about the component which has the same structure as the component described in FIG. 1 among the components of FIG.

  The semiconductor integrated circuit according to the second embodiment of the present invention includes an internal step-down power supply block 200, an internal step-up power supply block 201, and a reference generation circuit 104.

  The internal step-down power supply block 200 includes a 3.3V external power supply 102, an internal power supply 103 that requires 2.6V, a reference voltage 105 that is a 1.3V constant voltage generated from a constant voltage source or the like in the reference circuit 104, A first amplifier circuit 106 and a first amplifier circuit which output a detection signal L level when a reference voltage 105 and an internal power supply feedback voltage 111 described later are input and the internal power supply feedback voltage 111 becomes lower than the reference voltage 105. Based on the first detection signal 107 which is a detection signal generated at 106, the voltage of the step-down PMOS transistor 108 for generating the internal power supply 103 from the external power supply 102 or the internal boosting power supply 204 described later, and the voltage of the internal power supply 103. First resistance element 10 for outputting a half voltage of internal power supply 103 The second resistance element 110 having the same resistance value as the first resistance element 109, and the internal power supply that is output from the internal power supply 103 through the first resistance element 109 as a half voltage value of the internal power supply 103 The feedback voltage 111, an internal boost power supply 204 generated by an internal boost power supply block 201 described later, and an inverter circuit for inverting the signal logic of a second detection signal 119 generated in the internal boost power supply block 201 described later. The first logic circuit 205, the third detection signal 206 which is a signal obtained by inverting the signal logic of the second detection signal 119 by the first logic circuit 205, the source node of the external power supply 102 and the step-down PMOS transistor 108 And a node between both ends are connected when the third detection signal 206 is at an H level. A first switch 202 that is disconnected when the level is low, and a connection between an internal boosting power source 204 described later and the source node of the step-down PMOS transistor 108 are controlled by a second detection signal 119, and the second detection signal 119 is H The second switch 203 is configured to connect nodes at both ends at the level and to disconnect at the L level.

  The internal boost power supply block 201 includes a 3.3 V external power supply 102, an internal boost power supply 204 generated by performing a boost operation, a pump circuit 113 for boosting the external power supply 102 to generate the internal boost power supply 204, and the external power supply 102. Is automatically generated, and an oscillator circuit 114 for controlling whether or not to output this reference signal according to the level of the input control signal is generated based on the external power supply 102. Through the third resistance element 115 for outputting a half voltage of the external power supply 102, the fourth resistance element 116 having the same resistance value as the third resistance element 115, and the third resistance element 115. The external power supply feedback voltage 117, the reference voltage 105, and the external power supply feedback voltage 117 output as a half voltage value of the external power supply 102 The second amplifier circuit 118 that outputs the detection signal H level when the external power supply feedback voltage 117 becomes lower than the reference voltage 105, and is a detection signal generated by the second amplifier circuit 118 and an internal step-down power supply block The second detection signal 119 input also to the second detection signal 119, the second logic circuit 207 configured by an inverter circuit for inverting the signal logic of the second detection signal 119, and the second logic circuit 207 via the second logic circuit 207. 2 is a signal obtained by inverting the signal logic of the detection signal 119, the first logic signal 208 for controlling whether or not to output the reference signal generated by the oscillator circuit 114, and output from the oscillator circuit 114 to the pump circuit 113. It is composed of a second logic signal 124 that is an input oscillator signal for performing an internal boosting operation.

  In the internal step-down power supply block 200, the external power supply 102 passes through the first switch 202, or the internal booster power supply 204, which will be described later, passes through the second switch 203, and then passes through the step-down PMOS transistor 108. Current is supplied to the memory (not shown) as the internal power supply 103. The connection between the first switch 202 and the second switch 203 is switched by a second detection signal 119 generated by an internal boosting power supply block 201 described later according to the voltage level of the external power supply 102.

  On the other hand, in the internal boost power supply block 201, the external power supply 102 is supplied to the pump circuit 113, and when the second logic signal 124 for operating the pump circuit 113 is input from the oscillator circuit 114, the external power supply 102 is boosted. Thus, an internal boost power supply 204 is generated and supplied to the internal step-down power supply block 200. The oscillator circuit 114 generates a reference signal that is automatically generated internally with the supply of the external power supply 102 when the first logic signal 208, which is an inverted signal of the second detection signal 119, is at the L level. The circuit configuration is such that the signal 124 is output and nothing is output when the first logic signal 208 is at the H level.

  Regarding the second embodiment of the present invention configured as described above, first, an example where the external power supply 102 is in a normal voltage region, for example, the external power supply 102 is 3.3 V and the internal power supply 103 is 2.6 V is taken as an example. Will be described.

  First, in the internal step-down power supply block 200, when the internal power supply 103 falls below a desired voltage of 2.6 V, the internal power supply 103 is divided into two minutes through the first resistance element 109 and the second resistance element 110. 1 (<1.3 V) is input to the first amplifier circuit 106 as the internal power supply feedback voltage 111. On the other hand, the reference voltage 105, which is a constant voltage of 1.3 V generated by the reference generation circuit 104, is also input to the first amplifier circuit 106, and voltage comparison is performed between the two. In this case, since the internal power supply feedback voltage 111 (<1.3 V) is lower than the reference voltage 105 (= 1.3 V), the first amplifier circuit 106 outputs the first detection signal 107 as a detection signal. An L level signal is output. In response, the gate input of the step-down PMOS transistor 108 becomes L level, and the step-down PMOS transistor 108 is turned on. On the other hand, at this time, in the internal boost power supply block 201, since the external power supply 102 is 3.3 V, the third resistance element 115 and the fourth resistance element 116 for monitoring the voltage of the external power supply 102 are externally connected. An external power supply feedback voltage 117 (= 1.65 V) that is a half voltage of the power supply 102 is constantly generated. The external power supply feedback voltage 117 and the reference voltage 105 that is the constant voltage 1.3 V generated by the reference generation circuit 104 are input to the second amplifier circuit 118. Since the external power supply 102 is a normal voltage region and holds a voltage of 3.3 V, the external power supply feedback voltage 117 (= 1.65 V) exceeds the reference voltage 105 (= 1.3 V), and the two are compared. Then, the second amplifier circuit 118 outputs an L level signal as the second detection signal 119. In response to the fact that the second detection signal 119 is at the L level, in the internal step-down power supply block 200, the third detection signal 206, which is an inverted signal of the second detection signal 119, becomes an H level signal. An H level is applied to the first switch 202, and the first switch 202 is connected. On the other hand, since the second detection signal 119 is applied to the second switch 203 as the L level, the second switch 203 is in an open state, and the internal boost power supply 204 and the step-down PMOS transistor 108 are not connected. Open state.

  As a result, the first switch 202 is connected, the second switch 203 is turned off, and the step-down PMOS transistor 108 is turned on, so that the external power supply 102 is stepped down with the first switch 202 to the internal power supply 103. A current is supplied through the PMOS transistor 108 to raise the internal power supply 103 to a desired voltage of 2.6V. When a sufficient current is supplied to the internal power supply 103 and reaches the desired voltage of 2.6 V, the internal power supply feedback voltage 111 is set to a voltage half that of the internal power supply 103 and is thus set to 1.3 V. In the first amplifier circuit 106, since the internal power supply feedback voltage 111 becomes higher than the reference voltage 105, the first detection signal 107 is switched from the L level to the H level. In response to this, the gate input of the step-down PMOS transistor 108 is switched from the L level to the H level, so that the step-down PMOS transistor 108 is turned off and the current supply from the external power supply 102 to the internal power supply 103 is stopped.

  In this way, the internal step-down power supply block 200 performs the step-down operation when the internal power supply 103 falls below the desired voltage of 2.6 V, and supplies current from the external power supply 102 to the internal power supply 103. Operates to maintain 2.6V.

  On the other hand, at this time, the internal boost power supply block 201 is half of the external power supply 102 by the third resistance element 115 and the fourth resistance element 116 for monitoring the voltage of the external power supply 102 as described above. The external power supply feedback voltage 117 that is a voltage is constantly generated. The external power supply feedback voltage 117 and the reference voltage 105 that is the constant voltage 1.3 V generated by the reference generation circuit 104 are input to the second amplifier circuit 118. Since the external power supply 102 is a normal voltage region and holds a voltage of 3.3 V, the external power supply feedback voltage 117 (= 1.65 V) exceeds the reference voltage 105 (= 1.3 V), and the two are compared. Then, the second amplifier circuit 118 outputs an L level signal as the second detection signal 119. In response to the output of the second detection signal 119 to an L level, an H level signal is output to the first logic signal 208 that is the input of the oscillator circuit 114 via the second logic circuit 207. Since the first logic signal 208 that is an input is input at the H level, the oscillator circuit 114 does not output the internally generated reference signal and does not input anything to the pump circuit 113 in the subsequent stage, so that the voltage is boosted. The action is not performed.

  For this reason, the internal boosting power supply block 201 does not perform the boosting operation regardless of the voltage level of the internal power supply 103 when the external power supply 102 holds a voltage of 3.3 V, which is a normal voltage region. Also, no current is supplied as the internal boosting power source 204.

  Therefore, when the external power supply 102 is in the normal voltage range, when the voltage level of the internal power supply 103 decreases, current is supplied only from the internal step-down power supply block 200 and the voltage of the internal power supply 103 is maintained at 2.6V. To work.

  Next, a region where the external power supply 102 is at a low voltage, for example, a case where the external power supply 102 is 2.5 V and the internal power supply 103 is 2.6 V will be described as an example.

  First, in the internal step-down power supply block 200, when the internal power supply 103 falls below a desired voltage of 2.6 V, the internal power supply 103 is divided into two minutes through the first resistance element 109 and the second resistance element 110. 1 (<1.3 V) is input to the first amplifier circuit 106 as the internal power supply feedback voltage 111. On the other hand, the reference voltage 105, which is a constant voltage of 1.3 V generated by the reference generation circuit 104, is also input to the first amplifier circuit 106, and voltage comparison is performed between the two. In this case, since the internal power supply feedback voltage 111 (<1.3 V) is lower than the reference voltage 105 (= 1.3 V), the first amplifier circuit 106 outputs the first detection signal 107 as a detection signal. An L level signal is output. In response, the gate input of the step-down PMOS transistor 108 becomes L level, and the step-down PMOS transistor 108 is turned on. On the other hand, at this time, in the internal boost power supply block 201, since the external power supply 102 is 2.5 V, the third resistance element 115 and the fourth resistance element 116 for monitoring the voltage of the external power supply 102 are externally connected. An external power supply feedback voltage 117 (= 1.25 V), which is a half voltage of the power supply 102, is always generated. The external power supply feedback voltage 117 and the reference voltage 105 that is the constant voltage 1.3 V generated by the reference generation circuit 104 are input to the second amplifier circuit 118. Since the external power supply 102 is a low voltage region and is a voltage of 2.5 V, the external power supply feedback voltage 117 (= 1.25 V) is lower than the reference voltage 105 (= 1.3 V). The second amplifier circuit 118 outputs an H level signal as the second detection signal 119. In response to the fact that the second detection signal 119 is at the H level, in the internal step-down power supply block 200, the third detection signal 206 that is an inverted signal of the second detection signal 119 is an L level signal. The L level is applied to the first switch 202, and the first switch 202 is opened. On the other hand, since the second detection signal 119 is applied as the H level to the second switch 203, the second switch 203 is connected, and the internal boosting power source 204 and the step-down PMOS transistor 108 are connected. It becomes the state. That is, since the internal boost power supply 204 boosted by the internal boost power supply block 201 described later is supplied to the internal step-down power supply block 200, the internal boost power supply 204 internally passes through the second switch 203 and the step-down PMOS transistor 108. A current is supplied to the power supply 103 to raise the internal power supply 103 to a desired voltage of 2.6V. When the internal power supply 103 reaches 2.6 V, the internal power supply feedback voltage 111 is set to a voltage half that of the internal power supply 103 and thus reaches 1.3 V. In the first amplifier circuit 106, Since the power supply feedback voltage 111 becomes higher than the reference voltage 105, the first detection signal 107 is switched from the L level to the H level. In response to this, the gate input of the step-down PMOS transistor 108 is switched from the L level to the H level, so that the step-down PMOS transistor 108 is turned off, and the current supply from the internal boost power supply 204 to the internal power supply 103 is stopped.

  On the other hand, at this time, in the internal boost power supply block 201, the third resistance element 115 and the fourth resistance element 116 for monitoring the voltage of the external power supply 102 are external voltages that are half the voltage of the external power supply 102. A power supply feedback voltage 117 (= 1.25 V) is constantly generated. The external power supply feedback voltage 117 and the reference voltage 105 that is the constant voltage 1.3 V generated by the reference generation circuit 104 are input to the second amplifier circuit 118. Since the external power supply 102 is a low voltage region and is a voltage of 2.5 V, the external power supply feedback voltage 117 (= 1.25 V) is lower than the reference voltage 105 (= 1.3 V). The second amplifier circuit 118 outputs an H level signal as the second detection signal 119. In response to the output of the second detection signal 119 at the H level, an L level signal is output to the first logic signal 208 that is the input of the oscillator circuit 114 via the second logic circuit 207. Since the first logic signal 208 as an input is input at the L level, the oscillator circuit 114 outputs the internally generated reference signal to the pump circuit 113 as the second logic signal 124. The pump circuit 113 In response to this, a boosting operation is performed. The internal boost power supply 204 boosted by the pump circuit 113 is supplied to the internal step-down power supply block 200, and becomes the current source for supplying current to the internal power supply 103 by the operation of the internal step-down power supply block 200 described above. The operation at 200 supplies current until the internal power supply 103 reaches a desired voltage of 2.6V. When the external power supply 102 again exceeds the desired voltage of 2.6 V, which is the internal power supply 103, the external power supply feedback voltage 117 exceeds 1.3 V, so that the second output that is the output of the second amplifier circuit 118 is output. The detection signal 119 is switched from the H level to the L level, and the first logic signal 208 that is an input signal to the oscillator circuit 114 is switched from the L level to the H level via the second logic circuit 207 that is an inverter circuit. In response to this, the oscillator circuit 114 stops outputting the internally generated reference signal to the pump circuit 113, and the pump circuit 113 stops the boosting operation.

  As described above, when the external power supply 102 is in the low voltage region, the internal boost power supply block 201 is controlled to perform the boost operation according to the voltage level of the external power supply 102. When the voltage exceeds 2.6V, which is the desired voltage, the boost operation is not performed. When the external power supply 102 is less than 2.6V, the voltage boost operation is performed. When the voltage exceeds 2.6V, the voltage boost operation is stopped. Take action to do.

  Therefore, when the external power supply 102 is in a low voltage region, when the voltage level of the internal power supply 103 decreases, the internal step-down power supply block 200 cannot supply sufficient current from the external power supply 102 to the internal power supply 103. A current is supplied to the internal step-down power supply block 200 instead of the external power supply 102 using the internal step-up power supply 204 boosted in the step-up power supply block 201 as a power source, and the internal boost power supply 204 passes through the second switch 203 and the step-down PMOS transistor 108. The current is supplied to the internal power supply 103 to maintain the internal power supply 103 at a desired voltage of 2.6V.

  According to the configuration as described above, even when the voltage of the external power supply 102 falls below the voltage of the internal power supply 103 supplied to the memory, that is, when the voltage of the external power supply 102 becomes low, the internal step-down power supply block 200 By switching the power supply for supplying current to the internal power supply 103 from the external power supply 102 to the internal boost power supply 204 and supplying the current to the internal power supply 103, it becomes possible to supply a stable internal power supply 103 to the memory. Also from the viewpoint of power efficiency, a large area reduction and power reduction can be realized at the same time as in the case where a plurality of internal booster circuits are mounted as in the conventional example.

  Further, by sharing the reference generation circuit 104, the reference voltage 105, and the second detection signal 119 between the internal step-down power supply block 200 and the internal step-up power supply block 201, the circuit area can be reduced compared to the case where each circuit is individually configured. Can be greatly reduced.

  In addition, an internal power supply feedback voltage 111 for detecting whether or not the internal power supply 103 is lowered, and an external power supply feedback voltage 117 for detecting whether or not the external power supply 102 is lowered are respectively connected to the first resistance elements. 109, the second resistance element 110, the third resistance element 115, and the fourth resistance element 116 are used to detect the voltage after being converted to a half voltage, so that the external power supply 102 is lower than the internal power supply 103. Even in this case, since the same level of voltage (about 1.3 V) as the internal power supply feedback voltage 111 can be supplied to the first amplifier circuit 106 and the second amplifier circuit 118, a stable detection operation can be realized. In this case, for example, the reference voltage 105 generated by the reference generation circuit 104 is 2.6 V, and the internal power supply 103 is input to the first amplifier circuit 106 as it is without voltage conversion and is detected. When the external power supply 102 drops to 2.5V, that is, when the voltage falls below 2.6V, which is the desired voltage of the internal power supply 103, the reference generation circuit 104 has a reference voltage 105 up to 2.5V. Therefore, even if the internal step-down power supply block 200 and the internal step-up power supply block 201 are operated, the problem that the internal power supply 103 can only be raised to 2.5V can be solved. The external power supply feedback voltage 117 is also set to a half voltage of the external power supply 102 in accordance with the generation of the reference voltage 105 at a constant voltage of 1.3V.

  In this embodiment, the internal power supply feedback voltage 111 is set to a half voltage of the internal power supply 103, the external power supply feedback voltage 117 is set to a half voltage of the external power supply 102, and the reference voltage 105 is set to 1.3V. However, the present invention is not limited to this, and the same effect can be obtained if the internal power supply feedback voltage 111, the external power supply feedback voltage 117, and the reference voltage 105 are lower than the internal power supply 103. realizable.

  In this embodiment, an example in which the internal power supply feedback voltage 111, the external power supply feedback voltage 117, and the reference voltage 105 are set to voltages lower than the internal power supply 103 is shown. However, the present invention is not limited to this, and is shown as an example. Even if a higher voltage is set using a voltage conversion circuit such as a resistance element or a booster circuit, the reference voltage 105 can be externally supplied as a higher voltage using a voltage conversion circuit such as a resistance element or a booster circuit. Even when the power supply 102 has a low voltage, a sufficient operation as a power supply circuit can be realized, so that the same effect can be realized.

  In the present embodiment, an example in which a resistance element is used to generate the internal power supply feedback voltage 111 and the external power supply feedback voltage 117 has been described. However, the present invention is not limited to this, and another means for converting the voltage is used. However, the same effect can be realized.

  In the present embodiment, an example in which the reference voltage 105 is set to a constant voltage of 1.3 V has been described. However, the present invention is not limited to this, and the same voltage may be set in the reference generation circuit 104. The effect can be realized. By setting the internal power supply feedback voltage 111 to an arbitrary voltage, the voltage of the internal power supply 103 supplied to the memory can be freely set. Therefore, the memory requires the internal power supply 103 having a plurality of voltages. It is possible to cope with even cases.

  In the present embodiment, an example is shown in which the internal booster power supply block 201 is operated when the external power supply 102 falls below 2.6 V, which is the voltage of the internal power supply 103. However, the present invention is not limited to this. For example, when the voltage difference between the internal power supply 103 and the internal power supply 103 becomes small, even if the internal boost power supply block 201 is operated when the external power supply 102 drops to a voltage of about 2.7 V, for example, the same effect can be obtained. realizable. In this case, when the voltage difference between the external power supply 102 and the internal power supply 103 is reduced, a current is supplied from the external power supply 102 to the internal power supply 103 via the first switch 202 and the step-down PMOS transistor 108. By operating the internal boost power supply block 201 before the power efficiency decreases, it is possible to suppress the power efficiency from decreasing when the internal power supply 103 is supplied.

<< Third Embodiment >>
FIG. 3 is a diagram showing a schematic configuration of a semiconductor integrated circuit including an internal power supply circuit according to the third embodiment of the present invention. Embodiments of the present invention in a typical internal power generation operation of a semiconductor integrated circuit including an internal power supply circuit will be described below.

  In addition, the same code | symbol is provided about the component which has the same structure as the component described in FIG. 1 among the components of FIG.

  In addition to the configuration of the first embodiment of the present invention, in this embodiment, when the output of the internal step-down power supply block 101 and the output of the internal boost power supply block 300 are combined to form the internal power supply 103, the internal boost power supply The block 300 includes a circuit in which a filter composed of a fifth resistance element 301 and a capacitive element 302 is added on the output path of the pump circuit 113. The operation of the internal step-down power supply block 101 is the same as that of the first embodiment of the present invention.

  In general, when the internal power supply 103 is generated by performing the boosting operation internally, voltage fluctuation noise propagates to the internal power supply 103 due to voltage fluctuation caused by the pump operation, and a stable supply of the internal power supply 103 is achieved. When it becomes difficult or the voltage of the internal power supply 103 greatly exceeds the voltage of the external power supply 102, the current flows backward from the internal power supply 103 to the external power supply 102 via the step-down PMOS transistor 108. There is a concern that it will end up.

  On the other hand, according to the configuration of the present embodiment, by adding the fifth resistance element 301 and the capacitive element 302 to the output part of the internal power supply 103 in the internal boost power supply block 300, the pump The voltage fluctuation noise of the internal power supply 103 caused by the boosting operation in the circuit 113 is suppressed via the fifth resistance element 301 and the capacitive element 302, and the voltage fluctuation noise to the internal power supply 103 supplied to the memory is filtered. It becomes possible to supply as a more stable power supply.

  As a result, it is possible to supply the internal power supply 103 generated by the step-up / step-down operation to the memory as a more stable power supply without adding a complicated circuit and suppressing an increase in circuit area.

  In the present embodiment, a configuration in which a resistance element and a capacitance element are added to the internal power supply 103 is shown as an example. However, the present invention is not limited to this, and other means for suppressing voltage fluctuation, a clamp circuit, and protection The same effect can be realized by using a circuit or the like having a similar function for suppressing voltage fluctuation noise and current backflow.

  Further, in the case where a clamp circuit is used, even if the voltage of the internal power supply 103 exceeds the voltage of the external power supply 102, the current is prevented from flowing back from the internal power supply 103 to the external power supply 102. This effect can also be realized.

  In the present embodiment, an example in which voltage fluctuation suppression means is added to the internal boost power supply block 300 side is shown, but the present invention is not limited to this, and voltage fluctuation suppression means, a clamp circuit, The same effect can be realized even if a protection circuit or the like is installed.

<< Fourth Embodiment >>
FIG. 4 is a diagram showing a schematic configuration of a semiconductor integrated circuit including an internal power supply circuit according to the fourth embodiment of the present invention. Embodiments of the present invention in a typical internal power generation operation of a semiconductor integrated circuit including an internal power supply circuit will be described below.

  In addition, the same code | symbol is provided about the component which has the same structure as the component described in FIG. 1 among the components of FIG.

  In contrast to the configuration of the first embodiment of the present invention, in the present embodiment, in the internal step-down power supply block 400, the step-down NMOS transistor 401 and the first detection signal 107 are used instead of the step-down PMOS transistor 108. The third logic circuit 402, which is an inverter circuit for inverting the signal logic, and the fourth detection signal 403 output from the third logic circuit 402. The operation of the internal boost power supply block 112 is the same as that of the first embodiment of the present invention.

  Regarding the operation of the internal step-down power supply block 400, when the voltage of the internal power supply 103 falls below the desired voltage of 2.6 V and the current supply from the external power supply 102 becomes necessary, the first amplifier circuit 106 An L level first detection signal 107 is output. The first detection signal 107 becomes an inverted H level signal via the third logic circuit 402 that is an inverter circuit, and is input to the gate of the step-down NMOS transistor 401 as the fourth detection signal 403. . The step-down NMOS transistor 401 is turned on when an H level is applied to the gate, supplies current from the external power supply 102 to the internal power supply 103, and operates to maintain the internal power supply 103 at 2.6V.

  According to the above configuration, as in the first embodiment of the present invention, even when the voltage of the external power supply 102 decreases, the internal power supply 103 can be stably supplied, and the internal power supply 103 can be supplied. Even if the voltage exceeds the voltage of the external power supply 102, the back-down current can be prevented because the step-down transistor is composed of the NMOS transistor 401.

  As a result, the internal power supply 103 generated by the step-up / step-down operation is made more stable without changing the circuit area simply by changing the step-down transistor configuration with respect to the configuration of the first embodiment of the present invention. It is possible to prevent reverse current flow by supplying.

  In addition, you may combine each component in the said 1st-4th embodiment arbitrarily in the range which does not deviate from the meaning of this invention.

  The semiconductor integrated circuit according to the present invention is effective in stabilizing the generation of internal power, improving the operating voltage range, and reducing the circuit area with respect to lowering the SoC power supply specifications and lowering the external power supply voltage due to power supply voltage fluctuations. In particular, it is useful as a semiconductor integrated circuit having an internal power supply circuit.

101 Internal power supply block 102 External power supply 103 Internal power supply 104 Reference generation circuit 105 Reference voltage 106 First amplifier circuit 107 First detection signal 108 Step-down PMOS transistor 109 First resistance element 110 Second resistance element 111 Internal power supply Feedback voltage 112 Internal boost power supply block 113 Pump circuit 114 Oscillator circuit 115 Third resistance element 116 Fourth resistance element 117 External power supply feedback voltage 118 Second amplifier circuit 119 Second detection signal 120 First logic circuit 121 First logic circuit 121 3 detection signal 122 second logic circuit 123 first logic signal 124 second logic signal 200 internal step-down power supply block 201 internal boost power supply block 202 first switch 203 second switch 204 internal boost power supply 205 first Logic circuit 206 Third detection signal 207 Second logic circuit 208 First logic signal 300 Internal boost power supply block 301 Fifth resistance element 302 Capacitance element 400 Internal step-down power supply block 401 Step-down NMOS transistor 402 Third logic circuit 403 Fourth detection signal

Claims (19)

An internal step-down power supply block that performs step-down operation based on an external power supply;
An internal boost power supply block that performs a boost operation based on the external power supply,
In the region where the external power supply is a normal voltage, an internal power supply of a desired voltage is generated using only the internal step-down power supply block, and in the region where the external power supply is a low voltage, in addition to the internal step-down power supply block Or an internal power supply of the desired voltage using the internal boost power supply block instead of the internal step-down power supply block. The semiconductor integrated circuit according to claim 1,
The semiconductor integrated circuit according to claim 1, wherein the internal boost power supply block determines whether or not to operate according to a voltage value of the external power supply. The semiconductor integrated circuit according to claim 1,
The semiconductor integrated circuit according to claim 1, wherein the internal step-down power supply block determines whether or not to operate according to a voltage value of the external power supply. The semiconductor integrated circuit according to claim 1,
A reference generation circuit for generating a predetermined voltage;
A semiconductor integrated circuit, wherein a reference voltage generated by the reference generation circuit is input to the internal step-down power supply block and the internal step-up power supply block. The semiconductor integrated circuit according to claim 4, wherein
A semiconductor integrated circuit characterized in that the reference voltage is variable to a desired value in the reference generation circuit. The semiconductor integrated circuit according to claim 4 or 5,
The internal step-down power supply block is:
A first voltage conversion circuit for converting the voltage of the internal power source into a first feedback voltage;
A semiconductor integrated circuit comprising: a first internal power supply control circuit that inputs the first feedback voltage and the reference voltage and outputs a first detection signal. The semiconductor integrated circuit according to any one of claims 4 to 6,
The semiconductor integrated circuit, wherein the reference voltage and the first feedback voltage are lower than a voltage of the internal power supply. The semiconductor integrated circuit according to claim 6 or 7,
The internal step-down power supply block further includes a first internal power supply generation circuit that receives the first detection signal and generates the internal power supply from the external power supply, and the first internal power supply generation circuit includes a PMOS transistor. A semiconductor integrated circuit comprising: The semiconductor integrated circuit according to any one of claims 4 to 8,
The internal boost power supply block is
A second voltage conversion circuit for converting the voltage of the external power source into a second feedback voltage;
A semiconductor integrated circuit, comprising: a second internal power supply control circuit that inputs the second feedback voltage and the reference voltage and outputs a second detection signal. The semiconductor integrated circuit according to any one of claims 4 to 9,
The semiconductor integrated circuit, wherein the second feedback voltage is lower than voltages of the external power supply and the internal power supply. The semiconductor integrated circuit according to claim 9 or 10,
The second internal power supply control circuit includes:
A first logic circuit that receives the first detection signal and outputs a third detection signal;
A semiconductor integrated circuit comprising: a second logic circuit that receives the second detection signal and the third detection signal and outputs a first logic signal. The semiconductor integrated circuit according to claim 11, wherein
The internal boosted power supply block further includes a second internal power supply generation circuit that receives the first logic signal and outputs the internal power supply. The semiconductor integrated circuit according to any one of claims 1 to 12,
A semiconductor integrated circuit, further comprising a noise removal circuit or a protection circuit in a power supply wiring of the internal power supply. The semiconductor integrated circuit according to claim 13.
The semiconductor integrated circuit, wherein the noise removal circuit or the protection circuit is disposed in the internal boost power supply block. The semiconductor integrated circuit according to claim 13.
The semiconductor integrated circuit, wherein the noise removal circuit or the protection circuit is disposed in the internal step-down power supply block. The semiconductor integrated circuit according to claim 6 or 7,
The internal step-down power supply block further includes a first internal power supply generation circuit that receives the first detection signal and generates the internal power supply from the external power supply, and the first internal power supply generation circuit includes an NMOS transistor. A semiconductor integrated circuit comprising: An internal step-down power supply block that performs step-down operation based on the selected power supply;
An internal boost power supply block that generates an internal boost power supply based on an external power supply,
In the region where the external power supply is a normal voltage, the internal step-down power supply block generates an internal power supply of a desired voltage from the external power supply, and in the region where the external power supply is a low voltage, the internal boost power supply block is generated. A semiconductor integrated circuit, wherein the internal step-down power supply block generates an internal power supply of the desired voltage from the internal boosted power supply. The semiconductor integrated circuit according to claim 17.
The semiconductor integrated circuit according to claim 1, wherein the internal boost power supply block determines whether or not to operate according to a voltage value of the external power supply. The semiconductor integrated circuit according to claim 17.
Whether the internal step-down power supply block generates the internal power supply based on the external power supply or the internal boosted power supply is connected to the external power supply by a detection signal generated according to the voltage value of the external power supply The semiconductor integrated circuit is controlled by connecting one of the first switch and the second switch connected to the internal boost power supply.

Images