JP2013070168A - Flat surface type x-ray sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flat surface type X-ray sensor in which an internal driving timing and an external reference clock are matched with each other.SOLUTION: An X-ray generating apparatus generates X-ray at a predetermined time interval on the basis of an external reference clock, and a flat surface type X-ray sensor picks up X-ray images obtained by transmitting the generated X-ray through an imaging target object. An internal driving signal generating circuit 50 for generating an internal driving signal for the flat surface type X-ray sensor is provided with a PLL-based reference clock generating circuit 51. The reference clock generating circuit 51 has a voltage controlled oscillator 62, a frequency dividing circuit 63, and a phase comparing circuit 61. The voltage controlled oscillator 62 generates an internal reference clock by using a quartz oscillator, for example. The frequency dividing circuit 63 divides the internal reference clock by a predetermined frequency division ratio and outputs a frequency-divided clock. The phase comparing circuit 61 compares the phase of the external reference clock and the phase of the frequency-divided clock and inputs the phase difference into the voltage controlled oscillator 62.

Description

  This embodiment relates to a planar X-ray sensor.

  The incident X-ray is converted into light, and the light is taken out as an electric signal using photoelectric conversion elements arranged in an array on a plane, so that an X-ray image is output as a real-time digital signal. A solid state detector using a photoelectric conversion element array in which photoelectric conversion elements are arranged has been developed. Since it is a flat solid detector, it has excellent image quality and stability.

  This solid state detector is used together with an external device such as an X-ray generator. In general, an external device such as an X-ray generator generates a signal for generating X-rays based on an external reference clock and irradiates the X-rays. The photoelectric conversion element array converts the X-ray dose incident through the subject among the irradiated X-rays into electric charges and takes them out as electric signals. The external device also transmits an external reference clock to the planar X-ray sensor. However, a planar X-ray sensor using a photoelectric conversion element array usually generates an internal reference clock having a constant frequency by an internal clock generation circuit. Then, by dividing the clock, a drive signal that determines the internal operation timing is generated.

  The external device may change the synchronization frequency by changing the external reference clock depending on the object to be measured and the measurement content.

JP 2002-152599 A

  In the flat X-ray sensor, an image is a digital signal, and generally, the flat X-ray sensor operates on the basis of a timing signal provided at a specific frequency generated inside. For this reason, the operation cannot be completely synchronized with an external reference clock transmitted from an external device such as an X-ray generator, and an internal timing and deviation occur. As a result, the image may be disturbed.

  For example, when the internal read operation and the external synchronization signal match, a measure such as prohibiting the read for one cycle is performed. Since there is a leak charge in the photoelectric conversion element arranged in the flat sensor, if the internal readout is stopped for one cycle, the leak charge leaks to the image signal, resulting in fluctuations in the luminance level, image unevenness, etc. The problem will occur.

  Therefore, each embodiment aims to match the internal drive timing of the photoelectric conversion element array with the external reference clock that is a reference for the operation of the external device as much as possible.

  In order to solve the above-described problem, the planar X-ray sensor according to the embodiment captures an X-ray image in which an X-ray generation apparatus transmits X-rays generated at predetermined time intervals through an object to be photographed based on an external reference clock. In a planar X-ray sensor, a plurality of photoelectric conversion elements arranged two-dimensionally, a switching element provided for each of the photoelectric conversion elements, and the switching element provided for each row of the photoelectric conversion elements A photoelectric conversion element array having a gate line connected to each of the photoelectric conversion elements and a data line provided to each column of the photoelectric conversion elements and connected to the photoelectric conversion element via the switching element, and an internal reference clock A voltage-controlled oscillator to be generated, and a frequency dividing circuit that divides the internal reference clock by a predetermined frequency dividing ratio and outputs a frequency-divided clock; A phase comparison circuit that compares phases of the external reference clock and the divided clock and inputs the phase difference to the voltage controlled oscillator, and generates an internal drive signal based on the internal reference clock. A signal generation circuit; a gate drive circuit that applies a gate drive signal to the gate line based on the internal drive signal; and a readout that reads out a pixel signal from the photoelectric conversion element array via the data line based on the internal drive signal And a circuit.

  In addition, the planar X-ray sensor according to the embodiment is a planar X-ray sensor that captures an X-ray image in which an X-ray generated by a X-ray generator at a predetermined time interval based on an external reference clock passes through an object to be imaged. A plurality of photoelectric conversion elements arranged two-dimensionally, a switching element provided for each of the photoelectric conversion elements, and a gate provided for each row of the photoelectric conversion elements and connected to the switching elements A photoelectric conversion element array having a line and a data line provided for each column of the photoelectric conversion elements and connected to the photoelectric conversion elements via the switching elements, and generating a fixed clock of a predetermined frequency Count the number of clocks of the fixed clock in one cycle of the reference oscillator and the external reference clock, and divide based on the number of clocks An internal drive that generates an internal drive signal based on the internal reference clock, and a frequency determination circuit that calculates an internal reference clock by dividing the fixed clock by the division ratio A signal generation circuit; a gate drive circuit that applies a gate drive signal to the gate line based on the internal drive signal; and a readout that reads out a pixel signal from the photoelectric conversion element array via the data line based on the internal drive signal And a circuit.

1 is a block diagram of a planar X-ray sensor according to a first embodiment. 1 is a block diagram of an X-ray imaging system according to a first embodiment. It is a typical perspective view of the photoelectric conversion element array by 1st Embodiment. It is an equivalent circuit diagram of the photoelectric conversion element array according to the first embodiment. It is a timing chart in a 1st embodiment. 6 is a timing chart showing a change when the phase of the inner partial clock advances with respect to the external reference clock in the first embodiment. 6 is a timing chart showing changes when the phase of the inner partial clock is delayed with respect to the external reference clock in the first embodiment. It is a block diagram of the plane type X-ray sensor by a 2nd embodiment. It is a timing chart in a 2nd embodiment. It is a timing chart which shows a change when the phase of an inner part circumference clock is late to an external standard clock in a 2nd embodiment. It is a timing chart which shows change when the phase of an inner part circumference clock advances with respect to an external reference clock in a 2nd embodiment.

  Hereinafter, X-ray planar sensors according to some embodiments will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same or similar structure, and the overlapping description is abbreviate | omitted.

[First Embodiment]
FIG. 2 is a block diagram of the X-ray imaging system according to the first embodiment.

  The X-ray imaging system includes an X-ray generator 10 and a planar X-ray sensor 20. The X-ray generator 10 includes an external reference clock generator 11 and an X-ray generator 12. The external reference clock generator 11 generates an external reference clock. The external reference clock is a reference for the timing at which the X-ray generator 12 generates X-rays. The external reference clock is transmitted as a pulse signal. The X-ray generator 12 generates X-rays 13 at a predetermined cycle based on an external reference clock. For example, the X-ray generator 12 generates X-rays for every cycle of the external reference clock.

  The planar X-ray sensor 20 includes a photoelectric conversion element array 30, a gate drive circuit 22, a readout circuit 23, a drive control circuit 24, an image storage / transfer circuit 25, and an internal drive signal generation circuit 50.

  X-rays 13 that have passed through the imaging target 14 such as a patient are incident on the photoelectric conversion element array 30. The photoelectric conversion element array 30 converts the dose of the incident X-rays 13 into electric charges and outputs them as electric signals.

  The gate drive circuit 22 gives a gate drive signal to the photoelectric conversion element array 30. The readout circuit 23 reads out from the photoelectric conversion element array 30 an electrical signal obtained by converting the dose of incident X-rays 13 into electric charges.

  The internal drive signal generation circuit 50 generates an internal drive timing signal from an external reference clock supplied from the X-ray generator 10 in order to take out an electrical signal stored in the photoelectric conversion element array 30. More specifically, the internal drive signal generation circuit 50 receives an external reference clock signal from the external reference clock generator 11, generates a drive timing signal, and supplies the drive timing signal to the drive control circuit 24.

  The drive control circuit 24 drives the photoelectric conversion element array 30 according to the drive timing signal generated by the internal drive signal generation circuit 50. More specifically, the drive control circuit 24 controls the gate drive circuit 22 and the readout circuit 23 according to the drive timing signal. The image storage / transfer circuit 25 stores the electrical signal read by the reading circuit 23 and transfers it to the outside.

  FIG. 3 is a schematic perspective view of the photoelectric conversion element array according to the present embodiment. FIG. 4 is an equivalent circuit diagram of the photoelectric conversion element array according to the present embodiment.

  The photoelectric conversion element array 30 includes an array substrate 31 and a scintillator film 32. The array substrate 31 has a glass substrate 33. On the surface of the glass substrate 33, a plurality of fine pixels 34 are arranged in a square lattice pattern. Each pixel 34 includes a thin film transistor 35 and a photodiode 36. On the surface of the glass substrate 33, the same number of gate lines 37 as the square lattice rows in which the pixels 34 are arranged extend between the pixels 34. Further, on the surface of the glass substrate 33, the same number of data lines 38 as the number of square lattice columns in which the pixels 34 are arranged extend between the pixels 34.

  The scintillator film 32 is formed on the surface of the area where the pixels 34 of the array substrate 31 are arranged. The scintillator film 32 generates fluorescence in the visible light region when the X-ray 13 enters. The generated fluorescence reaches the surface of the array substrate 31.

  The array substrate 31 receives the fluorescence generated by the scintillator film 32 and generates an electrical signal. As a result, the visible light image generated in the scintillator film 32 by the incident X-rays is converted into image information expressed by an electrical signal.

  Each photodiode 36 is connected to a gate line 37 and a data line 38 through a thin film transistor 35 which is a switching element. In addition, a storage capacitor 39 is connected to each photodiode 36 in parallel.

  The photodiode 36 and the storage capacitor 39 connected in parallel to the photodiode 36 are connected to the data line 38 through the drain / source electrode of the thin film transistor 35. The gate electrode of the thin film transistor 35 is connected to the gate line 37.

  The gate electrodes of the thin film transistors 35 of the pixels 34 located in the same row of the array are connected to the same gate line 37. The photodiodes 36 and the storage capacitors 39 of the pixels 34 located in the same column of the array are connected to the same data line 38 via the thin film transistor 35. Each thin film transistor 35 has a switching function of accumulating and discharging charges generated by the incidence of fluorescence on the photodiode 36.

  The photoelectric conversion element array 30 needs to be scanned two-dimensionally because of its planar structure. The gate drive circuit 22 selects one row in the horizontal direction of the two-dimensionally arranged pixels 34 and gives a pulse-like signal for turning on the thin film transistor 35 to the gate line 37 corresponding to the one row. All the planes are selected by sequentially switching the lines selected by the gate drive circuit 22 in the vertical direction and scanning all the row selections. The readout circuit 23 is a circuit for scanning and reading out signals in the horizontal direction within one row selected by the gate drive circuit 22.

  As described above, by repeating the row selection by the gate driving circuit 22 and the signal reading in one row by the reading circuit 23, the signals of all the pixels 34 in the plane can be read. The image storage / transfer circuit 25 temporarily records sequentially read electrical signals, rearranges them into data suitable for image processing and image display, and transfers them. By these operations, the X-ray signal transmitted through the subject can be captured as two-dimensional data of the strength of the electric signal.

  3 and 4, the pixels are only described for 5 rows and 5 columns or 4 rows and 4 columns, but actually more pixels are formed according to the resolution and imaging area.

  FIG. 1 is a block diagram of the planar X-ray sensor according to the present embodiment.

  The internal drive signal generation circuit 50 includes a reference clock generation circuit 51, a frequency division / phase control circuit 52, and an internal synchronization signal generation circuit 53. The reference clock generation circuit 51 includes a phase comparison circuit 61, a voltage control oscillator 62, and a frequency divider circuit 63. The voltage controlled oscillator 62 is desirably a voltage controlled oscillator (VCxO) using a crystal oscillator that oscillates with high accuracy.

  The reference clock generation circuit 51 is a so-called phase synchronization circuit (PLL), and generates an internal reference clock in phase with the external reference clock generated by the external reference clock generator 11. The internal reference clock is 15 MHz, for example. Therefore, the period of the internal reference clock is 67 nsec.

  The external reference clock is input to the phase comparison circuit 61 as a pulse signal. The output of the phase comparison circuit 61 is input to the voltage controlled oscillator 62. The output signal of the voltage controlled oscillator 62 is transmitted to the frequency division / phase control circuit and also to the frequency division circuit 63. The frequency divider 63 divides the output signal of the voltage controlled oscillator 62 by a predetermined frequency division ratio. The divided clock output from the frequency dividing circuit 63 is input to the phase comparison circuit 61. The phase comparison circuit 61 compares the phases of the external reference clock and the divided clock, outputs a phase difference, and inputs it to the voltage controlled oscillator 62. In this way, the voltage controlled oscillator 62 generates an internal reference clock.

  The internal synchronizing signal generation circuit 53 receives a clock signal obtained by dividing the internal reference clock from the frequency dividing circuit 63, and generates an internal synchronizing signal. The frequency division / phase control circuit 52 receives the internal synchronization signal from the internal synchronization signal generation circuit 53 and also receives the internal reference clock from the voltage controlled oscillator 62 and generates a start pulse. The start pulse generated by the frequency division / phase control circuit 52 is given to the drive control circuit 24. When receiving the start pulse, the drive control circuit 24 starts processing. That is, the start pulse is an internal drive signal that indicates the timing of the start of processing by the drive control circuit 24.

  FIG. 5 is a timing chart in the present embodiment. FIG. 6 is a timing chart showing changes when the phase of the inner partial clock advances with respect to the external reference clock in the present embodiment. FIG. 7 is a timing chart showing a change when the phase of the inner partial clock is delayed with respect to the external reference clock in the present embodiment.

  As shown in FIG. 5, according to the present embodiment, the internal partial clock generated by the frequency divider circuit 63 is in phase with the external reference clock. When the phase of the inner partial clock is shifted from that of the external reference clock, the phase comparison circuit X detects the phase difference and converts the phase difference into a voltage value. The voltage controlled oscillator X is controlled by the voltage obtained by converting the phase difference.

  As shown in FIG. 6, when the internal partial clock advances with respect to the phase of the external reference clock, that is, when the frequency of the internal partial clock is higher than the frequency of the external reference clock, the voltage controlled oscillator X The oscillation frequency is controlled to decrease. That is, in this case, the cycle t2 of the internal reference clock after comparing the phases of the internal partial clock and the external reference clock is controlled to be longer than the cycle t1 of the internal partial clock before the phase comparison. .

  On the contrary, when the internal partial clock is delayed with respect to the phase of the external reference clock, that is, when the frequency of the internal partial clock is lower than the frequency of the external reference clock, the oscillation frequency of the voltage controlled oscillator X is set. Controlled in the direction of raising. That is, in this case, the period t3 of the internal reference clock after comparing the phases of the internal partial clock and the external reference clock is controlled to be longer than the period t1 of the internal partial clock before the phase comparison. .

  By these controls, the external reference clock and the internal partial clock are completely matched in frequency and phase. When shooting a moving image of 60 frames per second, the imaging interval is about 17 msec. However, when the frequency is tracked by the PLL circuit as in the present embodiment, the time required for frequency tracking is very small compared to the imaging interval, so the frequency follows until the next imaging. Further, once the external reference clock and the inner partial clock are synchronized, it is only necessary to follow the change from the synchronized state, so that the synchronization is faster.

  As described above, in the planar X-ray sensor 20 of the present embodiment, the clock generated by the circuit for generating the reference reference clock in the internal drive signal generation circuit 50 in order to make the external reference clock and the inner peripheral clock coincide with each other. The frequency is not fixed but variable. By making the internal reference clock variable according to the external reference clock, it is possible to make the frequency and phase of the external reference clock coincide with the frequency of the internal peripheral clock that is the reference for internal operation.

  When an internal reference clock is generated by oscillating a clock of a specific frequency regardless of the external reference clock, and the internal sync signal is also generated by dividing the clock, the phases of the external reference clock and the internal sync signal are completely Cannot match. That is, the external reference clock and the internal processing clock are in an asynchronous relationship. In this case, the following problems occur.

  When the X-ray generator 10 and the planar X-ray sensor 20 operate asynchronously, the external reference clock is input asynchronously with the processing clock of the planar X-ray sensor 20. When capturing a moving image, the external reference clock is normally input at a constant frequency, and the planar X-ray sensor 20 also operates in accordance with the external reference clock.

  The operation period (internal processing period) of the planar X-ray sensor 20 includes a signal accumulation period for capturing charges from transmission lines from X-rays, and a signal processing / transfer period for transferring received charges to an external device. Divided. The signal accumulation period is a period for determining the X-ray charge accumulation obtained by dividing the internal reference clock. For this reason, when the length of the signal accumulation period changes, the amount of stored charge also changes. The signal processing / transfer period also requires a predetermined time for processing. Therefore, the signal accumulation period and the signal processing / transfer period cannot be changed for each frame of the moving image. That is, the internal processing period is substantially constant in any frame.

  Therefore, there is a method in which the start timing of these operations is set by an external reference clock and a certain period is ensured to follow the external reference clock. In this method, when the sum of the signal accumulation period and the signal processing / transfer period is sufficiently shorter than the cycle of the external reference clock, synchronization can be achieved by providing a standby time. Conversely, if the sum of the signal accumulation period and the signal processing / transfer period is longer than the period of the external reference clock, for example, signal accumulation and signal processing / transfer are performed once every two periods of the external reference clock. By thinning out the reference clock, the planar X-ray sensor can be operated in synchronization with the external reference clock.

  However, when the external reference clock and the internal partial clock have almost the same cycle and do not fall within one cycle of the internal reference clock, or the cycle of the external reference clock is the sum of the signal accumulation time and the signal processing / transfer time. In the case of an integral multiple, there are cases where internal processing is in time for the external reference clock cycle and when it is not in time. If it is in time, the next synchronization signal transmitted from the external device can be used to proceed to the next processing. If it is not in time, the next synchronization of the next external reference clock is not performed and the next synchronization signal is not processed. The operation starts with the signal. That is, a period in which the synchronization signal cannot be followed occurs and one frame is missed at a specific timing.

  That is, when the period of the external reference clock substantially coincides with the period of the internal processing, or when the external synchronization signal becomes an integer multiple of the internal processing period, the problem is that within the period of one clock of the internal reference clock. In this case, a synchronization shift occurs, so that it cannot be controlled by an internal reference clock having a fixed period. The internal synchronization generated by dividing the internal reference clock and the external synchronization cause a shift within the period of one internal clock. Therefore, if the synchronization frequencies are almost the same, the period of the external reference clock every cycle. Is N times the period of the inner partial clock, a period in which processing is not in time for every N synchronizations occurs.

  Electric charges are accumulated in the photoelectric conversion elements in the flat sensor. Since this electric charge needs to be read out, it is connected to an element having a TFT structure. However, the charge leaks little by little through the semiconductor having the TFT structure, and there is a symptom that the charge moves to an adjacent pixel or a signal line. The amount of leakage occurs when readout is not performed from a pixel, and the characteristics differ depending on the pixel. Therefore, the greater the time difference during which readout is not performed, the greater the effect of leakage. As a result, when a period during which internal processing cannot follow the external reference clock occurs, due to the influence of leakage charge during that period, there is a problem that the amount of readout charge changes and the image brightness does not become constant due to the influence of leakage charge during that period. To do. As a result, it becomes a symptom in which the image brightness of the moving image fluctuates in a specific cycle.

  However, in this embodiment, the reference clock generation circuit 51 that generates the internal reference clock has a PLL configuration, and the internal reference clock is generated by the voltage controlled oscillator 62. The internal reference clock is frequency-divided by the frequency dividing circuit 63, and an internal partial clock having substantially the same frequency as the external reference clock is generated. At this time, the frequency dividing ratio of the frequency dividing circuit 63 is controlled so as not to exceed the oscillation range of the voltage controlled oscillator 62 in accordance with the period of the external reference clock.

  As a result, the timings of the external reference clock and the inner peripheral clock coincide with each other, and the start pulse that is a timing signal for starting processing in the planar X-ray sensor 20 has a timing corresponding to the external reference clock. As described above, according to the present embodiment, the internal drive timing of the photoelectric conversion element array and the external reference clock serving as a reference for the operation of the external device can be matched as much as possible.

  Therefore, the possibility that a situation in which the planar X-ray sensor 20 cannot process during a certain period of the external reference clock occurs is extremely small. When a moving image is shot, the possibility of missing one frame at a specific timing is extremely small. In addition, the influence of leakage charge from the pixel 34 can be suppressed.

  Further, according to the present embodiment, an image without flicker and unevenness can be obtained without using the same reference clock for an external device such as the X-ray generation device 10 and the planar X-ray sensor. Therefore, a planar X-ray sensor and an external device such as an X-ray generator can be designed independently. For this reason, even if the existing X-ray generator and the planar X-ray sensor of this embodiment are combined, an image free from flicker and unevenness can be obtained.

[Second Embodiment]
FIG. 8 is a block diagram of a planar X-ray sensor according to the second embodiment.

  The planar X-ray sensor of the present embodiment is provided with a synchronization tracking circuit 54 instead of the reference clock generation circuit 51 (see FIG. 1) of the first embodiment. The synchronization tracking circuit 54 includes a reference oscillator 72, a frequency determination circuit 71, and a frequency divider circuit 73.

  The reference oscillator 72 generates a fixed clock having a predetermined frequency. The reference oscillator 72 is, for example, a crystal oscillator, and generates a fixed clock having a very high frequency. The frequency determination circuit 71 counts the number of fixed clocks in one cycle of the external reference clock. Further, the frequency determination circuit 71 calculates a frequency division ratio based on the counted number of clocks. The frequency dividing circuit 73 divides the fixed clock generated by the reference oscillator 72 by this frequency dividing ratio to generate an internal reference clock.

  FIG. 9 is a timing chart in the present embodiment. FIG. 10 is a timing chart showing a change when the phase of the inner partial clock is delayed with respect to the external reference clock in the present embodiment. FIG. 11 is a timing chart showing changes when the phase of the inner partial clock advances with respect to the external reference clock in the present embodiment.

  The frequency determination circuit 71 calculates the frequency division ratio as follows. First, the number of fixed clocks in one cycle of the external reference clock is counted. Next, the number of clocks counted here is compared with a specified count number. Here, the specified count number represents the time required for internal processing as the number of fixed clocks oscillated by the reference oscillator 72.

  Consider a case where the fixed clock count in one cycle of the external reference clock is less than the value represented by the specified count. In this case, the internal processing is not completed during one cycle of the external reference clock. Therefore, in such a case, the external reference clock is adjusted to be longer than the shortest cycle in which internal processing is possible by thinning out the external reference clock by several pulses. For example, signal accumulation and signal reading / transfer are performed every two cycles of the external reference clock.

  In this way, the internal processing time is set so that the internal processing is completed during one external reference clock cycle or a predetermined cycle. That is, the count number of the fixed clock in one external reference clock cycle or a predetermined cycle is set not to be smaller than the specified count number. Further, the frequency division ratio is set so that the cycle of the internal partial clock is the same as the cycle of the external reference clock thinned out.

  Next, consider a case where the fixed clock count in one cycle of the external reference clock is larger than the specified count. In this case, when the internal partial clock is generated using the reference count number as the frequency division ratio, the frequency of the internal partial clock becomes higher than the frequency of the external reference clock. Therefore, the internal processing is completed in a time shorter than one cycle of the external reference clock. Therefore, after the completion of the internal processing, the next start pulse is delayed by several cycles of the reference clock. That is, the division ratio is increased. As a result, the internal processing can be appropriately completed for each cycle of the external reference clock.

  When the external reference clock cycle and internal processing cycle are almost the same, or when the external reference clock cycle is almost an integral multiple of the internal processing cycle, that is, when these frequencies are different, depending on the frequency difference As a result, a timing at which processing is not in time at intervals of several cycles occurs. In this case, in this embodiment, the drive control circuit 24 and the like are controlled without adjusting the frequency of the internal reference clock.

  The frequency dividing circuit 73 divides the fixed clock generated by the reference oscillator 72 in accordance with the external reference clock to generate an internal partial clock. If this inner peripheral clock is delayed compared to the external reference clock, the next external reference clock is not processed for one period, and the operation starts with the next synchronization signal. That is, a period in which the synchronization signal cannot be followed occurs and one frame is missed at a specific timing.

  In order to avoid this state, in this embodiment, the clock frequency division ratio of the frequency divider circuit 73 is always set so that the cycle of the inner partial clock is smaller than the cycle of the external reference clock. The frequency determination circuit 71 determines this frequency division ratio.

  When the period of the external reference clock is shorter than the time required for the internal processing, the external synchronization signal is adjusted so as to be the minimum processable period by thinning out the synchronization signal by several pulses. In addition, the frequency division ratio is adjusted so as to be the same as the external synchronization signal whose internal partial frequency clock is thinned. Further, when a delay occurs in the internal partial clock due to a difference of one clock, adjustment is performed as needed so that there is no phase delay by reducing the frequency division ratio by one clock. By continuously performing this operation, it is possible to eliminate the shift of one cycle of the external synchronization and absorb the time difference of one clock.

  As described above, according to the present embodiment, the internal drive timing of the photoelectric conversion element array and the external reference clock serving as a reference for the operation of the external device can be matched as much as possible. At this time, the leakage charge is reduced from a unit of several milliseconds to several tens of milliseconds corresponding to one cycle of the synchronization signal to several tens of nanoseconds to several microseconds, and thus is reduced to a negligible level.

  Moreover, you may combine this embodiment and 1st Embodiment. In this case, the frequency discriminating circuit determines whether or not the phase difference between the external reference clock and the inner peripheral clock is within one clock range of the fixed clock. If the phase difference is outside the one clock range, the processing of this embodiment is performed. If the phase difference is within one clock, the same processing as in the first embodiment is performed. By performing processing in such a combination, it is possible to avoid the influence of the leak charge for one clock generated in this embodiment.

[Other embodiments]
Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 10 ... X-ray generator, 11 ... External reference clock generator, 12 ... X-ray generator, 13 ... X-ray, 14 ... Imaging object, 20 ... Planar X-ray sensor, 22 ... Gate drive circuit, 23 ... Read-out circuit , 24 ... drive control circuit, 25 ... image storage / transfer circuit, 30 ... photoelectric conversion element array, 31 ... array substrate, 32 ... scintillator film, 33 ... glass substrate, 34 ... pixel, 35 ... thin film transistor, 36 ... photodiode, 37 ... Gate line, 38 ... Data line, 39 ... Storage capacitor, 50 ... Internal drive signal generation circuit, 51 ... Reference clock generation circuit, 52 ... Division / phase control circuit, 53 ... Internal synchronization signal generation circuit, 54 ... Synchronization Tracking circuit 61 ... Phase comparison circuit 62 ... Voltage controlled oscillator 63 ... Division circuit 71 ... Frequency determination circuit 72 ... Reference oscillator 73 ... Division circuit

Claims (4)

In a planar X-ray sensor that captures an X-ray image in which an X-ray generated by an X-ray generator at a predetermined time interval based on an external reference clock is transmitted through an object to be imaged,
A plurality of photoelectric conversion elements arranged two-dimensionally, a switching element provided for each of the photoelectric conversion elements, a gate line provided for each row of the photoelectric conversion elements and connected to the switching elements; A photoelectric conversion element array having a data line provided for each column of the photoelectric conversion elements and connected to the photoelectric conversion elements via the switching elements;
A voltage controlled oscillator that generates an internal reference clock; a frequency dividing circuit that divides the internal reference clock by a predetermined frequency dividing ratio to output a divided clock; and the external reference clock and the divided clock. A phase comparison circuit that compares phases and inputs the phase difference to the voltage controlled oscillator, and an internal drive signal generation circuit that generates an internal drive signal based on the internal reference clock;
A gate drive circuit for providing a gate drive signal to the gate line based on the internal drive signal;
A readout circuit that reads out a pixel signal from the photoelectric conversion element array via the data line based on the internal drive signal;
A flat X-ray sensor comprising:   The internal drive signal generation circuit counts the number of clocks of the fixed clock in one cycle of the reference oscillator that generates a fixed clock with a predetermined frequency and the external reference clock, and calculates a division ratio based on the number of clocks A synchronization tracking circuit comprising: a frequency determination circuit that performs frequency division, and a second frequency dividing circuit that divides the fixed clock by the frequency division ratio to generate a second internal reference clock; and the frequency determination circuit includes: An internal drive signal is generated based on the internal reference clock when the difference between the counted number of clocks and a predetermined specified clock number is less than a predetermined value, and based on the second internal reference clock otherwise. The planar X-ray sensor according to claim 1.   The predetermined specified number of clocks is larger than a value expressed by the number of fixed clocks for the time required to store charges in the photoelectric conversion element and the time required to read out a pixel signal from the photoelectric conversion element. The flat X-ray sensor according to claim 2, wherein the value of 1 is 1. In a planar X-ray sensor that captures an X-ray image in which an X-ray generated by an X-ray generator at a predetermined time interval based on an external reference clock is transmitted through an object to be imaged,
A plurality of photoelectric conversion elements arranged two-dimensionally, a switching element provided for each of the photoelectric conversion elements, a gate line provided for each row of the photoelectric conversion elements and connected to the switching elements; A photoelectric conversion element array having a data line provided for each column of the photoelectric conversion elements and connected to the photoelectric conversion elements via the switching elements;
A reference oscillator that generates a fixed clock of a predetermined frequency, a frequency determination circuit that counts the number of clocks of the fixed clock in one cycle of the external reference clock, and calculates a division ratio based on the number of clocks; A frequency dividing circuit that divides a fixed clock by the frequency dividing ratio to generate an internal reference clock, and an internal drive signal generation circuit that generates an internal drive signal based on the internal reference clock;
A gate drive circuit for providing a gate drive signal to the gate line based on the internal drive signal;
A readout circuit that reads out a pixel signal from the photoelectric conversion element array via the data line based on the internal drive signal;
A flat X-ray sensor comprising:

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