JP2013069993A - Semiconductor storage device and manufacturing method of the same - Google Patents

Abstract

A semiconductor memory device capable of appropriately silicidating a word line or a gate electrode in both a memory cell array and a peripheral circuit is provided.
A semiconductor memory device includes a semiconductor substrate, a floating gate provided above the semiconductor substrate, an intergate insulating film provided on the floating gate, and a control gate provided on the intergate insulating film. A plurality of memory cells including a gate electrode including a floating gate and a control gate electrically connected to each other; a sidewall film covering a side surface of the floating gate of the gate electrode; and a side surface of the control gate of the gate electrode. A peripheral circuit including a transistor having a spacer and a spacer provided on the side wall film. In the memory cell and the peripheral circuit, the upper part of the control gate is silicided.
[Selection] Figure 3

Description

  Embodiments described herein relate generally to a semiconductor memory device and a method for manufacturing the same.

  A NAND flash EEPROM is known as a nonvolatile semiconductor memory device that can be electrically rewritten and highly integrated. The memory cell transistor of the NAND flash EEPROM has a stack gate structure including a floating gate for accumulating charges and a control gate for controlling the voltage of the floating gate.

  In recent years, with the high integration of memory cells, the pattern of the memory cell array is miniaturized. As the memory cell array becomes finer, the wiring width becomes narrower and the wiring resistance increases. On the other hand, wiring resistance is reduced by siliciding the wiring.

  When siliciding the control gate (word line) of the memory cell array and the gate electrode of the peripheral circuit, an insulating film is filled between adjacent word lines or between adjacent gate electrodes. The insulating film is etched back to expose the upper portions of the word line and the gate electrode. A metal film is deposited on the exposed word line and gate electrode, and the upper portions of the word line and gate electrode are silicided.

  However, the interval between adjacent word lines in the memory cell array is narrower than the interval between adjacent gate electrodes in the peripheral circuit. Therefore, the insulating film is deeply etched in the peripheral circuit region, and the gate electrode of the peripheral circuit is exposed to be larger than the word line of the memory cell array. As a result, in the silicidation process, the amount of metal diffusing to the gate electrode of the peripheral circuit is larger than the amount of metal diffusing to the word line of the memory cell array, and the gate electrode of the peripheral circuit may be excessively silicided. .

  In the gate electrode of the peripheral circuit, a part of the IPD (Inter Poly-Si Dielectric) film is removed, and the floating gate and the control gate are connected. For this reason, if the gate electrode is silicided excessively, in the peripheral circuit, metal may diffuse not only to the control gate but also to the floating gate and the gate insulating film. In this case, there arises a problem that the characteristics of the elements of the peripheral circuit change. For example, the threshold voltage of the peripheral circuit transistor changes.

JP 2009-212158 A

  Provided is a semiconductor memory device in which a word line or a gate electrode can be appropriately silicided in both a memory cell array and a peripheral circuit.

  The semiconductor memory device according to the present embodiment includes a semiconductor substrate, a plurality of memory cells, and a peripheral circuit. The memory cell includes a floating gate provided above the semiconductor substrate, an intergate insulating film provided on the floating gate, and a control gate provided on the intergate insulating film. The peripheral circuit includes a transistor. The transistor includes a gate electrode including a floating gate and a control gate that are electrically connected to each other, a sidewall film that covers a side surface of the floating gate of the gate electrode, and a sidewall film that covers a side surface of the control gate of the gate electrode. In the memory cell and the peripheral circuit, the upper part of the control gate is silicided.

1 is a configuration diagram of a NAND flash EEPROM 1 according to a first embodiment. FIG. 1 is a configuration diagram of a memory cell array MCA according to a first embodiment. FIG. FIG. 6 is a cross-sectional view illustrating a configuration of a memory cell MC, a selection transistor SG, and a transistor Tr in a peripheral circuit. Sectional drawing which shows the manufacturing method of the memory 1 by 1st Embodiment. FIG. 5 is a cross-sectional view illustrating the method for manufacturing the memory 1 following FIG. 4. FIG. 6 is a cross-sectional view illustrating the method for manufacturing the memory 1 following FIG. 5. Sectional drawing which shows the manufacturing method of the memory 1 following FIG. FIG. 8 is a cross-sectional view illustrating the method for manufacturing the memory 1 following FIG. 7. FIG. 9 is a cross-sectional view illustrating the method for manufacturing the memory 1 following FIG. 8. FIG. 10 is a cross-sectional view illustrating the method for manufacturing the memory 1 following FIG. 9.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

  FIG. 1 is a configuration diagram of a NAND flash EEPROM (Electrically Erasable Programmable Read-Only Memory) 1 (hereinafter also simply referred to as a memory 1) according to the first embodiment. The memory 1 includes a memory cell array MCA and a peripheral circuit PRI. Memory cell array MCA and peripheral circuit PER are formed on one chip.

  The memory cell array MCA includes a plurality of memory cells MC that are two-dimensionally arranged in a matrix. The peripheral circuit PRI is formed around the memory cell array MCA and controls the memory cell array MCA. The peripheral circuit PRI includes, for example, a driver, a decoder, a buffer, a power supply circuit, and the like, and includes a plurality of semiconductor elements (not shown).

  FIG. 2 is a configuration diagram of the memory cell array MCA according to the first embodiment. The memory cell array includes a plurality of memory blocks BLOCK. FIG. 2 shows a configuration of a certain block BLOCKi (i is an integer). The block BLOCKi is a unit of data erasure and includes a plurality of NAND strings NS0 to NS5 connected to the bit line BL of each column. The NAND strings NS0 to NS5 include a plurality of memory cells MC connected in series, and select gate transistors SGS and SGD connected to both ends of these memory cells MC. In this example, five memory cells MC are connected in series in each NAND string NS, but usually 32 or 64 memory cells MC are connected in series. One ends of the NAND strings NS0 to NS5 are connected to the corresponding bit lines BL0 to BL5, and the other ends are connected to the common source line SL.

  The control gate CG of the memory cell MC is connected to the word lines WL0 to WL4 of the page to which the memory cell MC belongs. For example, the control gates of the memory cells MC belonging to the page j (j = 0 to 4) are connected to the word line WLj. The gates of the selection gate transistors SGD and SGS are connected to the selection gate line SGL1 or SGL2. A page is a unit of data reading or data writing.

  The plurality of word lines WL extend in the row direction, and the plurality of bit lines BL extend in the column direction so as to be substantially orthogonal to the row direction.

  As shown in FIG. 2, the memory cell MC corresponds to a lattice-shaped intersection formed by a word line WL and an active area (a surface portion of the semiconductor substrate 10 parallel to the bit line BL in this embodiment). Is provided. For example, the lattice-shaped intersections formed by the active areas parallel to the word lines WL0 to WL4 and the bit lines BL0 to BL5 are located in a 5 × 6 matrix. The memory cells MC are two-dimensionally arranged in a 5 × 6 matrix so as to correspond to these intersections. The block of this embodiment has 5 × 6 (30) memory cells MC, but the number of memory cells MC in one block is not limited to this.

  The memory cell MC is composed of an n-type FEF (Field-Effect Transistor) having a floating gate FG and a control gate CG. By applying a voltage to the control gate CG by the word line WL, charges (electrons) are injected into the floating gate FG, or charges (electrons) are discharged from the floating gate FG. As a result, data is written to the memory cell MC or data in the memory cell MC is erased. The memory cell MC has a threshold voltage corresponding to the amount of charges (electrons) accumulated in the floating gate FG. The memory cell MC can electrically store binary data (1 bit) or multi-value data (2 bits or more) as a difference in threshold voltage.

  FIGS. 3A and 3B are cross-sectional views illustrating the structures of the memory cell MC, the selection transistor SG, and the transistor Tr in the peripheral circuit. FIG. 3 shows a cross section in the column direction.

  As shown in FIG. 3A, in the memory cell array MCA, a plurality of memory cells MC are provided on the semiconductor substrate 10. The memory cell MC includes a tunnel gate insulating film 25 provided on the semiconductor substrate 10, a floating gate FG provided on the tunnel gate insulating film 25, and an inter-gate insulating film IPD (Inter Poly Dielectric) and a control gate CG provided on the inter-gate insulating film IPD.

  A plurality of memory cells MC adjacent in the column direction are electrically connected in series via a diffusion layer 20 formed in the semiconductor substrate 10. Thus, the plurality of memory cells MC adjacent in the column direction form NAND strings NS0 to NS5.

  The floating gate FG is formed using, for example, polysilicon. The lower portion of the control gate CG is formed using, for example, polysilicon, and the upper portion thereof is formed using, for example, silicide. That is, the control gate CG includes the polysilicon layer 70 and the silicide layer 71. The silicide layer 71 is formed using, for example, nickel silicide. The control gate CG extends in the row direction and also functions as a word line. Therefore, each control gate CG is shared by a plurality of memory cells MC adjacent in the row direction.

  A sidewall film 30 is buried between the floating gates FG and between the control gates CG of a plurality of memory cells MC adjacent in the column direction. The sidewall film 30 is formed using an insulating film such as a silicon oxide film, for example.

  The memory cell MC at the end of the MAND string is connected to the selection gate transistor SG via the diffusion layer 20. The selection gate transistor SG includes a tunnel gate insulating film 25 and a gate electrode G provided on the gate insulating film 26. Similarly to the memory cell MC, the gate electrode G includes a floating gate FG, an inter-gate insulating film IPD, and a control gate CG. However, a part of the inter-gate insulating film IPD is removed, and the control gate CG and the floating gate FG are electrically connected to each other. Thereby, the control gate CG and the floating gate FG function as one gate electrode G. The select gate transistor SG is configured to be in a conductive state in order to connect the corresponding NAND string NS to the bit line BL when selecting the memory cell MC.

  A sidewall film 30 is embedded between the gate electrode G of the selection gate transistor SG and the floating gate FG of the memory cell MC, and between the gate electrode G of the selection gate transistor SG and the control gate CG of the memory cell MC. ing. A sidewall film 30 is also provided on the side surface of the select gate transistor SG opposite to the side adjacent to the memory cell MC of the floating gate FG. That is, the sidewall film 30 covers the side surface of the floating gate FG in the gate electrode G of the selection gate transistor SG. The sidewall film 30 is formed using an insulating film such as a silicon oxide film, for example.

  A spacer 51 is provided on the sidewall film 30. The spacer 51 covers the side surface of the control gate CG in the gate electrode G of the selection gate transistor SG. The spacer 51 is provided on the side surface of the selection gate transistor SG opposite to the side adjacent to the memory cell MC, and is not provided on the side surface on the memory cell MC side. The spacer 51 is formed using an insulating film such as a silicon nitride film, for example.

  The spacer 51 covers the side surface of the control gate CG of the selection gate transistor SG on the sidewall film 30, thereby suppressing the gate electrode G of the selection gate transistor SG from being silicided excessively.

  The selection gate transistor SG is connected to the contact plug 90 via the diffusion layer 21 and is electrically connected to the bit line BL via the contact plug 90.

  Insulating films 40 and 50 are formed on the side surfaces of the sidewall film 30. The insulating film 40 is formed using, for example, a silicon oxide film, and the insulating film 50 is formed using, for example, a silicon nitride film. Further, interlayer insulating films 60 and 80 are provided on the insulating film 50. The interlayer insulating films 60 and 80 are formed using, for example, a silicon oxide film. The contact plug 90 penetrates through the insulating films 40 and 50 and the interlayer insulating films 60 and 80 and is in contact with the diffusion layer 21.

  As shown in FIG. 3B, the transistor Tr is provided over the semiconductor substrate 10 in the peripheral circuit. The transistor Tr includes a gate insulating film 26 that is thicker than the tunnel gate insulating film 25 and a gate electrode G provided on the gate insulating film 26. The gate electrode G is composed of a control gate CG and a floating gate FG, like the selection gate transistor SG, but a part of the inter-gate insulating film IPD is removed, and the control gate CG and the floating gate FG are Are electrically connected to each other. Thereby, the control gate CG and the floating gate FG function as one gate electrode G.

  Diffusion layers 22 are provided on both sides of the gate electrode G. The diffusion layer 22 functions as a source or a drain.

  The sidewall film 30 covers the side surfaces on both sides of the floating gate FG of the transistor Tr. A spacer 51 is provided on the sidewall film 30. The spacer 51 covers the side surface of the control gate CG in the gate electrode G of the transistor Tr.

  The spacer 51 covers the side surface of the control gate CG of the transistor Tr of the peripheral circuit PRI, thereby suppressing the gate electrode G of the transistor Tr from being excessively silicided.

  The upper portions of the control gates CG of the memory cell MC, the select gate transistor SG, and the transistor Tr of the peripheral circuit PRI are silicided and have a silicide layer 71. In the select gate transistor SG and the transistor Tr of the peripheral circuit PRI, the silicide layer 71 does not reach the floating gate FG. Therefore, in the present embodiment, the characteristics of the elements of the selection gate transistor SG and the peripheral circuit PRI can be appropriately controlled.

  4A to 10B are cross-sectional views illustrating the method for manufacturing the memory 1 according to the first embodiment. 4A to 10B, FIG. 4A shows a cross section of the memory cell array MCA, and FIG. 4B shows a cross section of the transistor Tr of the peripheral circuit PRI.

  First, the tunnel gate insulating film 25 and the gate insulating film 26 are formed on the semiconductor substrate 10 using a thermal oxidation method. Next, a material for the floating gate FG is deposited on the gate insulating films 25 and 26. For example, polysilicon is used as the material of the floating gate FG.

  After the formation of element isolation STI (Shallow Trench Isolation), the material of the intergate insulating film IPD is deposited on the material of the floating gate FG. As a material of the inter-gate insulating film IPD, for example, a silicon oxide film, a silicon nitride film, or a high-k film having a dielectric constant higher than that of the silicon oxide film is used.

  Next, in the peripheral circuit PRI, a part of the inter-gate insulating film IPD is removed in order to electrically connect the control gate CG to the floating gate FG.

  Next, a material for the control gate CG is deposited on the material for the inter-gate insulating film IPD. For example, polysilicon is used as the material of the control gate CG.

  Next, the control gate CG, the intergate insulating film IPD, and the floating gate FG are processed to form the control gate CG, the intergate insulating film IPD, and the floating gate FG. At this time, a hard mask HM is deposited on the material of the control gate CG, and the hard mask HM is patterned using a lithography technique and an RIE method. Using this patterned hard mask HM, the material of the control gate CG, the material of the intergate insulating film IPD, and the material of the floating gate FG may be processed. For the hard mask HM, for example, an insulating film such as a silicon nitride film is used.

  Next, diffusion layers 20, 21, and 22 are formed by introducing impurities using the control gate CG or the like as a mask.

  Next, the material of the sidewall film 30 is deposited between the adjacent floating gates FG, between the adjacent control gates CG, and on the semiconductor substrate 10. As the material of the sidewall film 30, for example, an insulating film such as a silicon oxide film is used.

  Further, the material of the sidewall film 30 is etched back. As a result, the sidewall film 30 exposes the upper surface of the control gate CG while filling between adjacent memory cells MC in the memory cell array MCA.

  In the peripheral circuit PRI, the sidewall film 30 is formed on the side surface of the floating gate FG in the gate electrode G of the transistor Tr. The side wall film 30 may cover the lower side surface of the control gate CG in the gate electrode G of the transistor Tr, but does not cover the upper side surface of the control gate CG. Therefore, at least the upper side surface of the control gate CG is exposed.

  Further, in the select gate transistor SG, the sidewall film 30 is formed on one side surface of the floating gate FG in the gate electrode G. The side wall film 30 may cover the lower side surface of the control gate CG in the gate electrode G of the selection gate transistor SG, but does not cover the upper side surface of the control gate CG. Therefore, at least the upper side surface of the control gate CG is exposed. As a result, the structure shown in FIGS. 4A and 4B is obtained.

  Next, as shown in FIGS. 5A and 5B, insulating films 40 and 50 are deposited on the sidewall film 30 and the control gate CG. For the insulating films 40 and 50, for example, an insulating film such as a silicon oxide film or a silicon nitride film is used. Further, an interlayer insulating film 60 is deposited on the insulating film 50. For the interlayer insulating film 60, for example, a silicon oxide film such as BPSG is used.

  Next, the interlayer insulating film 60 and the insulating films 40 and 50 are etched back until the upper surface of the control gate CG is exposed. As a result, the structure shown in FIGS. 6A and 6B is obtained. Usually, the interval between adjacent memory cells MC is narrower than the interval between adjacent elements in the peripheral circuit PRI, and the density of the planar layout of the memory cells MC of the memory cell array MCA is the density of the planar layout of the elements of the peripheral circuit PRI. Higher than. That is, there is a difference in density between the memory cell array MCA and the peripheral circuit PRI in the planar layout. Due to the difference in density, the amount of the sidewall film 30 to be etched back differs between the memory cell array MCA and the peripheral circuit PRI. For example, since the density of the planar layout of the memory cell array MCA is relatively high, the sidewall film 30 filled between the memory cells MC is not etched much. On the other hand, since the density of the planar layout of the peripheral circuit PRI is relatively low, the sidewall film 30 filled between the elements of the peripheral circuit PRI is often etched.

  Therefore, as shown in FIG. 6A, the sidewall film 30 filled between the memory cells MC is left so as to cover the side surfaces of the floating gate FG and the control gate CG. On the other hand, as shown in FIG. 6B, in the peripheral circuit PRI, the sidewall film 30 remains on the side surface of the floating gate FG in the gate electrode G of the transistor Tr, but the upper portion of the sidewall film 30 is etched. . Therefore, the upper side surface of the control gate CG in the gate electrode G of the transistor Tr in the peripheral circuit PRI is exposed.

  As shown in FIG. 6A, in the select gate transistor SG, the sidewall film 30 is left on the side surface F1 on the memory cell MC side among the side surfaces of the control gate CG. However, since the upper portion of the sidewall film 30 is etched on the side surface F2 opposite to the adjacent memory cell MC side among the side surfaces of the control gate CG, the sidewall film 30 does not remain on the side surface F2. That is, the sidewall film 30 is left on the side surface of the floating gate FG on the memory cell MC side, but is not left on the side surface of the control gate CG opposite to the memory cell MC side. Therefore, in the select gate transistor SG, the side surface of the gate electrode G opposite to the memory cell MC side of the control gate CG is exposed.

  Next, as shown in FIGS. 7A and 7B, a material for the spacer 51 is deposited on the control gate G, the sidewall film 30 and the interlayer insulating film 60. At this time, the spacers 51 are formed thick in the vertical direction on the side surfaces of the exposed transistor Tr of the peripheral circuit PRI and the gate electrode G of the selection gate transistor SG. As the material of the spacer 51, for example, an insulating film such as a silicon nitride film is used.

  Next, the material of the spacer 51 is anisotropically etched. As a result, the spacer 51 is left on the side surfaces of the transistor Tr of the peripheral circuit PRI and the gate electrode G of the selection gate transistor SG. More specifically, as shown in FIG. 8A, in the select gate transistor SG, the spacer 51 is formed on the sidewall film 30 formed on the side surface of the floating gate FG, and the memory cell of the control gate CG. The side opposite to the MC side is covered. As shown in FIG. 8B, in the peripheral circuit PRI, the spacer 51 is formed on the side wall film 30 formed on the side surface of the floating gate FG of the transistor Tr, and the side surface of the control gate CG of the transistor Tr is formed. Cover. Thereby, the control gate CG or the gate electrode G is exposed almost uniformly in the memory cell MC, the select gate transistor SG, and the transistor Tr of the peripheral circuit PRI.

  Next, as shown in FIGS. 9A and 9B, a metal film 65 is deposited on the control gate CG, the side wall film 30 and the spacer 51. For the metal film 65, for example, nickel or the like is used. At this time, spacers 51 are formed on the upper side surface of the gate electrode G of the transistor Tr and the upper side surface of the gate G of the selection gate transistor SG in the peripheral circuit PRI. Therefore, in the transistor Tr and the selection gate transistor SG of the peripheral circuit PRI, the metal film 65 covers the upper part of the control gate CG of the gate electrode G and does not contact the lower side surface of the control gate CG.

  Next, the control gate CG is silicided by the metal film 65 by performing heat treatment. Thereby, as shown in FIGS. 10A and 10B, a silicide layer 71 is formed on the upper portion of the control gate CG. Under the silicide layer 71, the polysilicon layer 70 remains.

  Here, in the memory cell array MCA, the sidewall film 30 is embedded between adjacent memory cells MC. Accordingly, the silicide layer 71 is formed on the upper part of the control gate CG of the memory cell MC, and the lower part remains polysilicon.

  In the select gate transistor SG, the side surface of the gate electrode G on the memory cell MC side is covered with the sidewall film 30, and the side surface of the gate electrode G opposite to the adjacent memory cell MC side is the sidewall film 30 and the spacer 51. It is covered by. Accordingly, also in the select gate transistor SG, the silicide layer 71 is formed on the upper part of the gate electrode G of the select gate transistor SG, and the lower part remains the polysilicon layer 70.

  In the transistor Tr of the peripheral circuit PRI, the side surface of the gate electrode G is covered with the sidewall film 30 and the spacer 51. Therefore, also in the peripheral circuit PRI, the silicide layer 71 is formed on the gate electrode G, and the lower portion remains the polysilicon layer 70.

  According to the present embodiment, when the silicide layer 71 is formed, the sidewall film 30 and the spacer 51 cover the side surface of the gate electrode G of the transistor Tr of the peripheral circuit PRI and the side surface of the gate electrode G of the selection gate transistor SG. Yes. Therefore, in the peripheral circuit PRI and the select gate transistor SG, the metal film 65 is prevented from diffusing below the gate electrode G (floating gate FG and gate insulating film 26), and the gate G is excessively silicided. Can be suppressed. Thereby, it is possible to suppress a change in the element characteristics (for example, the threshold voltage of the transistor Tr) of the peripheral circuit PRI.

  Further, in the planar layout, even if the density of the control gate CG or the gate electrode G is different on the semiconductor substrate 10, the memory cell array MCA and the peripheral circuit are provided by providing both the sidewall film 30 and the spacer 51. In PRI, the exposure amount of the control gate CG or the gate electrode G can be made substantially uniform. Thereby, in the memory cell array MCA and the peripheral circuit PRI, the silicide layer 71 can be formed with a substantially uniform thickness. As a result, it becomes easy to control the characteristics of the elements of the select gate transistor SG and the peripheral circuit PRI.

  The above embodiment is an embodiment of a NAND flash EEPROM, but the present invention can also be applied to a NOR flash EEPROM.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 ... Memory, MCA ... Memory cell array, PRI ... Peripheral circuit, MC ... Memory cell, Tr ... Transistor, SG ... Selection gate transistor, 10 ... Semiconductor substrate, 20- 22 ... diffusion layer, 25 ... tunnel gate insulating film, 26 ... gate insulating film, 30, 40, 50 ... sidewall film, 51 ... spacer, insulating film 60, 80 ... interlayer Insulating film, 70 ... polysilicon layer, 71 ... silicide layer, 90 ... contact plug, FG ... floating gate (charge storage layer), CG ... control gate, IPD ... between gates Insulation film

Claims (7)

Semiconductor substrate,
A plurality of memory cells including a charge storage layer provided above the semiconductor substrate, an intergate insulating film provided on the charge storage layer, and a control gate provided on the intergate insulating film; ,
A gate electrode including the charge storage layer and the control gate electrically connected to each other; a sidewall film covering a side surface of the charge storage layer of the gate electrode; and a side surface of the control gate of the gate electrode. And a peripheral circuit including a transistor having a spacer and a spacer provided on the sidewall film,
In the memory cell and the peripheral circuit, the upper part of the control gate is silicided,
A select transistor that is turned on when a certain memory cell is selected from the plurality of memory cells;
The selection transistor includes a gate electrode including the charge storage layer and the control gate electrically connected to each other, a sidewall film covering a side surface of the charge storage layer of the gate electrode, and the gate electrode of the gate electrode. A spacer that covers the side surface of the control gate and is provided on the sidewall film,
The upper part of the control gate of the selection transistor is silicided,
The spacer is provided on the side surface opposite to the adjacent memory cell side among the side surfaces of the control gate of the selection transistor, and is not provided on the side surface on the memory cell side,
2. A semiconductor memory device, wherein an interval between adjacent memory cells is narrower than an interval between adjacent elements in the peripheral circuit. Semiconductor substrate,
A plurality of memory cells including a charge storage layer provided above the semiconductor substrate, an intergate insulating film provided on the charge storage layer, and a control gate provided on the intergate insulating film; ,
A gate electrode including the charge storage layer and the control gate electrically connected to each other; a sidewall film covering a side surface of the charge storage layer of the gate electrode; and a side surface of the control gate of the gate electrode. And a peripheral circuit including a transistor having a spacer and a spacer provided on the sidewall film,
In the memory cell and the peripheral circuit, the upper part of the control gate is silicided. A select transistor that is turned on when a certain memory cell is selected from the plurality of memory cells;
The selection transistor includes a gate electrode including the charge storage layer and the control gate electrically connected to each other, a sidewall film covering a side surface of the charge storage layer of the gate electrode, and the gate electrode of the gate electrode. A spacer that covers the side surface of the control gate and is provided on the sidewall film,
3. The semiconductor memory device according to claim 2, wherein an upper portion of the control gate of the selection transistor is silicided.   2. The spacer according to claim 1, wherein the spacer is provided on a side surface opposite to the adjacent memory cell side among side surfaces of the control gate of the selection transistor, and is not provided on a side surface on the memory cell side. 4. The semiconductor memory device according to 3.   5. The semiconductor memory device according to claim 1, wherein an interval between adjacent memory cells is narrower than an interval between adjacent elements in the peripheral circuit. A method of manufacturing a semiconductor memory device comprising a memory cell array including a plurality of memory cells and a peripheral circuit provided around the memory cell array,
Forming a gate insulating film on the semiconductor substrate;
Forming a charge storage layer material on the gate insulating film;
Forming a gate insulating film material on the charge storage layer material;
Forming a control gate material on the inter-gate insulating film material;
Processing the control gate material, the intergate insulating film material and the charge storage layer material to form the control gate, the intergate insulating film and the charge storage layer,
Forming a sidewall film that fills between adjacent memory cells in the memory cell array and covers the side surfaces of the charge storage layer in the peripheral circuit;
In the peripheral circuit, forming a spacer covering the side surface of the control gate and provided on the sidewall film,
Depositing a metal film on the control gate;
A method of manufacturing a semiconductor memory device, comprising: siliciding the control gate in the memory cell and the peripheral circuit. The semiconductor memory device further includes a selection transistor that is turned on when a certain memory cell is selected from the plurality of memory cells.
The sidewall film covers a side surface of the charge storage layer of the selection transistor,
The spacer covers the side surface of the control gate of the selection transistor and is also formed on the sidewall film of the selection transistor,
7. The method of manufacturing a semiconductor memory device according to claim 6, wherein when the control gate is silicided, the upper part of the control gate of the selection transistor is also silicided.

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