JP2013058678A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent reduction of a width dimension of a floating gate electrode film at a part facing a substrate at the time of forming an element isolation insulation film.SOLUTION: A semiconductor device of a present embodiment comprises: a semiconductor substrate; a gate insulation film formed on the semiconductor substrate; and a gate electrode formed on the gate insulation film, in which a floating gate electrode film, an interelectrode insulation film, and a control gate electrode film are laminated. The floating gate electrode film includes a polycrystalline silicon layer having a lower silicon layer containing nitrogen and an upper silicon layer substantially not containing nitrogen. A dimension in a gate width direction of the lower silicon layer is made larger than a dimension in the gate width direction of the upper silicon layer.

Description

  Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the semiconductor device.

  For example, in a NAND flash memory device, as a configuration of a memory cell transistor, a charge storage layer (floating gate electrode film) is formed on a semiconductor substrate via a gate insulating film (tunnel insulating film), and an interelectrode insulating film is formed thereon. The control gate electrode film is stacked via the electrode. In the NAND flash memory device, when forming an STI (shallow trench isolation) structure with the recent miniaturization, a coating type element isolation insulating film such as polysilazane is applied in the element isolation trench, and a high-temperature steam atmosphere is formed. The coating type element isolation insulating film is reformed by heat treatment.

  In the case of the above STI structure, when the coating type element isolation insulating film is modified, an oxidizing atmosphere diffuses in the element isolation insulating film during the heat treatment in a high-temperature water vapor atmosphere to form a floating gate electrode film. The surface of the crystalline silicon film may be selectively oxidized. When the surface of the polycrystalline silicon film is oxidized, the width dimension of the polycrystalline silicon film becomes smaller than the width dimension of the silicon substrate that becomes the active region. In such a configuration in which the width of the polycrystalline silicon film is reduced, the capacitance of the capacitor between the silicon substrate formed via the tunnel insulating film and the floating gate electrode film is reduced, and tunnel insulation is performed when writing to the memory cell transistor. Since the amount of charge penetrating the film is reduced, there is a problem that the writing voltage is increased. In the case of the above configuration, since the distance between the word line and the silicon substrate becomes short, electrons may flow directly to the word line instead of the floating gate electrode film at the time of writing, which may cause a problem that writing is not performed. there were.

Japanese Patent Laid-Open No. 11-8298

  Accordingly, a semiconductor device and a method for manufacturing the semiconductor device are provided that can prevent the width dimension of the portion of the floating gate electrode film facing the substrate from being reduced when the element isolation insulating film is formed.

  The semiconductor device according to this embodiment includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a gate insulating film formed on the gate insulating film, and a floating gate electrode film, an interelectrode insulating film, and a control gate electrode film are stacked. Gate electrode. And the floating gate electrode film is composed of a polycrystalline silicon layer having a lower silicon layer containing nitrogen and an upper silicon layer substantially free of nitrogen, and the dimension of the lower silicon layer in the gate width direction is The upper silicon layer was made larger than the dimension in the gate width direction.

1 is an equivalent circuit diagram showing a part of a memory cell array of a NAND flash memory device according to a first embodiment; Schematic plan view showing a partial layout pattern of the memory cell region (A) is a schematic cross-sectional view shown along line 3A-3A in FIG. 2, (b) is a schematic cross-sectional view shown along line 3B-3B in FIG. Sectional drawing shown along the 3B-3B line in FIG. 2 in the middle of manufacture (the 1) Sectional drawing shown along the 3B-3B line in FIG. 2 in the middle of manufacture (the 2) Sectional drawing shown along the 3B-3B line in FIG. 2 in the middle of manufacture (the 3) Sectional drawing shown along the 3B-3B line in FIG. 2 in the middle of manufacture (the 4) Sectional drawing shown along the 3B-3B line in FIG. 2 in the middle of manufacture (the 5) Sectional drawing shown along the 3B-3B line in FIG. 2 in the middle of manufacture (the 6) Sectional drawing shown along the 3B-3B line in FIG. 2 in the middle of manufacture (the 7) The figure explaining the manufacturing process of an amorphous silicon layer The figure which shows distribution of write-in voltage Vpgm

Hereinafter, an embodiment will be described with reference to the drawings. The drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.
(First embodiment)
First, the configuration of the NAND flash memory device of this embodiment will be described.

  FIG. 1 is an equivalent circuit diagram showing a part of a memory cell array formed in a memory cell region of a NAND flash memory device. The memory cell array of the NAND flash memory device is configured by arranging a plurality of NAND cell units (memory units) Su in a matrix. The NAND cell unit Su includes two select gate transistors Trs1 and Trs2, and a plurality (for example, 32) of memory cell transistors Trm connected in series between the select gate transistors Trs1 and Trs2. A plurality of memory cell transistors Trm in the NAND cell unit Su are configured to share a source / drain region between adjacent ones.

  A plurality of memory cell transistors Trm arranged in the X direction (corresponding to the word line direction and the gate width direction) in FIG. 1 are commonly connected by a word line WL. Further, the selection gate transistors Trs1 arranged in the X direction in FIG. 1 are commonly connected by a selection gate line SGL1, and the selection gate transistors Trs2 are commonly connected by a selection gate line SGL2. The drain of the select gate transistor Trs1 is connected to the bit line BL via the bit line contact CB. The bit line BL is formed to extend in the Y direction (corresponding to the bit line direction and the gate length direction) orthogonal to the X direction in FIG. The source of the select gate transistor Trs2 is connected to a source line SL extending in the X direction in FIG.

  FIG. 2 is a plan view showing a layout pattern of a part of the memory cell region. A plurality of STIs 2 as element isolation regions extending along the Y direction in FIG. 2 are formed on the silicon substrate 1 as a semiconductor substrate at predetermined intervals in the X direction in FIG. Thus, the active regions 3 extending along the Y direction in FIG. 2 are separately formed in the X direction in FIG. The word lines WL of the memory cell transistors are formed so as to extend along a direction (X direction in FIG. 2) orthogonal to the active region 3, and a plurality of word lines WL are formed at predetermined intervals in the Y direction in FIG.

  Further, the selection gate line SGL1 of the pair of selection gate transistors is formed so as to extend along the X direction in FIG. Bit line contacts CB are formed in the active region 3 between the pair of select gate lines SGL1. A gate electrode MG of the memory cell transistor is formed on the active region 3 intersecting with the word line WL, and a gate electrode SG of the selection gate transistor is formed on the active region 3 intersecting with the selection gate line SGL1.

  Next, the gate electrode structure in the memory cell region of this embodiment will be described with reference to FIG. 3A is a diagram schematically showing a cross section taken along line 3A-3A (bit line direction, Y direction) in FIG. 2, and FIG. 3B is a diagram showing line 3B-3B in FIG. It is a figure which shows typically the cross section which follows (a word line direction, a X direction).

  As shown in FIGS. 3A and 3B, a plurality of element isolation grooves 4 are formed on the p-type silicon substrate 1 so as to be spaced apart from each other in the X direction in FIG. These element isolation trenches 4 isolate the active region 3 in the X direction. An element isolation insulating film 5 is formed in the element isolation trench 4 and constitutes an element isolation region (STI) 2.

  The memory cell transistor includes an n-type diffusion layer 6 formed on the silicon substrate 1, a gate insulating film (tunnel insulating film) 7 formed on the silicon substrate 1, and a gate electrode provided on the gate insulating film 7. MG. The gate electrode MG includes a floating gate electrode film FG serving as a charge storage layer, an interelectrode insulating film 9 formed on the floating gate electrode film FG, and a control gate electrode film CG formed on the interelectrode insulating film 9. Have The diffusion layer 6 is formed on both sides of the gate electrode MG of the memory cell transistor in the surface layer of the silicon substrate 1, and constitutes a source / drain region of the memory cell transistor.

  The gate insulating film 7 is formed on the silicon substrate 1 (active region 3). For example, a silicon oxynitride film is used as the gate insulating film 7. As the floating gate electrode film FG, for example, a polycrystalline silicon layer (conductive layer) 8 doped with an impurity such as phosphorus is used. The polycrystalline silicon layer 8 has a laminated structure of a lower layer silicon layer 8a and an upper layer silicon layer 8b.

The lower silicon layer 8a is a silicon layer having a high nitrogen concentration, for example, a silicon layer having a nitrogen concentration of about 1 × 10 ²¹ cm ⁻³ and has a thickness of, for example, about 10 nm. The dimension of the lower silicon layer 8a in the gate width direction (left and right direction in FIG. 3B) is substantially equal to the dimension of the silicon substrate 1 below the gate insulating film 7 in the gate width direction. The upper silicon layer 8b is a silicon layer that does not substantially contain nitrogen, and has a film thickness of, for example, about 70 nm. The dimension of the upper silicon layer 8b in the gate width direction (left and right direction in FIG. 3B) is smaller than the dimension of the lower silicon layer 8a in the gate width direction. That is, the dimension of the lower silicon layer 8a in the gate width direction is configured to be larger than the dimension of the upper silicon layer 8b in the gate width direction.

Between the lower silicon layer 8a and the upper silicon layer 8b, a crystal blocking layer 8c composed of, for example, a layer (monolayer) for one oxygen atom is interposed as a boundary layer for preventing diffusion of nitrogen therebetween. ing. The oxygen concentration in the crystal blocking layer 8c is, for example, about 5 × 10 ¹⁴ cm ⁻² . A specific method for forming the lower silicon layer 8a, the upper silicon layer 8b, and the crystal blocking layer 8c will be described later.

  The interelectrode insulating film 9 is formed along the upper surface of the element isolation insulating film 5, the upper side surface of the floating gate electrode film FG, and the upper surface of the floating gate electrode film FG. It functions as an insulating film between the electrodes. As the interelectrode insulating film 9, for example, a film having a laminated structure of silicon oxide film / silicon nitride film / silicon oxide film (each film thickness is, for example, 3 nm to 10 nm), that is, a so-called ONO film is used.

  The control gate electrode film CG is composed of the conductive layer 10 that functions as the word line WL of the memory cell transistor. The conductive layer 10 is made of, for example, a polycrystalline silicon layer 10a doped with an impurity such as phosphorus, and any of tungsten (W), cobalt (Co), nickel (Ni), etc. formed immediately above the polycrystalline silicon layer 10a. It has a laminated structure with a silicide layer 10b silicided with such a metal. In the present embodiment, the silicide layer 10b is made of, for example, nickel silicide (NiSi). Note that all of the conductive layer 10 may be formed of the silicide layer 10b (that is, the silicide layer alone).

  As shown in FIG. 3A, the gate electrodes MG of the memory cell transistors are juxtaposed in the Y direction, and the gate electrodes MG are electrically separated from each other by the electrode separation grooves 11. . An insulating film 12 between memory cells is formed in the groove 11. As the insulating film 12 between the memory cells, for example, a silicon oxide film or a low dielectric constant insulating film using TEOS (tetraethyl orthosilicate) is used. On the upper surface of the inter-memory cell insulating film 12, the upper side surface and the upper surface of the control gate electrode film CG, an interlayer insulating film 13 made of, for example, a silicon oxide film is formed.

  Next, an example of a method for manufacturing the NAND flash memory device according to the present embodiment will be described with reference to process cross-sectional views shown in FIGS. 4 to 10 schematically show the manufacturing stage of the cross-sectional structure corresponding to FIG.

  First, as shown in FIG. 4, for example, a silicon oxynitride film is formed as a gate insulating film 7 on the surface of the p-type silicon substrate 1 by combining a known thermal oxidation method and thermal nitridation method. Thereafter, an amorphous silicon layer 8 using, for example, phosphorus as an impurity, which becomes the floating gate electrode film FG, is formed by a LP-CVD (Low Pressure Chemical Vapor Deposition) method.

In this case, the film is formed according to the sequence shown in FIG. 11 using an LP-CVD apparatus (not shown). Specifically, first, in a state where the temperature is set to, for example, 520 ° C. and the pressure is set to, for example, 0.5 Torr, for example, SiH ₄ gas is, for example, 1000 sccm, inert gas (helium, nitrogen, argon, etc.) ), For example, 100 sccm of PH ₃ gas diluted to 1 vol% and 5 sccm of NH ₃ gas are introduced. By continuing this film formation state for about 10 minutes, for example, an amorphous lower silicon layer having a film thickness of about 10 nm, a nitrogen concentration of, for example, 1 × 10 ²¹ cm ⁻³ , and phosphorus as an impurity. 8a is formed.

Thereafter, the supply of SiH ₄ , PH ₃ , NH ₃ gas is stopped, and N ₂ O gas is introduced into the reaction vessel, for example, 1000 sccm. For example, by continuing the introduction of N ₂ O gas for about 5 minutes, the crystal blocking layer 8c composed of a monolayer for one oxygen atom is formed. Subsequently, the supply of N ₂ O gas is stopped, and again, for example, 1000 sccm of SiH ₄ gas is introduced into the reaction vessel, and PH ₃ gas diluted to 1 vol% with an inert gas is introduced, for example, 100 sccm. By continuing this film formation state for about 1 hour, for example, an amorphous upper silicon layer 8b having a film thickness of about 70 nm, containing no nitrogen, and using phosphorus as an impurity is formed. Finally, the reaction vessel is evacuated and purged. Thereby, an amorphous silicon layer 8 to be the floating gate electrode film FG is formed.

The nitrogen concentration of the lower silicon layer 8a of the amorphous silicon layer 8 to be the floating gate electrode film FG formed here is about 1 × 10 ²¹ cm ⁻³ . The oxygen concentration of the crystal blocking layer 8c is, for example, 5 × 10 ¹⁴ cm ⁻² . The upper silicon layer 8b does not contain nitrogen. The amorphous silicon layer 8 (the lower silicon layer 8a and the upper silicon layer 8b) contains phosphorus having an impurity concentration of about 2 × 10 ^{20 to} 3 × 10 ²⁰ cm ⁻³ as an impurity.

The amorphous silicon layer 8, that is, the lower layer silicon layer 8a and the upper layer silicon layer 8b are in an amorphous state immediately after the film formation, and a crystallization heat process is performed later, The polycrystalline silicon layer 8 is formed. When this crystallization heat step is performed, nitrogen in the lower silicon layer 8a moves to the interface (surface), but a crystal blocking layer 8c is provided between the lower silicon layer 8a and the upper silicon layer 8b. Therefore, nitrogen is prevented from moving into the upper silicon layer 8b. As a result, the nitrogen concentration in the lower silicon layer 8a can be maintained at a set concentration (for example, about 1 × 10 ²¹ cm ⁻³ ).

  Next, as shown in FIG. 5, a hard mask silicon nitride film 14 is formed on the amorphous silicon layer 8 by chemical vapor deposition. Thereafter, a photoresist (not shown) is applied on the silicon nitride film 14, and the resist is patterned by exposure and development. Subsequently, the silicon nitride film 14 is etched by RIE (reactive ion etching) using the patterned resist as a mask, and then the amorphous silicon layer 8 (floating gate electrode film FG), the gate insulating film 7, and the silicon substrate 1. Is etched to form a groove 4 for element isolation (see FIG. 6).

  Thereafter, as shown in FIG. 7, for example, a coating type element isolation insulating film 5 such as polysilazane is applied and buried in the processed groove 4. Subsequently, for example, heat treatment is performed in a high-temperature steam atmosphere at 550 ° C. to modify the coating type element isolation insulating film 5. At this time, since the upper silicon layer 8b of the polycrystalline silicon layer 8 to be the floating gate electrode film FG does not contain nitrogen, oxidation proceeds selectively during the heat treatment, and the gate width direction (the horizontal direction in FIG. 7) ) The dimensions become thinner. On the other hand, since the lower silicon layer 8a of the polycrystalline silicon layer 8 has a high nitrogen concentration, oxidation hardly proceeds at the time of the heat treatment, and it is prevented that the dimension in the gate width direction is reduced. Thereby, a substantially convex floating gate electrode film FG (polycrystalline silicon layer 8) having a thick lower (bottom) portion can be formed.

  Next, planarization is performed using chemical mechanical polishing (CMP) until the silicon nitride film 14 is exposed, and then the element isolation insulating film 5 is selectively etched using the RIE method to obtain a floating gate electrode film. The element isolation insulating film 5 between the FGs (polycrystalline silicon layer 8) is dropped. In this case, the element isolation insulating film 5 is dropped so that, for example, about 80 to 90% is exposed from the upper part of the height of the polycrystalline silicon layer 8 to be the floating gate electrode film FG. Thereafter, the silicon nitride film 14 remaining on the polycrystalline silicon layer 8 is selectively etched and removed by wet etching such as a phosphoric acid solution to obtain a structure as shown in FIG.

  Next, as shown in FIG. 9, an interelectrode insulating film 9 having a thickness of, for example, about 12 nm is formed on the exposed surfaces of the polycrystalline silicon layer 8 and the element isolation insulating film 5. As the interelectrode insulating film 9, a film having a laminated structure of silicon oxide film / silicon nitride film / silicon oxide film is formed by a known process. In this case, the height of the upper surface of the lower silicon layer 8 a of the polycrystalline silicon layer 8 is configured to be equal to or lower than the height of the lowermost portion of the interelectrode insulating film 9.

  Thereafter, a doped polycrystalline silicon layer to be the conductive layer 10 (control gate electrode film CG) is formed on the interelectrode insulating film 9 by using the CVD method, and a structure as shown in FIG. 10 is obtained. Here, when the conductive layer 10 is formed, the floating gate electrode film FG having a convex cross section having a laminated structure of the lower silicon layer 8a containing nitrogen and the upper silicon layer 8b not containing nitrogen is formed. The opening width of the portion where the element isolation insulating film 5 is dropped is wide, and the embedding property of the conductive layer 10 between the floating gate electrode films FG is improved. For example, phosphorus (P) is used as an impurity of the doped polycrystalline silicon layer to be the conductive layer 10.

  Thereafter, an electrode separation groove 11 (see FIG. 3A) is formed by a known process to obtain a plurality of gate structures. Next, the surface of the silicon substrate 1 at the inner bottom portion of the groove 11 is doped with an impurity by using an ion implantation method to form a diffusion layer 6. Next, an inter-memory cell insulating film 12 is formed in the trench 11 as an inter-cell gate insulating film, and then planarized and dropped. Further, after a nickel silicide (NiSi) layer 10b is formed on the polycrystalline silicon layer (conductive layer) 10, an interlayer insulating film 13 is formed as shown in FIG. Further, although not shown, a NAND flash memory device chip is formed through processes such as contact formation and wiring layer formation.

  In the present embodiment having such a configuration, the amorphous silicon layer 8 to be the floating gate electrode film FG has a lower silicon layer 8a containing nitrogen and an upper silicon layer 8b containing no nitrogen. As a result, when the coating type element isolation insulating film 5 is applied to the element isolation trench 4 and subsequently subjected to heat treatment in a high-temperature steam atmosphere, the coating type element isolation insulating film 5 is modified. Since the silicon layer 8a has a high nitrogen concentration, oxidation hardly proceeds at the time of the heat treatment, and it can be prevented that the dimension in the gate width direction is reduced. That is, according to the present embodiment, the dimension of the lower silicon layer 8a in the gate width direction can be made larger than the dimension of the upper silicon layer 8b in the gate width direction. In other words, the dimension in the gate width direction of the polycrystalline silicon layer 8a in the lower (bottom) portion of the floating gate electrode film FG facing the silicon substrate 1 (active region 3) is the gate width of the silicon substrate 1 that becomes the active region 3. It can be configured to have approximately the same dimensions as the direction. For this reason, according to the present embodiment, the capacitance of the capacitor between the silicon substrate 1 formed via the gate insulating film 7 and the floating gate electrode film FG is not reduced. The amount of charge penetrating the film 7 is not reduced, and therefore, it is possible to prevent the write voltage from increasing.

In this embodiment, since the nitrogen concentration of the lower silicon layer 8a is set to about 1 × 10 ²¹ cm ⁻³ , when the gate width dimension of the gate electrode MG is about 20 nm, the coating type element isolation insulating film The oxidation of the lower silicon layer 8a could be sufficiently suppressed during the heat treatment for reforming 5. Specifically, the thinning amount of the upper silicon layer 8b was about 2 nm on one side, whereas the thinning amount of the lower silicon layer 8a could be suppressed to 1 nm or less on one side. This can sufficiently prevent the write voltage from increasing.

  Furthermore, in the present embodiment, the oxidation of the lower silicon layer 8a can be sufficiently suppressed during the heat treatment, so that the thickening of the end portion of the gate insulating film 7 due to the heat treatment, so-called bird's beak can be reduced. Furthermore, according to the present embodiment, since a carrier trap level is selectively formed at the interface of the floating gate electrode film FG on the gate insulating film 7 side, the voltage at the time of writing in the memory cell transistor (referred to as Vpgm). Can be reduced. Since Vpgm is reduced, the electric field applied to the gate insulating film 7 can be suppressed, so that the reliability of write / erase can be improved.

  Further, in the present embodiment, since the lower dimension of the lower silicon layer 8a in the lower (bottom) portion of the floating gate electrode film FG can be suppressed, the control gate electrode film CG (word line WL) can be reduced. The distance between the lowermost part and the silicon substrate 1 that becomes the active region 3 becomes longer. For this reason, electrons do not enter the floating gate electrode film FG and do not flow directly to the control gate electrode film CG, and generation of memory cells that are not written can be suppressed.

  Furthermore, according to the present embodiment, it is possible to suppress variations in the write voltage Vpgm as indicated by a curve P in FIG. A curve P in FIG. 12 shows the distribution of the write voltage Vpgm of this embodiment, and a curve Q in FIG. 12 shows the distribution of the write voltage Vpgm of the conventional configuration. From FIG. 12, it can be seen that the distribution of the write voltage Vpgm of this embodiment is sharp, that is, the write voltage Vpgm of this embodiment has little variation.

(Other embodiments)
In addition to the embodiment described above, the following configuration may be adopted.
In the above embodiment, the nitrogen concentration of the lower silicon layer 8a of the polycrystalline silicon layer 8 to be the floating gate electrode film FG is about 1 × 10 ²¹ cm ⁻³ , but the present invention is not limited to this, and the lower silicon layer 8a The nitrogen concentration may be set in the range of about 1 × 10 ^{21 to} 5 × 10 ²¹ cm ^−3, and the nitrogen concentration is within the above range so that good characteristics can be obtained according to various conditions such as the gate width dimension. And set as appropriate. If the nitrogen concentration of the lower silicon layer 8a is set to exceed about 5 × 10 ²¹ cm ⁻³ , fixed charges are generated in the lower silicon layer 8a, so that the erase characteristics of the memory cell transistor are deteriorated. There is a fear. If the nitrogen concentration of the lower silicon layer 8a is set to less than about 1 × 10 ²¹ cm ⁻³ , the oxidation of the lower silicon layer 8a may not be sufficiently suppressed during the heat treatment of the coating type element isolation insulating film 5. .

In the above embodiment, when the crystal blocking layer 8c is formed between the lower silicon layer 8a and the upper silicon layer 8b, the N ₂ O gas is introduced into the reaction vessel. , O ₂ gas may be introduced, and the same crystal blocking layer 8c can be formed even with this configuration.

  In the above embodiment, a film having a laminated structure of silicon oxide film / silicon nitride film / silicon oxide film is used as the interelectrode insulating film 9. However, the present invention is not limited to this. For example, a single high dielectric constant is used. Insulating film, or film having a laminated structure of silicon oxide film / high dielectric constant insulating film / silicon oxide film, or film having a laminated structure of silicon nitride film / silicon oxide film / silicon nitride film / silicon oxide film / silicon nitride film May be used.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  In the drawings, 1 is a silicon substrate, 2 is an STI, 3 is an active region, 4 is an element isolation trench, 5 is an element isolation insulating film, 7 is a gate insulating film, 8 is a silicon layer, 8a is a lower silicon layer, and 8b is an upper layer. A silicon layer, 8c is a crystal blocking layer, 9 is an interelectrode insulating film, and 10 is a conductive layer.

Claims (5)

A semiconductor substrate;
An element isolation groove for separating a surface layer portion of the semiconductor substrate into an active region;
An element isolation insulating film embedded in the element isolation trench;
A gate insulating film formed on an active region of the semiconductor substrate;
A gate electrode formed on the gate insulating film, and including a floating gate electrode film, an interelectrode insulating film, and a control gate electrode film,
The floating gate electrode film is formed between a lower silicon layer containing nitrogen at a concentration of 1 × 10 ^{21 to} 5 × 10 ²¹ cm ^−3, an upper silicon layer not containing nitrogen, the lower silicon layer, and the upper silicon layer. It is composed of a polycrystalline silicon layer having a crystal blocking layer that prevents diffusion of intervening nitrogen,
The size in the gate width direction of the lower silicon layer is configured to be larger than the size in the gate width direction of the upper silicon layer,
A semiconductor device characterized in that a height of an upper surface of the lower silicon layer is set to be equal to or lower than a height of a lowermost portion of the interelectrode insulating film. A semiconductor substrate;
A gate insulating film formed on the semiconductor substrate;
A gate electrode formed on the gate insulating film, and including a floating gate electrode film, an interelectrode insulating film, and a control gate electrode film,
The floating gate electrode film is composed of a polycrystalline silicon layer having a lower silicon layer containing nitrogen and an upper silicon layer substantially free of nitrogen,
A semiconductor device, wherein a dimension of the lower silicon layer in the gate width direction is larger than a dimension of the upper silicon layer in the gate width direction.   3. The semiconductor device according to claim 2, wherein a height of an upper surface of the lower silicon layer is set to be equal to or lower than a height of a lowermost portion of the interelectrode insulating film. 4. The semiconductor device according to claim 2, wherein the concentration of nitrogen contained in the lower silicon layer is set to 1 × 10 ^{21 to} 5 × 10 ²¹ cm ⁻³ . Forming a gate insulating film on the semiconductor substrate;
Forming a floating gate electrode film by laminating a lower silicon layer containing nitrogen and an upper silicon layer not containing nitrogen on the gate insulating film;
Forming an element isolation trench in the floating gate electrode film, the gate insulating film and the semiconductor substrate;
Forming an element isolation insulating film by applying an insulating film in the element isolation trench and then performing a heat treatment to process the floating gate electrode film;
Forming an interelectrode insulating film on the element isolation insulating film and the floating gate electrode film;
And a step of forming a control gate electrode film on the interelectrode insulating film.

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