JP2013030984A - Delay-locked loop circuit and lockup method - Google Patents

Abstract

An object of the present invention is to increase the lock-up time while suppressing an increase in layout area.
A delay locked loop circuit according to the present invention includes a delay line, an initial delay monitoring unit, a phase comparison unit, a delay control unit, and a fine delay unit, and includes initial delay monitoring. The unit 4 includes a plurality of phase comparison flip-flops that compare phases of a reference clock and unit delay clocks output by some of the unit delay units, and the phase comparison flip-flops The initial delay monitoring is performed for the entire range by repeating the comparison step by step in units of numbers.
[Selection] Figure 1

Description

  The present invention relates to a delay locked loop (hereinafter referred to as DLL) circuit, and more particularly to a lockup circuit.

  The DLL circuit is widely used to realize a phase adjustment function in a DDR memory interface or the like.

  Patent Document 1 is intended to lock up a DLL circuit at high speed, has a function of performing initial delay monitoring, and generates an initial setting code by the initial delay monitoring. is there. As shown in FIG. 2, the DLL circuit according to the same document includes a clock input buffer (100) (numbers quoted in the same reference are shown in parentheses), initial operation setting means (200), delay line ( 300), fine delay means (400), clock driver (500), delay compensation means (600), phase comparison means (700), initial delay monitoring means (800), and shift register (900).

  The delay line (300) includes n unit delay units (310 <1: n>) connected in series as shown in FIG. Each unit delay unit (310 <1: n>) is configured to output n unit delay clocks (udly <1: n>) one by one.

  The initial delay monitoring means (800) compares the phases of the reference clock (clk_ref) and the n-1 bit unit delay clock (udly <1: n-1>) as shown in FIG. The initial phase information extraction unit (810) that generates the initial phase code (iniph <1: n-1>) and the initial phase code (iniph <1: n-1>) are decoded and the initial setting code (initet < 1: n>) may be included. The first decoding unit 820 may be included.

  The unit delay (clock udly <1: n-1>) output from the delay line (300) is transmitted to the initial delay monitoring means (800). The initial delay monitoring means (800) compares the phases of the n-1 unit delay clocks (udly <1: n-1>) and the reference clock (clk_ref), respectively, and the reference clock (clk_ref) and the feedback clock (clk_fb). ), The initial setting code (initet <1: n>) is generated. In order to make the phases of the reference clock (clk_ref) and the feedback clock (clk_fb) close to each other, it is necessary to know how much the delay line (300) should delay the reference clock (clk_ref). As a result, the initial setting for minimizing the phase difference between the reference clock (clk_ref) and the feedback clock (clk_fb) by n-1 unit delay clocks (udly <1: n-1>) output from the delay line 300. The logical value of the code (initet <1: n>) can be extracted.

  Patent documents 2 to 5 are disclosed as prior arts related to the present invention.

JP 2009-141954 A JP 2003-8411 A JP 2004-110490 A JP 2007-124363 A JP 2000-298532 A

  In recent years, it has been particularly demanded to increase the lock-up time of DLL circuits. In general, in order to speed up the lockup in a DLL circuit, it is necessary to add a circuit for monitoring the initial phase delay and a circuit for determining the number of stages of the delay circuit having a desired phase delay from the result of the initial phase delay. . Such addition of the monitoring circuit and the determination circuit leads to an increase in layout area, and the increase in layout area leads to an increase in the cost of the LSI chip. Therefore, development of a circuit capable of realizing a high lockup time while suppressing an increase in layout area is required.

  According to the technique according to Patent Document 1, the lockup time can be increased, but an increase in layout area becomes a problem. The reason is as follows.

  The delay line (300) includes n unit delay units (310 <1: n>) connected in series, and each unit delay unit (310 <1: n>) includes n unit delay clocks ( udly <1: n>) is output one by one. The initial delay monitoring means (800) compares the phases of the reference clock (clk_ref) and the n-1 bit unit delay clock (udly <1: n-1>), respectively, and the initial phase code (iniph <1: n-1>) to generate an initial phase information extraction unit (810). Further, the initial phase information extraction unit (810) includes n-1 sixth flip-flops (FF6 <1: n-1>) connected in series.

  In the DLL circuit according to Patent Document 1 having the above configuration, unit delay clocks (udly <1: n−1>) are extracted for initial delay monitoring by the number of unit delay units (310) in the delay line (300). There is a need. Also, the initial phase information extraction unit (810) in the initial delay monitoring means (800) requires flip-flops (FF6) by the number of bits of each unit delay clock (udly <1: n-1>). . Furthermore, although not specified in the document, the flip-flop (FF6) is serially 2 at least for each bit of the unit delay clock (udly <1: n-1>) as a countermeasure against the flip-flop metas. Generally, two or more are connected. Therefore, in order to lock up the DLL circuit according to the same document at high speed, a wiring resource for extracting a unit delay clock (udly <1: n-1>) for initial delay monitoring and a flip for extracting initial phase information The number of unit (FF6) is twice as many as the number of unit delay units (310). Therefore, an increase in layout area due to an increase in wiring, elements, etc. cannot be avoided.

  One aspect of the present invention includes a plurality of unit delay units connected in series and each outputting a unit delay clock, a delay line for inputting a reference clock and a stage number control signal, and outputting a phase delay clock, and the reference clock And an initial delay monitoring means for inputting the unit delay clock and outputting a unit delay stage number setting signal as a result of initial delay monitoring, and a phase comparison means for inputting the reference clock and the feedback clock and outputting a phase comparison result signal A delay control means for inputting the unit delay stage number setting signal and the phase comparison result signal, outputting the stage number control signal and the fine delay control signal, and inputting the phase delay clock and the fine delay control signal, Fine delay means for outputting a feedback clock, and the initial delay monitor And a plurality of phase comparison flip-flops for comparing the phases of the reference clock and the unit delay clock output from some of the unit delay units. This is a delay locked loop circuit that performs the initial delay monitoring for the entire range by repeating the comparison step by step with the number of flip-flops as a unit.

  Another aspect of the present invention includes a plurality of unit delay units connected in series, each of which outputs a unit delay clock, a delay line that inputs a reference clock and a stage number control signal, and outputs a phase delay clock; An initial delay monitoring unit that inputs the reference clock and the unit delay clock and outputs a unit delay stage number setting signal that is a result of initial delay monitoring; inputs the reference clock and the feedback clock; and outputs a phase comparison result signal A phase comparison means; a delay control means for inputting the unit delay stage number setting signal and the phase comparison result signal; and outputting the stage number control signal and the fine delay control signal; and the phase delay clock and the fine delay control signal are inputted. And a fine delay means for outputting the feedback clock. A lockup method for a loop circuit, comprising: comparing a phase of the reference clock and the unit delay clock output from some unit delay units of the plurality of unit delay units; and And performing the initial delay monitoring for the entire range by repeating the comparison step by step with the number of unit delay clocks as a unit.

  As a result, the number of unit delay clocks required for initial delay monitoring and the number of flip-flops for extracting initial phase information are smaller than in the prior art.

  According to the present invention, it is possible to increase the lockup time while suppressing an increase in layout area. In addition, an increase in current consumption due to an increase in elements can be prevented.

It is a figure which shows the structure of the DLL circuit which concerns on Embodiment 1 of this invention. FIG. 3 is a diagram illustrating a circuit configuration of a delay line according to the first embodiment. 3 is a diagram illustrating a circuit configuration of an initial delay monitoring unit according to Embodiment 1. FIG. It is a flowchart which shows the lockup flow in the DLL circuit which concerns on Embodiment 1-3. In Embodiment 1 and 2, it is a figure which illustrates the list | wrist of the unit delay part used as the object at the time of dividing and performing initial delay monitoring. In Embodiments 1-3, it is a figure which illustrates the reference | standard which determines the presence or absence of a phase edge. 6 is a diagram illustrating a phase relationship between a reference clock and a unit delay clock input to the initial delay monitoring unit according to the first embodiment. FIG. It is a figure which shows the structure of the DLL circuit which concerns on Embodiment 2 of this invention. 5 is a diagram showing a circuit configuration of a delay line according to Embodiments 2 and 3. FIG. 6 is a diagram illustrating a circuit configuration of an initial delay monitoring unit according to Embodiment 2. FIG. It is a figure which shows the structure of the DLL circuit which concerns on Embodiment 3 of this invention. FIG. 10 is a diagram illustrating a circuit configuration of an initial delay monitoring unit according to a third embodiment. In Embodiment 3, it is a figure which illustrates the list | wrist of the unit delay part used as the object at the time of dividing and performing initial delay monitoring.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a DLL circuit 1 according to Embodiment 1 of the present invention. The DLL circuit 1 includes a clock input buffer 2, a delay line 3, an initial delay monitoring unit 4, a delay control unit 5, a fine delay unit 6, a clock driver 7, and a phase comparison unit 8.

  The clock input buffer 2 receives an external clock CLK_IN and outputs a reference clock CLK_REF.

  The delay line 3 receives the reference clock CLK_REF and the unit delay unit stage number control signal DLYSEL <1: 4n>, and outputs the phase delay clock DOUT and the unit delay clock DLY <n: 1>.

  The fine delay unit 6 receives the phase delay clock DOUT and the fine delay control signal FINECNT and generates a phase delay clock CLK_FB.

  The initial delay monitoring unit 4 receives the reference clock CLK_REF and the unit delay clock DLY <n: 1>, and outputs a unit delay stage number setting signal INT_DLY_CNT as an initial delay monitoring result.

  The phase comparator 8 receives the reference clock CLK_REF and the feedback clock CLK_FB, and outputs a phase comparison result signal PHCMP.

  The delay control unit 5 sets the number of stages of the unit delay unit, receives the phase comparison result signal PHCMP and the unit delay stage number setting signal INT_DLY_CNT as the initial delay monitoring result, and inputs the unit delay unit stage number control signal DLYSEL <1: 4n. > And a fine delay control signal FINECNT are output.

  The clock driver 7 receives the phase delay clock CLK_FB and outputs the phase delay clock CLK_OUT.

  FIG. 2 shows a circuit configuration of the delay line 3. The delay line 3 includes 4n unit delay units 11 <1> to 11 <4n>.

  The unit delay unit 11 <4n> receives the reference clock CLK_REF, the GND level input, and the unit delay unit stage number control signal DLYSEL <4n>, and outputs the unit delay clock CD4n. The unit delay unit 11 <4n-1> receives the unit delay clock CD4n, the reference clock CLK_REF, and the unit delay unit stage number control signal DLYSEL <4n-1>, and outputs the unit delay clock CD4n-1.

  As described above, each of the 4n unit delay units 11 <1> to 11 <4n> inputs the stage number control signal DLYSEL, the reference clock CLK_REF, and the unit delay clock output from the previous unit delay unit 11. The unit delay units 11 <4n> to 11 <1> are connected in series.

  Some of the unit delay units 11 <1> to 11 <n> output unit delay clocks DLY <n> to DLY <1>, respectively, and the unit delay unit 11 <1> outputs a phase delay clock OUT. .

  FIG. 3 shows a circuit configuration of the initial delay monitoring unit 4. The initial delay monitoring unit 4 includes initial delay phase comparison flip-flops 16 <1> to 16 <n>, initial delay phase comparison flip-flops 17 <1> to 17 <n>, and an initial delay control unit 18. .

  The initial delay phase comparison flip-flop 16 <1> outputs the initial phase information INIPH1 <1> with the reference clock CLK_REF as a clock input and the unit delay clock DLY <1> as a data input. The phase comparison flip-flop 17 <1> outputs the initial phase information INIPH2 <1> with the initial phase information INIPH1 <1> as a data input and the reference clock CLK_REF as a clock input. Similarly, the initial delay phase comparison flip-flop 16 <2> receives the reference clock CLK_REF and the unit delay clock DLY <2> as inputs, and outputs a unit delay phase INIPH1 <2>. The phase comparison flip-flop 17 <2> receives the initial phase information INIPH1 <2> and the reference clock CLK_REF, and outputs the initial phase information INIPH2 <2>.

  As described above, combinations of the phase comparison flip-flops 16 <1: n> and the phase comparison flip-flops 17 <1: n> are provided by the number of unit delay clocks DLY <1: n>. Yes. The number n of combinations of the phase comparison flip-flops 16 and 17 corresponds to ¼ of the total number 4n of the unit delay units 11 <1> to 11 <4n> of the delay line 3. Initial phase information INIPH2 <1: n> is generated from each phase comparison flip-flop 17 <1: n>.

  The initial delay control unit 18 receives the initial phase information INIPH2 <1: n>, and outputs a unit delay stage number setting signal INT_DLY_CNT as an initial delay monitoring result.

  The operation of the DLL circuit 1 will be described below. FIG. 4 shows a lock-up flow in the DLL circuit 1. The lockup flow includes an initial delay monitoring flow S10, a fine adjustment delay control S17, and a phase lock determination S18.

  The initial delay monitoring flow S10 includes delay line group setting S11, edge search S12, determination of presence / absence of phase edge S13, switching to the next delay line group S14, initial delay control code calculation S15, and initial delay control code setting S16. .

  The initial delay monitoring flow S10 is performed immediately after the start of the flow, and thereafter, processing is performed in the order of fine adjustment delay control S17 and phase lock determination S18, leading to locking.

  In the initial delay monitoring flow S10, the determination S13 of the presence or absence of a phase edge is performed after the delay line group setting S11 and the edge search S12. If it is determined in the determination S13 that there is no phase edge, the switching to the next delay line group S14 is performed, and then the delay line group setting S11 is performed again. On the other hand, if it is determined in the determination S13 that there is a phase edge, the initial delay control flow S10 and the initial delay control code setting S16 are performed, and then the initial delay monitoring flow S10 is completed.

  The DLL circuit 1 according to the present embodiment includes n unit delay clocks DLY <n: 1> output from the delay line 3. This number is 1/4 of the total number of stages 4n of the unit delay units 11 <1> to 11 <4n>. As shown in the delay line 3 of FIG. 2, among the unit delay units 11 <1> to 11 <4n> connected in series, the unit delay clocks of some of the unit delay units 11 <1> to 11 <n>. Are output as unit delay clock DLY <n: 1>.

  The unit delay clock DLY <n: 1> is input to the initial delay monitoring unit 4. As shown by the initial delay monitoring unit 4 in FIG. 3, the unit delay clock DLY <n: 1> is the n initial delay phase comparison flip-flops 16 <that are ¼ of the total number 4n of the unit delay units 11. Input to 1> to 16 <n>. In the present embodiment, since the number of flip-flops necessary for the countermeasure against metas is assumed to be two, the unit delay clock DLY <n: 1> has n initial delay phase comparison flip-flops. Input also to 17 <1> to 17 <n>.

  Hereinafter, the above-described configuration is applied to the flow of FIG. The initial delay monitoring flow S10 performs a delay line group setting S11 for enabling the delay line 3 to be divided into groups and monitored first. In the setting S11, the unit delay unit 11 of the delay line 3 is set to a desired number of stages by the unit delay unit stage number control signal DLYSEL <4n: 1>. Specifically, the delay line group setting S11 is performed using a list as shown in FIG.

  FIG. 5 exemplifies a list of unit delay units that are targets when initial delay monitoring is performed in a divided manner. The unit delay unit stage number control signal DLYSEL <4n: is output so that a signal delayed from the unit delay clock DLY <n: 1> is output according to the stage number list passing through the unit delay unit 11 in the “1” row of the monitoring order. 1> controls the number of stages passing through the unit delay units 11 <1> to 11 <4n> of the delay line 3. As for the monitoring order “1”, the unit delay unit stage number control signal DLYSEL <n−1: 1> so that the input clock CLK_IN passes through the unit delay units 11 <1> to 11 <n> of the delay line 3. Is fixed to “1”, and the stage number control signal DLYSEL <4n: n> of the unit delay unit is fixed to “0”. As a result, the unit delay clock DLY <n: 1> of the unit delay unit 11 to be a desired initial delay monitoring target is obtained.

  Next, an edge search S12 is performed. FIG. 7 illustrates the phase relationship between the reference clock CLK_REF input to the initial delay monitoring unit 4 and the unit delay clock DLY <n: 1>. The edge search S12 searches for the most appropriate one based on the phase relationship between the reference clock CLK_REF input to the initial delay monitoring unit 4 and the unit delay clock DLY <n: 1>. For example, if it is desired to have the same phase as the phase of the reference clock CLK_REF, the unit delay clock DLY <n: 1> whose phase is closest to that of the reference clock CLK_REF is searched, and DLY <n-2> or DLY is searched. <N-1> is determined to be most appropriate. As means for capturing the phase relationship between the reference clock CLK_REF and the unit delay clock DLY <n: 1> in the edge search S12, a phase comparison flip-flop 16 <1: n> and a phase comparison flip-flop 17 <1: n> are used. Used. As a result, the data unit delay clock DLY <n: 1> is captured at the edge of the reference clock CLK_REF, and the initial phase information INIPH <b> 2 <1: n> is supplied to the initial delay control unit 18.

  The determination S13 of the presence / absence of a phase edge is performed based on the initial phase information INIPH2 <1: n> captured in the edge search S12. FIG. 6 illustrates a criterion for determining the presence or absence of a phase edge. The presence / absence of phase edge is determined by collating the data pattern of the initial phase information INIPH2 <1: n> with the pattern in the table in the phase edge determination order. The collation pattern shown in FIG. 6 illustrates a case where the unit delay clock DLY <n: 1> whose phase is closest to the reference clock CLK_REF is searched. The presence / absence of the phase edge is determined by checking whether or not the data pattern shown in each row in order from the phase edge determination order “1” matches the initial phase information INIPH2 <1: n>. If they match, the determination S13 ends, and the process proceeds to the initial delay control code calculation S15. In this way, by searching whether the pattern of “10” from the left of the row is included in the value of the initial phase information INIPH2 <1: n>, the unit delay clock having the same phase as the reference clock CLK_REF is searched. Although it can be determined whether or not there is DLY <n: 1>, the pattern in FIG. 6 is determined by three values of “100”. This is because the phase comparison flip-flop 16 <1: n> or 17 <1: n due to the jitter of the input clock CLK_IN, the phase of the reference clock CLK_REF and the unit delay clock DLY <n: 1> being close to each other, and the like. This is because it is assumed that the value of the initial phase information INIPH2 <1: n> becomes unstable due to the metas generated at>, so that no erroneous determination occurs in the determination of the presence or absence of the phase edge.

  If it is determined in the determination S13 that there is no phase edge coincidence, switching S14 to the next delay line group is performed. In the switching S14, after the initial delay monitoring target shown in FIG. 5 is updated to the list of the unit delay unit 11 of the next delay line 3, the delay line group setting S11 is performed.

  The delay line group setting S11 is configured so that a delayed signal is output to the unit delay clock DLY <n: 1> according to the setting of the stage number list passing through the unit delay unit 11 in the “2” row of the monitoring order. The number of stages passing through the unit delay units 11 <1> to 11 <4n> of the delay line 3 is controlled by the stage number control signal DLYSEL <4n: 1> of the delay unit. As for the monitoring order “2”, the unit delay unit stage number control signal DLYSEL <2n−1: 1 so that the reference clock CLK_REF passes through the unit delay units 11 <1> to 11 <2n-2> of the delay line 3. > Is fixed to “1”, and the unit delay unit stage number control signal DLYSEL <4n: 2n−2> is fixed to “0”, so that the unit delay clock DLY of the unit delay unit 11 to be a target of initial delay monitoring is set. <N: 1> is obtained.

  In addition, the list of the number of stages passing through the unit delay unit 11 of the delay line 3 to be monitored for initial delay shown in FIG. 5 is set so that the number of stages of the target unit delay unit 11 overlaps before and after the monitoring order. ing. This is because the clock signal input to the input clock CLK_IN generally has a jitter component. Therefore, the number of stages of the unit delay unit 11 to be overlapped is adjusted according to the jitter amount of the clock, and the phase before and after the monitoring order is adjusted. This is in order not to miss the edge. Thereafter, similarly, the processing is repeated until it is determined in step S13 that there is a phase edge.

  If it is determined in the determination S13 that the phase edges match, an initial delay control code calculation S15 is performed to calculate the number of stages of the unit delay unit 11 in which the phase edge is found. This calculation is obtained based on a location where the list of unit delay units 11 that are monitored in FIG. 5 matches the pattern shown in FIG. For example, when the second pattern in the monitoring order in FIG. 5 and the third pattern in the phase edge determination order in FIG. 6 match, the vicinity of the unit delay unit 11 <n + 1> or the unit delay unit 11 <n + 2> This is the number of stages of the unit delay unit 11 that becomes a delay. The initial delay control code setting S16 completes the initial delay monitoring flow S10 by setting the number of stages of the unit delay unit 11 obtained in the initial delay control code calculation S15 to the stage number control signal DLYSEL <4n: 1> of the unit delay unit. To do.

  Thereafter, fine adjustment delay control S17 and phase lock determination S18 are performed. These processes are the same as those for a general DLL circuit lockup. If the phase comparison result PHCMP output from the phase comparison unit 8 is coincident in the phase lock determination S18, it is determined that the DLL circuit is locked, and the lock-up flow ends.

  According to the DLL circuit 1, the unit delay clock DLY <n: 1> for initial delay monitoring is extracted from a part of the plurality of unit delay units 11 <1> to 11 <4n> included in the delay line 3. The unit delay clock DLY <n: 1> is input to the initial delay phase comparison flip-flops 16 <1: n> and 17 <1: n>. The number n of combinations of the phase comparison flip-flops 16 and 17 corresponds to ¼ of the total number 4n of the unit delay units 11. That is, when the number of combinations of the phase comparison flip-flops 16 and 17 is N and the total number of the unit delay units 11 is M, a relationship of M = 4N is established. As a result, the range for performing the initial delay monitoring is divided into four stages for each group, and lockup is performed. As a result, it is possible to increase the lockup time while suppressing an increase in the number of unit delay clocks necessary for initial delay monitoring and the number of flip-flops that extract initial phase information, that is, an increase in layout area. In addition, an increase in current consumption due to an increase in elements can be prevented.

  In this embodiment, the case where the relationship of M = 4N is shown. However, if the relationship of M = α · N (α is an integer of 2 or more) is established, the same effect as described above can be obtained. it can.

Embodiment 2
FIG. 8 shows a configuration of the DLL circuit 21 according to the second embodiment of the present invention. The DLL circuit 21 is different from the DLL circuit 1 according to the first embodiment in the configurations of the delay line 24 and the initial delay monitoring unit 25.

  FIG. 9 shows a circuit configuration of the delay line 24 according to the present embodiment. The delay line 24 includes 4n unit delay units 11 <1> to 11 <4n>, and outputs a unit delay clock DLY <4n: 1> to the outside. Other than this configuration, the configuration is the same as that of the delay line 3 according to the first embodiment.

  FIG. 10 shows a circuit configuration of the initial delay monitoring unit 25 according to the present embodiment. The initial delay monitoring unit 25 receives the unit delay clock DLY <4n: 1> and the selection signal SEL output from the initial delay control unit 18 and outputs a unit delay clock selection result SELDLY <1: n>. A selection circuit 26 is included. The unit delay clock selection result SELDLY <n: 1> is input to the initial delay phase comparison flip-flops 16 <1> to 16 <n>. Other than this configuration, the configuration is the same as that of the initial delay monitoring unit 4 according to the first embodiment.

  The lock-up flow in the DLL circuit 21 is the same as in FIG. 4, and the example of the list of unit delay units when performing the initial delay monitoring in a divided manner is also the same as in FIG. This example is the same as FIG.

  In the delay line group setting S11 of the initial delay monitoring flow S10 in the DLL circuit 21, unit delay clocks DLY <4n: 1 output from all 4n unit delay units 11 <1> to 11 <4n> included in the delay line 24: > Is input to the initial delay monitoring unit 25. The unit delay clock selection circuit 26 of the initial delay monitoring unit 25 receives the unit delay clock DLY <4n: 1>, generates a unit delay clock selection result SELDLY <n: 1> using the list shown in FIG. These are output to flip-flops 16 <1> to 16 <n> for initial delay phase comparison. Operations after the edge search S12 are the same as those in the first embodiment.

  As described above, in the DLL circuit 21 according to the present embodiment, the unit delay clocks DLY <4n: 1> output from all the unit delay units 11 <1> to 11 <4n> included in the delay line 24 are Input to the initial delay monitoring unit 25. The unit delay clock selection circuit 26 refers to the list shown in FIG. 5 and outputs the unit delay clock selection result SELDLY <n: 1> to the initial delay phase comparison flip-flops 16 <1> to 16 <n>. . Thereby, when designing the delay line 24, the initial delay monitoring unit 25 has the bit width of the unit delay clock DLY output from the unit delay units 11 <4n> to 11 <1> as in the first embodiment. There is no need to match the initial delay phase comparison flip-flops 17 <1> to 17 <n>. As a result, the delay line 24 can be designed prior to the initial delay monitoring unit 25, and the already designed delay line 24 can be easily used.

Embodiment 3
FIG. 11 shows the configuration of the DLL circuit 31 according to the third embodiment of the present invention. The DLL circuit 31 has a Master / Slave configuration and includes a Master-DLL circuit 34 and a Slave-Delay circuit 35.

  The same unit delay unit stage number control signal DLYSEL <1: 4n> is input to the four delay lines 3 from the delay control unit 5 for setting the number of unit delay unit stages, and the same fine delay is also input to the four fine delay units 6. A control signal FINECNT is input.

  In the Master-DLL circuit 34, the reference clock CLK_REF is input to the first (leftmost in the figure) delay line 3, and the phase delay clock CO1, the reference clock CLK_REF and the initial delay monitoring unit 37 output from the delay line 3 are output. The delay line group selection signal DLY_GSEL <1> is input to the delay line group selection circuit 41. The selection clock signal CS1 output from the delay line group selection circuit 41 is input to the first fine delay unit 6, and the fine delay unit 6 outputs the phase delay clock FO1.

  The phase delay clock FO1 is input to the second delay line 3, and the phase delay clock CO2, the phase delay clock FO1, and the delay line group selection signal DLY_GSEL <2> output from the delay line 3 are selected as the delay line group. Input to the circuit 42. The selection clock signal CS2 output from the delay line group selection circuit 42 is input to the second fine delay unit 6, and the fine delay unit 6 outputs the phase delay clock FO2.

  The phase delay clock FO2 is input to the third delay line 3, and the phase delay clock CO3, the phase delay clock FO2, and the delay line group selection signal DLY_GSEL <3> output from the delay line 3 are selected as the delay line group. Input to the circuit 43. The selection clock signal CS3 output from the delay line group selection circuit 43 is input to the third fine delay unit 6, and the fine delay unit 6 outputs the phase delay clock FO3.

  The phase delay clock FO3 is input to the fourth delay line 3, and the phase delay clock CO4 output from the delay line 3 is input to the fourth fine delay unit 6. The feedback clock CLK_FB output from the fine delay unit 6 is input to the phase comparison unit 8. The other configuration of the Master-DLL circuit 34 is the same as that of the DLL circuit 21 according to the second embodiment shown in FIG.

  In the slave-delay circuit 35, the external clock CLK2_IN is input to the clock input buffer 45, and the clock input buffer 45 outputs the clock CLK_INT. The delay line 3 receives the clock CLK_INT and outputs the phase delay clock CO5. The fine delay unit 6 receives the phase delay clock CO5 and outputs the phase delay clock FO5. The clock driver 46 receives the phase delay clock FO5 and generates and outputs the phase delay clock CLK2_OUT.

  FIG. 12 shows a circuit configuration of the initial delay monitoring unit 37 according to the present embodiment. The initial delay monitoring unit 37 is different from the initial delay monitoring unit 25 according to the second embodiment in that the initial delay control unit 50 newly outputs a delay line group selection signal DLY_GSEL <1: 3>. To do. Other than this configuration, the initial delay monitoring unit 25 is the same.

  As described above, the DLL circuit 31 according to the present embodiment is a Master / Slave system. The unit delay unit stage number control signal DLYSEL <1: 4n> and the fine delay control signal FINECNT output from the Master-DLL circuit 34 are input to the Slave-Delay circuit 35, and the unit delay unit 11 <1> of the delay line 3 is input. The number of stages of ˜11 <4n> and the delay control of the fine delay unit 6 are performed.

  In the configuration of the Master-DLL circuit 34 shown in FIG. 11, the feedback clock CLK_FB that outputs the reference clock CLK_REF through four combinations of the delay line 3 and the fine delay unit 6 and the reference clock CLK_REF are the phase comparison unit. 8 The number of stages of the unit delay units 11 <1> to 11 <4n> of the delay line 3 and the delay control of the fine delay unit 6 are the same unit so that the phase of the feedback clock CLK_FB is in phase with the reference clock CLK_REF. This is performed by a delay unit stage number control signal DLYSEL <1: 4n> and a fine delay control signal FINECNT. By performing delay control so that the reference clock CLK_REF and the feedback clock CLK_FB have the same phase, the four combinations of the delay line 3 and the fine delay unit 6 are delay-controlled by a delay amount corresponding to the phase 360 degrees of the reference clock CLK_REF. That's right. Each combination of the delay line 3 and the fine delay unit 6 corresponds to a delay amount of 90 degrees in phase of the reference clock CLK_REF.

  In the configuration of the Slave-Delay circuit 35 shown in FIG. 11, since there is one combination of the delay line 3 and the fine delay unit 6, the Slave-Delay circuit 35 is configured such that the external clock CLK2_IN is a 90-degree phase of the reference clock CLK_REF. The phase delay clock CLK2_OUT delayed by an amount corresponding to is output.

  The lock-up flow in the Master-DLL circuit 34 is the same as in FIG. FIG. 13 illustrates a list of unit delay units 11 that are targets when the initial delay monitoring according to the present embodiment is divided and performed. The list includes a list of the number of stages passing through the monitoring order, the delay line group selection DLY_GSEL <1: 3>, and the unit delay units 11 <1> to 11 <4n> of the four delay lines 3 to be monitored for initial delay. included. The stage number list lists the number of stages that pass through the unit delay units 11 <1> to 11 <4n> of the four delay lines 3 of the Master-DLL circuit 34 to be monitored in the order of monitoring the initial delay. It is a thing.

  In the delay line group setting S11 of the initial delay monitoring flow S10 shown in FIG. 4, the delay line group selection DLY_GSEL <1: 3> is set so as to be the number of stages of the unit delay unit 11 shown in the list of FIG. As in the second mode, the unit delay clock DLY <4n: 1> is selected by the unit delay clock selection circuit 26 of the initial delay monitoring unit 37.

  The flow after the edge search S12 is the same as that of the first embodiment. As shown in FIG. 6, the patterns corresponding to the values of the initial phase information INIPH2 <1: n> are collated along the phase edge determination order. A determination S13 of the presence or absence of a phase edge is performed.

  In the first embodiment, the target unit delay units 11 are overlapped so that the unit delay units 11 of the delay line 3 to be monitored for initial delay shown in FIG. 5 do not miss the phase edge before and after the monitoring order. This is the same for the third embodiment. As shown in FIG. 13, the combinations of the number of stages of the unit delay units 11 are similarly set before and after the setting of the delay line group selection DLY_GSEL <1: 3> is switched. The delay line group selection DLY_GSEL <1: 3> is set to the value of the initial phase information INIPH2 <1: n> in the initial delay monitoring unit 37, for example, in the case of shifting from the monitoring order 5 to 6 in FIG. 6, the initial delay control unit 50 of the initial delay monitoring unit 37 determines the value of the delay line group selection DLY_GSEL <1: 3>. The output is changed from “111” to “110”. As a result, the delay line group selection circuits 41 to 43 are switched from the path that does not pass through all the delay lines 3 to the path that only the delay line group selection circuit 43 passes through the delay line 3, and the unit delay clock selection circuit 26 is combined as shown in FIG. Unit delay clock DLY <4n: 1> is selected so that the unit delay clock selection result SELDLY <1: n> is output. Subsequent operations are the same as those in the second embodiment.

  As described above, the DLL circuit 31 according to the present embodiment includes the delay line group selection circuits 41 to 43 and the initial delay monitoring unit 37 in the Master-DLL circuit 34. As a result, when a high-speed lockup function is added to a Master / Slave DLL circuit, an increase in the number of elements of the flip-flop for extracting the initial phase information can be suppressed as in the second embodiment.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

1, 21, 31 DLL circuit 2 Clock input buffer 3, 24 Delay line 4, 25, 37 Initial delay monitoring unit 5 Delay control unit 6 Fine delay unit 7 Clock driver 8 Phase comparison unit 11 Unit delay unit 16, 17 For phase comparison Flip-flop 18 Initial delay control unit 26 Unit delay clock selection circuit 34 Master-DLL circuit 35 Slave-Delay circuit 41, 42, 43 Delay line group selection circuit

Claims (6)

A plurality of unit delay units connected in series, each of which outputs a unit delay clock, a delay line for inputting a reference clock and a stage number control signal and outputting a phase delay clock;
Initial delay monitoring means for inputting the reference clock and the unit delay clock and outputting a unit delay stage number setting signal as a result of initial delay monitoring;
Phase comparison means for inputting the reference clock and the feedback clock and outputting a phase comparison result signal;
A delay control means for inputting the unit delay stage number setting signal and the phase comparison result signal, and outputting the stage number control signal and the fine delay control signal;
Fine delay means for inputting the phase delay clock and the fine delay control signal and outputting the feedback clock;
With
The initial delay monitoring means includes a plurality of phase comparison flip-flops for comparing the phases of the reference clock and the unit delay clock output by some of the unit delay units. The initial delay monitoring is performed for the entire range by repeating the comparison step by step with the number of phase comparison flip-flops as a unit.
Delay lock loop circuit. When the total number of the unit delay units is M and the number of the phase comparison flip-flops is N, a relationship of M = α × N (α is an integer of 2 or more) holds.
The delay locked loop circuit according to claim 1. The total number O of the phase comparison flip-flops is O = N × P, where P is the number of flip-flop stages required for metas countermeasures.
The delay locked loop circuit according to claim 2. The delay line outputs the unit delay clocks from all the unit delay units to the initial delay monitoring unit,
The initial delay monitoring means includes unit delay clock selection means for outputting a part of all the unit delay clocks to the phase comparison flip-flop.
The delay lock loop circuit according to claim 1. With Master / Slave method,
A circuit on the master side inputs a plurality of the delay lines, the same number of fine delay means as the number of the delay lines, the reference clock, the phase delay clock, and the delay line group selection signal, and selects the selected clock signal to the fine delay unit. A plurality of delay line group selection means for outputting
The delay control means outputs the stage number control signal to all the delay lines, and outputs the fine delay control signal to all the fine delay means,
A circuit on the slave side includes a delay line for outputting another reference clock different from the reference clock, and a stage number control signal output from the other reference clock and the delay control means, and outputting the phase unit clock. And a fine delay means for inputting the outputted phase unit clock and a fine delay control signal outputted by the delay control means and outputting a phase delay clock.
The delay lock loop circuit according to claim 1. A plurality of unit delay units connected in series, each of which outputs a unit delay clock, a delay line for inputting a reference clock and a stage number control signal and outputting a phase delay clock;
Initial delay monitoring means for inputting the reference clock and the unit delay clock and outputting a unit delay stage number setting signal as a result of initial delay monitoring;
Phase comparison means for inputting the reference clock and the feedback clock and outputting a phase comparison result signal;
A delay control means for inputting the unit delay stage number setting signal and the phase comparison result signal, and outputting the stage number control signal and the fine delay control signal;
Fine delay means for inputting the phase delay clock and the fine delay control signal and outputting the feedback clock;
A lock-up method of a delay locked loop circuit comprising:
Comparing the phase of the reference clock and the unit delay clock output by some of the unit delay units of the plurality of unit delay units;
Performing the initial delay monitoring for the entire range by repeating the comparison stepwise in units of the number of unit delay clocks used for the comparison;
A lockup method for a delay locked loop circuit comprising:

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