JP2013021790A - Control circuit and control method for switching power supply, and test device using them - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switching power supply with improved load response while maintaining synchronization with another circuit.SOLUTION: A pulse-width modulator 10 generates a pulse-width modulation signal Shaving a duty ratio adjusted so that a feedback voltage Vaccording to an output voltage Vof a switching power supply 4 is close to a predetermined reference voltage V. A low-side comparator 30 generates a first comparison signal CMP1 asserted when the feedback voltage Vis lower than a low-side threshold voltage V. A driver 20 (a) drives a switching transistor M1 on the basis of the pulse-width modulation signal Swhen the first comparison signal CMP1 is negated, and (b1) synchronizes the pulse-width modulation signal Sand drives the switching transistor M1 on the basis of a first fixed pulse signal S1 having a predetermined first pulse width when the first comparison signal CMP1 is asserted.

Description

  The present invention relates to a power supply device.

  In order to supply a stable voltage to the load, a step-up, step-down or step-up / step-down DC / DC converter is used. The DC / DC converter control method includes a voltage mode, a peak current mode, an average current mode, and the like.

FIG. 1 is a diagram illustrating a configuration example of a voltage mode step-down DC / DC converter. The DC / DC converter 4 receives the direct-current voltage _VIN from the direct-current power supply 6 at the input terminal P1, steps down the voltage, and supplies it to the load 8 connected to the output terminal P2.

Pulse width modulator 10r, as the output voltage _{V OUT} of the DC / DC converter 4 is equal to a predetermined reference voltage _{V REF,} to adjust the duty ratio of the pulse width modulation (PWM) signal _{S PWM.} Driver 20r in response to the PWM signal _{S PWM,} and drives the switching transistor M1 and the synchronous rectification transistor M2.

The error amplifier 12 of the pulse width modulator 10r generates an error voltage _VERR corresponding to an error between the feedback voltage _VFB corresponding to the output voltage _VOUT and a predetermined reference voltage _VREF . The PWM comparator 16 compares the sawtooth wave or triangular wave periodic signal V _OSC having a predetermined frequency with the error voltage V _ERR and generates a PWM signal S _PWM whose level changes at each intersection of the two voltages.

  In the DC / DC converter 4r of FIG. 1, the phase rotation increases because of the second-order lag system of the inductor L1 and the output capacitor C1. Accordingly, the phase compensator 14 must be provided after or integrally with the error amplifier 12 to reduce the gain of the feedback loop of the high frequency component. In other words, the transient response characteristic is sacrificed in exchange for the stability of the system. This problem may occur in other types of DC / DC converters including peak current mode, average current mode, fixed on-time (off-time) mode, and may also occur in AC / DC converters.

US Patent Application Publication No. 2006 / 0097712A1

  In order to solve the problem of the transient response characteristic of feedback control using an error amplifier, a hysteresis control type DC / DC converter may be used. In the hysteresis control method, the hysteresis comparator compares the output voltage of the DC / DC converter with a threshold voltage (reference voltage) having hysteresis, and switches the switching transistor according to the comparison result. This method eliminates the need for a phase compensator, and can achieve a high-speed response.

On the other hand, the hysteresis control type DC / DC converter has a problem that the switching frequency varies from moment to moment. When the switching frequency fluctuates, it cannot be synchronized with other DC / DC converters or other circuits.
Further, since ripples are superimposed on the output voltage in principle, it is difficult to reduce noise. Further, if the load capacitor capacity is increased in order to improve the transient response, the intended operation cannot be obtained, and a certain amount of equivalent series resistance (ESR) is required for the load capacitor.

  The present invention has been made in view of such a situation, and one of exemplary purposes of an aspect thereof is to provide a switching power supply with improved load response while maintaining synchronization with another circuit.

  One embodiment of the present invention relates to a control circuit for a switching power supply including a switching transistor. The control circuit includes a pulse width modulator that generates a pulse width modulation signal whose duty ratio is adjusted so that the feedback voltage according to the output voltage of the switching power supply approaches a predetermined reference voltage, and the feedback voltage is set lower than the reference voltage. A lower comparator that generates a first comparison signal that is asserted when the feedback voltage is lower than the lower threshold voltage, and the pulse width modulation signal and the first comparison (A) when the first comparison signal is negated, the switching transistor is driven based on the pulse width modulation signal; and (b1) when the first comparison signal is asserted, the pulse width modulation signal A driver that drives a switching transistor based on a first fixed pulse signal that is synchronized and has a predetermined first pulse width , Comprising a.

  According to this aspect, when the load is stable, the switching transistor is driven based on the pulse width modulation signal, and the output voltage of the switching power supply is stabilized near the target level corresponding to the reference voltage. When the load current increases rapidly, in other words, when the load suddenly increases, the response of the pulse width modulator cannot follow, the feedback voltage drops to the lower threshold voltage, and the first comparison signal is asserted. Thereby, since the control based on the pulse width modulation signal is shifted to the control based on the first fixed pulse signal, the feedback voltage can be immediately brought close to the reference voltage, and the responsiveness can be improved. In addition, since the first fixed pulse signal is generated in synchronization with the pulse width modulation signal, even if a transition occurs between the control based on the first fixed pulse signal and the control based on the pulse width modulation signal, Synchronization with other circuits can be maintained.

  The duty ratio of the first fixed pulse signal may be 90% or more. The duty ratio of the first fixed pulse signal may be 100%.

  When the first comparison signal is asserted, the driver may output a first fixed pulse signal that maintains a level for turning on the switching transistor continuously over a plurality of periods of the pulse width modulation signal.

  Another embodiment of the present invention is also a control circuit. The control circuit includes a pulse width modulator that generates a pulse width modulation signal in which a duty ratio is adjusted so that a feedback voltage according to an output voltage of a switching power supply approaches a predetermined reference voltage, and a feedback voltage from the reference voltage. An upper comparator that generates a second comparison signal that is asserted when the feedback voltage becomes higher than the upper threshold voltage, and compares the pulse width modulation signal and the second comparison signal with a predetermined upper threshold voltage set high. (A) When the second comparison signal is negated, the switching transistor is driven based on the pulse width modulation signal. (B2) When the second comparison signal is asserted, it is synchronized with the pulse width modulation signal. And a driver for driving the switching transistor based on a second fixed pulse signal having a predetermined second pulse width. It includes server and, the.

  According to this aspect, when the load is stable, the switching transistor is driven based on the pulse width modulation signal, and the feedback voltage is stabilized near the reference voltage. When the load current decreases rapidly, in other words, when the load suddenly becomes lighter, the response of the pulse width modulator cannot follow, the feedback voltage rises to the upper threshold voltage, and the second comparison signal is asserted. Thereby, since the control based on the pulse width modulation signal is shifted to the control based on the second fixed pulse signal, the feedback voltage can be immediately brought close to the reference voltage, and the responsiveness can be improved. In addition, since the second fixed pulse signal is generated in synchronization with the pulse width modulation signal, even if a transition occurs between the control based on the second fixed pulse signal and the control based on the pulse width modulation signal, Synchronization with other circuits can be maintained.

  The duty ratio of the second fixed pulse signal may be 10% or less. The duty ratio of the second fixed pulse signal may be 0%.

  When the second comparison signal is asserted, the driver may output a second fixed pulse signal that maintains a level that continuously turns off the switching transistor over a plurality of periods of the pulse width modulation signal.

  Another aspect of the present invention relates to a test apparatus. The test apparatus includes a switching power supply that supplies power to the device under test. The switching power supply is controlled by a control circuit.

  It should be noted that any combination of the above-described constituent elements, and those in which constituent elements and expressions of the present invention are mutually replaced between methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to an aspect of the present invention, the load response of a switching power supply can be improved while maintaining synchronization with another circuit.

It is a figure which shows the structural example of the step-down DC / DC converter of a voltage mode. It is a circuit diagram which shows the DC / DC converter structure which concerns on embodiment. FIGS. 3A and 3B are circuit diagrams illustrating a configuration example of the pulse synthesis unit. It is a block diagram of a test apparatus provided with the DC / DC converter of FIG.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are electrically connected to each other in addition to the case where the member A and the member B are physically directly connected. It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as their electric It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.

FIG. 2 is a circuit diagram showing a configuration of the DC / DC converter 4 according to the embodiment. The DC / DC converter 4 is a synchronous rectification step-down converter, and an input voltage _VIN from the DC power supply 6 is input to an input terminal P1 thereof. A load 8 is connected to the output terminal P2 of the DC / DC converter 4, and an output voltage _VOUT that has been stepped down to a target level by reducing the input voltage _VIN is supplied to the load 8.

  The DC / DC converter 4 includes a control circuit 100 and an output circuit 102. The output circuit 102 includes a switching transistor M1, a synchronous rectification transistor M2, an inductor L1, and an output capacitor C1. Since the configuration of the output circuit 102 is general, the description thereof is omitted.

The control circuit 100 receives the feedback voltage V _FB corresponding to the output voltage _VOUT , and drives the switching transistor M1 and the synchronous rectification transistor M2 so that it matches the reference voltage V _REF corresponding to the target level of the output voltage. .

  The control circuit 100 includes a pulse width modulator 10, a driver 20, a lower comparator 30, and an upper comparator 32.

The pulse width modulator 10 outputs a PWM signal S _PWM whose duty ratio (pulse width) is adjusted so that the feedback voltage V _FB corresponding to the output voltage _VOUT of the DC / DC converter 4 approaches a predetermined reference voltage V _REF. Generate. The pulse width modulator 10 of FIG. 2 is a circuit that performs so-called voltage mode control, but is not particularly limited, and various known modulators that can be used in the future, such as a peak current mode and an average current mode. Is applicable.

The pulse width modulator 10 in FIG. 2 includes an error amplifier 12, a phase compensator 14, a PWM comparator 16, and an oscillator 18. The error amplifier 12 amplifies an error between the feedback voltage V _FB and the reference voltage V _REF and generates an error voltage V _ERR corresponding to the error. The phase compensator 14 removes the high frequency component of the error voltage _VERR . The phase compensator 14 may be configured by combining a low-pass filter or a low-pass filter and a high-pass filter in parallel. Specifically, the error amplifier 12 is a gm amplifier, and the phase compensator 14 may include a capacitor and a resistor connected in series between the output terminal of the error amplifier 12 and the ground terminal.

The oscillator 18 generates a periodic voltage V _OSC of a triangular wave or a sawtooth wave having a predetermined frequency. The oscillator 18 generates a clock signal CLK that is synchronized with the periodic signal V _OSC and has the same frequency. The period of the periodic signal V _OSC and the clock signal CLK is written as T _p . PWM comparator 16, an error voltage _{V ERR} compared to the periodic voltage _{V OSC,} the first level when the V _{ERR> V OSC} (e.g. _high), when V ERR _{<V OSC} second level (e.g., low level) A PWM signal S _PWM is output. The duty ratio of the PWM signal S _PWM (the ratio of the high level period to the period T _p ) is feedback controlled so that the feedback voltage V _FB approaches the reference voltage V _REF .

The lower comparator 30 compares the feedback voltage V _FB corresponding to the output voltage V _OUT of the DC / DC converter 4 with a predetermined lower threshold voltage V _{TH_L} set lower than the reference voltage V _REF . V _TH — _L = V _REF −ΔV _L The lower comparator 30 generates a first comparison signal CMP1 that is asserted (high level) when the feedback voltage _VFB becomes lower than the lower threshold voltage _{VTH_L} .

The upper comparator 32 compares the feedback voltage V _FB with a predetermined upper threshold voltage V _{TH_H} set higher than the reference voltage V _REF . Let V _TH — _H = V _REF + ΔV _H. The upper comparator 32 generates the second comparison signal CMP2 that is asserted (high level) when the feedback voltage _VFB becomes higher than the upper threshold voltage _{VTH_H} .

The driver 20 receives the PWM signal S _PWM , the first comparison signal CMP1, the second comparison signal CMP2, and the clock signal CLK. The driver 20 drives the switching transistor M1 and the synchronous rectification transistor M2 as follows.

(A) When both the first comparison signal CMP1 and the comparison signal CMP2 are negated, in other words, the driver 20 changes the feedback voltage _VFB from the lower threshold voltage _{VTH_L} to the upper threshold voltage _{VTH_H.} The switching transistor M1 and the synchronous rectification transistor M2 are driven based on the PWM signal _SPWM . Specifically, driver 20, PWM signal _{S PWM} has the high level period, turns on the switching transistor M1, off the synchronous rectification transistor M2, PWM signal _{S PWM} has the low level period, turns off the switching transistor M1, synchronization The rectifying transistor M2 is turned on. Note that a dead time may be inserted in order to prevent both the switching transistor M1 and the synchronous rectification transistor M2 from being turned on simultaneously.

(B1) When the first comparison signal CMP1 is asserted, that is, when the feedback voltage _VFB is lower than the lower threshold voltage _{VTH_L} , the driver 20 determines the switching transistor M1 and the switching transistor M1 based on the first fixed pulse signal S1. The synchronous rectification transistor M2 is driven.

First fixed pulse signal S1 is synchronized with the PWM signal _{S PWM,} and has a predetermined first pulse width. For example, the first duty ratio of the first fixed pulse signal S1 is preferably 90% or more. In the present embodiment, the first duty ratio is 100%.

(B2) When the second comparison signal CMP2 is asserted, that is, when the feedback voltage _VFB exceeds the upper threshold voltage _{VTH_H} , the driver 20 switches the switching transistor M1 and the synchronous rectification based on the second fixed pulse signal S2. The transistor M2 is driven.

Second fixed pulse signal S2, as the first fixed pulse signal S1 PWM signal _{S PWM} and synchronized, and has a predetermined second pulse width. For example, the second duty ratio of the second fixed pulse signal S2 is preferably 10% or less. In the present embodiment, the second duty ratio is 0%. That is, the second pulse width is zero.

The driver 20 includes a pulse synthesis unit 22 and a drive unit 24. The pulse synthesizer 22 passes the PWM signal S _PWM from the pulse width modulator 10 when both the first comparison signal CMP1 and the second comparison signal CMP2 are negated (low level). The pulse synthesis unit 22, when the first comparison signal CMP1 is asserted during the one period T _p of the clock signal CLK, and to fix the output at a high level, and outputs a first fixed pulse signal S1. Pulse synthesizing unit 22, the second fixed pulse signal S2 is asserted during the one period T _p of the clock signal CLK, and to fix the output thereof to a low level, and outputs a second fixed pulse signal S2. Incidentally pulse synthesizing unit 22 receives a feedback signal in accordance with the inductor current I _L flowing through the inductor L1, it may be a built-in circuit for current mode control.

FIGS. 3A and 3B are circuit diagrams illustrating a configuration example of the pulse synthesis unit 22. The pulse synthesis unit 22a in FIG. 3A includes a selector SEL and a flip-flop FF. The flip-flop FF latches the first comparison signal CMP1 and the second comparison signal CMP2 for each edge of the clock signal CLK. The selector SEL selects one of the PWM signal S _PWM , the high level voltage V _H , and the low level voltage V _L according to the output signal of the flip-flop FF.

The pulse synthesizer 22b in FIG. 3B includes a flip-flop FF, logic gates OR1, and AND1. The OR gate OR1 generates a logical sum of the PWM signal _SPWM and the latched first comparison signal CMP1. When the first comparison signal CMP1 is asserted, the output of the OR gate OR1 is fixed at a high level over one cycle of the clock signal CLK. The AND gate AND1 generates a logical product of the output of the OR gate OR1 and the inverted signal (# Q2) of the output Q2 of the flip-flop FF. When the second comparison signal CMP2 is asserted, the output of the AND1 gate AND1 is fixed at a low level over one period of the clock signal CLK.

  The configuration of the pulse synthesizing unit 22 is not limited to that shown in FIG. 3, but can be configured by a digital circuit or an analog circuit, and the configuration is not particularly limited.

2 drives the switching transistor M1 and the synchronous rectification transistor M2 in a complementary manner based on the signals S _PWM , S1, and S2 from the pulse synthesis unit 22.

  The above is the configuration of the DC / DC converter 4 according to the embodiment. Next, the operation will be described.

(First control)
In a steady state where the load fluctuation is small, the feedback voltage V _FB is maintained near the reference voltage V _REF . When V _{TH_L} <V _FB <V _{TH_H} holds, both the first comparison signal CMP1 and the second comparison signal CMP2 are negated, and the output voltage _VOUT is maintained at the target level by the feedback loop including the pulse width modulator 10. Be drunk.

(Second control)
When a load change occurs, the pulse width modulator 10 cannot follow the change, and the output voltage _VOUT and the feedback voltage _VFB change. When the load current flowing through the load 8 increases rapidly or the input voltage _VIN decreases rapidly, the output voltage _VOUT decreases, and V _FB <V _{TH_L} and the first comparison signal CMP1 is asserted. As a result, immediately over one period _{T p} of the clock signal CLK (PWM signal), the switching transistor M1 is turned on, the synchronous rectification transistor M2 is fixed to OFF. This is also referred to as second control. As a result, feedback is applied in the direction in which the output voltage _VOUT increases, and control returns to the control by the pulse width modulator 10 when the state returns to the state of V _{TH_L} <V _FB . If the second control over one clock does not return to the first control, the second control is continued in the subsequent period.

(Third state)
On the other hand, when the load current flowing through the load 8 rapidly decreases or the input voltage _VIN increases rapidly, the output voltage _VOUT increases, and V _FB > V _{TH_H} and the second comparison signal CMP2 is asserted. . As a result, immediately over one period _{T p} of the clock signal CLK (PWM signal), the switching transistor M1 is turned off, synchronous rectification transistor M2 is fixed to ON. This is called third control. As a result, feedback is applied in the direction in which the output voltage _VOUT decreases, and when the state returns to the state of V _FB <V _{TH — H} , control by the pulse width modulator 10 is restored. If the third control over one clock does not return to the first control, the third control is continued in the subsequent period.

Thus, according to the DC / DC converter 4 according to the embodiment, the output voltage _VOUT can be kept near the target level with a small ripple by the pulse width modulator 10 having the design compensator in the steady state.

Further, when a steep load fluctuation or input voltage fluctuation occurs and the output voltage _VOUT deviates from the target level, the control immediately switches to the second control or the third control by the lower comparator 30 or the upper comparator 32. Since the feedback loops of the second control and the third control do not have a phase compensator, they have extremely high responsiveness. Therefore, the output voltage _VOUT can be returned to the original target level in a very short time compared to the first control using the pulse width modulator 10.

Furthermore, the first fixed pulse signal S1 and the second fixed pulse signal S2 generated in the feedback control including the lower comparator 30 and the upper comparator 32 are both synchronized with the clock signal CLK, that is, the PWM signal _SPWM . . Therefore, in any case of the feedback control by the pulse width modulator 10 and the feedback control by the lower comparator 30 or the upper comparator 32, the synchronous operation with the oscillator 18 is always guaranteed, and the DC / DC converter 4 and others It is possible to maintain the synchronization of the circuit blocks.

Here, the effect of the DC / DC converter 4 according to the embodiment becomes clearer by comparison with the following comparison technique.
(Comparison technology)
In order to compensate for the drawbacks of the voltage mode and the hysteresis mode, a control circuit combining the voltage mode and the hysteresis mode will be examined. The control circuit according to this comparative technique operates in a voltage mode in a steady state, and can obtain a satisfactory output voltage regulation. Further, when the load fluctuates or the input voltage fluctuates, the operation is performed in the hysteresis mode, and the fluctuation of the output voltage can be suppressed by the high speed response.

  However, since the control circuit according to the comparative technique operates in synchronization with the internal oscillator in the steady state, the frequency synchronization with the external circuit is possible. However, in the transient state, both frequency synchronization and phase synchronization with the external circuit cannot be achieved. Problems arise.

  On the other hand, since the DC / DC converter 4 according to the embodiment always operates in synchronization with the oscillator 18, it is possible to obtain an effect that frequency synchronization and phase synchronization with an external circuit can be maintained.

Subsequently, a preferable setting of the threshold voltages V _{TH_H} and V _{TH_L} will be described. The on-time of the switching transistor M1 is written as T _on and the off-time is written as T _OFF . If the dead time is ignored, T _ON + T _OFF = T _p holds.

During the period in which V _{TH_L} <V _FB <V _{TH_H} is satisfied, the output voltage _VOUT is stabilized at the target level V _OUT1 by the pulse width modulator 10. Ripple [Delta] I ₁ of the inductor current _{I L} flowing through the inductor L1 in the first state is given by equation (1).
ΔI _a = (V _IN −V _OUTa ) T _ON / L = V _OUTa · T _OFF / L (1)

During a period when V _FB <V _{TH — L and} the second control is performed, the switching transistor M1 is turned on and the synchronous rectification transistor M2 is turned off for one cycle T _p of the clock signal CLK. Ripple [Delta] it _b of the inductor current _{I L} at this time is given by Equation (2).
ΔI _b = (V _IN −V _OUTb ) · T _p / L (2)
V _{OUTb in} Equation (2) represents an average level of the output voltage _VOUT during the second control,
V _OUTb = V _OUTa + V _dropb (2a)
Is assumed to hold. However, V _dropb <0.

During a period of V _{TH — H} <V _{FB in} the third state, the switching transistor M1 is turned off and the synchronous rectification transistor M2 is turned on for one cycle T _p of the clock signal CLK. Ripple [Delta] I _c of the inductor current _{I L} at this time is given by Equation (3).
ΔI _c = (V _OUTc ) · T _p / L (3)
V _{OUTc in} Equation (3) represents the average level of the output voltage V _OUT in the third state,
V _OUTc = V _OUTa + V _dropc (3a)
Is assumed to hold. However, V _dropc > 0.

Rewriting equations (2) and (3) with instantaneous values yields equations (2b) and (3b).
ΔI _b (t) = (V _IN −V _OUTa −V _dropb ) · t / L (2b)
ΔI _c (t) = (V _OUTa + V _dropc ) · t / L (3b)

From the expressions (2b) and (3b), the fluctuation amounts ΔV _OUTb and ΔV _OUTc of the output voltage _VOUT during the second control and the third control are given by the expressions (4) and (5), respectively.
ΔV _OUTb = 1 / C × ∫ ₀ ^Tp {(V _IN −V _OUTa −V _dropb ) · t / L} dt
= (V _IN −V _OUTa −V _dropb ) · T _p ² / 2CL (4)
ΔV _OUTc = 1 / C × ∫ ₀ ^Tp {(V _OUTa + V _dropc ) · t / L} dt
= (V _OUTa + V _dropc ) · T _p ² / 2CL (5)

_Assuming that V _dropb and V _dropc are both negligibly small with respect to V _IN −V _OUT and V _OUT , equations (6) and (7) are obtained.
ΔV _OUTb ≈ (V _IN −V _OUTa ) · T _p ² / 2CL (6)
ΔV _OUTc ≈V _OUTa · T _p ² / 2CL (7)

ΔV _OUTb and ΔV _{OUTc in} Expressions (6) and (7) are changes in the output voltage _VOUT when the switching transistor M1 and the synchronous rectification transistor M2 are driven by the first fixed pulse signal S1 and the second fixed pulse signal S2, respectively. Indicates the amount.

Therefore, when ΔV _OUTb ≦ V _dropb , the output voltage V Vc is controlled by switching to the control with the first fixed pulse signal S1 and when ΔV _OUTc ≧ V _dropc , the control with the second fixed pulse signal S2. _OUT can be maintained at the target level V _OUTa . Therefore, the threshold voltages V _{TH_L} and V _{TH_H} may be determined as follows.
_{V TH_L = V REF + ΔV L} = V REF -K b · (V IN -V OUTa) · T p 2 / 2CL
V _TH — _H = V _REF + ΔV _H = V _REF + K _c · (V _OUTa · T _p ² / 2CL)
Here, K _b and K _c are coefficients for increasing the stability of the system, and are set to 1 or more.

Considering the ripple of the output voltage _VOUT , when ΔV _OUTb ≦ V _dropb + V _ripple / 2, the control is switched to the first fixed pulse signal S1, and ΔV _OUTc ≧ V _droppc −V _ripple / 2 In addition, the control may be switched to the control using the second fixed pulse signal S2. Therefore, the threshold voltages V _{TH_L} and V _{TH_H} may be determined as follows.
_{V TH_L = V REF -K b ·} (V IN -V OUTa) · T p 2 / 2CL + V ripple / 2
_{V TH_H = V REF + K c} · (V OUTa · T p 2 / 2CL) -V ripple / 2

In a system in which V _IN and V _OUT are fixed, the threshold voltages V _{TH_L} and V _{TH_H} may be fixed by treating the ripple V _ripple as a constant. Alternatively, to detect the inductor current _{I L,} it may estimate the ripple _{V Ripplestart.} For example, the current mode pulse width modulator 10 has a means for detecting the inductor current IL, which may be used. In this case, the threshold voltages V _{TH_L} and V _{TH_H} can be changed according to the estimated ripple V _ripple , and better control can be performed.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and various modifications may exist in each of those constituent elements, each processing process, and a combination thereof. Hereinafter, such modifications will be described.

(Modification 1) About the type of converter Although the synchronous rectification step-down DC / DC converter 4 has been described in the embodiment, the present invention is not limited thereto. For example, it can be applied to a diode rectification type converter having a diode instead of the synchronous rectification transistor M2. Further, instead of the inductor L1 of the output circuit 102, the present invention can be similarly applied to an insulating converter having a transformer.
Further, the present invention can be applied to a step-up or step-up / step-down DC / DC converter. In these modified examples, the circuit topology of the output circuit 102 may be changed as appropriate, and the configuration of the driver 20 may be modified. Furthermore, the present invention can be applied to an AC / DC converter or a DC / AC converter. That is, it can be applied to various switching power supplies including switching transistors.

(Modification 2) Number of Comparators In the embodiment, the case where the two lower comparators 30 and the upper comparator 32 are provided has been described, but the present invention is not limited thereto. If it is desired to suppress only the drop of the output voltage _VOUT , the upper comparator 32 can be omitted. If only the increase of the output voltage _VOUT is desired to be suppressed, the lower comparator 30 can be omitted.

  Alternatively, a plurality of lower comparators 30 and upper comparators 32 may be provided. In this case, a fixed pulse signal having a different pulse width may be generated for each comparator. For example, when M lower comparators 30 are provided, when the output of the i-th (1 ≦ i ≦ M) lower comparator 30 is asserted, the switching transistor M1 is continuously turned on for i cycles of the clock signal. You may make it do. Similarly, when N upper comparators 32 are provided, when the output of the j-th (1 ≦ j ≦ N) lower comparator 30 is asserted, the switching transistor M1 is continuously connected during the j period of the clock signal. It may be turned off.

(Modification 3) About the pulse widths of the first fixed pulse signal S1 and the second fixed pulse signal S2 In the embodiment, the duty ratio of the first fixed pulse signal S1 is 100%, and the duty ratio of the second fixed pulse signal S2 is Although the case of 0% has been described, the present invention is not limited thereto.
If the amount of change ΔV _OUTb by the second control when the first duty ratio of the first fixed pulse signal S1 is 100% is too large, the first duty ratio may be set to a value smaller than 100%. Similarly, when the change amount ΔV _OUTc by the third control when the second duty ratio of the second fixed pulse signal S2 is 0% is too large, the second duty ratio may be set to a value larger than 0%.

On the other hand, when the change amount ΔV _OUTb by the second control when the first duty ratio of the first fixed pulse signal S1 is 100% is too small, the lower threshold voltage V _{TH_L} is close to the reference voltage V _REF. The circuit operation may become unstable. In this case, the first fixed pulse signal S1 may be maintained at a level at which the switching transistor M1 is continuously turned on over a period of a plurality of n (n is an integer of 2 or more) of the PWM signal (clock signal). That is, the second control may be executed in units of (n × Tp). It can be said that the first duty ratio of the first fixed pulse signal S1 at this time is n × 100%. A clock signal obtained by dividing the clock signal CLK by 1 / n may be supplied to the pulse synthesis unit 22 in FIG.

If the change amount ΔV _OUTc by the third control when the second duty ratio of the second fixed pulse signal S2 is 0% is too small, the upper threshold voltage V _{TH_H} becomes too close to the reference voltage V _REF , Circuit operation may become unstable. In this case, the second fixed pulse signal S2 may be continuously maintained at a level at which the switching transistor M1 is turned off continuously over a period of plural n (n is an integer of 2 or more) of the PWM signal (clock signal). That is, the third control may be executed in units of (n × Tp). A clock signal obtained by dividing the clock signal CLK by 1 / n may be supplied to the pulse synthesis unit 22 in FIG.

(Modification 4)
The assignment of the high level and low level of each signal is an example. For example, in the embodiment, the assertion is described as high level and the negate is described as low level. However, the high level and the low level may be inverted.

  Finally, the use of the DC / DC converter 4 will be described. FIG. 4 is a block diagram of the test apparatus 2 including the DC / DC converter 4 of FIG. The test apparatus 2 gives a signal to the DUT (device under test) 1 and compares the signal from the DUT 1 with an expected value to determine whether the DUT 1 is good or bad.

  The test apparatus 2 includes a driver DR, a comparator (timing comparator) CP, a DC / DC converter 4 and the like. The driver DR outputs a test signal (test pattern) to the DUT 1. This test signal is generated by a timing generator TG, a pattern generator PG, a waveform shaper FC (all not shown) or the like (not shown) and is input to the driver DR. A signal output from the DUT 1 is input to the comparator CP. The comparator CP compares the signal from the DUT 1 with a predetermined threshold value, and latches the comparison result at an appropriate timing. The output of the comparator CP is compared with its expected value.

Output terminal P2 of the DC / DC converter 4 is connected to the power terminal VDD of DUT1 via the power line _{L VDD.} A bypass capacitor (capacitor C1) is connected in the immediate vicinity of the power supply terminal VDD of DUT1. When the DC / DC converter 4 and the DUT 1 are disposed apart from each other, that is, when the power supply line L _VDD is long, the voltage V _FB corresponding to the voltage _VOUT close to the power terminal VDD of the DUT 1 is fed back to the control circuit 100 May be. In this case, some of the feedback voltages V _FB for the error amplifier 12, the lower comparator 30, and the upper comparator 32 are taken out from locations close to the output circuit 102, and some of the rest are taken from locations close to the power supply terminal VDD of the DUT 1. You may take it out. As a result, the oscillation tolerance can be increased and the system can be stabilized.

  During the test, the DUT 1 is given various test patterns, and the operating current of the DUT 1 varies dynamically. Therefore, when the response speed of the DC / DC converter 4 is low, the voltage of the power supply terminal VDD varies greatly. If the power supply voltage fluctuates, even if the DUT 1 is a normal product, there is a possibility that a fail determination is made. For this reason, the DC / DC converter 4 of the test apparatus 2 is required to have high-speed response. The above-described DC / DC converter 4 is suitable for the test apparatus 4 because of its good response.

  The test apparatus 2 is provided with a large number of DC / DC converters 4 in order to test a huge number of DUTs at the same time, but it is desirable that the plurality of DC / DC converters 4 can operate synchronously. Also from this viewpoint, the DC / DC converter 4 of the embodiment can be suitably used for a test apparatus. However, it is needless to say that the use of the DC / DC converter 4 is not limited to the test apparatus 2 and can be used in various fields.

  Although the present invention has been described based on the embodiments, the embodiments merely show the principle and application of the present invention, and the embodiments depart from the idea of the present invention defined in the claims. Many modifications and changes in the arrangement are allowed within the range not to be performed.

DESCRIPTION OF SYMBOLS 1 ... DUT, 2 ... Test apparatus, 4 ... DC / DC converter, 6 ... DC power supply, 8 ... Load, P1 ... Input terminal, P2 ... Output terminal, 10 ... Pulse width modulator, 12 ... Error amplifier, 14 ... Phase Compensator 16 ... PWM comparator 18 ... Oscillator 20 ... Driver 22 ... Pulse synthesis unit 24 ... Drive unit 30 ... Lower comparator 32 ... Upper comparator CMP1 ... First comparison signal CMP2 ... Second comparison Signal, S1 ... first fixed pulse signal, S2 ... second fixed pulse signal, 100 ... control circuit, 102 ... output circuit, M1 ... switching transistor, M2 ... synchronous rectification transistor, L1 ... inductor, C1 ... output capacitor.

Claims (13)

A switching power supply control circuit including a switching transistor,
A pulse width modulator that generates a pulse width modulation signal in which a duty ratio is adjusted so that a feedback voltage corresponding to an output voltage of the switching power supply approaches a predetermined reference voltage;
The feedback voltage is compared with a predetermined lower threshold voltage set lower than the reference voltage and generates a first comparison signal that is asserted when the feedback voltage falls below the lower threshold voltage. Side comparator,
Receiving the pulse width modulation signal and the first comparison signal; (a) when the first comparison signal is negated, driving the switching transistor based on the pulse width modulation signal; and (b1) the first comparison signal. A driver that drives the switching transistor based on a first fixed pulse signal that is synchronized with the pulse width modulation signal and has a predetermined first pulse width when the comparison signal is asserted;
A control circuit comprising:   The control circuit according to claim 1, wherein a duty ratio of the first fixed pulse signal is 100%.   The control circuit according to claim 1, wherein a duty ratio of the first fixed pulse signal is 90% or more.   When the first comparison signal is asserted, the driver outputs the first fixed pulse signal that maintains a level for turning on the switching transistor continuously over a plurality of periods of the pulse width modulation signal. The control circuit according to claim 1. An upper comparator that compares the feedback voltage with a predetermined upper threshold voltage set higher than the reference voltage and generates a second comparison signal that is asserted when the feedback voltage becomes higher than the upper threshold voltage; In addition,
The driver receives the second comparison signal in addition to the pulse width modulation signal and the first comparison signal, and (a) when both the first comparison signal and the second comparison signal are negated, The switching transistor is driven based on a pulse width modulation signal, and (b1) a first fixed pulse that is synchronized with the pulse width modulation signal and has a predetermined first duty ratio when the first comparison signal is asserted. The switching transistor is driven based on a signal, and (b2) when the second comparison signal is asserted, based on a second fixed pulse signal that is synchronized with the pulse width modulation signal and has a predetermined second pulse width. The control circuit according to claim 1, wherein the control circuit drives the switching transistor. A switching power supply control circuit including a switching transistor,
A pulse width modulator that generates a pulse width modulation signal in which a duty ratio is adjusted so that a feedback voltage corresponding to an output voltage of the switching power supply approaches a predetermined reference voltage;
An upper comparator that compares the feedback voltage with a predetermined upper threshold voltage set higher than the reference voltage and generates a second comparison signal that is asserted when the feedback voltage is higher than the upper threshold voltage; ,
Receiving the pulse width modulation signal and the second comparison signal; (a) when the second comparison signal is negated, driving the switching transistor based on the pulse width modulation signal; and (b2) the second comparison signal. A driver that drives the switching transistor based on a second fixed pulse signal that is synchronized with the pulse width modulation signal and has a predetermined second pulse width when the comparison signal is asserted;
A control circuit comprising:   The control circuit according to claim 5 or 6, wherein a duty ratio of the second fixed pulse signal is 0%.   The control circuit according to claim 5 or 6, wherein a duty ratio of the second fixed pulse signal is 10% or less.   When the second comparison signal is asserted, the driver outputs the second fixed pulse signal that maintains a level for turning off the switching transistor continuously over a plurality of periods of the pulse width modulation signal. The control circuit according to claim 5 or 6.   A test apparatus comprising: a switching power supply for supplying power to a device under test, wherein the switching power supply is controlled by the control circuit according to claim 1. A control method of a switching power supply including a switching transistor,
Generating a pulse width modulation signal in which a duty ratio is adjusted so that a feedback voltage according to an output voltage of the switching power supply approaches a predetermined reference voltage;
Comparing the feedback voltage with a predetermined lower threshold voltage set lower than the reference voltage, and generating a first comparison signal that is asserted when the feedback voltage is lower than the lower threshold voltage; When,
(A) when the first comparison signal is negated, drive the switching transistor based on the pulse width modulation signal; and (b1) when the first comparison signal is asserted, the pulse width modulation signal. And driving the switching transistor based on a first fixed pulse signal having a predetermined first pulse width.
A control method comprising: Comparing the feedback voltage with a predetermined upper threshold voltage set higher than the reference voltage and generating a second comparison signal that is asserted when the feedback voltage is higher than the upper threshold voltage. Prepared,
(A) When both the first comparison signal and the second comparison signal are negated, the switching transistor is driven based on the pulse width modulation signal, and (b1) when the first comparison signal is asserted Drives the switching transistor based on a first fixed pulse signal synchronized with the pulse width modulation signal and having a predetermined first pulse width, and (b2) when the second comparison signal is asserted, 12. The control method according to claim 11, wherein the switching transistor is driven based on a second fixed pulse signal that is synchronized with a pulse width modulation signal and has a predetermined second pulse width. A control method of a switching power supply including a switching transistor,
Generating a pulse width modulation signal in which a duty ratio is adjusted so that a feedback voltage according to an output voltage of the switching power supply approaches a predetermined reference voltage;
Comparing the feedback voltage with a predetermined upper threshold voltage set higher than the reference voltage and generating a second comparison signal that is asserted when the feedback voltage is higher than the upper threshold voltage;
(A) when the second comparison signal is negated, drive the switching transistor based on the pulse width modulation signal; and (b2) when the second comparison signal is asserted, the pulse width modulation signal. And driving the switching transistor based on a second fixed pulse signal having a predetermined second pulse width,
A control method comprising:

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