JP2013021219A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method of the same, which can relax electric field concentration at a boundary part between neighboring two semiconductor layers to improve dielectric strength voltage.SOLUTION: A semiconductor device includes an exposed surface 11a of a first semiconductor layer 11, one surface 12a of a second semiconductor layer 12 and surfaces 13Aa, 13Ba of third semiconductor layers 13A, 13B. Because the exposed surface 11a, the one surface 12a, and the surfaces 13Aa, 13Ba are formed so as to have substantially no level differences on borders of the exposed surface 11a, the one surface 12a, and the surfaces 13Aa, 13Ba, a flat gate oxide film 16 with no level difference can be formed on a flat surface Q composed of the exposed surface 11a, the one surface 12a, and the surfaces 13Aa, 13Ba. Accordingly, functions of the gate oxide film 16 are not hindered by electric field concentration on a specific part of the gate oxide film 16 to cause decrease in gate dielectric strength voltage.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technique that can alleviate electric field concentration and improve dielectric strength.

  For example, as a substrate material used for a semiconductor device that controls a high breakdown voltage and a large current, a silicon wafer has been conventionally used. An example of a semiconductor element using a silicon wafer as a substrate material is a MOSFET. Although a large current cannot flow, the MOSFET can be used as a high-speed switching element up to several MHz. However, in recent years, MOSFETs having both a large current and a high-speed switching property have been demanded. In order to realize a MOSFET having such a large current and high-speed switching property, silicon carbide (SiC) is used as a substrate material.

  SiC is a chemically very stable material, has a wide band gap, and has excellent characteristics that it is extremely stable as a semiconductor even in a high temperature environment. SiC also has an excellent feature that the maximum electric field strength that causes avalanche breakdown in the semiconductor substrate is 10 times or more larger than Si.

  An example of a semiconductor device using such a SiC substrate is a planar type MOSFET (see, for example, Patent Document 1). When manufacturing such a planar type MOSFET, for example, as shown in FIG. 8, a channel region 102 is formed in a semiconductor substrate 101, a source region 103 is formed inside the channel region 102, and then a gate oxide film 104 is formed. , And the gate electrode 105 are sequentially formed to form a MOSFET transistor structure.

  Such channel region 102 and source region 103 are obtained by performing ion implantation using the oxide film 106 as a mask, as shown in FIG. When the oxide film 106 has a predetermined shape, a part of the uniformly formed oxide film is removed using a patterned photoresist as a mask.

JP 2008-108869 A

  However, in the manufacture of the conventional MOSFET, a step is generated between the region where the oxide film is left on the surface of the semiconductor substrate and the region where the oxide film is removed, and this step reduces the function of the gate oxide film. There was a problem.

  That is, in the conventional example shown in FIG. 7, when the oxide film 106 is formed in a predetermined shape, if the oxide film 106 is completely removed to the surface of the semiconductor substrate 101 as a base, a part of the semiconductor substrate 101 is also etched. End up. As a result, a step S is generated between the region of the surface of the semiconductor substrate 101 where the oxide film 106 is left and the region where the oxide film is removed. When the transistor structure is formed in a state where such a step S exists, the step is reflected in the gate oxide film 104 shown in FIG. As a result, the electric field concentrates on the step portion of the gate oxide film 104, and the function of the gate oxide film 104 is greatly deteriorated, such as a reduction in gate dielectric strength.

  The present invention has been made in view of the above problems, and provides a semiconductor device and a method of manufacturing the same that can alleviate electric field concentration and improve dielectric strength at the boundary between two adjacent semiconductor layers. The purpose is to do.

In order to solve the above problems, some aspects of the present invention provide the following semiconductor device, Schottky barrier diode, and method for manufacturing the semiconductor device.
That is, a semiconductor device of the present invention includes a first conductivity type semiconductor substrate, a first conductivity type first semiconductor layer formed on one main surface of the semiconductor substrate, and a part of the first semiconductor layer. An exposed surface exposed in the opening region of the first semiconductor layer, and at least a second conductive type second semiconductor layer that exposes the first semiconductor layer in a predetermined opening region. And the height of the step between the first semiconductor layer and the second semiconductor layer at the boundary between the first semiconductor layer and the one surface of the second semiconductor layer extending around the opening region is the exposed surface or the surface of the one surface The roughness is smaller than the smaller value.

A step at a boundary between the exposed surface of the first semiconductor layer and one surface of the second semiconductor layer is 10 nm or less.
In addition, the exposed surface of the first semiconductor layer and the one surface of the second semiconductor layer may spread without a step on the same plane.

  The semiconductor device is a junction barrier Schottky diode, and a metal layer is further disposed on the first semiconductor layer and the second semiconductor layer, and the first semiconductor layer is an n-type that is Schottky joined to the metal layer. The semiconductor and the second semiconductor layer are each composed of a p-type semiconductor.

The semiconductor device is a MOS field effect transistor, a third semiconductor layer of a first conductivity type formed so that a surface is exposed at a part of the second semiconductor layer, the first semiconductor layer, the first semiconductor layer, Further comprising two semiconductor layers, and a gate oxide film and a gate electrode that are arranged in an overlapping manner across the third semiconductor layer,
The step at the boundary between the second semiconductor layer and the third semiconductor layer is formed so that the surface roughness of one surface of the second semiconductor layer or the surface of the third semiconductor layer is smaller than the smaller value. It is characterized by.

  The semiconductor substrate is made of silicon carbide.

  The method of manufacturing a semiconductor device of the present invention includes a step of forming an etching stop layer overlying one main surface of the first conductivity type semiconductor substrate, a step of forming an ion blocking layer overlying the etching stop layer, Removing a portion of the ion blocking layer to form an opening, exposing the etching stop layer at the opening, removing the etching stop layer in a range exposed at the opening; And a step of performing ion implantation toward the semiconductor substrate.

The semiconductor substrate after the ion implantation is further provided with a step of performing a heat treatment of at least 1400 ° C. to activate the implanted ions.
The method further includes the step of forming a sacrificial oxide film before or after the step of forming the etching stop layer.

The step of removing the etching stop layer is a dry process.
The ion blocking layer is made of a silicon oxide film, and the etching stop layer is made of polycrystalline silicon.
The semiconductor substrate is made of silicon carbide.

  According to the present invention, the height of the step between the first semiconductor layer and the second semiconductor layer is any of the surface roughness of the exposed surface of the first semiconductor layer and the surface roughness of one surface of the second semiconductor layer. It is formed so as to be smaller. That is, there is substantially no step at the boundary between the first semiconductor layer and the second semiconductor layer, and the exposed surface of the first semiconductor layer and one surface of the second semiconductor layer constitute the same plane that spreads without a step. .

  Thus, when another functional layer such as an oxide film is stacked on the plane constituted by the exposed surface of the first semiconductor layer and one surface of the second semiconductor layer, the functional layer is formed flat without a step. This suppresses the concentration of the electric field on a specific portion of the functional layer. Therefore, it is possible to realize a semiconductor device in which the electric field concentration on a specific portion is reduced and the withstand voltage is increased.

It is sectional drawing which shows MOSFET which is an example of the semiconductor element of this invention. It is sectional drawing which showed the manufacturing method of the semiconductor element of this invention in steps. It is sectional drawing which showed the manufacturing method of the semiconductor element of this invention in steps. It is sectional drawing which showed the manufacturing method of the semiconductor element of this invention in steps. It is sectional drawing which showed the manufacturing method of the semiconductor element of this invention in steps. It is sectional drawing which shows SBD which is an example of the semiconductor element of this invention. . It is sectional drawing which shows the manufacturing process of the semiconductor element (MOSFET) of a prior art example. It is sectional drawing of the semiconductor element (MOSFET) of a prior art example.

A semiconductor device, a Schottky barrier diode, and a method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings. In the following embodiments, a MOS field effect transistor (MOSFET) will be described as an example of a semiconductor device, but the semiconductor device of the present invention is not limited to a MOSFET.
The following embodiments are specifically described for better understanding of the gist of the invention, and do not limit the configuration of the invention unless otherwise specified. In addition, the drawings used in the following description may show the main parts in an enlarged manner for convenience in order to make the features of the present invention easier to understand. It is not always the same.

(Configuration of MOSFET)
FIG. 1 is a cross-sectional view showing a configuration example of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) which is an embodiment of a semiconductor device of the present invention.
This MOSFET (semiconductor device) 1 is a power MOSFET designed to handle a large amount of power and has a high switching speed and a high conversion efficiency in a low voltage region. It is done. Hereinafter, a planar gate type N-channel MOSFET will be exemplified.

The semiconductor substrate 10 may be made of, for example, SiC (silicon carbide) which is an n-type (first conductivity type) semiconductor doped with about 2 × 10 ¹⁸ cm ⁻³ of nitrogen as an impurity. As is well known, SiC (silicon carbide) has different types of crystal structures such as 2H, 3C, 4H, 6H, 8H, 10H, and 15R depending on the arrangement of C atoms and Si atoms. Even SiC can be used as the semiconductor substrate 10.

A first semiconductor layer 11 is formed on one main surface 10 a of the semiconductor substrate 10. The first semiconductor layer 11 may be, for example, a layer in which n ^- type (first conductivity type) SiC doped with about 1.0 × 10 ¹⁶ cm ^{−3 of} n-type impurities is laminated to a thickness of about 10 μm. The first semiconductor layer 11 may be formed on one main surface 10a of the semiconductor substrate 10 by epitaxial growth.

A second semiconductor layer 12 is further formed in a partial region of the first semiconductor layer 11. For example, the second semiconductor layer 12 may be a region made of p-type (second conductivity type) SiC doped with about 2.1 × 10 ¹⁷ cm ^{−3 of} Al ions. The second semiconductor layer 12 is formed by performing ion implantation on a partial region of the first semiconductor layer 11.

  The periphery of the region where the second semiconductor layer 12 is formed is an opening region 19 that exposes the first semiconductor layer 11, and the exposed surface 11 a of the first semiconductor layer 11 is exposed inside the opening region 19. Further, one surface 12a of the second semiconductor layer 12 extends around the exposed surface 11a. That is, the exposed surface 11a of the first semiconductor layer 11 and the one surface 12a of the second semiconductor layer 12 spread on the same plane Q.

Third semiconductor layers 13 </ b> A and 13 </ b> B are further formed in a partial region of the second semiconductor layer 12. The third semiconductor layers 13A and 13B may be, for example, a region made of n ⁺ type (first conductivity type) SiC doped with about 1.0 × 10 ¹⁹ cm ^{−3 of} n type impurities. The third semiconductor layers 13A and 13B serve as source regions, and the region between the second semiconductor layers 12 serves as a drain region. The third semiconductor layers 13 </ b> A and 13 </ b> B are formed by performing ion implantation on a partial region of the second semiconductor layer 12.

  The respective surfaces 13Aa and 13Ba of the third semiconductor layers 13A and 13B spread on the same plane Q as the exposed surface 11a of the first semiconductor layer 11 and the one surface 12a of the second semiconductor layer 12.

Further, a gate oxide film 16 and a gate electrode 17 are formed in order on the plane Q across the first semiconductor layer 11, the second semiconductor layer 12, and the third semiconductor layer 14.
The gate oxide film 16 may be made of SiO _{2 having a} thickness of about 100 nm, for example. The gate electrode 17 may be made of, for example, polysilicon. The gate electrode 17 is stacked on the plane Q via the gate oxide film 16, and the periphery is covered with an interlayer insulating film 18.

  As is well known, the MOSFET 1 configured as described above forms a channel on the surface of the second semiconductor layer 12, which is a p-type semiconductor, when a voltage is applied to the gate electrode 17. As a result, conduction between the third semiconductor layers 13A and 13B (source region) and the region (drain region) between the second semiconductor layers 12 becomes possible. The current value at this time can be controlled by the voltage applied to the gate electrode 17.

In the MOSFET 1 of the present invention, the height of the step S1 at the boundary between the exposed surface 11a of the first semiconductor layer 11 and the one surface 12a of the second semiconductor layer 12 is the surface roughness of the exposed surface 11a and the height of the one surface 12a. It is formed so as to be smaller than any of the surface roughness (see the lower right in FIG. 1).
For example, the surface roughness (average) of the exposed surface 11a of the first semiconductor layer 11 is about 5 to 15 nm, and the surface roughness (average) of the one surface 12a of the second semiconductor layer 12 is about 5 to 15 nm. It is said. Therefore, the height of the boundary step S1 is smaller than the surface roughness. The height of the boundary step S1 is formed to be 10 nm or less, for example.

  Accordingly, there is substantially no step at the boundary between the exposed surface 11 a of the first semiconductor layer 11 and the one surface 12 a of the second semiconductor layer 12, and the exposed surface 11 a of the first semiconductor layer 11 and the second semiconductor layer 12 The one surface 12a is the same plane Q that spreads without a step.

On the other hand, the height of the step S2 at the boundary between the one surface 12a of the second semiconductor layer 12 and the surfaces 13Aa and 13Ba of the third semiconductor layers 13A and 13B is also the surface roughness of the surface 12a and the surfaces of the surfaces 13Aa and 13Ba. It is formed so as to be smaller than any roughness (see the lower left in FIG. 1).
For example, the surface roughness (average) of the surfaces 13Aa and 13Ba of the third semiconductor layers 13A and 13B is about 5 to 20 nm. Accordingly, the height of the step S2 at the boundary is formed smaller than the surface roughness. The height of the boundary step S2 is, for example, 10 nm or less.

  As a result, there is substantially no step at the boundary between the one surface 12a of the second semiconductor layer 12 and the surfaces 13Aa and 13Ba of the third semiconductor layers 13A and 13B. The surfaces 13Aa and 13Ba of the semiconductor layers 13A and 13B are the same plane Q extending without a step, and together with the exposed surface 11a described above, the exposed surface 11a of the first semiconductor layer 11, the one surface 12a of the second semiconductor layer 12, and The surfaces 13Aa and 13Ba of the third semiconductor layers 13A and 13B form the same plane Q that does not substantially have a step at each boundary and spreads without a step.

In this way, the exposed surface 11a of the first semiconductor layer 11, the one surface 12a of the second semiconductor layer 12, and the surfaces 13Aa and 13Ba of the third semiconductor layers 13A and 13B are formed so that the step is substantially eliminated. As a result, the flat gate oxide film 16 can be formed on the flat surface Q including the exposed surface 11a, the entire surface 12a, and the surfaces 13Aa and 13Ba.
As a result, the electric field concentrates on a specific portion of the gate oxide film 16, and the function of the gate oxide film 16 such as a decrease in the gate withstand voltage is not significantly impaired.

That is, in the conventional MOSFET shown in FIG. 8, a step S is generated between the region of the surface of the semiconductor substrate 101 where the oxide film is left and the region where the oxide film is removed, and the gate oxide film 104 also has a step. It will be reflected. As a result, the electric field concentrates on the step portion of the gate oxide film 104, and the function of the gate oxide film 104 is greatly deteriorated, such as a reduction in gate dielectric strength.
However, in the present embodiment, since the flat gate oxide film 16 without a step is formed on the plane Q, the electric field concentration on a specific portion of the gate oxide film 16 is alleviated, and the MOSFET 1 with an increased withstand voltage can be realized. .
A method for obtaining a MOSFET that substantially eliminates such a step will be described in detail below.

(Manufacturing method of MOSFET)
Next, an example of a method for manufacturing the MOSFET having the configuration shown in FIG. 1 will be described. 2 to 5 are cross-sectional views illustrating an example of a method of manufacturing a semiconductor device according to the present invention in stages.
When manufacturing a MOSFET which is an example of the semiconductor device of the present invention, a semiconductor substrate 10 is first prepared as shown in FIG. As the semiconductor substrate 10, for example, a SiC wafer made of SiC (silicon carbide) which is an n-type (first conductivity type) semiconductor doped with about 2 × 10 ¹⁸ cm ⁻³ of nitrogen as an impurity may be used.

Then, the first semiconductor layer 11 is stacked on one main surface 10 a of the semiconductor substrate 10. The first semiconductor layer 11 may be, for example, a layer in which n ⁻ type (first conductivity type) SiC doped with n type impurities of about 1.0 × 10 ¹⁶ cm ^{−3 is} stacked with a thickness of about 10 μm. . The first semiconductor layer 11 may be formed on one main surface 10a of the semiconductor substrate 10 by epitaxial growth.

  Next, as shown in FIG. 2B, an etching stop layer 21 is formed on the upper surface of the first semiconductor layer 11 (step of forming an etching stop layer over one main surface of the semiconductor substrate). Further, as shown in FIG. 2C, an ion blocking layer 22 is formed on the upper surface of the etching stop layer 21 (step of forming an ion blocking layer overlying the etching stop layer).

  The etching stop layer 21 may be made of, for example, polycrystalline silicon or silicon nitride. In forming the etching stop layer 21, film formation may be performed by a dry process such as CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), or the like.

The ion blocking layer 22 may be made of, for example, silicon oxide (SiO ₂ ). In forming the ion blocking layer 22, for example, film formation may be performed by a dry process such as CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), or the like.

  Next, as shown in FIG. 2D, the ion blocking layer 22 is patterned into a predetermined shape by photolithography. For example, the ion blocking layer 22 is left in a region where ion implantation is not performed, and the ion blocking layer 22 in a portion to be the second semiconductor layer is removed. As a result, an opening 23 exposing the etching stop layer 21 is formed in the portion to be the second semiconductor layer (the ion blocking layer is partially removed to form an opening, and the etching stop is formed in the opening. Exposing the layer).

  In patterning the ion blocking layer 22 serving as a mask when performing ion implantation for forming the second semiconductor layer into a predetermined shape, etching is performed between the ion blocking layer 22 and the first semiconductor layer 11. A stop layer 21 is formed. This prevents the surface layer of the first semiconductor layer 11 from being scraped when the ion blocking layer 22 is removed by dry etching, for example.

  That is, conventionally, when the ion blocking layer serving as a mask is patterned into a predetermined shape, the ion blocking layer is dried until it reaches the surface layer of the first semiconductor layer so that the ion blocking layer does not remain on the surface layer of the first semiconductor layer. It was necessary to remove by etching. However, in this case, it is difficult to prevent a part of the surface layer of the first semiconductor layer from being etched by dry etching, and a step is generated in the surface layer of the first semiconductor layer between the portion where the ion blocking layer is left ( (See FIG. 7).

  On the other hand, in the method for manufacturing a semiconductor device of the present invention, an etching stop layer 21 made of a material different from the ion blocking layer 22, for example, polycrystalline silicon or silicon nitride, is interposed between the ion blocking layer 22 and the first semiconductor layer 11. By forming it, even if the portion to be removed of the ion blocking layer 22 is completely removed, the surface layer of the first semiconductor layer 11 may be damaged or partially removed due to the presence of the etching stop layer 21. There is nothing.

In order to realize such an action, it is preferable that the material of the etching stop layer 21 is made of a material that is difficult to be removed by dry etching when the ion blocking layer 22 is formed in a predetermined pattern. For example, when the ion blocking layer 22 is made of silicon oxide (SiO ₂ ), the etching stop layer 21 is preferably made of polycrystalline silicon or silicon nitride.

  Next, as shown in FIG. 3A, the portion of the etching stop layer 21 exposed at the opening 23 is removed (step of removing the etching stop layer in the range exposed at the opening). The etching stop layer 21 may be removed by a dry process. Specifically, RIE (Reactive Ion Etching) using a fluorine radical as an etching gas can be mentioned. In this case, it is preferable to use a remote plasma method as a method for supplying fluorine radicals.

  Furthermore, as a remote plasma method, it is preferable to use an electron cyclotron resonance (ECR) plasma using a discharge generated by applying a microwave of 2.45 GHz and a magnetic field and resonantly absorbing the microwave. The etching gas used for the remote plasma method may be a gas containing at least fluorocarbon and oxygen.

  According to such a step of removing the etching stop layer 21, the etching stop layer 21 exposed at the opening 23 can be reliably removed until the surface layer of the first semiconductor layer 11 is exposed, and the exposed first semiconductor The layer 11 itself is not shaved. As a result, the surface layer (surface) of the first semiconductor layer 11 includes a region where the ion blocking layer 22 which becomes a mask in the next step is left (covered), and a region where the ion blocking layer 22 is removed and exposed. It spreads in a uniform plane Q with no step between them. Here, the term “no step” means that a step having a height larger than the surface roughness of the surface (one surface) of the first semiconductor layer 11 is removed from the region where the ion blocking layer 22 is left and the ion blocking layer 22 removed. It does not occur between the specified areas.

Next, as shown in FIG. 3B, a second semiconductor layer that becomes a p-type (second conductivity type) semiconductor by doping impurities to a predetermined depth of the first semiconductor layer 11 using the ion blocking layer 22 as a mask. 12 is formed (step of ion implantation toward the semiconductor substrate). In forming the second semiconductor layer 12, for example, Al ions may be doped to about 2.1 × 10 ¹⁷ cm ⁻³ to form a region made of p-type (second conductivity type) SiC.

  Next, as shown in FIG. 3C, the ion blocking layer 22 and the etching stop layer 21 below the ion blocking layer 22 used as a mask for forming the second semiconductor layer 12 are removed. The removal of the ion blocking layer 22 as a mask is removed by wet etching, and the etching stop layer 21 is removed by using dry etching such as the above-described remote plasma method to thereby form the first semiconductor layer 11 and the second semiconductor layer 11. The semiconductor layer 12 can be reliably removed without being scraped.

  Through these steps, the one surface 12a of the second semiconductor layer 12 and the exposed surface 11a of the first semiconductor layer 11 exposed by the opening region 19 of the second semiconductor layer 12 are uniform with no step at the boundary. A flat plane Q is formed. Here, the term “no step” refers to a step having a height greater than both the surface roughness of the exposed surface 11a of the first semiconductor layer 11 and the surface roughness of the one surface 12a of the second semiconductor layer 12. That is, it does not occur at the boundary between the exposed surface 11 a of the semiconductor layer 11 and the one surface 12 a of the second semiconductor layer 12.

A sacrificial oxide film (through film) may be further formed between the etching stop layer 21 and the first semiconductor layer 11 or between the first semiconductor layer 11 and the ion blocking layer 22. Such a sacrificial oxide film (through film) is made of, for example, silicon oxide (SiO ₂ ), and protects the lower layer film when the ion blocking layer 22 and the etching stop layer 21 are removed by a dry process.

  Next, as shown in FIG. 3 (d), the etching stop layer 26 and the ion blocking layer 27 are again formed so as to overlap the plane Q formed by the exposed surface 11 a of the first semiconductor layer 11 and the one surface 12 a of the second semiconductor layer 12. Form.

  The etching stop layer 26 may be made of, for example, polycrystalline silicon or silicon nitride. In forming the etching stop layer 26, film formation may be performed by a dry process such as CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), or the like.

The ion blocking layer 27 may be made of, for example, silicon oxide (SiO ₂ ). In forming the ion blocking layer 27, film formation may be performed by, for example, a dry process such as CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), or the like.

  Next, as shown in FIG. 4A, the ion blocking layer 27 is patterned into a predetermined shape by photolithography. For example, the ion blocking layer 27 in a region where no ion implantation is performed is left, and a portion of the ion blocking layer 27 corresponding to the source region of the third semiconductor layer is removed. As a result, an opening 28 exposing the etching stop layer 26 is formed in the portion that becomes the source region of the third semiconductor layer.

  In patterning the ion blocking layer 27 serving as a mask when performing ion implantation for forming the source region of the third semiconductor layer into a predetermined shape, the ion blocking layer 27 and the second semiconductor layer 12 An etching stop layer 26 is formed therebetween. This prevents the surface layer of the second semiconductor layer 12 from being scraped when the ion blocking layer 27 is removed by dry etching, for example.

  That is, by forming an etching stop layer 26 made of a material different from that of the ion blocking layer 27, for example, polycrystalline silicon or silicon nitride, between the ion blocking layer 27 and the first semiconductor layer 13, the ion blocking layer 27 is formed. Even if the portion to be removed is completely removed, the surface layer of the second semiconductor layer 12 is not damaged due to the presence of the etching stop layer 26, or a part thereof is not scraped off.

In order to realize such an action, it is preferable that the material of the etching stop layer 26 is made of a material that is not easily removed by dry etching when forming the ion blocking layer 26 in a predetermined pattern. For example, when the ion blocking layer 27 is made of silicon oxide (SiO ₂ ), the etching stop layer 26 is preferably made of polycrystalline silicon or silicon nitride.

  Next, as shown in FIG. 4B, the etching stop layer 26 exposed at the opening 28 is removed. The removal of the etching stop layer 26 may be performed by a dry process. Specifically, RIE (Reactive Ion Etching) using a fluorine radical as an etching gas can be mentioned. In this case, it is preferable to use a remote plasma method as a method for supplying fluorine radicals.

  According to such a step of removing the etching stop layer 26, the etching stop layer 26 exposed at the opening 28 can be reliably removed until the surface layer of the second semiconductor layer 12 is exposed, and the exposed second semiconductor. The layer 12 itself is not scraped. As a result, the surface layer (surface) of the second semiconductor layer 12 includes a region where the ion blocking layer 27 which becomes a mask in the next step is left (covered), and a region where the ion blocking layer 27 is removed and exposed. It spreads in a uniform plane Q with no step between them. Here, the term “no step” means that a step having a height larger than the surface roughness of the surface (one surface) of the second semiconductor layer 12 is removed from the region where the ion blocking layer 27 remains and the ion blocking layer 27 are removed. It does not occur between the specified areas.

Next, as shown in FIG. 4C, an impurity is doped to a predetermined depth of the second semiconductor layer 12 using the ion blocking layer 27 as a mask to form an n ⁺ type (first conductivity type) semiconductor. Layers 13A and 13B are formed. In forming the third semiconductor layers 13A and 13B, for example, an n-type impurity may be doped by about 1.0 × 10 ¹⁹ cm ⁻³ to form a region made of n ⁺ -type (first conductivity type) SiC. The third semiconductor layers 13A and 13B are used as source regions.

  Next, as shown in FIG. 4D, the ion blocking layer 27 and the etching stop layer 26 underneath are removed as a mask for forming the third semiconductor layers 13A and 13B. The removal of the ion blocking layer 27 as a mask is removed by wet etching, and the etching stop layer 26 is also removed by using the first semiconductor layer 11 and the second semiconductor layer 11 by dry etching such as the remote plasma method described above. The semiconductor layer 12 can be reliably removed without being scraped.

  Through these steps, the surfaces 13Aa and 13Ba of the third semiconductor layers 13A and 13B and the one surface 12a of the second semiconductor layer 12 form a uniform plane Q having no step at the boundary. Note that the absence of a step here means a step having a height greater than the surface roughness of one surface 12a of the second semiconductor layer 12 and the surface roughness of the surfaces 13Aa and 13Ba of the third semiconductor layer 13. That is, it does not occur at the boundary between the one surface 12a of the second semiconductor layer 12 and the surfaces 13Aa and 13Ba of the third semiconductor layers 13A and 13B.

  Through the above-described steps, the exposed surface 11a of the first semiconductor layer 11, the one surface 12a of the second semiconductor layer 12, and the surfaces 13Aa and 13Ba of the third semiconductor layers 13A and 13B constitute the same plane Q and have no step. Spread like.

  Thereafter, in order to activate the second semiconductor layer 12 and the third semiconductor layers 13A and 13B formed by ion implantation, that is, to activate the implanted ions, the second semiconductor layer 12 and the third semiconductor layers 13A and 13B are included. The entire semiconductor substrate 10 is heat-treated to about 1400 ° C., for example.

Next, as shown in FIG. 4D, the gate oxide film 16 and the gate electrode 17 are formed so as to overlap the first semiconductor layer 11, the second semiconductor layer 12, and the third semiconductor layers 13A and 13B. It is formed in order. The gate oxide film 16 may be made of SiO _{2 having a} thickness of about 100 nm, for example. The gate electrode 17 may be made of, for example, polysilicon.

  Then, as shown in FIG. 5A, after patterning the gate electrode, an interlayer insulating film 18 is further formed so as to cover the gate electrode 17 to insulate the periphery of the gate electrode 17, and the semiconductor device of the present invention. As a result, the MOSFET 1 is completed.

  When the gate electrode 17 and the gate oxide film 16 are formed, the exposed surface 11a of the first semiconductor layer 11, the one surface 12a of the second semiconductor layer 12, and the surfaces 13Aa and 13Ba of the third semiconductor layers 13A and 13B are the same. Therefore, the gate electrode 17 and the gate oxide film 16 formed on the plane Q can be formed flat (with a uniform thickness) without any step. Become. As a result, the obtained MOSFET 1 has a MOSFET (semiconductor device) 1 in which the electric field is not concentrated on a specific portion of the gate oxide film 16 and the withstand voltage is not lowered, and the electric field concentration is reduced and the withstand voltage is improved. Can be obtained.

(Configuration of SBD)
FIG. 6 is a cross-sectional view showing an example of a junction barrier Schottky diode (JBS) which is another embodiment of the semiconductor device of the present invention.
The junction barrier Schottky diode (JBS) 3 has an n-type (first conductivity type) first semiconductor layer 31 formed on one main surface 30 a of the semiconductor substrate 30. A p-type (second conductivity type) second semiconductor layer 32 is formed on the surface layer side of the first semiconductor layer 31. The second semiconductor layer 32 includes a region 32A having a constant impurity concentration and a region 32B having an impurity concentration profile.

  The first semiconductor layer 31 is exposed as an exposed surface 31 a in the opening region 39 of the second semiconductor layer 32. The exposed surface 31a and the one surface 32a of the second semiconductor layer 31 have no step at the boundary and constitute a uniform plane Q. Then, a metal layer 33 is formed so as to overlap the plane Q.

Thereby, the metal layer 33 can be formed evenly and flatly with a uniform thickness without a step.
In such a junction barrier Schottky diode (JBS) 3 as well, the metal layer 33 can be identified by forming without a step at the boundary between the exposed surface 31a of the first semiconductor layer 31 and the one surface 32a of the second semiconductor layer 31. It is possible to obtain a JBS (semiconductor device) 3 in which the electric field is concentrated on the portion, the increase in leakage current is reduced, the electric field concentration is reduced, and the increase in leakage current is small.

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device (MOSFET), 3 ... Semiconductor device (JBS), 10 ... Semiconductor substrate, 11 ... 1st semiconductor layer, 11a ... Exposed surface, 12 ... 2nd semiconductor layer, 12a ... One side.

Claims (12)

A first conductivity type semiconductor substrate;
A first semiconductor layer of a first conductivity type formed on one main surface of the semiconductor substrate;
A second conductivity type second semiconductor layer formed so as to cover a part of the first semiconductor layer and exposing the first semiconductor layer in a predetermined opening region;
The first semiconductor layer and the second semiconductor layer at a boundary between an exposed surface of the first semiconductor layer exposed in the opening region and one surface of the second semiconductor layer extending around the opening region. The height of the step between the semiconductor layer and the semiconductor layer is formed such that the surface roughness of the exposed surface of the first semiconductor layer or one surface of the second semiconductor layer is smaller than the smaller value. A semiconductor device.   The semiconductor device according to claim 1, wherein a step at a boundary between the exposed surface of the first semiconductor layer and one surface of the second semiconductor layer is 10 nm or less.   2. The semiconductor device according to claim 1, wherein the exposed surface of the first semiconductor layer and the one surface of the second semiconductor layer extend on the same plane.   The semiconductor device is a junction barrier Schottky diode, and a metal layer is further disposed on the first semiconductor layer and the second semiconductor layer, and the first semiconductor layer is an n-type that is Schottky joined to the metal layer. 4. The semiconductor device according to claim 1, wherein the semiconductor and the second semiconductor layer are each composed of a p-type semiconductor. The semiconductor device is a MOS field effect transistor, a third semiconductor layer of a first conductivity type formed so that a surface is exposed at a part of the second semiconductor layer, the first semiconductor layer, the first semiconductor layer, Further comprising two semiconductor layers, and a gate oxide film and a gate electrode that are arranged in an overlapping manner across the third semiconductor layer,
The step at the boundary between the second semiconductor layer and the third semiconductor layer is formed so that the surface roughness of one surface of the second semiconductor layer or the surface of the third semiconductor layer is smaller than the smaller value. The semiconductor device according to claim 1, wherein the semiconductor device is provided.   6. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of silicon carbide. Forming an etching stop layer overlying one main surface of the first conductivity type semiconductor substrate;
Forming an ion blocking layer overlying the etching stop layer;
Removing a portion of the ion blocking layer to form an opening, and exposing the etching stop layer at the opening;
Removing the etching stop layer in a range exposed at the opening;
Performing ion implantation toward the semiconductor substrate;
A method for manufacturing a semiconductor device, comprising:   8. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of activating the implanted ions by performing a heat treatment at least 1400 [deg.] C. on the semiconductor substrate after the ion implantation.   9. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of forming a sacrificial oxide film before or after the step of forming the etching stop layer.   10. The method of manufacturing a semiconductor device according to claim 7, wherein the step of removing the etching stop layer is a dry process.   11. The method of manufacturing a semiconductor device according to claim 7, wherein the ion blocking layer is made of a silicon oxide film, and the etching stop layer is made of polycrystalline silicon.   The method for manufacturing a semiconductor device according to claim 7, wherein the semiconductor substrate is made of silicon carbide.

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