JP2013004943A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device.SOLUTION: A semiconductor device 10 comprises: an IGBT chip 15 and a diode chip 16 each of which is mounted on a heat spreader 19 via solder 17; and a clip 20 mounted on the chips via solder 18 in a bridging manner. The clip 20 includes grooves 20g formed on a second face 20b and a fourth face 20e of the clip 20, which are respectively bent in a direction away from a first face 20a and a third face 20d which are connected to respective chips. Accordingly, at the time of solder reflow, the solder 18 to be absorbed is lead into the groove 20g thereby to inhibit absorption 18a of the solder 18. Because of this, a thickness of the solder 18 on each chip is ensured and heat stress applied to each chip in a power cycle test and the like is relaxed.

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a semiconductor device mounted with a power semiconductor element and a technique effective when applied to the manufacturing thereof.

  As a semiconductor package (semiconductor device) having a double-sided heat dissipation structure, an IGBT (Insulated Gate BipolarTransistor) chip and a diode chip are incorporated in, for example, Japanese Patent Application Laid-Open No. 2008-227131 (Patent Document 1). There is disclosed a structure in which a U-shaped elastic body is arranged on top and both elastic bodies are connected by plate terminals.

  Moreover, as a semiconductor device mounted with a power semiconductor element, for example, in Japanese Patent Application Laid-Open No. 2010-103222 (Patent Document 2), an IGBT element and a diode element are incorporated, and “K” is formed on each of the IGBT element and the diode element. A structure in which a U-shaped terminal block is joined and both terminal blocks are connected by an external connection terminal is disclosed.

  Moreover, as a semiconductor device used for in-vehicle motor control or the like, for example, in Japanese Patent Application Laid-Open No. 2008-21796 (Patent Document 3), one IGBT and one diode are packaged together, and both are connected by clips. A structure is disclosed.

JP 2008-227131 A JP 2010-103222 A Japanese Patent Application Laid-Open No. 2008-217176

  As an example of a semiconductor device on which a power semiconductor element is mounted, a semiconductor device used for in-vehicle motor control is known.

  The semiconductor device shown in FIG. 41 and FIG. 42 shows the structure of a comparative semiconductor device that the present inventors have conducted a comparative study, and is used, for example, for in-vehicle motor control.

  In the semiconductor device 80, one IGBT chip 81 and one diode chip 82 are packaged, and the IGBT and the diode are packaged as separate semiconductor chips (hereinafter also simply referred to as chips).

  The IGBT chip 81 and the diode chip 82 are sealed by a sealing body 86 made of a resin, and solder 84 is provided on a heat spreader 83 that is a chip mounting portion (also referred to as a die pad) exposed on the lower surface of the sealing body 86. It is mounted through.

  In the semiconductor device 80, a plate-like clip 87 is connected to the IGBT chip 81 and the diode chip 82 via solder 85. One end of the clip 87 is connected to an emitter terminal 88 which is an external connection terminal via a solder 89. That is, the plate-like clip 87 is soldered across the diode chip 82, the IGBT chip 81, and the emitter terminal 88. This is because a large current flows through the emitter terminal 88 and the connection using a wire is insufficient in strength. For example, a plate-like clip 87 made of a copper plate or the like is used.

  Here, the detailed shape of the plate-like clip 87 will be described. As shown in FIG. 43, the clip 87 is formed by connecting a soldering surface 90 to the semiconductor chip, a surface 91 bent from the connecting surface 90 in a direction away from the semiconductor chip, and further bending from the surface 91. And a horizontal plane 92. That is, the clip 87 requires a surface 91 formed by bending in a direction away from the semiconductor chip to be connected for the following first to third reasons.

  First, since a large current flows through the clip 87, it is necessary to secure a distance between the exposed portion of the semiconductor chip and the clip 87 (N portion in FIG. 43) because of the breakdown voltage. Second, it is necessary to relieve the thermal stress generated between the tip-emitter terminals by the bent portion. Third, in order to enhance the heat dissipation effect of the clip 87 itself, it is preferable that the area of the clip 87 is as large as possible. Therefore, a stepped shape by a bent portion is effective.

  From the above, the clip 87 needs to have a surface 91 that is bent in a direction away from the semiconductor chip to be connected.

  In the assembly of the semiconductor device 80, as shown in FIG. 43, two solders 84 are disposed on the heat spreader 83, and thereafter, an IGBT chip 81 and a diode chip 82 are disposed on each solder 84, and each of these solders 84 is further disposed. After the clip 87 is disposed on the chip via the solder 85, each solder is melted by reflow and the clip 87 is soldered to each semiconductor chip.

  However, when each solder is melted by reflow, one end of the emitter terminal 88 and the clip 87 is solder-connected by the solder 89, so this portion (P portion) serves as a fulcrum and the clip 87 is connected to the diode chip 82. The other end sinks to the heat spreader 83 side by its own weight as shown in the Q part.

  As a result, the distance between the connection surface 90 of the clip 87 and the diode chip 82 is narrowed, and the melted solder 85 on the diode chip 82 is sucked onto the surface 91 formed by bending from the connection surface 90 of the clip 87. Happens. That is, the solder sucking phenomenon occurs on the chip.

  Thereby, the solder thickness between the diode chip 82 and the clip 87 is reduced, and the semiconductor device 80 is assembled in this state.

  Various tests are performed on the semiconductor device 80 after the assembly is completed. For example, chip cracks are generated due to thermal stress generated when the semiconductor chip generates heat in a power cycle test (a test that generates heat from the chip itself) or the like. It is a problem to occur. That is, since the solder 85 on the diode chip 82 is thin, the diode chip 82 is cracked by the stress caused by the thermal stress during the power cycle test described above.

  Note that each of Patent Document 1 (Japanese Patent Laid-Open No. 2008-227131), Patent Document 2 (Japanese Patent Laid-Open No. 2010-103222), and Patent Document 3 (Japanese Patent Laid-Open No. 2008-21796) has a clip (U-shaped). There is no description or suggestion of solder wicking at the time of connection of the elastic body, terminal block), and it is considered that the problem of solder wicking also occurs in the structures of Patent Documents 1-3.

  44 to 46 show the case where one semiconductor chip is mounted on the semiconductor device, for example, the case of the semiconductor device 94 mounted with one transistor chip 93.

  Also in the assembly of such a semiconductor device 94, as shown in FIG. 46, when solder connection is performed by reflow of the clip 87, the emitter terminal 88 and one end of the clip 87 are soldered by the solder 89. (P part) becomes a fulcrum, and the other end of the clip 87 connected to the transistor chip 93 sinks to the heat spreader 83 side by its own weight as shown in the Q part.

  As a result, the gap between the connection surface 90 of the clip 87 and the transistor chip 93 is narrowed, and the melted solder 85 on the transistor chip 93 is sucked onto the surface 91 formed by bending from the connection surface 90 of the clip 87. Happens. That is, the solder sucking phenomenon occurs on the chip.

  As a result, the solder thickness between the transistor chip 93 and the clip 87 is reduced, and the semiconductor device 94 is assembled in this state.

  Therefore, similarly to the semiconductor device 80, the solder 85 on the transistor chip 93 is thin with respect to the semiconductor device 94, so that the transistor chip 93 is cracked by stress due to thermal stress during the power cycle test. Will occur.

  The present invention has been made in view of the above problems, and an object thereof is to provide a technique capable of improving the reliability of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to a typical embodiment includes a plate-like conductor member that is partially soldered to a chip main surface and has a bent portion that is bent in a direction away from the chip. A groove is formed along the bent portion.

  Further, in the method of manufacturing a semiconductor device according to a typical embodiment, when the plate-like conductor member on which the stand portion is formed is heat-treated and soldered to the semiconductor chip, the plate-like conductor member is used by the stand portion. Solder in a supported state.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The occurrence of chip cracks can be reduced or prevented, and the reliability of the semiconductor device can be improved.

It is a perspective view which shows an example of the structure of the semiconductor device of Embodiment 1 of this invention. FIG. 2 is a perspective view illustrating an example of a structure on a back surface side of the semiconductor device illustrated in FIG. 1. FIG. 2 is a plan view showing an example of the internal structure of the semiconductor device shown in FIG. 1 through a sealing body. It is sectional drawing which shows the structure cut | disconnected by the AA line shown in FIG. FIG. 2 is an equivalent circuit diagram illustrating an example of circuit operation of the semiconductor device illustrated in FIG. 1. FIG. 2 is a plan view showing an example of the structure of an IGBT chip incorporated in the semiconductor device of FIG. 1. It is a fragmentary sectional view which shows an example of the structure of the IGBT chip | tip shown in FIG. FIG. 2 is a plan view illustrating an example of a structure of a diode chip incorporated in the semiconductor device of FIG. 1. It is a fragmentary sectional view which shows an example of the structure of the diode chip shown in FIG. FIG. 2 is a partial cross-sectional view and an enlarged partial cross-sectional view showing an example of the structure of the semiconductor device shown in FIG. 1. FIG. 2 is a manufacturing flow diagram illustrating an example of an assembly procedure of the semiconductor device of FIG. 1. 2A and 2B are a plan view and a cross-sectional view illustrating an example of a structure after solder foil mounting and chip mounting are completed in the assembly of the semiconductor device of FIG. 2A is a plan view and a cross-sectional view illustrating an example of a structure after completion of mounting of a solder foil and mounting of a clip in the assembly of the semiconductor device of FIG. 2 is a plan view, a cross-sectional view, and an enlarged partial cross-sectional view showing an example of a structure after completion of reflow and wire bonding in the assembly of the semiconductor device of FIG. FIG. 2 is a plan view and a side view showing an example of a resin mold and a structure after completion of exterior plating in the assembly of the semiconductor device of FIG. 1. It is a top view which permeate | transmits and shows an example of the internal structure of the semiconductor device of Embodiment 2 of this invention. It is sectional drawing which shows the structure cut | disconnected by the AA line shown in FIG. FIG. 17 is a plan view showing an example of a structure during reflow in assembling the semiconductor device of FIG. 16. It is a fragmentary sectional view which shows the structure of FIG. 18 in a partial cross section. FIG. 20 is a side view schematically showing the structure of FIG. 19. It is a top view which shows an example of the structure of the stand part shown in FIG. It is sectional drawing which shows the structure cut | disconnected by the AA line shown in FIG. FIG. 17 is a manufacturing flow diagram illustrating an example of the assembly procedure of the semiconductor device of FIG. 16. FIG. 17 is a plan view and a cross-sectional view illustrating an example of a structure after solder foil mounting and chip mounting are completed in the assembly of the semiconductor device of FIG. 16. FIG. 17 is a plan view and a cross-sectional view illustrating an example of a structure after completion of mounting of a solder foil and mounting of a clip in the assembly of the semiconductor device of FIG. FIG. 17 is a plan view and a cross-sectional view illustrating an example of a structure after completion of reflow and stand section cutting / flux cleaning in the assembly of the semiconductor device of FIG. 16. FIG. 17 is a plan view, a cross-sectional view, and a side view showing an example of a structure after completion of wire bonding and resin molding in the assembly of the semiconductor device of FIG. 16. It is a top view which shows an example of the structure after the completion of exterior plating in the assembly of the semiconductor device of FIG. It is a top view which permeate | transmits the sealing body and shows the internal structure of the semiconductor device of the modification of Embodiment 2 of this invention. It is a fragmentary sectional view which shows the structure of FIG. 29 in a partial cross section. FIG. 30 is an enlarged partial side view showing an example of the structure of the semiconductor device shown in FIG. 29. It is a top view which permeate | transmits the sealing body and shows the internal structure of the semiconductor device of Embodiment 3 of this invention. It is a fragmentary sectional view which shows the structure of FIG. 32 in a partial cross section. FIG. 33 is an enlarged partial side view showing an example of the structure of the semiconductor device shown in FIG. 32. FIG. 33 is an equivalent circuit diagram showing an example of circuit operation of the semiconductor device shown in FIG. 32. FIG. 33 is a plan view showing an example of a structure during reflow in assembling the semiconductor device of FIG. 32. It is a fragmentary sectional view which shows the structure of FIG. 36 in a partial cross section. FIG. 38 is a side view schematically showing the structure of FIG. 37. It is a top view which shows an example of the structure of the stand part shown in FIG. It is sectional drawing which shows the structure cut | disconnected by the AA line shown in FIG. It is a top view which permeate | transmits the sealing body and shows the internal structure of the semiconductor device of a comparative example. It is a fragmentary sectional view which shows the structure of FIG. 41 in a partial cross section. 42 is a side view showing a structure during reflow in assembling the semiconductor device of FIG. 41. FIG. It is a top view which permeate | transmits the sealing body and shows the internal structure of the semiconductor device (1 chip mounting type) of a comparative example. It is a fragmentary sectional view which shows the structure of FIG. 44 in a partial cross section. FIG. 45 is a side view showing a structure during reflow in the assembly of the semiconductor device of FIG. 44.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.

  Further, in the following embodiments, regarding constituent elements and the like, when “consisting of A”, “consisting of A”, “having A”, and “including A” are specifically indicated that only the elements are included. It goes without saying that other elements are not excluded except in the case of such cases. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. Further, even a plan view may be hatched for easy understanding of the drawing.

(Embodiment 1)
1 is a perspective view showing an example of the structure of the semiconductor device according to the first embodiment of the present invention, FIG. 2 is a perspective view showing an example of the structure on the back side of the semiconductor device shown in FIG. 1, and FIG. 3 is shown in FIG. 4 is a plan view showing an example of the internal structure of the semiconductor device through a sealing body, FIG. 4 is a cross-sectional view showing a structure cut along the line AA shown in FIG. 3, and FIG. 5 is a circuit of the semiconductor device shown in FIG. It is an equivalent circuit diagram which shows an example of operation | movement. 6 is a plan view showing an example of the structure of the IGBT chip incorporated in the semiconductor device of FIG. 1, FIG. 7 is a partial sectional view showing an example of the structure of the IGBT chip shown in FIG. 6, and FIG. FIG. 9 is a partial sectional view showing an example of the structure of the diode chip shown in FIG. 8, and FIG. 10 shows an example of the structure of the semiconductor device shown in FIG. It is a partial sectional view and an enlarged partial sectional view.

  The semiconductor device according to the first embodiment is, for example, a semiconductor device 10 on which a power semiconductor element used for in-vehicle motor control or the like is mounted, and includes two semiconductor chips. That is, the semiconductor device 10 is obtained by packaging two semiconductor chips into one package. In the first embodiment, the semiconductor device 10 includes an IGBT chip 15 that is a first semiconductor chip in which an IGBT is formed and a second semiconductor chip in which a diode is formed. A case where a certain diode chip 16 is mounted will be described.

  As shown in FIG. 1, a sealing body 11 having a substantially rectangular (rectangular) planar shape is formed at the center of the semiconductor device 10. The sealing body 11 is made of a sealing resin, and one of two side surfaces corresponding to the short side of the rectangular upper surface (the surface of the sealing body 11) has a collector terminal 12 that is an external connection terminal. And part of the signal terminal 14 is provided. Further, on the side surface opposite to the side surface of the sealing body 11 on which the collector terminal 12 is formed, a part of the emitter terminal 13 and the signal terminal 14 which are external connection terminals are formed. The collector terminal 12 and the emitter terminal 13 are formed with openings 12a and 13a for screwing, respectively.

  In addition, as shown in FIG. 2, a part of the heat spreader 19 that also serves as a chip mounting portion (also referred to as a die pad) is exposed on the back surface opposite to the front surface of the sealing body 11. Thus, part of the heat spreader 19 is exposed on the back side of the sealing body 11, so that the heat dissipation efficiency during the operation of the semiconductor device 10 can be improved.

  Next, the internal structure of the semiconductor device 10 will be described. In FIG. 3, the sealing body 11 covering the upper surface of the semiconductor device 10 is not shown, and the internal structure is shown.

  As shown in FIGS. 3 and 4, a heat spreader 19 is provided inside the sealing body 11, and a collector terminal 12 that is an external connection terminal is integrally formed on the heat spreader 19. That is, the collector terminal 12 formed integrally with the heat spreader 19 is exposed from one side surface of the sealing body 11.

  On the heat spreader 19, an IGBT chip 15, which is a first semiconductor chip on which an IGBT is formed, is mounted via a solder 17. Further, the IGBT chip 15 is arranged next to the IGBT chip 15 next to the IGBT chip 15. Similarly, the diode chip 16 which is the second semiconductor chip is mounted via the solder 17.

  Here, the IGBT chip 15 in which the IGBT is formed has a collector electrode 46 (see FIG. 7) formed on the back surface 15b side, and the collector electrode 46 is electrically connected to the heat spreader 19 via the solder 17. Yes. That is, the collector electrode 46 formed on the back surface 15 b of the IGBT chip 15 is electrically connected to the collector terminal 12 formed integrally with the heat spreader 19 via the heat spreader 19.

  On the other hand, the diode chip 16 in which the diode is formed has a cathode 63 (see FIG. 9) on the back surface 16b side, and the cathode 63 is electrically connected to the collector terminal 12 via the heat spreader 19. For this reason, the collector electrode 46 of the IGBT and the cathode 63 of the diode are electrically connected.

  Further, an emitter electrode 40 and a plurality of bonding pads 41 to 45 are formed on the main surface (upper surface) 15a side of the IGBT chip 15 as shown in FIG. On the other hand, an anode electrode 62 is formed on the main surface (upper surface) 16a side of the diode chip 16 as shown in FIG. The emitter electrode 40 formed on the main surface 15 a side of the IGBT chip 15 and the anode electrode 62 formed on the main surface 16 a side of the diode chip 16 are formed in a flat plate shape that is mounted via the solder 18. They are connected by a clip 20 that is a plate-like conductor member.

  Therefore, the emitter electrode 40 of the IGBT and the anode electrode 62 of the diode are electrically connected by the clip 20. The clip 20 is also called a plate electrode. Hereinafter, the term clip 20 is used as a plate-like electrode (plate-like conductor member). The main surface 15a of the IGBT chip 15 on which the IGBT is formed means the upper surface of the IGBT chip 15. That is, the main surface 15 a of the IGBT chip 15 indicates a surface opposite to the surface that contacts the heat spreader 19 of the IGBT chip 15.

  Similarly, the main surface 16a of the diode chip 16 in which the diode is formed means the upper surface of the diode chip 16. That is, the main surface 16a of the diode chip 16 indicates a surface opposite to the surface that contacts the heat spreader 19 of the diode chip 16.

  Here, the clip 20 is made of, for example, a flat conductor member mainly composed of copper, and the emitter electrode 40 on the main surface 15 a of the IGBT chip 15 and the anode electrode 62 on the main surface 16 a of the diode chip 16. And connected. This is because a large current flows through the emitter electrode 40. In the wire connection, there is a problem that the on-resistance increases due to an increase in resistance due to aluminum and an increase in resistance due to a fine wire, and the wire is a thin wire. However, there is a problem that the heat capacity is small and the heat dissipation characteristics are deteriorated. However, as in the semiconductor device 10 of the first embodiment, the problem is caused by connecting with the clip 20 which is a plate-like conductor member mainly composed of copper. Has solved. That is, since the resistance of copper is smaller than the resistance of aluminum, the on-resistance can be reduced by connecting with the clip 20 whose main component is copper. Further, since the clip 20 has a wide flat plate shape, the cross-sectional area is larger than that of the wire, and as a result, the on-resistance can be further reduced. Further, since the clip 20 has a flat plate shape, the heat capacity of the clip 20 itself can be made larger than the heat capacity of the wire itself, and the contact area of the IGBT chip 15, the diode chip 16 and the clip 20 can be increased. Since it can be made larger than the connection by wire, the heat radiation efficiency can be improved.

  The clip 20 is connected to an emitter terminal 13 which is an external connection terminal via a solder 27. The emitter terminal 13 is formed on the other end side opposite to the one end side of the heat spreader 19 on which the collector terminal 12 that is an external connection terminal is formed, and is not electrically connected to the heat spreader 19. That is, when the emitter terminal 13 is connected to the heat spreader 19, the collector terminal 12 and the emitter terminal 13 are directly connected to each other, so that a short circuit is not caused. That is, the emitter terminal 13 is connected to the emitter electrode 40 of the IGBT chip 15 via the clip 20.

  As shown in FIGS. 1 and 2, a signal terminal 14 is formed on the other end side of the heat spreader 19 where the emitter terminal 13 is formed and on one end side of the heat spreader 19 where the collector terminal 12 is formed. As shown in FIG. 3, on the other end side of the heat spreader 19, in addition to the emitter terminal 13, there are temperature detection terminals 21, 22, an external connection gate terminal 23, a Kelvin detection terminal 24, and a current detection terminal 25. Is formed. These terminals are electrically connected to the bonding pads 41 to 45 formed on the main surface (upper surface) 15 a of the IGBT chip 15 using wires 28.

  Therefore, the IGBT chip 15 is disposed closer to the emitter terminal 13 of the heat spreader 19 than the diode chip 16. With this arrangement, the bonding pads 41 to 45 formed on the IGBT chip 15, the temperature detection terminals 21 and 22, the external connection gate terminal 23, the Kelvin detection terminal 24, and the current detection terminal 25, Therefore, the bonding pads 41 to 45 and the terminals 21 to 25 can be easily connected by the wire 28.

  A Kelvin detection terminal 26 connected to the collector terminal 12 which is an external connection terminal is formed on one end side of the heat spreader 19. Here, in the semiconductor device 10, the IGBT chip 15 connected to each of the temperature detection terminals 21 and 22, the external connection gate terminal 23, the Kelvin detection terminal 24, and the current detection terminal 25 using the wire 28. The clip 20 is not disposed on the bonding pads 41 to 45. That is, the bonding pads 41 to 45 of the IGBT chip 15 are formed in a region that does not overlap the clip 20 in plan view.

  For this reason, it can prevent that the wire 28 and clip 20 which connect to the bonding pads 41-45 contact, and can improve the reliability of the semiconductor device 10. FIG. Furthermore, since it is not necessary to provide a spacer under the clip 20, the thickness of the semiconductor device 10 can be reduced. For this reason, size reduction of the semiconductor device 10 can be promoted.

  Further, in the semiconductor device 10 according to the first embodiment, the clip 20 and the emitter terminal 13 are connected via the solder 27 as shown in FIGS. 3 and 4, but at that time, the clip 20 and the emitter terminal 13 are connected. Is formed of a separate structure, and the clip 20 and the emitter terminal 13 formed of separate structures are connected via a solder 27.

  Next, the circuit configuration and operation of the elements formed on the IGBT chip 15 shown in FIG. 5 will be described with reference to FIGS.

  First, as shown in FIG. 6, an emitter electrode 40 and bonding pads 41 to 45 are formed on the main surface (upper surface) 15 a of the IGBT chip 15. The emitter electrode 40 is connected to the clip 20 shown in FIG. 4, and is connected to the emitter terminal 13 that is an external connection terminal via the clip 20. On the other hand, the bonding pad 41 is connected to the temperature detection terminal 21 shown in FIG. 3 using a wire 28, and the bonding pad 42 is connected to the temperature detection terminal 22 using a wire 28. Similarly, the bonding pad 43 is connected to the external connection gate terminal 23 using the wire 28, and the bonding pad 44 is connected to the Kelvin detection terminal 24 using the wire 28. Further, the bonding pad 45 is connected to the current detection terminal 25 using a wire 28.

  Further, the collector electrode 46 shown in FIG. 7 is formed on the back surface 15 b of the IGBT chip 15. The collector electrode 46 is connected to the heat spreader 19 shown in FIG. 4 and is connected to the collector terminal 12 which is an external connection terminal formed integrally with the heat spreader 19.

  Here, as shown in FIG. 5, the IGBT chip 15 is formed with an IGBT 50, a detection IGBT 51, and a temperature detection diode 52. The IGBT 50 is a main IGBT and is used for driving a three-phase motor. In the IGBT 50, an emitter electrode 40, a collector electrode 46, and a gate electrode 43a are formed. The gate electrode 43a is connected to the bonding pad 43 of FIG. 6 formed on the upper surface of the IGBT chip 15 by internal wiring. Since the bonding pad 43 is connected to the external connection gate terminal 23 of FIG. 3, the gate electrode 43 a of the IGBT 50 is connected to the external connection gate terminal 23. The external connection gate terminal 23 is connected to a control circuit (not shown), and a signal from the control circuit is applied to the gate electrode 43a of the IGBT 50 through the external connection gate terminal 23, so that the control circuit The IGBT 50 can be controlled.

  The detection IGBT 51 is provided for detecting the current flowing between the collector and the emitter of the IGBT 50. That is, the inverter circuit is provided to detect the current flowing between the collector and emitter of the IGBT 50 in order to protect the IGBT 50. This IGBT 51 for detection is connected to the collector electrode 46 and the gate electrode 43a similar to the IGBT 50, and has a sense emitter electrode 45a. The sense emitter electrode 45a is connected to a bonding pad 45 formed on the main surface 15a of the IGBT chip 15 by an internal wiring. Since the bonding pad 45 is connected to the current detection terminal 25, the sense emitter electrode 45 a of the detection IGBT 51 is eventually connected to the current detection terminal 25.

  The current detection terminal 25 is connected to a current detection circuit provided outside the semiconductor device 10. This current detection circuit detects the collector-emitter current of the IGBT 50 based on the output of the sense emitter electrode 45a of the detection IGBT 51, and cuts off the gate signal applied to the gate electrode of the IGBT 50 when an overcurrent flows. The IGBT 50 is protected.

  The temperature detection diode 52 is provided to detect the temperature of the IGBT 50. That is, the temperature of the IGBT 50 is detected by changing the voltage of the temperature detection diode 52 according to the temperature of the IGBT 50. This temperature detection diode 52 has a pn junction formed by introducing impurities of different conductivity types into polysilicon, and has a cathode 41a and an anode electrode 42a. The cathode 41a is connected to a bonding pad 41 formed on the main surface 15a of the IGBT chip 15 by internal wiring. Similarly, the anode electrode 42a is connected to a bonding pad 42 formed on the main surface 15a of the IGBT chip 15 by internal wiring.

  Therefore, the cathode 41a of the temperature detection diode 52 is connected to the temperature detection terminal 21 via the bonding pad 41, and the anode electrode 42a of the temperature detection diode 52 is connected to the temperature detection terminal 22 via the bonding pad 42. ing. The temperature detection terminals 21 and 22 are connected to a temperature detection circuit provided outside the semiconductor device 10. This temperature detection circuit indirectly detects the temperature of the IGBT 50 based on the output between the temperature detection terminals 21 and 22 connected to the cathode 41a and the anode electrode 42a of the temperature detection diode 52, and the detected temperature is When the temperature exceeds a certain temperature, the gate signal applied to the gate electrode of the IGBT 50 is cut off to protect the IGBT 50.

  Next, a common emitter electrode 44a, which is another terminal, protrudes from the emitter electrode 40 of the IGBT 50. The common emitter electrode 44a is connected to a bonding pad 44 formed on the main surface 15a of the IGBT chip 15 by internal wiring. Since the bonding pad 44 is connected to the Kelvin detection terminal 24, the common emitter electrode 44a is eventually connected to the Kelvin detection terminal 24. The Kelvin detection terminal 24 is connected to a Kelvin detection circuit provided outside the semiconductor device 10. This Kelvin detection circuit is provided for the purpose of canceling the wiring resistance so that the potential of the IGBT 50 does not become unstable due to wiring or the like. That is, the wiring resistance of the emitter electrode 40 itself is canceled based on the output from the common emitter electrode 44a having the same potential as the emitter electrode 40.

  Similarly, the Kelvin detection terminal 26 of FIG. 3 branched from the collector electrode 46 of the IGBT 50 shown in FIG. 5 is provided. The Kelvin detection terminal 26 is connected to a Kelvin detection circuit provided outside the semiconductor device 10. This Kelvin detection circuit is also provided for the purpose of canceling the wiring resistance so that the potential of the IGBT 50 does not become unstable due to wiring or the like. That is, the wiring resistance of the collector electrode 46 itself is canceled based on the output of the Kelvin detection terminal 26 having the same potential as the collector electrode 46.

  Thus, since the semiconductor device 10 is configured to be connectable to the current detection circuit, the temperature detection circuit, and the Kelvin detection circuit, the operation reliability of the IGBT 50 included in the semiconductor device 10 is improved. Can do.

Next, as shown in FIG. 7, the IGBT 50 has a collector electrode 46 formed on the back surface of the semiconductor chip, and a p ⁺ type semiconductor region 54 is formed on the collector electrode 46. An n ⁺ type semiconductor region 55 is formed on the p ⁺ type semiconductor region 54, and an n ⁻ type semiconductor region 56 is formed on the n ⁺ type semiconductor region 55. Then, n ^- -type on the semiconductor region 56 is p-type semiconductor region 57 is formed, through the p-type semiconductor region 57, n ^- trench 59 reaching the semiconductor region 56 is formed.

Further, an n ⁺ type semiconductor region 58 serving as an emitter region is formed in alignment with the trench groove 59. A gate insulating film 60 made of, for example, a silicon oxide film is formed inside the trench groove 59, and a gate electrode 43 a is formed through the gate insulating film 60. The gate electrode 43a is formed of, for example, a polysilicon film and is formed so as to fill the trench groove 59. In the IGBT 50 configured as described above, the gate electrode 43a is connected to the bonding pad 43 shown in FIG. 6 through an internal wiring. Similarly, the n ⁺ type semiconductor region 58 serving as an emitter region is connected to the emitter electrode 40 shown in FIG. The p ⁺ type semiconductor region 54 serving as a collector region is connected to a collector electrode 46 formed on the back surface of the semiconductor chip. The IGBT 50 combines the high-speed switching characteristics and voltage drive characteristics of the MISFET and the low ON voltage characteristics of the bipolar transistor. The n ⁺ type semiconductor region 55 is also called a buffer layer. In the n ⁺ -type semiconductor region 55, a depletion layer that grows from the p-type semiconductor region 57 into the n ⁻ -type semiconductor region 56 when the IGBT 50 is turned off is formed below the n ⁻ -type semiconductor region 56. It is provided to prevent a punch-through phenomenon that comes into contact with the p ⁺ type semiconductor region 54. An n ⁺ type semiconductor region 55 is provided for the purpose of limiting the amount of holes injected from the p ⁺ type semiconductor region 54 to the n ⁻ type semiconductor region 56.

Next, the operation of the IGBT 50 will be described. First, the operation of turning on the IGBT 50 will be described. By applying a sufficiently positive voltage between the gate electrode 43a and the n ⁺ type semiconductor region 58 serving as the emitter region, the MISFET having the trench gate structure is turned on. Then, a forward bias is applied between the p ⁺ type semiconductor region 54 and the n ⁻ type semiconductor region 56 constituting the collector region, and hole injection occurs from the p ⁺ type semiconductor region 54 to the n ⁻ type semiconductor region 56. Subsequently, as many electrons as the positive charges of the injected holes are collected in the n ⁻ type semiconductor region 56. As a result, the resistance of the n ⁻ type semiconductor region 56 decreases (conductivity modulation), and the IGBT 50 is turned on.

A junction voltage between the p ⁺ -type semiconductor region 54 and the n ⁻ -type semiconductor region 56 is applied to the ON voltage, but the resistance value of the n ⁻ -type semiconductor region 56 is reduced by one digit or more due to conductivity modulation. At a high breakdown voltage that occupies the majority, the IGBT 50 has a lower ON voltage than the MISFET. Therefore, it can be seen that the IGBT 50 is an effective device for increasing the breakdown voltage.

Next, an operation for turning off the IGBT 50 will be described. When the voltage between the gate electrode 43a and the n ⁺ type semiconductor region 58 serving as the emitter region is lowered, the MISFET having the trench gate structure is turned off. Then, the hole injection from the p ⁺ type semiconductor region 54 to the n ⁻ type semiconductor region 56 stops, and the holes already injected also have a lifetime and decrease. The remaining holes directly flow out to the p ⁺ type semiconductor region 54 (tail current), and when the outflow is completed, the IGBT 50 is turned off. In this way, the IGBT 50 can be operated.

  Next, the configuration of the diode chip 16 mounted on the heat spreader 19 will be described. As shown in FIG. 8, an anode electrode 62 is formed on the main surface (upper surface) 16 a side of the diode chip 16. On the other hand, similarly, a cathode 63 is formed on the back side of the diode chip 16 as shown in FIG.

Next, the element structure of the diode will be described. A cathode 63 is formed on the back surface 16 b of the diode chip 16 as shown in FIG. 9, and an n ⁺ type semiconductor region 64 is formed on the cathode 63. An n ⁻ type semiconductor region 65 is formed on the n ⁺ type semiconductor region 64, and a p type semiconductor region 66 is formed on the n ⁻ type semiconductor region 65 so as to be spaced apart. A p ⁻ type semiconductor region 67 is formed between the p type semiconductor regions 66. An anode electrode 62 is formed on the p-type semiconductor region 66 and the p ⁻ -type semiconductor region 67. The anode electrode 62 is made of, for example, aluminum-silicon.

According to the diode element 16c configured as described above (see FIG. 5), when a positive voltage is applied to the anode electrode 62 and a negative voltage is applied to the cathode 63, the n ⁻ type semiconductor region 65 and the p type semiconductor region 66 The pn junction between them is forward biased and current flows. On the other hand, when a negative voltage is applied to the anode electrode 62 and a positive voltage is applied to the cathode 63, the pn junction between the n ⁻ type semiconductor region 65 and the p type semiconductor region 66 is reverse-biased and no current flows. In this way, the diode element 16c can be operated.

  Here, as shown in FIG. 8, the anode electrode 62 is formed on the main surface 16a of the diode chip 16, and as shown in FIG. 6, the emitter electrode 40 is formed on the main surface 15a of the IGBT chip 15. . The anode electrode 62 and the emitter electrode 40 are connected by the clip 20 shown in FIG. On the other hand, the cathode 63 shown in FIG. 9 is formed on the back surface 16 b of the diode chip 16, and the collector electrode 46 shown in FIG. 7 is formed on the back surface 15 b of the IGBT chip 15. The cathode 63 and the collector electrode 46 are connected by the heat spreader 19 shown in FIG. Therefore, the IGBT and the diode are connected in antiparallel. The function of the diode at this time will be described.

  If the load is a pure resistor that does not include inductance, a diode is unnecessary because there is no energy to circulate. However, when a circuit including an inductance such as a motor is connected to the load, there is a mode in which the load current flows in the opposite direction to the ON switch. At this time, a single switching element such as an IGBT does not have a function of allowing a reverse current to flow, and therefore a diode needs to be connected in antiparallel to the switching element such as an IGBT. That is, in an inverter circuit, when an inductance is included in a load as in motor control, when a switching element such as an IGBT is turned off, the energy stored in the inductance must be released. The IGBT alone cannot flow a reverse current for releasing the energy stored in the inductance. Therefore, a diode is connected in antiparallel to the IGBT in order to recirculate the electric energy stored in the inductance. That is, the diode has a function of flowing a reverse current in order to release the electrical energy stored in the inductance. In addition, it is necessary to give a high frequency characteristic also to a diode according to the switching frequency of IGBT.

  Next, the feature of the shape of the clip 20 provided in the semiconductor device 10 of the first embodiment will be described. First, as shown in FIG. 4, the IGBT chip 15 and the diode chip 16 are arranged side by side via the solder 17 on the heat spreader 19 that also serves as a chip mounting portion. Further, a clip 20 is mounted on the IGBT chip 15 and the diode chip 16 via solder 18. In the semiconductor device 10, the clip 20 is electrically connected to the emitter electrode 40 shown in FIG. 6 on the main surface 15 a of the IGBT chip 15 and the anode electrode 62 shown in FIG. 8 on the main surface 16 a of the diode chip 16 via the solder 18. While being connected, one end is electrically connected to the emitter terminal 13 of the plurality of external connection terminals.

  At that time, the shape of the clip 20 is such that the IGBT chip 15 and the diode chip 16 are more in shape than the regions of the clip 20 (first surface 20a and third surface 20d shown in FIG. 10) in contact with the IGBT chip 15 and the diode chip 16. The region of the clip 20 located between them (the fifth surface 20n shown in FIG. 10) protrudes upward (convex shape). That is, the position of the area of the clip 20 (inter-chip area) between the IGBT chip 15 and the diode chip 16 is larger than the position of the area (contact area) of the clip 20 in contact with the IGBT chip 15 or the diode chip 16. It is away from the heat spreader 19.

  As a result, the excess solder 18 is absorbed by the convex shape of the clip 20, and as a result, the excess solder 18 travels along the side surface of the IGBT chip 15 and is connected to the solder 17 formed at the lower part of the IGBT chip 15. Can be prevented.

  Further, since a large current flows in the clip 20, it is necessary to secure a distance between the exposed portion of the IGBT chip 15 and the diode chip 16 and the clip 20 (D portion in FIG. 10) because of the breakdown voltage. Furthermore, it is necessary to relieve the thermal stress generated between the tip-emitter terminals by the bent portion. Also, in order to enhance the heat dissipation effect by the clip 20 itself, it is preferable that the area of the clip 20 is as large as possible. Therefore, it is effective to have a convex shape by a bent portion.

  As described above, the clip 20 requires a surface that is bent in a direction away from the IGBT chip 15 and the diode chip 16 to be connected.

  That is, as shown in FIG. 10, the clip 20 is in a direction away from the IGBT chip 15 and the first surface 20 a connected to the emitter electrode 40 (see FIG. 6) of the main surface 15 a of the IGBT chip 15 via the solder 18. The second surface 20b formed by bending from the first surface 20a, the third surface 20d connected to the anode electrode 62 (see FIG. 8) of the main surface 16a of the diode chip 16 via the solder 18, and the diode chip 16 And a fourth surface 20e formed by bending from the third surface 20d in the direction of separation.

  Further, along the second surface 20b and the fourth surface 20e, along the ridge (bending portion, bent portion) 20c at the boundary between the first surface 20a and the second surface 20b, and between the third surface 20d and the fourth surface 20e. A groove 20g is formed along the boundary ridge (bending portion, bent portion) 20f.

  In other words, the second surface 20b and the fourth surface 20e bent in the direction away from each semiconductor chip from the first surface 20a and the third surface 20d connected to each semiconductor chip of the clip 20 are respectively ridge portions (bending portions, bending portions). ) A groove 20g is formed along 20c and 20f. The groove 20g prevents (suppresses) the sucking-up 18a at the time of heat melting (heat treatment) due to reflow of the solder 18, etc. As shown in the enlarged view of FIG. 10, the solder 18 melts and sucks up. In this case, the solder 18 is inserted into the groove 20g so as not to be sucked upward from the groove 20g. Thus, the thickness of the solder 18 between each semiconductor chip and the clip 20 is secured. This is for preventing the first surface 20a and the third surface 20d of the clip 20 from approaching each semiconductor chip (not to lower).

  Therefore, it is preferable that the groove 20g is formed at a position as low as possible (position as close to the ridges 20c and 20f as possible) on the second surface 20b and the fourth surface 20e. Furthermore, it is preferable that the grooves 20g are formed in a plurality of rows along the ridges 20c and 20f, respectively. For example, in the structure shown in FIG. 10, the grooves 20g are formed in two rows. Thus, by forming the grooves 20g in a plurality of rows, the effect of preventing or suppressing the sucking-up 18a of the solder 18 can be further enhanced.

  The cross-sectional shape of the groove 20g may be V-shaped as shown in the partial cross-sectional view of FIG. 10, for example, may be U-shaped or the like. The shape is not particularly limited as long as it can prevent or suppress the rising 18a.

  Next, the assembly of the semiconductor device 10 according to the first embodiment will be described with reference to the flowchart shown in FIG.

  11 is a manufacturing flow diagram showing an example of the assembly procedure of the semiconductor device of FIG. 1. FIG. 12 is a plan view and a cross-sectional view showing an example of the structure after the solder foil mounting and chip mounting in the assembly of the semiconductor device of FIG. 13 is a plan view and a cross-sectional view showing an example of the structure after mounting of the solder foil and clip in the assembly of the semiconductor device of FIG. 1, and FIG. 14 is a structure after completion of reflow and wire bonding in the assembly of the semiconductor device of FIG. FIG. 15 is a plan view and a side view showing an example of a structure after completion of resin molding and exterior plating in the assembly of the semiconductor device of FIG.

  First, solder foil mounting shown in step S1 of FIG. 11 is performed. Here, as shown in step S <b> 1 of FIG. 12, two solder foils (first solder) 30 for the IGBT chip 15 and the diode chip 16 are arranged on the heat spreader 19 that is the chip mounting portion of the lead frame 29. The lead frame 29 is formed with a heat spreader 19 serving as a chip mounting portion and a heat radiating member at the center, and a plurality of external connection terminals such as a collector terminal 12 and an emitter terminal 13 are provided at both ends of the heat spreader 19. Terminals and the like are formed. The heat spreader 19 is integrally formed with the collector terminal 12, and a plurality of external connection terminals such as the collector terminal 12 and the emitter terminal 13 are integrally connected with the frame portion 29a.

  Note that flux is applied to the heat spreader 19 before mounting the solder foil.

  The solder foil 30 as the first solder is a thin chip-like foil made of solder.

  Thereafter, chip mounting shown in step S2 of FIG. 11 is performed. First, a flux is applied to the solder foil 30. After applying the flux, as shown in step S <b> 2 of FIG. 12, the IGBT chip 15 is mounted on one solder foil 30, and the diode chip 16 is mounted on the other solder foil 30. At this time, the IGBT chip 15 and the diode chip 16 are arranged so that the back surface 15b and the back surface 16b of the IGBT chip 15 and the diode chip 16 face the heat spreader 19 through the solder foil 30, respectively.

  Thereafter, solder foil mounting shown in step S3 of FIG. 11 is performed. First, flux is applied to the IGBT chip 15 and the diode chip 16. After the flux application, as shown in step S3 of FIG. 13, the solder foil 31 as the second solder is disposed on the emitter electrode 40 and the anode electrode 62 on the main surfaces 15a and 16a of the IGBT chip 15 and the diode chip 16, respectively. Further, the solder paste 32 as the third solder is applied (arranged) on the emitter terminal 13 as the external connection terminal.

  Thereafter, the clip mounting shown in step S4 of FIG. 11 is performed. First, flux is applied to the solder foil 31 and the solder paste 32. After applying the flux, as shown in step S4 of FIG. 13, the clip 20 is disposed on the IGBT chip 15 and the diode chip 16 via the solder foil 31, respectively. Further, one end of the clip 20 is disposed on the solder paste 32 on the emitter terminal 13.

  The clip 20 is a thin plate-like conductor member made of a copper plate or the like. As shown in FIG. 10, a first surface 20a connected to the IGBT chip 15 and a second surface 20b formed by bending from the first surface 20a. The third surface 20d connected to the diode chip 16 and the fourth surface 20e formed by bending from the third surface 20d are provided. At this time, the second surface 20 b is bent in a direction away from the IGBT chip 15, and the fourth surface 20 e is bent in a direction away from the diode chip 16. Further, along each of the second surface 20b and the fourth surface 20e, a ridge 20c at the boundary between the first surface 20a and the second surface 20b, and a ridge 20f at the boundary between the third surface 20d and the fourth surface 20e. A groove 20g is formed. At that time, the grooves 20g are formed in a plurality of rows (for example, two rows) as shown in the enlarged partial sectional view of step S5 in FIG.

  In the clip mounting in step S4 using such a clip 20, the first surface 20a is positioned on the emitter electrode 40 of the main surface 15a of the IGBT chip 15 via the solder foil 31, and the third surface 20d. Is positioned on the anode electrode 62 of the main surface 16a of the diode chip 16 via the solder foil 31, and one end of the clip 20 is positioned on the emitter terminal 13 which is an external connection terminal via the solder paste 32.

  That is, the plate-like clip 20 is disposed across the IGBT chip 15, the diode chip 16, and the emitter terminal 13.

  Then, the reflow shown in step S5 of FIG. 11 is performed. Here, the solder foils 30 and 31 and the solder paste 32 are melted (heat treated) through a reflow furnace, and the respective members are fixed. That is, the heat spreader 19 is connected to the IGBT chip 15 and the diode chip 16 by melting and fixing the solder foil 30 through a reflow furnace, and further the IGBT chip 15 is melted and fixed. The diode chip 16 and the clip 20 are connected to each other, and the solder paste 32 is melted and fixed to connect one end of the clip 20 to the emitter terminal 13 that is an external connection terminal.

  Here, when the solder foil 31 is melted, it becomes the solder 18, and as shown in the enlarged partial sectional view of step S5 in FIG. 14, the sucking up 18a is caused, and the second surface 20b and the fourth surface 20e of the clip 20 in FIG. In the second surface 20b and the fourth surface 20e, grooves 20g are formed along the ridges 20c and 20f. As a result, the solder 18 about to be sucked up enters the groove 20g and does not suck up any more. That is, by forming the groove 20g, the sucking up 18a of the solder 18 can be suppressed or prevented.

  Accordingly, the height of the sucked-up 18a of the melted solder foil 31 (solder 18) is 20 g or less.

  As a result, the thickness of the solder 18 between each semiconductor chip and the clip 20 is ensured so that the first surface 20a and the third surface 20d of the clip 20 do not approach each semiconductor chip (do not fall). Can do.

  In addition, since the grooves 20g are formed in two rows along the ridges 20c and 20f, the effect of preventing or suppressing the sucking-up 18a of the solder 18 can be further enhanced.

  After reflowing, flux cleaning is performed. Here, cleaning for removing the aforementioned flux is performed using a chemical solution or the like.

  After flux cleaning, wire bonding in step S6 of FIG. 11 is performed. Here, as shown in the plan view of step S6 of FIG. 14, each of the bonding pads 41 to 45 on the main surface 15a of the IGBT chip 15 and each of the plurality of signal terminals 14 serving as external connection terminals are connected to the wire 28. Electrically connect with. The wire 28 is a thin wire made of, for example, aluminum.

  After wire bonding, the resin mold of step S7 in FIG. 11 is performed. Here, as shown in the diagram of step S7 in FIG. 15, the sealing body 11 is formed of a sealing resin, and the IGBT chip 15, the diode chip 16, the clip 20, the plurality of wires 28, and a part of the heat spreader 19 are formed. Seal with resin. For example, transfer molding is performed using a sealing resin such as an epoxy resin.

  After resin molding, exterior plating in step S8 in FIG. 11 is performed. Here, as shown in the plan view of step S <b> 8 in FIG. 15, the portion (external connection terminal or the like) exposed from the sealing body 11 of the lead frame 29 is covered with the exterior plating 36. The exterior plating 36 is, for example, solder plating.

  After the exterior plating, the separation and molding in step S9 in FIG. 11 is performed. Here, the collector terminal 12, the emitter terminal 13, and the plurality of signal terminals 14 are cut and bent from the frame portion 29a of the lead frame 29 shown in the plan view of step S8 of FIG. 15, and the assembly shown in step S10 is completed. Become. That is, the assembly of the semiconductor device 10 shown in FIGS. 1 and 2 is completed.

  According to the semiconductor device 10 and the manufacturing method thereof in the first embodiment, the first surface 20a connected to each semiconductor chip of the clip 20 that is a plate-like conductor member and the third surface 20d are away from each semiconductor chip. Since the groove 20g is formed in the bent second surface 20b and the fourth surface 20e, the solder 18 that is melted and sucked up between the semiconductor chip and the clip 20 can enter the groove 20g at the time of solder reflow. Can do.

  As a result, the sucking up 18a of the solder 18 can be suppressed or prevented, and the height of the sucking up 18a of the melted solder 18 can be made equal to or less than the groove 20g.

  Therefore, the solder 18 on each semiconductor chip can be held on the respective semiconductor chip, and as a result, the first surface 20a and the third surface 20d of the clip 20 are kept away from each semiconductor chip (so as not to be lowered). To reflow).

  Thereby, the thickness of the solder 18 between the IGBT chip 15 and the clip 20 and the thickness of the solder 18 between the diode chip 16 and the clip 20 can be ensured.

  As a result, since the thickness of the solder 18 on each semiconductor chip is secured, the thermal stress applied to the IGBT chip 15 and the diode chip 16 in a power cycle test after assembling the semiconductor device can be reduced.

  As a result, thermal stress applied to the IGBT chip 15 and the diode chip 16 in a power cycle test after assembling the semiconductor device can be reduced.

  As a result, generation of chip cracks in the semiconductor device 10 can be reduced or prevented, and the reliability of the semiconductor device 10 can be improved.

(Embodiment 2)
16 is a plan view showing an example of the internal structure of the semiconductor device according to the second embodiment of the present invention through a sealing body, and FIG. 17 is a cross-sectional view showing the structure cut along the line AA shown in FIG. 18 is a plan view showing an example of the structure during reflow in assembling the semiconductor device of FIG. 16, FIG. 19 is a partial sectional view showing the structure of FIG. 18 in a partial cross section, and FIG. 20 is a schematic view of the structure of FIG. 21 is a plan view showing an example of the structure of the stand part shown in FIG. 18, and FIG. 22 is a cross-sectional view showing the structure cut along the line AA shown in FIG. FIG. 23 is a manufacturing flow diagram showing an example of the assembly procedure of the semiconductor device of FIG. 16, and FIG. 24 is a plan view and a cross-section showing an example of the structure after solder foil mounting and chip mounting in the assembly of the semiconductor device of FIG. FIG. 25 is a plan view and a cross-sectional view showing an example of the structure after solder foil mounting and clip mounting is completed in the assembly of the semiconductor device of FIG. 16, and FIG. FIG. 27 is a plan view, a cross-sectional view, and a side view showing an example of the structure after completion of wire bonding and resin molding in the assembly of the semiconductor device of FIG. 28 is a plan view showing an example of a structure after completion of exterior plating in the assembly of the semiconductor device of FIG.

  The semiconductor device of the second embodiment is a power semiconductor device 37 as in the first embodiment, and the structure thereof is the same as that of the semiconductor device 10 of the first embodiment as shown in FIGS. However, the difference from the semiconductor device 10 is that, as shown in FIG. 18, the clip 20 is provided with a stand portion 20h (cut and separated after assembly), and each semiconductor chip in the reflow process of the assembly. -The reflow is performed by supporting the clip 20 by the stand portion 20h so as to ensure the thickness of the solder 18 between the clips 20.

  18 to 20 show the structure during the reflow process of assembling the semiconductor device 37. The lower end portion 20i of the stand portion 20h provided on the clip 20 is brought into contact with the heat spreader 19 which is a chip mounting portion, and the stand The solder reflow is performed in a state where the clip 20 is supported by the portion 20h so that the clip 20 is not lowered. Thereby, the thickness of the solder 18 between each semiconductor chip and the clip 20 can be ensured.

  21 and 22 show the structure of the stand portion 20h connected to the clip 20, and after the reflow is completed, the stand portion 20h is cut at the position indicated by the portion C in FIG. Therefore, the stand portion 20h does not remain in the semiconductor device 37 after the assembly is completed.

  In addition, as shown in FIG. 21, the through-hole 20m is formed in the location (cut | disconnection location of C section) which connected the main-body part 20j and the stand part 20h of the clip 20. As shown in FIG. Thereby, it can cut | disconnect easily at the time of the cutting | disconnection of the stand part 20h after completion | finish of reflow.

  Further, a V-groove (other groove) 20k is formed at a location where the main body portion 20j of the clip 20 and the stand portion 20h are connected (cut portion of the C portion) as shown in FIG. Thereby, it can cut | disconnect more easily at the time of the cutting | disconnection of the stand part 20h after completion | finish of reflow.

  Note that both the through-hole 20m and the V-groove 20k, which are the aforementioned means for facilitating the disconnection of the stand portion 20h, may be formed, or only one of them may be formed. As shown in FIGS. 21 and 22, it goes without saying that the effect of facilitating cutting is greatest when both are formed.

  When two semiconductor chips, IGBT chip 15 and diode chip 16, are mounted on heat spreader 19 as in semiconductor device 37 of the second embodiment, stand unit 20h connected to clip 20 is shown in FIG. As shown in FIGS. 19 and 20, one IGBT chip 15 and one diode chip 16 are provided on both sides in the arrangement direction, and the lower ends 20i of the two stand parts 20h are as shown in FIGS. And the diode chip 16 are preferably provided so as to be in contact with the heat spreader 19, respectively.

  That is, since the two stand portions 20h can be supported at positions on both sides of the IGBT chip 15 and the diode chip 16, and can be supported at a position between the IGBT chip 15 and the diode chip 16, the clip 20 Both the portion connected to the IGBT chip 15 (first surface 20a) and the portion connected to the diode chip 16 (third surface 20d) can be supported substantially evenly, and the first surface 20a of the clip 20 and the IGBT chip 15 Both the thickness of the solder 18 between them and the thickness of the solder 18 between the third surface 20d and the diode chip 16 can be ensured.

  Next, assembly of the semiconductor device 37 according to the second embodiment will be described with reference to a flowchart shown in FIG.

  First, solder foil mounting shown in step S21 of FIG. 23 is performed. Here, as shown in step S21 of FIG. 24, two solder foils (first solder) 30 for the IGBT chip 15 and the diode chip 16 are arranged on the heat spreader 19 which is the chip mounting portion of the lead frame 29. The lead frame 29 is formed with a heat spreader 19 serving as a chip mounting portion and a heat radiating member at the center, and a plurality of external connection terminals such as a collector terminal 12 and an emitter terminal 13 are provided at both ends of the heat spreader 19. Terminals and the like are formed. The heat spreader 19 is integrally formed with the collector terminal 12, and a plurality of external connection terminals such as the collector terminal 12 and the emitter terminal 13 are integrally connected with the frame portion 29a.

  Note that flux is applied to the heat spreader 19 before mounting the solder foil.

  The solder foil 30 as the first solder is a thin chip-like foil made of solder.

  Thereafter, chip mounting shown in step S22 of FIG. 23 is performed. First, a flux is applied to the solder foil 30. After the flux application, the IGBT chip 15 is mounted on one solder foil 30 and the diode chip 16 is mounted on the other solder foil 30 as shown in step S22 of FIG. At this time, the IGBT chip 15 and the diode chip 16 are arranged so that the back surface 15b and the back surface 16b of the IGBT chip 15 and the diode chip 16 face the heat spreader 19 through the solder foil 30, respectively.

  Thereafter, solder foil mounting shown in step S23 of FIG. 23 is performed. First, flux is applied to the IGBT chip 15 and the diode chip 16. After applying the flux, as shown in step S23 of FIG. 25, the solder foil 31 as the second solder is disposed on the emitter electrode 40 and the anode electrode 62 on the main surfaces 15a and 16a of the IGBT chip 15 and the diode chip 16, respectively. Further, the solder paste 32 as the third solder is applied (arranged) on the emitter terminal 13 as the external connection terminal.

  Thereafter, the clip mounting shown in step S24 of FIG. 23 is performed. First, flux is applied to the solder foil 31 and the solder paste 32. After the flux application, the clip 20 is disposed on the IGBT chip 15 and the diode chip 16 via the solder foil 31, respectively, as shown in step S24 of FIG. Further, one end of the clip 20 is disposed on the solder paste 32 on the emitter terminal 13.

  The clip 20 is a thin plate-like conductor member made of a copper plate or the like, and as shown in FIG. 20, a first surface 20a connected to the IGBT chip 15 and a second surface 20b formed by bending from the first surface 20a. The third surface 20d connected to the diode chip 16 and the fourth surface 20e formed by bending from the third surface 20d are provided. At this time, the second surface 20 b is bent in a direction away from the IGBT chip 15, and the fourth surface 20 e is bent in a direction away from the diode chip 16.

  Further, the clip 20 of the second embodiment is provided with a stand portion 20h extending in a direction intersecting with the first surface 20a. As shown in FIG. 21, one (one) stand portion 20h is provided on each side of the main body portion 20j of the clip 20. Further, a through-hole 20m is formed at a location where the main body portion 20j and the stand portion 20h of the clip 20 are connected (cut portion of the C portion in FIG. 21), and the main body portion 20j and the stand portion 20h are also connected. As shown in FIG. 22, a V groove (another groove) 20k is formed at the left portion (the cut portion of the portion C in FIG. 21).

  When such a clip 20 is used and the clip is mounted, the first surface 20a is positioned on the emitter electrode 40 of the main surface 15a of the IGBT chip 15 via the solder foil 31, and the third surface 20d is soldered. One end of the clip 20 is positioned via the solder paste 32 on the anode terminal 62 of the main surface 16a of the diode chip 16 via the foil 31 and further on the emitter terminal 13 which is an external connection terminal.

  That is, the plate-like clip 20 is disposed across the IGBT chip 15, the diode chip 16, and the emitter terminal 13.

  At this time, the lower end portion 20i of the stand portion 20h of the clip 20 is disposed at a height (position) that contacts the heat spreader 19 that is the chip mounting portion or that forms a very small gap with the heat spreader 19. It has become a state.

  Thereafter, the reflow shown in step S25 of FIG. 23 is performed. Here, as shown in the diagram of step S25 in FIG. 26, the solder foils 30 and 31 and the solder paste 32 shown in FIG. 25 are melted (heat treated) through a reflow furnace, and the respective members are fixed. That is, the heat spreader 19 is connected to the IGBT chip 15 and the diode chip 16 by melting and fixing the solder foil 30 through a reflow furnace, and further the IGBT chip 15 is melted and fixed. The diode chip 16 and the clip 20 are connected to each other, and the solder paste 32 is melted and fixed to connect one end of the clip 20 to the emitter terminal 13 that is an external connection terminal.

  Here, the solder foil 31 becomes the solder 18 when melted. At this time, since the solder 18 is in a molten state, even if the lower end 20 i of the stand part 20 h is slightly separated from the heat spreader 19, the lower end 20 i of the stand part 20 h can be reliably brought into contact with the heat spreader 19. As a result, it is possible to form a state in which the clip 20 is supported by the stand portion 20h so that the first surface 20a and the third surface 20d of the clip 20 do not approach the IGBT chip 15 and the diode chip 16, respectively.

  That is, as shown in FIG. 20, the thickness of the solder 18 between the IGBT chip 15 and the clip 20 and the thickness of the solder 18 between the diode chip 16 and the clip 20 are secured, and the first surface 20a and the first surface 20a of the clip 20 are secured. Reflow can be performed so that the three surfaces 20d do not approach each semiconductor chip (so as not to be lowered).

  After the reflow is completed, the stand part cutting and flux cleaning shown in step S26 of FIG. 23 are performed. First, the stand part 20h is cut at the position shown in part C of FIG. At that time, the stand portion 20 h is cut and separated from the main body portion 20 j of the clip 20. The stand part 20h is cut using, for example, mold cutting.

  In addition, as shown in FIG. 21, since the through-hole 20m is formed in the location (cutting location of C part) which connected the main-body part 20j and the stand part 20h of the clip 20, cutting | disconnection of the stand part 20h is easy. Can be done.

  Further, as shown in FIG. 22, a V-groove (other groove) 20k is formed at a location where the main body portion 20j of the clip 20 and the stand portion 20h are connected (the cut location of the portion C in FIG. 21). The stand 20h can be cut more easily.

  Therefore, by providing the through-hole 20m and the V-groove 20k at the cutting portion of the stand portion 20h, cutting can be facilitated, and cutting is performed by bending cutting or the like without adopting the above-described die cutting. It is also possible to do.

  Further, flux cleaning is performed after the cutting of the stand portion 20h. Here, cleaning for removing the aforementioned flux is performed using a chemical solution or the like.

  After flux cleaning, wire bonding shown in step S27 of FIG. 23 is performed. Here, as shown in the diagram of step S <b> 27 in FIG. 27, each of the bonding pads 41 to 45 on the main surface 15 a of the IGBT chip 15 and each of the plurality of signal terminals 14 that are external connection terminals are connected by wires 28. Connect electrically. The wire 28 is a thin wire made of, for example, aluminum.

  After wire bonding, the resin mold of step S28 in FIG. 23 is performed. Here, as shown in the diagram of step S28 in FIG. 27, the sealing body 11 is formed of a sealing resin, and the IGBT chip 15, the diode chip 16, the clip 20, the plurality of wires 28, and a part of the heat spreader 19 are formed. Seal with resin. For example, transfer molding is performed using a sealing resin such as an epoxy resin.

  After the resin molding, exterior plating in step S29 in FIG. 23 is performed. Here, as shown in the plan view of step S29 in FIG. 28, the portion (external connection terminal or the like) exposed from the sealing body 11 of the lead frame 29 is covered with the exterior plating 36. The exterior plating 36 is, for example, solder plating.

  After the exterior plating, the separation and molding in step S30 in FIG. 23 is performed. Here, the collector terminal 12, the emitter terminal 13, and the plurality of signal terminals 14 are cut and bent from the frame portion 29a of the lead frame 29 shown in the plan view of step S29 in FIG. 28, and the assembly is completed as shown in step S31. Become. That is, the assembly of the semiconductor device 37 (see FIG. 16) having the same external structure as the semiconductor device 10 shown in FIGS. 1 and 2 is completed.

  According to the method for manufacturing the semiconductor device 37 of the second embodiment, as shown in FIG. 20, by performing solder reflow while the clip 20 is supported by the stand portion 20 h provided on the clip 20, the IGBT chip 15. And the first surface 20a of the clip 20 and the distance between the diode chip 16 and the third surface 20d of the clip 20 are secured to each semiconductor chip. Reflow can be performed so as not to approach (do not fall).

  Thereby, since the space | interval with the clip 20 on each semiconductor chip is ensured, the reflow can be performed while suppressing or preventing the suction 18a of the solder 18 on each semiconductor chip.

  As a result, the thickness of the solder 18 between the IGBT chip 15 and the clip 20 and the thickness of the solder 18 between the diode chip 16 and the clip 20 can be ensured.

  Thereby, since the thickness of the solder 18 on each semiconductor chip is ensured, the thermal stress applied to the IGBT chip 15 and the diode chip 16 in the power cycle test after assembling the semiconductor device can be reduced.

  As a result, generation of chip cracks in the semiconductor device 37 can be reduced or prevented, and the reliability of the semiconductor device 37 can be improved.

  The other effects obtained by the method for manufacturing the semiconductor device 37 according to the second embodiment are the same as the effects obtained by the method for manufacturing the semiconductor device 10 according to the first embodiment. .

  Next, a modification of the second embodiment will be described.

  29 is a plan view showing the internal structure of a semiconductor device according to a modification of the second embodiment of the present invention through a sealing body, and FIG. 30 is a partial cross-sectional view showing the structure of FIG. 31 is an enlarged partial side view showing an example of the structure of the semiconductor device shown in FIG.

  In the modification of the second embodiment, the clip 20 of the first embodiment is provided with a groove 20g, and the clip 20 of the second embodiment is provided with a stand portion 20h, and the clip 20 is supported by the stand portion 20h. This is a combination of a manufacturing method for performing reflow in a state.

  That is, in the semiconductor device 38 according to the modification of the second embodiment, as shown in FIG. 31, the second surface 20b and the fourth surface 20e of the clip 20 are provided with grooves 20g, and the reflow process of the assembly is performed. The reflow is performed in a state where the clip 20 is supported by the stand portion 20 h provided on the clip 20.

  The shape of the groove 20g, the location where it is provided, and the like are the same as the groove 20g of the clip 20 of the first embodiment. The shape of the stand portion 20h and the place where the stand portion 20h is provided are the same as in the semiconductor device 37 of the second embodiment.

  Furthermore, since the manufacturing method of the semiconductor device 38 of the modification is the same as the manufacturing method of the semiconductor device 37 of the second embodiment, the duplicate description is omitted.

  According to the semiconductor device 38 and the manufacturing method thereof in the modification, since the sucked-up 18a of the solder 18 can be suppressed or prevented by the groove 20g, the thickness of the solder 18 on each semiconductor chip can be ensured.

  Furthermore, when reflowing the assembly of the semiconductor device 38, the gap between the first surface 20 a of the clip 20 and the IGBT chip 15 is performed by supporting the clip 20 by the stand portion 20 h connected to the clip 20 and performing reflow. In addition, reflow can be performed while ensuring the distance between the third surface 20d and the diode chip 16, and as a result, the thickness of the solder 18 on each semiconductor chip can be ensured.

  Therefore, the thickness of the solder 18 on each semiconductor chip can be more reliably ensured by the combination of the groove 20g and the stand portion 20h.

  Thereby, the thermal stress applied to the IGBT chip 15 and the diode chip 16 in a power cycle test or the like can be further alleviated.

  As a result, generation of chip cracks in the semiconductor device 38 can be further reduced or prevented, and the reliability of the semiconductor device 38 can be further improved.

(Embodiment 3)
32 is a plan view showing the internal structure of the semiconductor device according to the third embodiment of the present invention through a sealing body, FIG. 33 is a partial cross-sectional view showing the structure of FIG. 32 in partial cross-section, and FIG. FIG. 35 is an enlarged partial side view showing an example of the structure of the semiconductor device shown in FIG. 32, and FIG. 35 is an equivalent circuit diagram showing an example of the circuit operation of the semiconductor device shown in FIG. 36 is a plan view showing an example of the structure during reflow in assembling the semiconductor device of FIG. 32, FIG. 37 is a partial cross-sectional view showing the structure of FIG. 36 in a partial cross section, and FIG. 38 shows the structure of FIG. FIG. 39 is a side view schematically showing, FIG. 39 is a plan view showing an example of the structure of the stand portion shown in FIG. 36, and FIG. 40 is a cross-sectional view showing the structure cut along line AA shown in FIG.

  The semiconductor device of the third embodiment is a power semiconductor device 39 as in the first embodiment, but shows a case where there is one semiconductor chip mounted on the heat spreader 19. That is, in the semiconductor device 39, one semiconductor chip is incorporated inside.

  In the third embodiment, a case where one semiconductor chip to be incorporated is an IGBT chip 15 as shown in FIG. 32 will be described as an example.

  In the third embodiment, the groove 20g is formed in the clip 20 of the semiconductor device 39 as shown in FIG. 34, and further, the stand 20h provided in the clip 20 in the reflow process of the assembly. Reflow is performed so as to support the clip 20 and ensure the thickness of the solder 18 between each semiconductor chip and the clip 20.

  Therefore, in the structure of the semiconductor device 39 shown in FIGS. 32 to 34, the diode chip 16 is removed from the structure of the semiconductor device 10 of the first embodiment, and only the portion connected to the diode chip 16 is removed even in the shape of the clip 20. It is the same as that.

  Therefore, as shown in FIG. 34, the clip 20 has a ridge at the boundary between the first surface 20a and the second surface 20b on the second surface 20b formed by bending from the first surface 20a that is solder-connected to the IGBT chip 15. The grooves 20g are formed in two rows along the portion 20c.

  Note that the circuit configuration and operation of the IGBT chip 15 shown in FIG. 35 in the semiconductor device 39 are the same as those of the IGBT chip 15 shown in FIG. 5 of the first embodiment, and thus description thereof is omitted here.

  Further, since the structure other than the clip 20 of the semiconductor device 39 is substantially the same as that of the semiconductor device 10 of the first embodiment, the redundant description thereof will be omitted.

  Next, the assembly of the semiconductor device 39 according to the third embodiment will be described. In the reflow process, the clip 20 is supported by the stand portion 20h so as to secure the thickness of the solder 18 between the IGBT chip 15 and the clip 20, and the reflow is performed. I do.

  Here, FIGS. 36 to 38 show the structure during the reflow process of assembling the semiconductor device 39, and the lower end 20i of the stand part 20h provided on the clip 20 is brought into contact with the heat spreader 19 which is a chip mounting part. Then, solder reflow is performed in a state where the clip 20 is supported by the stand portion 20h so that the clip 20 is not lowered, and thereby the thickness of the solder 18 between the IGBT chip 15 and the clip 20 can be ensured. it can.

  39 and 40 show the structure of the stand part 20h connected to the clip 20, and after the reflow is completed, the stand part 20h is cut at the position shown in part C of FIG. Therefore, the stand part 20h does not remain in the semiconductor device 39 after the assembly is completed. In the semiconductor device 39 of the third embodiment, only one (one) stand part 20h of the clip 20 is provided, and this stand part 20h extends in a direction intersecting the first surface 20a. ing.

  As shown in FIG. 39, also in the third embodiment, a through-hole 20m is formed at a location where the main body portion 20j of the clip 20 and the stand portion 20h are connected (cut location at the C portion). Thereby, it can cut | disconnect easily at the time of the cutting | disconnection of the stand part 20h after completion | finish of reflow.

  Furthermore, as shown in FIG. 40, a V-groove (other groove) 20k is formed at a location where the main body portion 20j of the clip 20 and the stand portion 20h are connected (a cut location of the portion C). Thereby, it can cut | disconnect more easily at the time of the cutting | disconnection of the stand part 20h after completion | finish of reflow. Here, both the through-hole 20m and the V-groove 20k, which are the above-described means for facilitating the disconnection of the stand portion 20h, may be formed, or only one of them may be formed. As shown in FIGS. 39 and 40, it goes without saying that the effect of facilitating cutting is greatest when both are formed.

  As described above, the main body portion 20j of the clip 20 is provided with the stand portion 20h connected to the main body portion 20j, so that the reflow can be performed by supporting the clip 20 by the stand portion 20h in the reflow process of the assembly. it can.

  Note that the details of the assembly of the semiconductor device 39 of the third embodiment are the same as the assembly of the semiconductor device 37 of the second embodiment, and a description thereof will be omitted.

  According to the semiconductor device 39 and the manufacturing method thereof of the third embodiment, the groove 20g is formed in the clip 20 as shown in FIG. 34, as in the semiconductor device 38 of the modification of the second embodiment. In addition, the sucking-up 18a of the solder 18 on the IGBT chip 15 can be suppressed or prevented, and as a result, the thickness of the solder 18 on the IGBT chip 15 can be ensured.

  Further, at the time of reflow for assembling the semiconductor device 39, as shown in FIG. 38, the clip 20 is supported by the stand portion 20h connected to the clip 20, and reflow is performed. Reflow can be performed while ensuring a gap with the IGBT chip 15, and as a result, the thickness of the solder 18 on the IGBT chip 15 can be ensured.

  Therefore, the combination of the groove 20g and the stand portion 20h can ensure the thickness of the solder 18 on the IGBT chip 15 more reliably, and can further alleviate the thermal stress applied to the IGBT chip 15 in a power cycle test or the like. it can.

  As a result, generation of chip cracks in the semiconductor device 39 can be further reduced or prevented, and the reliability of the semiconductor device 39 can be further improved.

  In the semiconductor device 39 according to the third embodiment, at least one of the groove 20g formed in the clip 20 or the stand portion 20h provided in the clip 20 may be formed. It does not have to be.

  As described above, the groove 20g formed in the clip 20 or the stand portion 20h provided in the clip 20 can be effective even in the semiconductor device 39 in which one semiconductor chip is incorporated.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the first and second embodiments, the case where two semiconductor chips are incorporated in the semiconductor device, the first semiconductor chip is an IGBT chip, and the second semiconductor chip is a diode chip is described. The first semiconductor chip may be a diode chip, and the second semiconductor chip may be an IGBT chip.

  The semiconductor chip incorporated in the semiconductor device may be a chip other than the IGBT chip or the diode chip.

  Further, when two semiconductor chips are incorporated in the semiconductor device, the groove 20g formed in the clip 20 may be formed at each location corresponding to both semiconductor chips of the clip 20, or either one of them. It may be formed at a location corresponding to the semiconductor chip.

10 Semiconductor Device 11 Sealing Body 12 Collector Terminal (External Connection Terminal)
12a Opening 13 Emitter terminal (external connection terminal)
13a Opening 14 Signal terminal (External connection terminal)
15 IGBT chip (first semiconductor chip)
15a Main surface 15b Back surface 16 Diode chip (second semiconductor chip)
16a Main surface 16b Back surface 16c Diode element 17 Solder 18 Solder 18a Sucking up 19 Heat spreader (chip mounting portion)
20 clips (plate conductor member)
20a First surface 20b Second surface 20c Edge 20d Third surface 20e Fourth surface 20f Edge 20g Groove 20h Stand 20i Lower end 20j Main body 20k V-groove (other groove)
20m Through hole 20n Fifth surface 21, 22 Temperature detection terminal 23 External connection gate terminal 24 Kelvin detection terminal 25 Current detection terminal 26 Kelvin detection terminal 27 Solder 28 Wire 29 Lead frame 29a Frame 30 Solder foil (first 1 solder)
31 Solder foil (second solder)
32 Solder paste (3rd solder)
36 Exterior plating 37, 38, 39 Semiconductor device 40 Emitter electrode 41 Bonding pad 41a Cathode 42 Bonding pad 42a Anode electrode 43 Bonding pad 43a Gate electrode 44 Bonding pad 44a Common emitter electrode 45 Bonding pad 45a Sense emitter electrode 46 Collector electrode 50 IGBT
51 IGBT for detection
52 Temperature sensing diode 54 p ⁺ type semiconductor region 55 n ⁺ type semiconductor region 56 n ⁻ type semiconductor region 57 p type semiconductor region 58 n ⁺ type semiconductor region 59 trench groove 60 gate insulating film 61 emitter wiring 62 anode electrode 63 cathode 64 n ⁺ type semiconductor region 65 n ⁻ type semiconductor region 66 p type semiconductor region 67 p ⁻ type semiconductor region 80 semiconductor device 81 IGBT chip 82 diode chip 83 heat spreader 84, 85 solder 86 sealing body 87 clip 88 emitter terminal 89 solder 90 connection Surface 91 Surface 92 Horizontal surface 93 Transistor chip 94 Semiconductor device

Claims (17)

A first semiconductor chip comprising a main surface and a back surface, and electrodes formed on the main surface;
A second semiconductor chip comprising a main surface and a back surface, electrodes are formed on the main surface, and are arranged side by side with the first semiconductor chip;
A chip mounting portion on which the first semiconductor chip and the second semiconductor chip are mounted;
A plurality of external connection terminals exposed to the outside;
The first semiconductor chip is electrically connected to the electrode on the main surface and the electrode on the main surface of the second semiconductor chip, respectively, and one end is electrically connected to any of the plurality of external connection terminals. A plate-like conductor member;
Have
The plate-like conductor member is formed by being bent from the first surface in a direction away from the first semiconductor chip, and a first surface connected to the electrodes on the main surface of the first semiconductor chip via solder. A second surface, a third surface connected to the electrode of the main surface of the second semiconductor chip via solder, and a fourth surface formed by bending from the third surface in a direction away from the second semiconductor chip. With a surface,
On at least one of the second surface and the fourth surface of the plate-like conductor member, a ridge at the boundary between the first surface and the second surface or a ridge at the boundary between the third surface and the fourth surface A semiconductor device, wherein a groove is formed along the portion. The semiconductor device according to claim 1,
The semiconductor device, wherein the groove is formed on the second surface and the fourth surface of the plate-like conductor member. The semiconductor device according to claim 2,
A semiconductor device, wherein the grooves are formed in a plurality of rows. The semiconductor device according to claim 1,
One of the first semiconductor chip and the second semiconductor chip is a semiconductor chip in which an IGBT is formed, and either one is a semiconductor chip in which a diode is formed. A semiconductor chip comprising a main surface and a back surface, and electrodes formed on the main surface;
A chip mounting portion on which the semiconductor chip is mounted;
A plurality of external connection terminals exposed to the outside;
A plate-like conductor member that is electrically connected to the electrode of the main surface of the semiconductor chip, and one end of which is electrically connected to any of the plurality of external connection terminals;
Have
The plate-like conductor member includes a first surface that is connected to the electrode on the main surface of the semiconductor chip via solder, and a second surface that is bent from the first surface in a direction away from the semiconductor chip. With
A semiconductor device, wherein a groove is formed in the second surface of the plate-like conductor member along a ridge portion at a boundary between the first surface and the second surface. (A) On the chip mounting portion of the lead frame having a chip mounting portion and a plurality of external connection terminals, the first semiconductor chip and the second semiconductor chip are respectively connected via the first solder, and the back surface of each semiconductor chip is the chip A step of arranging it so as to face the mounting portion;
(B) A second solder is disposed on the main surface electrode of each of the first semiconductor chip and the second semiconductor chip, and a third solder is disposed on any one of the plurality of external connection terminals. And a process of
(C) A plate-shaped conductor member comprising a first surface, a second surface formed by bending from the first surface, a third surface, and a fourth surface formed by bending from the third surface. The first surface is positioned on the electrode on the main surface of the first semiconductor chip via the second solder, and the third surface of the plate-like conductor member is positioned on the first solder via the second solder. (2) Positioning the electrode on the main surface of the semiconductor chip, and further positioning one end of the plate-like conductor member on any one of the plurality of external connection terminals via the third solder When,
(D) Heat treatment is performed to melt and fix the first solder, thereby connecting the chip mounting portion to the first semiconductor chip and the second semiconductor chip, and melting and fixing the second solder. By connecting the first semiconductor chip and the second semiconductor chip and the plate-like conductor member, and melting and fixing the third solder, the one end of the plate-like conductor member and the plurality of the plurality of plate-like conductor members are fixed. Connecting any one of the external connection terminals;
Have
The second surface of the plate-like conductor member is bent in a direction away from the first semiconductor chip, and the fourth surface is bent in a direction away from the second semiconductor chip;
At least one of the second surface and the fourth surface has a groove along a ridge portion at the boundary between the first surface and the second surface or a ridge portion at the boundary between the third surface and the fourth surface. Formed,
The method of manufacturing a semiconductor device, wherein when the heat treatment is performed in the step (d), the height of the melted second solder is less than or equal to the groove. The method of manufacturing a semiconductor device according to claim 6.
A method of manufacturing a semiconductor device, wherein the groove is formed in the second surface and the fourth surface of the plate-like conductor member. The method of manufacturing a semiconductor device according to claim 7.
A method of manufacturing a semiconductor device, wherein the grooves are formed in a plurality of rows. The method of manufacturing a semiconductor device according to claim 6.
One of the first semiconductor chip and the second semiconductor chip is a semiconductor chip in which an IGBT is formed, and either one is a semiconductor chip in which a diode is formed. (A) On the chip mounting portion of the lead frame having a chip mounting portion and a plurality of external connection terminals, the first semiconductor chip and the second semiconductor chip are respectively connected via the first solder, and the back surface of each semiconductor chip is the chip A step of arranging it so as to face the mounting portion;
(B) A second solder is disposed on the main surface electrode of each of the first semiconductor chip and the second semiconductor chip, and a third solder is disposed on any one of the plurality of external connection terminals. And a process of
(C) intersects the first surface, the second surface formed by bending from the first surface, the third surface, the fourth surface formed by bending from the third surface, and the first surface. The plate-like conductor member is positioned on the electrode of the main surface of the first semiconductor chip via the second solder, the plate-like conductor member having a stand portion extending in the direction. The third surface of the second semiconductor chip is positioned on the electrode on the main surface of the second semiconductor chip via the second solder, and the third surface is disposed on any one of the plurality of external connection terminals. A step of positioning one end of the plate-like conductor member via solder;
(D) Heat treatment is performed to melt and fix the first solder, thereby connecting the chip mounting portion to the first semiconductor chip and the second semiconductor chip, and melting and fixing the second solder. By connecting the first semiconductor chip and the second semiconductor chip and the plate-like conductor member, and melting and fixing the third solder, the one end of the plate-like conductor member and the plurality of the plurality of plate-like conductor members are fixed. Connecting any one of the external connection terminals;
(E) cutting and separating the stand part of the plate-like conductor member from the main body part of the plate-like conductor member;
Have
The second surface of the plate-like conductor member is bent in a direction away from the first semiconductor chip, and the fourth surface is bent in a direction away from the second semiconductor chip;
In the step (d), the lower end of the stand portion of the plate-like conductor member is brought into contact with the chip mounting portion so that the first surface and the third surface do not approach each semiconductor chip. A method of manufacturing a semiconductor device, wherein the heat treatment is performed in a state where the semiconductor device is supported. The method of manufacturing a semiconductor device according to claim 10.
A method of manufacturing a semiconductor device, wherein another groove is formed at a location where the main body portion and the stand portion of the plate-like conductor member are connected. The method of manufacturing a semiconductor device according to claim 10.
A through hole is formed at a location where the main body portion and the stand portion of the plate-like conductor member are connected to each other. The method of manufacturing a semiconductor device according to claim 10.
One of the stand portions of the plate-like conductor member is provided on each side of the first semiconductor chip, and the lower ends of the two stand portions are respectively connected to the first semiconductor chip and the second semiconductor chip. A method of manufacturing a semiconductor device, wherein the semiconductor device is provided so as to be in contact with each of the chip mounting portions at a position therebetween. The method of manufacturing a semiconductor device according to claim 10.
One of the first semiconductor chip and the second semiconductor chip is a semiconductor chip in which an IGBT is formed, and either one is a semiconductor chip in which a diode is formed. The method of manufacturing a semiconductor device according to claim 10.
At least one of the second surface and the fourth surface has a groove along a ridge portion at the boundary between the first surface and the second surface or a ridge portion at the boundary between the third surface and the fourth surface. A method for manufacturing a semiconductor device, wherein the semiconductor device is formed. (A) A semiconductor chip is disposed on the chip mounting portion of a lead frame having a chip mounting portion and a plurality of external connection terminals so that the back surface of the semiconductor chip faces the chip mounting portion via a first solder. And a process of
(B) disposing second solder on the electrode on the main surface of the semiconductor chip, and disposing third solder on any one of the plurality of external connection terminals;
(C) The first surface of a plate-like conductor member having a first surface and a second surface bent from the first surface is connected to the main surface of the semiconductor chip via the second solder. A step of positioning one end of the plate-like conductor member via the third solder on any one of the plurality of external connection terminals; and
(D) performing a heat treatment, melting and fixing the first solder, connecting the chip mounting portion and the semiconductor chip, and melting and fixing the second solder; Connecting the plate-like conductor member, and melting and fixing the third solder to connect one end of the plate-like conductor member and any one of the plurality of external connection terminals;
Have
The second surface of the plate-like conductor member is bent in a direction away from the semiconductor chip;
A groove is formed in the second surface along a ridge at the boundary between the first surface and the second surface,
The method of manufacturing a semiconductor device, wherein the second solder melted when the heat treatment is performed in the step (d) has a height equal to or less than the groove. (A) A semiconductor chip is disposed on the chip mounting portion of a lead frame having a chip mounting portion and a plurality of external connection terminals so that the back surface of the semiconductor chip faces the chip mounting portion via a first solder. And a process of
(B) disposing second solder on the electrode on the main surface of the semiconductor chip, and disposing third solder on any one of the plurality of external connection terminals;
(C) The first surface of the plate-like conductor member having a first surface, a second surface formed by bending from the first surface, and a stand portion extending in a direction intersecting the first surface. The plate-like conductor is positioned on the electrode on the main surface of the semiconductor chip via the second solder, and the plate-like conductor is interposed on any one of the plurality of external connection terminals via the third solder. Positioning one end of the member;
(D) performing a heat treatment, melting and fixing the first solder, connecting the chip mounting portion and the semiconductor chip, and melting and fixing the second solder; Connecting the plate-like conductor member, and melting and fixing the third solder to connect one end of the plate-like conductor member and any one of the plurality of external connection terminals; ,
(E) cutting and separating the stand part of the plate-like conductor member from the main body part of the plate-like conductor member;
Have
The second surface of the plate-like conductor member is bent in a direction away from the semiconductor chip;
In the step (d), the lower end portion of the stand portion of the plate-like conductor member is brought into contact with the chip mounting portion, and the first surface is supported by the stand portion so as not to approach the semiconductor chip. A method for manufacturing a semiconductor device, wherein the heat treatment is performed.

Images