JP2012243251A - Memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce risk of producing large noise at time of reading data in a memory system in which a plurality of memory devices are commonly connected to a memory controller.SOLUTION: The memory system comprises: a memory controller 32; and a plurality of memory devices 12a-12d. Each data terminal 20d of the memory devices 12a-12d is commonly connected to the memory controller 32. The memory device 12 includes a memory cell array 14 and a data output circuit 18 that outputs data read from the memory cell array 14. Timing when the memory devices 12a-12d output data is adjusted to be different from each other.

Description

  The present invention relates to a memory system, and more particularly to a memory system having a configuration in which a plurality of memory devices are commonly connected to a memory controller.

  In a memory system including a memory device such as a DRAM (Dynamic Random Access Memory), a plurality of memory devices may be commonly connected to one memory controller in order to increase the memory capacity of the entire system. The memory controller is a control device that issues various commands such as a read command and a write command to the memory device, and also receives read data and transmits write data. The memory controller is often provided between a CPU (Central Processing Unit) and a memory device, but the CPU itself may serve as a memory controller.

Japanese Patent No. 3558599

  When the memory device outputs data (read data), temporary power supply noise occurs. Memory systems are usually designed to operate with such noise tolerance. However, in the case of a memory system in which a plurality of memory devices as described above are commonly connected to a single memory controller, if a plurality of memory devices output read data simultaneously, a plurality of noises may be superimposed, resulting in a large noise. is there. Such a large noise may cause a malfunction of the memory device or the memory controller.

  A memory system according to the present invention includes a memory controller and a plurality of memory devices that are commonly connected to the memory controller and operate based on commands issued from the memory controller. The memory device includes a memory cell array and a data output circuit that outputs data (read data) read from the memory cell array to a memory controller. In a plurality of memory devices, the output timing of data (read data) is adjusted to be different from each other.

  According to the present invention, in a memory system of a type in which a plurality of memory devices are commonly connected to a memory controller, it is easy to reduce the risk of large noise occurring when reading data.

1 is a schematic cross-sectional view of a memory system. It is a typical top view of a memory chip. It is a block diagram of the wiring structure of the memory system in the first to fourth embodiments. 2 is a block diagram of main parts of a memory device and a memory controller in the first embodiment. FIG. It is a circuit diagram of a data output circuit. 6 is a time chart showing the relationship between internal clock signal ICLK and data output timing in the first embodiment. It is a block diagram of the principal part of the memory device and memory controller in 2nd Embodiment. 10 is a time chart showing the relationship between internal clock signal ICLK and data output timing in the second embodiment. It is a block diagram of the principal part of the memory device and memory controller in 3rd Embodiment. 10 is a time chart showing the relationship between internal clock signal ICLK and data output timing in the third embodiment. It is a block diagram of the principal part of the memory device and memory controller in 4th Embodiment. It is a circuit diagram of an output timing adjustment circuit and a data output circuit. It is a time chart which shows the relationship between the internal clock signal ICLK in 4th Embodiment, and the timing of data output. It is a flowchart of an output timing adjustment operation of read data DQ. It is a block diagram of the principal part of the memory device and memory controller in the modification 1 of 4th Embodiment. It is a block diagram of the principal part of the memory device and memory controller in the modification 2 of 4th Embodiment. It is a block diagram of the principal part of the memory device and memory controller in 5th Embodiment.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic cross-sectional view of the memory system 10. In the memory system 10, two memory chips 22a and 22b and one memory controller 32 are stacked. The memory chips 22a and 22b and the memory controller 32 are all one-chip semiconductor devices using a silicon substrate. The memory chip 22 in this embodiment (first to fifth embodiments) is a general-purpose DRAM chip having the same configuration.

  The general-purpose DRAM is a DRAM including a “front end unit” that performs an interface with the outside, and a “back end unit” that accesses a plurality of memory cell arrays. Examples include SDRAM (Synchronous Dynamic Random Access Memory), DDR1 (Double Data Rate 1) type SDRAM, DDR2 (Double Data Rate 2) type SDRAM, DDR3 (Double Data Rate 3) type SDRAM, and the like. Here, the so-called prefetch operation is not performed in the SDRAM, while the DDR1, DDR2, and DDR3 SDRAMs perform prefetch operations in 2-bit units, 4-bit units, and 8-bit units, respectively.

  In the read operation, the read data of the read data of the number of bits corresponding to the number of bits in the SDRAM is 1 bit per the data input / output terminal from the back end unit in one access in the SDRAM, and in the DDR type SDRAM in the petit fetch operation in parallel. read out. In the DDR type SDRAM, read data is output through parallel / serial conversion by the front end unit. In the write operation, write data of 1 bit per data input / output terminal per data input / output terminal is serially input to the front end portion in one access, and the number of bits corresponding to the number of bits in the petit fetch operation is input to the DDR type SDRAM. In the DDR type SDRAM, the write data is supplied to the back end unit through serial / parallel conversion by the front end unit. The general-purpose DRAM is not a so-called “core chip” in which only the back end portion is integrated.

  The memory chips 22a and 22b and the memory controller 32 are provided with a number of through silicon vias TSV (Through Silicon Via) penetrating the silicon substrate. Adjacent chips are electrically connected by the through electrode TSV. The memory controller 32 is electrically connected to the wiring provided on the surface 41 of the interposer 40 through the through silicon via TSV. The memory controller 32 and the memory chips 22a and 22b are protected by the sealing resin 50.

  The interposer 40 is a circuit board made of resin, and a plurality of external terminals (solder balls) SB are formed on the back surface 42 thereof. The interposer 40 functions as a rewiring board for ensuring the mechanical strength of the memory system 10 and increasing the electrode pitch. That is, the electrodes formed on the front surface 41 of the interposer 40 are drawn out to the back surface 42 by through-hole electrodes, and the pitch of the external terminals SB is expanded by the rewiring layer provided on the back surface 42.

  FIG. 2 is a schematic plan view of the memory chip 22a. The memory chip 22a in this embodiment is divided into four areas. Memory devices 12a to 12b are assigned to the respective areas. The same applies to the memory chip 22b. That is, since each of the two memory chips 22 includes four memory devices 12, the memory system 10 includes a total of eight memory devices 12. In the memory chip 22a, four channels CH0 to CH3 are allocated to the four memory devices 12a to 12d. Each channel CH is provided with an individual through electrode TSV. The memory device 12 communicates with the memory controller 32 via the assigned channel CH.

  FIG. 3 is a block diagram of a wiring structure of the memory system 10 in the first to fourth embodiments. The two memory chips 22a and 22b share the four channels CH0 to CH3. In the case of the channel CH0, the clock terminal 30a, address terminal 30b, command terminal 30c and data terminal 30d provided in the memory controller 32 are the clock terminal 20a, address terminal 20b, command terminal 20c and data terminal 30d provided in the memory chips 22a and 22b. The data terminals 20d are commonly connected to each other. The same applies to the other channels CH.

  The external clock signal CLK, the address ADD, and the command CMD output from the memory controller 32 are commonly supplied to the two memory chips 22a and 22b via the four channels CH. Read data DQ output from the memory chips 22a and 22b is input to the memory controller 32 via the four channels CH0 to CH3. The write data DQ output from the memory controller 32 is also input to the memory chips 22a and 22b via the channels CH0 to CH3. In the present embodiment, 128 data terminals are provided for each channel CH. Therefore, 512 channels (128 × 4) bits of read data and write data can be transferred simultaneously by four channels CH.

  The memory controller 32 selects the memory chips 22a and 22b according to the chip selection signal. The chip selection signal may be supplied to each of the memory chips 22a and 22b using a wiring provided individually for each of the memory chips 22a and 22b. On the other hand, when a chip selection signal is supplied to the memory chips 22a and 22b via a common wiring, a chip address is assigned to each of the memory chips 22a and 22b, and the value of the chip selection signal matches the chip address. Should be selected.

[First Embodiment]
FIG. 4 is a block diagram of main parts of the memory chips 22a and 22b and the memory controller 32 in the first embodiment. Since the circuit configuration of each memory device 12 is the same, only the configuration of the memory device 12a corresponding to the channel CH0 of the memory chip 22a is representatively shown in FIG.

  The memory device 12a includes a memory cell array 14, an access control circuit 16 that accesses the memory cell array 14, and a data output circuit 18 that outputs read data read from the memory cell array 14 to a data terminal 20d. In FIG. 4, 128 data terminals 20d are collectively represented as one data terminal 20d.

  Memory cell array 14 includes a large number of memory cells MC. The address ADD supplied from the address terminal 20 b and the command CMD supplied from the command terminal 20 c are input to the access control circuit 16. When the command CMD is a read command, the access control circuit 16 reads data from the memory cell specified by the address ADD and supplies it to the data output circuit 18. The data output circuit 18 outputs the read data to the outside based on the output enable signal EN supplied from the access control circuit 16 and the output timing signal CLKO supplied from the clock terminal 20a via the buffer 64. . The circuit configuration of the data output circuit 120 will be described later. The output timing signal CLKO in the first embodiment is a signal obtained by buffering the internal clock signal ICLK supplied from the clock terminal 20a by the buffer 64.

  The memory controller 32 supplies an address ADD, a command CMD, and an internal clock signal ICLK to each of the channels CH0 to CH3. Various circuits included in the memory device 12 operate according to the internal clock signal ICLK. The data output circuit 18 is synchronized with the output timing signal CLKO (internal clock signal ICLK). Various signals supplied to the channel CH0 are supplied in common to the two memory devices 12 on which the memory chips 22a and 22b are mounted. The same applies to the other channels CH.

  In the memory controller 32, an address generation circuit 24, a command generation circuit 26, and a clock generation circuit 28 are provided for each channel CH. The command generation circuit 26 and the address generation circuit 24 operate according to various clock signals supplied from the clock generation circuit 28. The address generation circuit 24 supplies the address ADD to the memory device 12, and the command generation circuit 26 supplies the command CMD to the memory device 12.

  The memory controller 32 further includes a timing adjustment circuit 34. The timing adjustment circuit 34 supplies the external clock signal CLK supplied from the outside to the clock generation circuit 28 of each channel CH as the internal clock signal ICLK. The timing adjustment circuit 34 in the first embodiment shifts the timing of the internal clock signal ICLK for each channel CH.

  In the timing adjustment circuit 34, the external clock signal CLK is input to the latch circuit 36. Each time the latch circuit 36 detects the rising edge of the external clock signal CLK, the latch circuit 36 inverts the internal clock signal ICLK as its output. That is, the external clock signal CLK is divided by ½ by the latch circuit 36.

  Internal clock signal ICLK is inverted by an inverter and supplied to channels CH0 to CH3 (clock generation circuits 28a to 28d). However, the internal clock signal ICLK supplied to the channels CH1 to CH3 other than the channel CH0 is delayed by the delay elements D1 to D3. Specifically, internal clock signal ICLK is delayed by delay element D1 for channel CH1, delay elements D1 and D2 for channel CH2, and delay elements D1 to D3 for channel CH3, respectively. As a result, the timings of the internal clock signals ICLK supplied to the channels CH0 to CH3 are inconsistent with each other.

  FIG. 5 is a circuit diagram of the data output circuit 18. The data output circuit 18 receives the read data Data and the output enable signal EN, generates a P-side drive signal OP1 and an N-side drive signal ON1, and a P-side drive in synchronization with the output timing signal CLKO. Latch circuits 44 and 46 that respectively latch the signal OP1 and the N-side drive signal ON1, a pull-up buffer 48 that is ON / OFF controlled by the P-side drive signal OP2 output from the latch circuit 44, and the latch circuit 46. And a pull-down buffer 52 that is on / off controlled by the N-side drive signal ON2. The pull-up buffer 48 is composed of a P-channel type MOS transistor, the source of which is connected to the higher power supply VDDQ, and the drain of which is connected to the data terminal 20d. The pull-down buffer 52 is composed of an N-channel MOS transistor, the source of which is connected to the lower power supply VSSQ, and the drain of which is connected to the data terminal 20d.

  When the output enable signal EN is inactivated to the low level, the logic circuit 38 sets the P-side drive signal OP1 to the high level and the N-side drive signal ON1 to the low level regardless of the logical value of the read data Data. To do. As a result, both the pull-up buffer 48 and the pull-down buffer 52 are turned off, and the data terminal 20d is in a high impedance state.

  When the output enable signal EN is activated to a high level, if the read data Data is at a high level, both the P-side drive signal OP1 and the N-side drive signal ON1 are at a low level, and the read data Data is at a low level. If present, both the P-side drive signal OP1 and the N-side drive signal ON1 are at a high level. When the P-side drive signal OP1 and the N-side drive signal ON1 are latched by the latch circuits 44 and 46, either the pull-up buffer 48 or the pull-down buffer 52 is turned on, so that the data terminal 20d has the same logic as the read data Data. Driven to level. The latch timing of the P-side drive signal OP1 and the N-side drive signal ON1 by the latch circuits 44 and 46 is synchronized with the output timing signal CLKO. As described above, the timing of the output timing signal CLKO is shifted for each channel CH by the delay elements D1 to D3.

  FIG. 6 is a time chart showing the relationship between the internal clock signal ICLK and the data output timing in the first embodiment. The timing at which the access control circuit 16 acquires the command CMD and the address ADD is synchronized with the internal clock signal ICLK. The timing at which the data output circuit 18 outputs the data read from the memory cell array 14 to the data terminal 20d is synchronized with the output timing signal CLKO (internal clock signal ICLK). Due to the delay elements D1 to D3, the timing of the internal clock signal ICLK supplied to the channels CH0 to CH4 is slightly shifted, so the timing at which data is output from each channel CH is also shifted. Power supply noise is generated by the operation of the pull-up buffer 48 or the pull-down buffer 52. In the first embodiment, since the output timing of the read data does not match for each channel CH, it is difficult for these noises to be superimposed.

  When the internal clock signal ICLK having the same timing is supplied for each channel CH, noise at the time of data output is also generated at the same timing. In this case, the power supply noise is superimposed in the memory system 10, resulting in a large power supply noise. When the number of memory devices 12 is large, there is a possibility of particularly large noise. When large noise occurs, there is a risk that the memory chips 22a and 22b and the memory controller 32 malfunction. By shifting the timing of the internal clock signal ICLK in advance in the memory controller 32 as in the memory system 10 of the first embodiment, noise can be dispersed and generation of large noise can be prevented.

[Second Embodiment]
FIG. 7 is a block diagram of main parts of the memory chips 22a and 22b and the memory controller 32 in the second embodiment. The second embodiment differs from the first embodiment in the configuration of the timing adjustment circuit 34, but the other points are the same. The timing adjustment circuit 34 in the second embodiment also shifts the timing of the internal clock signal ICLK for each channel CH.

  In the timing adjustment circuit 34, the external clock signal CLK is input to the latch circuit 54. The internal clock signal ICLK1 that is the output of the latch circuit 54 is inverted every time the rising edge of the external clock signal CLK is detected.

  The internal clock signal ICLK1 is supplied to the channel CH3 (clock generation circuit 28c) as it is, and is supplied to the channel CH0 (clock generation circuit 28a) after being inverted by an inverter. Channels CH0 and CH2 (memory devices 12a and 12c) are called a first group.

  The internal clock signal ICLK1 is also input to the latch circuit 56. The external clock signal CLK is also supplied to the latch circuit 56 by inverted logic. As a result, the internal clock signal ICLK2 that is the output of the latch circuit 56 is inverted every time a fall edge of the external clock signal CLK is detected.

  The internal clock signal ICLK2 is also supplied to the channel CH3 (clock generation circuit 28d) as it is, and is supplied to the channel CH1 (clock generation circuit 28b) after being inverted by an inverter. Channels CH1 and CH3 (memory devices 12b and 12d) are called a second group.

  In summary, the first group of memory devices 12 are synchronized with the rising edge of the external clock signal CLK, and the second group of memory devices 12 are synchronized with the falling edge of the external clock signal CLK. Further, in the first group, the internal clock signal ICLK1 supplied to the channel CH0 is an inverted signal of the internal clock signal ICLK1 supplied to the channel CH3. The same applies to the second group. As a result, in the channels CH0 to CH3, the internal clock signal ICLK is shifted by ¼ period.

  FIG. 8 is a time chart showing the relationship between the internal clock signal ICLK and the data output timing in the second embodiment. Since the timing of the internal clock signal ICLK supplied to the channels CH0 to CH3 is shifted by ¼ period, the timing at which data is output from each channel CH is also shifted by ¼ period.

  Since the timing of the internal clock signal ICLK supplied to the four channels CH is shifted by ¼ period, noise on the data signal line is greatly dispersed. As in the first embodiment, the delay elements D1 to D3 can be used to make 1/4 period dispersion. However, when there are four channels CH, a configuration like the timing adjustment circuit 34 of the second embodiment is also possible. In general, when n channels CH exist, noise can be most dispersed when the internal clock signal ICLK is shifted by 1 / n cycles.

[Third Embodiment]
FIG. 9 is a block diagram of main parts of the memory chips 22a and 22b and the memory controller 32 in the third embodiment. The third embodiment is different from the first and second embodiments in the configuration of the timing adjustment circuit 34, but the other points are the same. The timing adjustment circuit 34 in the third embodiment also shifts the timing of the internal clock signal ICLK for each channel CH.

  In the timing adjustment circuit 34, the external clock signal CLK is input to the latch circuit 36. The internal clock signal ICLK, which is the output of the latch circuit 36, is inverted every time the rising edge of the external clock signal CLK is detected.

  As for the internal clock signal ICLK, an inverted signal by the inverter is supplied to the channels CH0 and CH1 (clock generation circuits 28a and 28b). In addition, signals that are re-inverted by the inverter are supplied to the channels CH2 and CH3 (clock generation circuits 28c and 28d). In the third embodiment, channels CH0 and CH1 (memory devices 12a and 12b) are referred to as a first group, and channels CH2 and CH3 (memory devices 12c and 12d) are referred to as a second group.

  The internal clock signal ICLK supplied to the first group of memory devices 12 is an inverted signal of the internal clock signal ICLK supplied to the second group of memory devices 12. The internal clock signal ICLK supplied to the first group (channels CH0 and CH1) is common. The internal clock signal supplied to the second group (channels CH2 and CH3) is also common.

  FIG. 10 is a time chart showing the relationship between the internal clock signal ICLK and the data output timing in the second embodiment. Since the timing of the internal clock signal ICLK supplied to the first group (channels CH0 and CH1) and the second group (channels CH2 and CH3) is shifted by ½ period, the timing at which data is output from each group is also included. There is a 1/2 cycle shift.

  Since the internal clock signal ICLK with the same timing is supplied to the first group (channels CH0 and CH1), noise is superimposed. As a result, the noise is larger than in the first and second embodiments. The same applies to the second group (channels CH2 and CH3). However, all noises of the four channels CH0 to CH3 are not superimposed. When the superposition of about two noises is allowed, the timing adjustment circuit 34 of the third embodiment has an advantage that the circuit configuration can be simplified.

  By applying the method of the fourth embodiment described later, the internal clock signal ICLK of the channel CH0 and the internal clock signal ICLK of the channel CH1 are shifted on the memory device 12 side, or the internal clock signal ICLK of the channel CH2 and the channel CH3 The internal clock signal ICLK may be shifted.

[Fourth Embodiment]
FIG. 11 is a block diagram of main parts of the memory chips 22a and 22b and the memory controller 32 in the fourth embodiment. The timing adjustment circuit 34 in the fourth embodiment is the same as that in the third embodiment. In the fourth embodiment, a data input circuit 60 and an input timing measurement circuit 62 are added to the memory controller 32. In addition, an output timing adjustment circuit 58 is added to each memory device 12.

  The timing adjustment circuit 34 in the fourth embodiment supplies the same internal clock signal ICLK to the clock generation circuits 28a to 28d. In other words, the internal clock signal ICLK having the same timing is supplied from the memory controller 32 to each memory device 12.

  The output timing adjustment circuit 58 mounted on the memory device 12 supplies an output timing signal CLKO obtained by delaying the internal clock signal ICLK to the data output circuit 18. In other words, the timing difference between the internal clock signal ICLK and the output timing signal CLKO in the fourth embodiment is adjusted not by the memory controller 32 but by the output timing adjustment circuit 58. The amount of delay by the output timing adjustment circuit 58 differs depending on the channel CH. The amount of delay is set for each memory device 12 by the command CMD.

  The input timing measurement circuit 62 of the memory controller 32 generates an input timing signal CLKI. The data input circuit 60 latches the read data DQ read from the memory cell array 14 in synchronization with the input timing signal CLKI. The input timing measurement circuit 62 measures the timing at which the data input circuit 60 latches the read data DQ.

  Specifically, after data read is instructed by the command CMD, the input timing measurement circuit 62 continuously generates the input timing signal CLKI at a high frequency. The data input circuit 60 tries to latch the read data DQ every time the input timing signal CLKI is detected. The input timing measurement circuit 62 measures the timing when the latch is successful (the number of times the input timing signal CLKI is generated until the latch is successful). As a result, the input timing measurement circuit 62 measures the time from when the read command is supplied until the read data DQ is actually detected by the data input circuit 60.

  For example, the input timing measurement circuit 62 generates the input timing signal CLKI 30 times continuously after issuing the read command. The data input circuit 60 tries to latch the read data DQ that should be output from the data terminal 20d in response to the input timing signal CLKI 30 times. If the channel CH0 is successfully latched by the 13th and subsequent input timing signal CLKI, the data output timing of the channel CH0 is specified by the number “13”. Further details are as described in Japanese Patent Application No. 2010-145514. In general, the data output timing between channels CH may slightly shift due to variations in the manufacturing process.

  The command generation circuits 26 a to 26 d issue a setting command based on the measurement result by the input timing measurement circuit 220. The setting command is a command for causing the output timing adjustment circuit 58 to increase the delay amount by one unit. Here, one unit corresponds to one cycle of the input timing signal CLKI, but it is not necessarily the same.

  As an example, it is assumed that the data output timings of the channels CH0 to CH3 are 12, 13, 14, and 13 times. Here, for the channels CH1 to CH3, if the output timing is adjusted so as to be 13 → 16 times, 14 → 20 times, 13 → 24 times, as a result, the output timing of each channel CH is dispersed by 4 units. Will be. In the above example, the delay amount of the output timing adjustment circuit 58 is adjusted by issuing the setting command to the channel CH1 three times (13 + 3 = 16). Similarly, the number of setting commands issued to channel CH2 and channel CH3 is 6 times and 11 times, respectively.

  FIG. 12 is a circuit diagram of the data output circuit 18 and the output timing adjustment circuit 58 in the fourth embodiment. Also in the fourth embodiment, the latch timing of the P-side drive signal OP1 and the N-side drive signal ON1 by the latch circuits 44 and 46 is synchronized with the output timing signal CLKO. The output timing signal CLKO is generated when the external clock CLK input to the clock terminal 20a passes through the buffer 64 and the variable delay circuits 66 and 68. The delay amounts of the variable delay circuits 66 and 68 are controlled by the above setting command. Since one memory device 12 has 128 data terminals 20 d, the output timing signal CLKO that has passed through the variable delay circuits 66 and 68 is branched by the clock tree 70 and distributed to the respective data output circuits 18.

  FIG. 13 is a time chart showing the relationship between the internal clock signal ICLK and the data output timing in the fourth embodiment. In the fourth embodiment, the internal clock signal ICLK is supplied from the memory controller 32 to the channels CH0 to CH3 at the same timing.

  The delay amounts of the variable delay circuits 66 and 68 included in the output timing adjustment circuit 58 are adjusted for each channel CH. As a result, the timing of data output in the channels CH0 to CH3 is dispersed. In the fourth embodiment, the memory controller 32 performs delay control by a setting command, but it is not necessary to delay the internal clock signal ICLK that is actually supplied to the memory device 12.

  FIG. 14 is a flowchart of the operation of adjusting the output timing of the read data DQ. The memory controller 32 selects one channel CH from the channels CH0 to CH3 (S10). Here, it is assumed that channel CH0 is selected. The command generation circuit 26a of the memory controller 32 issues a read command to the channel CH0 (S12). At the same time, the input timing measurement circuit 62 continuously activates the input timing signal CLKI. The data input circuit 60 tries to latch the read data DQ every time the input timing signal CLKI is activated. The input timing measurement circuit 62 specifies the timing at which the latch is successful (S14).

  The memory controller 32 selects the next channel CH from the channels CH1 to CH3 (S16). Here, it is assumed that the channel CH1 is selected. The command generation circuit 26b issues a setting command for increasing the delay amount in the output timing adjustment circuit 58 of the channel CH1 (S18). The command generation circuit 26b issues a read command to the channel CH1 (S20), and the input timing measurement circuit 62 measures the timing at which the data input circuit 60 latches the read data DQ (S22). If the output timing difference Td between the channel CH0 and the channel CH1 is larger than the predetermined threshold Th (Y in S24), in other words, if the output timing is sufficiently shifted, the process proceeds to S26. If Td is equal to or less than Th (N in S24), a setting command is issued to further increase the delay amount by one unit (S18). By repeating such processing, the output timings of channel CH0 and channel CH1 are dispersed.

  After sufficiently shifting the timing (Y in S24), if there remains a channel CH to be adjusted, the process proceeds to S16, and the next channel CH is selected (S16). Here, channel CH2 is selected after channel CH1, and the output timing of the data of channel CH1 and channel CH2 is distributed. Similarly, the output timing of the data of channel CH2 and channel CH3 is also distributed. When the output timing of channel CH3 is determined (Y in S26), the process ends.

  FIG. 15 is a main block diagram of the memory chips 22a and 22b and the memory controller 32 according to Modification 1 of the fourth embodiment. In the first modification, the delay amount of the variable delay circuit 66 and the like to be determined based on the measurement result of the input timing measurement circuit 62 is set at the time of shipment from the factory. Such a specific delay amount may be stored in the command generation circuit 26a or the like. In this case, the command generation circuit 26 may read the delay amount at power-on and set it in each output timing adjustment circuit 58. The data output timing of each data output circuit 18 may be measured by an external measuring device at the time of factory shipment, and an appropriate delay amount based on the measurement result may be registered in the command generation circuit 26. Note that the delay amount may be set in advance in the variable delay circuit 66 included in the output timing adjustment circuit 58.

  FIG. 16 is a main block diagram of the memory chips 22a and 22b and the memory controller 32 according to Modification 2 of the fourth embodiment. In the second modification, the clock generation circuit 28, the command generation circuit 26, and the address generation circuit 24 are unified for all channels CH. In the fourth embodiment, since it is not necessary to shift the timing of the internal clock signal ICLK for each channel CH in the memory controller 32, such a configuration is possible.

[Fifth Embodiment]
FIG. 17 is a block diagram of main parts of the memory device and the memory controller in the fifth embodiment. In the fifth embodiment, one memory chip 22 corresponds to one channel CH. In other words, this is a type in which one memory device 12 is mounted on one memory chip 22. Others are the same as in the second embodiment. The same applies to the point that a plurality of memory devices 12 are commonly connected to one memory controller 32. All or part of the memory chips 22a to 22d may be stacked as shown in FIG. FIG. 17 shows a configuration in which one memory chip 22 corresponds to one channel CH based on the second embodiment, but one channel CH based on the first, third to fourth embodiments. Alternatively, one memory chip 22 may correspond to each other.

  The present invention has been described based on some embodiments. Those skilled in the art will understand that these embodiments are examples, and that various modifications and changes are possible within the scope of the claims of the present invention, and that such modifications and changes are also within the scope of the claims of the present invention. It is where it is done. Accordingly, the description and drawings herein are to be regarded as illustrative rather than restrictive.

  10 memory system, 12 memory device, 14 memory cell array, 16 access control circuit, 18 data output circuit, 22 memory chip, 24 address generation circuit, 26 command generation circuit, 28 clock generation circuit, 32 memory controller, 34 timing adjustment circuit, 36 latch circuit, 38 logic circuit, 40 interposer, 44 latch circuit, 46 latch circuit, 48 pull-up buffer, 50 sealing resin, 52 pull-down buffer, 54 latch circuit, 56 latch circuit, 58 output timing adjustment circuit, 60 data input Circuit, 62 input timing measurement circuit, 64 buffer, 66 variable delay circuit, 68 variable delay circuit, 70 clock tree, TSV through electrode, CH channel, ADD address, CMD command, CL K external clock signal, ICLK internal clock signal, CLKO output timing signal, CLKI input timing signal, EN output enable signal, D1-D3 delay elements.

Claims (17)

A memory controller;
First and second memory devices each operating based on a command issued from the memory controller,
The first and second memory devices are:
A memory cell array;
A data output circuit for outputting data read from the memory cell array to the memory controller,
The memory system, wherein the first and second memory devices are adjusted to output the data at different output timings.   The memory system according to claim 1, wherein the memory controller further includes a timing adjustment circuit that varies the output timing of each of the first and second memory devices. The memory device further includes an output timing adjustment circuit for adjusting the output timing,
2. The memory system according to claim 1, wherein the first and second memory devices output the data at the output timings different from each other according to settings of the output timing adjustment circuits.   The timing adjustment circuit of the memory controller receives an external clock signal, generates first and second clock signals having different phases according to the external clock signal, and the first memory device has the first clock 3. The data according to claim 2, wherein the data is output at the output timing according to a signal, and the second memory device outputs the data at the output timing according to the second clock signal. Memory system.   The timing adjustment circuit of the memory controller generates the first and second clock signals from the external clock signal by first and second delay elements corresponding to the first and second delay times. The memory system according to claim 4. A plurality of third memory devices each operating based on the command issued from the memory controller;
The third memory device is
A memory cell array and a data output circuit for outputting data read from the memory cell array to the memory controller;
The memory controller generates a plurality of clock signals having different phases by (1 / the total number of the first and second memory devices and the plurality of third memory devices),
Each of the first, second memory device, and the plurality of third memory devices outputs the data at the output timing corresponding to one clock signal of the plurality of clock signals. The memory system according to claim 1, wherein: Further comprising third and fourth memory devices, each of which operates based on the command issued from the memory controller;
The third and fourth memory devices are:
A memory cell array and a data output circuit for outputting data read from the memory cell array to the memory controller;
The memory controller receives an external clock signal and generates a first clock signal corresponding to a rising edge of the external clock signal and a second clock signal corresponding to a fall edge of the external clock signal;
The first and third memory devices output the data in response to the first clock signal;
The memory system according to claim 1, wherein the second and fourth memory devices output the data according to the second clock signal. The memory controller generates first and third internal clock signals having different phases according to the first clock signal, and second and second phases having different phases according to the second clock signal. 4 internal clock signals,
8. The memory system according to claim 7, wherein each of the first to fourth memory devices outputs the data according to the first to fourth internal clock signals.   The first internal clock signal and the third internal clock signal are in an anti-phase relationship with each other, and the second internal clock signal and the fourth internal clock signal are in an anti-phase relationship with each other. The memory system according to claim 8.   The memory controller includes an input timing measurement circuit that measures the timing at which the data is input, and based on the measurement result of the input timing measurement circuit, the output timing adjustment circuit of the first and second memory devices. 4. The memory system according to claim 3, wherein a setting is adjusted, and the output timing at which the first and second memory devices output the data is adjusted.   4. The memory system according to claim 3, wherein each of the first and second memory devices stores a unique delay time and adjusts a setting of the output timing adjustment circuit according to the delay time.   2. The memory system according to claim 1, wherein the memory controller and the first and second memory devices are packaged on one interposer.   2. The memory system according to claim 1, wherein the first and second memory devices are stacked on each other.   2. The memory system according to claim 1, wherein the memory controller and the first and second memory devices are stacked on each other.   15. The data terminal provided in the plurality of memory devices and the data terminal provided in the memory controller are connected to each other through through electrodes penetrating the plurality of memory devices. The described memory system.   2. The memory system according to claim 1, wherein the first and second memory devices are formed on a single semiconductor chip.   The memory system according to claim 1, wherein the first and second memory devices are formed on different semiconductor chips.

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