JP2012230378A - Phase-shift mask with assist phase region - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the distortion of shape at the perimeter of an exposure field.SOLUTION: A phase-shift mask has a checkerboard array and a sub-resolution assist phase pattern surrounding the checkerboard array. The checkerboard array comprises alternating phase-shift regions R that have a relative phase difference of 180 degrees. Sub-resolution assist phase regions R' reside adjacent to the corresponding phase-shift regions R and have a relative phase difference of 180 degrees thereto. The sub-resolution assist phase regions R' are formed to mitigate undesirable edge effects in photolithographically photoresist processing.

Description

  This application is a continuation-in-part of US patent application (No. 12 / 928,862) “LED manufacturing by photolithography using a phase shift mask” filed on Dec. 21, 2010. The above US application is included herein.

  The present invention relates generally to phase shift masks used in photolithography, and in particular to phase shift masks having assist phase regions.

  Phase shift masks are used in various photolithography techniques for manufacturing semiconductor integrated circuits and light emitting diodes (LEDs). A phase shift mask has a relative phase difference compared to a mask method in which chromium is deposited on a quartz glass plate, and the transparent region of the phase shift mask is on a conventional quartz glass plate. It is different from the mask method to attach chrome. An advantage of having a selected phase difference in the transparent region in the phase shift mask is that the transparent region can be configured with an electric field amplitude added so that the image intensity (contrast) becomes sharper. As a result, the resolution of the image in the photoresist can be improved.

US Pat. No. 6,455,877 US Pat. No. 7,259,399 US Pat. No. 7,436,001

  As an example of a phase shift mask, a periodic pattern of alternating phase shift regions, ie, 0 degree and 180 degree (π) phase regions can be included. Such a phase shift mask is useful for improving the resolution of the alternating pattern. However, the improved image contrast ends at the edge of the lithography exposure field. This is because the alternating pattern ends. As a result, the feature pattern formed adjacent to the edge of the exposure field is easily distorted due to discontinuity due to phase interference. This problem has been addressed in the past by configuring a phase shift mask and exposure field that ensures that distorted parts that are not ultimately used to form the actual device are printed in areas on the wafer. It was. However, not all production applications have such flexibility. For this reason, the conventional alternating phase shift mask cannot be used.

  One example of a production application where the distorted shape at the edge of the exposure field can be problematic is LED manufacturing. LEDs are increasingly becoming more efficient due to constant improvements in LED manufacturing and LED design. However, a general limitation on the luminous efficiency of an LED is due to total internal reflection of light emitted within the LED. For example, in the case of an LED based on gallium nitride (GaN), the n-type doped layer and the p-type doped layer are formed on the surface of a semiconductor substrate (eg, sapphire). These n-type and p-type GaN layers sandwich the active layer. The surface of one GaN layer is in contact with air. The light generated in this active layer is emitted uniformly in all directions. However, gallium nitride has a relatively high refractive index (refractive index = about 3). As a result, there is a maximum incident angle cone (exit cone) on the contact surface between gallium nitride and air. Light emitted from the p-GaN-air interface is emitted within this maximum incident angle cone. However, Snell's law is obeyed outside the part where the reflected light returns to the GaN structure.

  In order to improve the luminous efficiency of LEDs, certain types of LEDs are formed on a roughened substrate surface. The rough substrate surface scatters the light reflected from the inner surface and guides part of the light into the exit cone to emit light from the LED. Thereby, the luminous efficiency of LED can be improved.

  During manufacture, a method of manufacturing a substrate with a roughened surface that is easy to operate and consistent is desirable to obtain LEDs of the same structure and performance. In order to achieve this object, it is desirable to form a substrate having a rough surface by a method other than the characteristic pattern distortion method described above.

  One aspect of the present invention is a phase shift mask used in a photolithographic projection system having a resolution limit. This phase shift mask has a checkerboard array of phase shift regions R having a size equal to or larger than the resolution limit. Adjacent phase shift regions R have a relative phase difference of 180 degrees. The array also has a peripheral edge. This phase shift mask further has a plurality of assist phase regions R ′. The assist phase region R ′ is disposed so as to be adjacent to at least a part of the peripheral edge. The size of each assist phase region R ′ is smaller than the resolution limit, and has a relative phase shift difference of 180 degrees between adjacent phase shift regions R.

  In this phase shift mask, the peripheral edge preferably has four sides. The phase shift regions are preferably arranged so as to be adjacent to each other through four sides.

  This phase shift mask preferably has four corners defined by the four sides. The assist phase regions R ′ are adjacent to each other through four corners.

  In this phase shift mask, the assist phase region R 'is preferably arranged so as to be adjacent to the entire periphery of the checkerboard array.

  This phase shift mask preferably further comprises an opaque layer adjacent to the periphery defined by the assist phase region R '.

  Another aspect of the present invention is a phase shift mask used in a photolithographic projection system having a resolution limit and a wavelength. The phase shift mask has a mask body. The mask body has a surface, and the mask body is typically transparent for photolithographic projection system wavelengths. This phase shift mask has a checkerboard array of phase shift regions R supported on the surface of the mask body and formed to have a size equal to or larger than the resolution limit. Adjacent regions R have a phase difference of 180 degrees. The checkerboard array has a peripheral edge, and the peripheral edge includes a plurality of edges and four corners. The phase shift mask further includes a plurality of assist phase regions R ′ held on the surface of the substrate. Each assist phase region R 'is smaller than the resolution limit. The assist phase region R ′ is disposed adjacent to a plurality of sides and four corners and surrounds the periphery. In addition, each assist phase region R ′ has a phase shift difference of 180 degrees between the adjacent phase shift region R and the adjacent assist phase region R ′.

  The phase shift mask preferably includes an opaque layer adjacent to the periphery defined by the assist phase region R ′.

  Another aspect of the present invention is a photolithography patterning method for a semiconductor substrate. The method includes providing a semiconductor substrate having a surface that supports a layer of photoresist. The method also includes the step of photolithographic projection of the phase shift mask pattern onto the layer of photoresist. This phase shift mask pattern has a checkerboard array composed of phase shift regions R. The phase shift region R is adjacent to another phase shift region R having a phase difference of 180 degrees. The checkerboard array has a peripheral edge. Further, each of the plurality of assist phase regions R ′ is formed smaller than the resolution limit. These assist phase regions R ′ are disposed so as to be adjacent to at least a part of the peripheral edge. Each assist phase region R ′ has a phase shift difference of 180 degrees with the adjacent phase shift region R. The method further includes processing the photoresist to form a periodic array of photoresist.

  The method preferably includes a photoresist processing procedure to form an array of substrate pins defining a roughened substrate surface. The method preferably further includes the step of forming a pn junction multilayer structure on the roughened substrate surface.

  In this method, the semiconductor substrate is preferably made of sapphire.

  In this method, the nominal wavelength of the photolithographic projection is 365 nm, which is unit magnification.

  In this method, the dimension of the substrate pin is preferably 1 micron or less. Further, in this method, it is preferable that the photolithography projection is performed with a numerical aperture of 0.5 or less.

  In this method, it is preferable that the phase shift mask further includes an opaque layer adjacent to the periphery defined by the assist phase region R ′.

  In this method, the photolithographic projection includes a step of stitching a plurality of exposure fields together to form a substantially continuous array of photoresist pins in a photoresist layer that covers substantially the entire substrate. It is preferable to provide.

  Another aspect of the present invention is a method for manufacturing an LED. The method includes photolithography exposure of a photoresist supported on a semiconductor substrate to form an array of photoresist pins in the photoresist, and a peripheral edge surrounded by an array of sub-resolution assist phase regions. And passing the illumination light through a phase shift mask having a checkerboard phase shift pattern. The method also includes processing the array of photoresist pins to form an array of substrate pins defining a roughened substrate surface. In addition, the method includes forming a pn multilayer structure on the roughened substrate surface to manufacture the LED. The roughened substrate surface scatters the light generated in the pn multilayer structure to increase the amount of light emitted by the LED compared to a conventional LED that does not have a roughened substrate surface. It has become.

  In this method, it is preferable that the phase shift mask further includes an opaque layer adjacent to a peripheral edge defined by the sub-resolution assist phase region.

  In this method, the photolithographic exposure of the photoresist is preferably performed with a numerical aperture of 0.5 or less.

  In this method, the photolithographic exposure of the photoresist is preferably performed at a nominal wavelength of 365 nm and unit magnification.

  In this method, the photolithographic exposure of the photoresist preferably includes the step of forming a substantially continuous array of photoresist pins covering substantially the entire substrate by joining a plurality of exposure fields.

  In this method, it is preferable that the method further includes a step of overlapping a part of the plurality of exposure fields corresponding to the assist phase region in the phase shift mask.

  Additional features and advantages of the invention will be set forth in the detailed description that follows and will be apparent to those skilled in the art from the description, and include the contents of the specification, ie, the detailed description and claims that follow. It can be easily conceived from the scope and the attached drawings. The claims form part of this specification and are included in the detailed description.

  The general description given so far and the detailed description that follows are intended to provide an overview or framework for understanding the nature and features of the invention as claimed. The accompanying drawings are provided for a further understanding of the invention and are incorporated in and constitute a part of this specification. These drawings illustrate various embodiments of the present invention. These drawings are provided together with the present specification to explain the principle and operation of the present invention.

1 is a schematic cross-sectional view showing an example of a gallium nitride based LED having a roughened substrate surface defined by an array of pins. FIG. A graph showing the relationship between the measurement increase rate (%) of the amount of light from the LED and the dimension (micron) of the pin in the LED having a uniform array of pins defined on the rough sapphire substrate surface shown in FIG. It is. FIG. 6 is a perspective view showing a portion of a uniform array of pins. FIG. 5 is an enlarged perspective view showing four adjacent pins in an array of pins. An interval S between adjacent pins, a pin diameter D, and a pin height H are shown. 1 is a schematic diagram of a photolithographic system used to carry out photolithographic projections and the overall method according to the invention. FIG. 6 is a more detailed view of the example photolithography system shown in FIG. Along with the exposure field, including inset A showing the exposure field, inset B showing the LED area in the exposure field, and inset C showing the array of photoresist pins formed in the LED area, as well as the exposure field. It is a top view of the example of the board | substrate which has an alignment mark. A part of phase shift mask (an example) in which a mask pattern having a region R including a 0-degree phase-shifting light-transmitting region _R0 and a 180-degree (π) phase-shifting light-transmitting region _Rπ is formed is shown. FIG. FIG. 8B is an enlarged view showing four regions R in the phase shift mask shown in FIG. 8A. FIG. 4 is a schematic diagram illustrating another example of a phase shift mask that can be used to form an array of submicron pins. The individual phase shift regions are separated from each other and are formed in a polygonal shape. FIG. 9B is similar to FIG. 9A, but the phase shift region is circular. It is an electron microscope scanning image which shows the example of the array of the columnar material formed as a photoresist pin which has a thickness of 3 microns. A phase shift mask with regions R ₀ , R _π , and L / 2 = 0.6, similar to that shown in FIG. 8A, is used. FIG. 8B is an overall view showing an example of a chromeless phase shift mask having the checkerboard array shown in FIG. 8A. It also has a sub-resolution assist phase region. FIG. 11B is an enlarged view showing an example of a region shown as “AA” in FIG. 11A, which is a part of a phase mask pattern including a configuration example of a main checkerboard phase shift pattern and a corresponding assist phase region. FIG. 11C is similar to FIG. 11B, but the assist phase region configuration further includes a corner assist phase region. FIG. 5 is a schematic diagram illustrating an example of an array of photoresist pins formed by a checkerboard pattern / phase shift mask that does not include a sub-resolution assist phase region. This figure shows how the peripheral pin is distorted as compared with the inner (center side) pin. FIG. 12B is similar to FIG. 12A, but the checkerboard pattern / phase shift mask includes a sub-resolution assist phase region and how the peripheral photoresist pins are substantially the same as the inner pins. Is shown. FIG. 2 is a cross-sectional view showing a two-dimensional model of an array of photoresist pins formed on a (positive) photoresist layer based on data generated using photolithography modeling software. This figure shows the beneficial effect of the sub-resolution assist phase region. It is sectional drawing which shows the example of the board | substrate with which the process which forms the array of a pin in the board | substrate surface using the photolithographic projection with a phase shift mask and photolithographic processing technique in the LED manufacturing method which concerns on this invention was performed. It is sectional drawing which shows the example of the board | substrate with which the process which forms the array of a pin in the board | substrate surface using the photolithographic projection with a phase shift mask and photolithographic processing technique in the LED manufacturing method which concerns on this invention was performed. It is sectional drawing which shows the example of the board | substrate with which the process which forms the array of a pin in the board | substrate surface using the photolithographic projection with a phase shift mask and photolithographic processing technique in the LED manufacturing method which concerns on this invention was performed. It is sectional drawing which shows the example of the board | substrate with which the process which forms the array of a pin in the board | substrate surface using the photolithographic projection with a phase shift mask and photolithographic processing technique in the LED manufacturing method which concerns on this invention was performed. It is sectional drawing which shows the example of the board | substrate with which the process which forms the array of a pin in the board | substrate surface using the photolithographic projection with a phase shift mask and photolithographic processing technique in the LED manufacturing method which concerns on this invention was performed.

  Reference will now be made in detail to embodiments of the present invention as illustrated in the accompanying drawings. Wherever possible, the same or similar reference numbers / reference symbols will be used for the same or similar parts throughout the drawings. The drawings are not necessarily to scale. Those skilled in the art will also appreciate that the drawings are simplified to illustrate features of the present invention. For example, with respect to phase shift masks, such masks may include thousands of phase regions, but in some drawings, a limited number of phase regions are shown for purposes of illustration.

  The characteristics of the phase shift mask having the assist phase region according to the present invention will be described in relation to the structure of the LED with reference to the drawings. Thus, information regarding the structure and manufacture of LEDs using photolithography is described as follows.

(Example of LED structure)
FIG. 1 is a cross-sectional view illustrating an example of a gallium nitride based LED 10. Examples of gallium nitride based LEDs are disclosed in US Pat. Nos. 6,455,877, 7,259,399, and 7,436,001. The contents of these patents are incorporated herein. The present invention is not limited to gallium nitride based LEDs, but benefits from increased light emission on a roughened substrate surface formed by an array of pins as described herein. It can be applied to all kinds of LEDs formed using photolithographic projection and processing techniques.

  The LED 10 has a substrate 20 with a surface 22. Examples of the material of the substrate 20 include sapphire, silicon carbide (SiC), gallium nitride (GaN), silicon (Si), and the like. Nitride gallium nitride layer “n-GaN layer” 40 and n-type doped gallium nitride layer “p-GaN layer” 50 having a surface 52 and p-type doping on substrate 20. A gallium multilayer structure 30 is provided. The active layer 60 is sandwiched between an n-GaN layer 40 provided adjacent to the substrate 20 and the p-GaN layer 50. In other gallium-based LED embodiments, the gallium nitride multilayer structure 30 is inverted so that the p-GaN layer 50 is adjacent to the substrate 20. The active layer 60 can include, for example, a multiple quantum well (MQW) structure such as an undoped GaInN / GaN superlattice. Thus, the GaN multilayer structure 30 defines a pn junction and is more common as a pn coupled multilayer structure. For example, the surface 52 may be roughened to increase the amount of light emitted from the LED.

The surface 22 of the substrate 20 is provided with an array 70 of pins 72 that defines the roughness of the surface 22. More specifically, an array 70 of pins 72 is etched on the surface 22 of the substrate 20, and the pins 72 are formed of the material of the substrate. In order to improve the light emission efficiency from the LED, the pin 72 preferably has a size (for example, diameter or width D) that is 2 to 10 times larger than the wavelength λ _LED emitted from the LED. If the wavelength λ _LED is, for example, 400 to 700 nm, it should be noted that the LED wavelength in the GaN layers 40 and 50 is approximately 1/2. This is because the refractive index n of GaN makes the wavelength in the GaN layers 40 and 50 about 150 nm to 250 nm (ie, λ _LED / n). In some embodiments, in order to scatter light efficiently within the n-GaN layer 40, the dimension D of the pin 72 is from about 0.5 microns to about 3 microns. Furthermore, the spacing S between adjacent pins 72 described above can be adjusted between 0.5 microns and 3 microns. Also, the height H of the pin 72 can be adjusted between up to about 3 microns (see FIGS. 3 and 4).

  FIG. 1 shows an LED 10 having an inclined portion 80 formed in a GaN multilayer structure 30. The inclined portion 80 constitutes an exposed surface portion 42 of the n-GaN layer 40 that serves as a shelf portion that supports one of the two electrical contacts 90 (that is, the n-contact 90n). Examples of n-contact materials include titanium / gold, nickel / gold, titanium / aluminum, or a combination thereof. The other electrical contact 90 is a p-contact 90 p and is disposed on the surface 52 of the p-GaN layer 50. Examples of the material of the p-contact are nickel / gold and chrome / gold. An example of the distance d1 is about 4 microns, and an example of the distance d2 is about 1.4 microns. A typical example of the LED 10 is a 1 mm × 1 mm square.

(Improvement of LED luminous efficiency)
FIG. 2 shows the measured increase rate (%) of the amount of light from the LED and the dimensions of the pin in the LED 10 (microns) having the uniform array 70 of pins 72 defining the surface 22 of the roughened sapphire substrate 20 shown in FIG. ). FIG. 3 is a perspective view showing a portion of a uniform array 70 of pins 72. FIG. 4 is an enlarged perspective view showing four adjacent pins 72 in the array 70 of pins 72. An interval S between adjacent pins 72, a diameter D of the pins 72, and a height H of the pins 72 are shown. The amount of light emitted from the LED having the unscratched sapphire surface 22 is shown at the “zero (0)” position, and the increase in LED light emission is measured in relation to the reference value (0%). Regarding the pin dimensions in this graph, when the height is increased or decreased, the pin moves to the right of the “zero (0)” position, that is, the “no roughening” position.

  According to the graph of FIG. 2, it can be seen that the LED emission amount increases as the pin 72 becomes higher and thinner. In a uniform array 70, overlay requirements are not critical and a few defects are not particularly problematic. However, the size of the pin 72 is important in that it affects the reproducibility and consistency of the mass production process when the pin 72 is formed. Any appropriate cross-sectional shape can be applied to the pin 72, and it may be a cylindrical shape as shown. The pin 72 does not have to be cylindrical (that is, it may have an inclined or non-straight side surface), a rectangular or square cross-sectional shape, a kidney bean shape, or the like. May be. FIG. 14E shows, for example, a pyramidal pin 72. In some embodiments, the photoresist pin 72 ′ may be cylindrical, but the corresponding pin 72 substantially formed on the surface 22 of the substrate 20 is the substrate pin 72 ′ by the photoresist pin 72 ′. It is not formed into a cylindrical shape because of the process used to form the film.

  In general, a pin 72 formed with a resolution limit of a photolithographic projection process (described later) used to form the pin 72 and dimensions in the vicinity thereof has a round shape instead of a square shape. Therefore, the diameter or width D of the pin 72 is handled as a representative dimension or effective dimension in the cross-sectional dimension of the pin 72. The cross-sectional shape is not particularly limited. For example, when the pin has an elliptical cross-sectional shape, the diameter D of the pin may be the major axis dimension of the ellipse.

  As described above, the pin 72 can have a diameter D of sub-micron (eg, D = 0.5 microns). Forming such pins 72 with current photolithographic techniques will generally require a photolithographic system having an imaging capability of 0.5 microns. However, such photolithographic systems are generally designed to form the limiting layer (ie, the smallest dimension layer) in conventional semiconductor integrated circuit manufacturing and are severely used for LED manufacturing. It is considered expensive.

  The present invention includes a photolithographic system and method for forming an array 70 of pins 72 on the surface 22 of the substrate 20 in order to produce an LED 10 with higher LED emission efficiency than an LED having a smooth surface substrate. It is. However, the photolithographic system and method described herein is suitable for implementation using a non-limit layer photolithographic system in combination with a selected type of phase shift mask. This phase shift mask is compatible with the numerical aperture and illumination (ie, “sigma”) of the photolithographic system to form the pins 72 to the desired dimensions. By using the photolithographic system, smaller pins 72 can be printed with an appropriate depth of focus (DOF) as compared to the case of using a conventional chrome glass (non-phase shift mask).

(Photolithographic projection)
It is well known that a lattice-like structure can be created in a photoresist by using two coherent rays that intersect. Under normal conditions, the two coherent rays of incident angle θ and wavelength λ interfere with each other to produce a periodic lattice-like structure in the photoresist. The period P is given by P = λ / (2 × Sinθ). By superimposing four coherent rays, that is, two rays in the x direction and two rays in the y direction, a two-dimensional lattice (checkerboard) pattern can be generated on the xy plane.

  FIG. 5 is a diagram showing an abstracted photolithography system 100, and FIG. 6 is a diagram showing an example of the photolithography system 100 in detail. Cartesian XYZ coordinates are shown. The photolithographic system 100 is configured to be able to perform photolithographic projection. Photolithographic projection is also referred to as “photolithographic exposure”. This is because the projection is nothing but exposure of the photosensitive material, that is, the photoresist. Photolithographic projection or photolithographic exposure generally captures light that has passed through a mask and performs projection with the captured light within the DOF on the image plane. In order to record the image, the photosensitive material is disposed within the DOF.

  As shown in FIGS. 5 and 6, the photolithographic system 100 includes an illumination 106, a mask stage 110, a projection lens 120, and a movable substrate stage 130 along the system axis A1. The mask stage 110 supports a phase shift mask 112 that transmits light having an irradiation wavelength used in the photolithographic system 100. The phase shift mask 112 includes a mask body 111 having a surface 114 and supports a phase shift mask pattern 115 formed on the surface 114.

  The amount of phase shift determined by the thickness d and refractive index n of the material of the layer is given by Δφ = 2π × (n−1) × d / λ. λ is the wavelength of the photolithographic projection. As an example of the material of the phase shift mask 112, quartz or quartz glass can be given. In this example, the phase shift mask pattern 115 is formed by selective etching, selective addition of phase shift mask material, or a combination thereof that creates regions of different thickness on the surface 114 of the phase shift mask 112. Has been.

  The movable substrate stage 130 supports the substrate 20. The substrate 20 may be a wafer. In this example, the photolithographic system 100 is a 1: 1 system (ie, unit magnification) with a numerical aperture of 0.3 and operates at a mid-ultraviolet wavelength such as i-line (usually 365 nm). In other embodiments, a reduced photolithographic system can be used. In some embodiments, the photolithographic system 100 is suitable for non-limit layer manufacturing processes in semiconductor manufacturing processes. A suitable photolithographic system 100 for implementing the photolithographic system and method disclosed herein is a sapphire 100 photolithographic system available from Ultratech, Inc., San Jose, California.

  The embodiment of the projection lens 120 has various aperture stops AS that define the diameter DP of the pupil P and the pupil plane PP. The illumination 106 is configured to illuminate the phase shift mask 112 by preparing a source image SI that occupies a part of the pupil P. In one embodiment, the source image SI is a uniform circular disc having a diameter DSI. The partial coherence factor of the photolithographic system 100 is defined by σ = DSI / DP. The pupil P is considered to be circular. In the case of a source image SI different from a simple uniform circular disk, the definition of the partial coherence factor σ is more complicated. In one embodiment, the illumination of the phase shift mask 112 is Koehler illumination or a modification thereof.

  The photolithographic system 100 further includes an optical positioning system 150. As shown, the optical positioning system 150 is a positioning system through a lens, and may use a mechanical field positioning system. Examples of optical positioning systems are disclosed in US Pat. Nos. 5,402,205, 5,621,813, and 6,898,306, US application Ser. No. 12 / 592,735. These patents and applications are incorporated herein.

  FIG. 7 is a plan view showing an example of the substrate 20 having the exposure field EF formed by the photolithographic system 100. The substrate 20 further includes an overall positioning mark 136G used for overall positioning, and a detailed positioning mark 136F used for detailed positioning (see inset A). In this embodiment, both types of positioning marks 136 are present in the exposure field scribing area 137 between or adjacent to the exposure fields EF. The exposure field EF will be described later in more detail in relation to the configuration when the phase shift mask 112 is used in the photolithography process for manufacturing the LED 10.

Figure 6 is disposed along the axis A2, of an optical positioning system 150 having a light source 152 for emitting alignment light 153 having a wavelength lambda _A is shown. The beam splitter 154 is disposed at the intersection of the axis A2 and the axis A3 orthogonal thereto. The lens 156 and the fold mirror 158 are disposed along the axis A3. The fold mirror 158 bends the axis A3 to be an axis A4 parallel to the system axis A1. The axis A4 passes through the mask 112 and the projection lens 120 and reaches the substrate 20. The optical positioning system 150 further includes an image sensor 160 disposed along an axis A3 proximate to the beam splitter 154 opposite the lens 156 and fold mirror 158. The image sensor 160 is electrically connected to an image processing unit 164 configured to process a digital image captured by the image sensor 160. The image processing unit 164 is electrically connected to the display unit 170 and the movable substrate stage 130.

  In general operation of the photolithographic system 100, the light 108 from the illumination 106 irradiates the phase shift mask 112 and the phase shift mask pattern 115 on the phase shift mask 112. The phase shift mask pattern 115 is projected onto the surface 22 of the substrate 20 beyond the selective exposure field EF (FIG. 7) by the exposure 121 from the projection lens 120. The positioning pattern 115W forms a substrate positioning reference mark 136. The surface 22 of the substrate 20 is generally coated with a photosensitive material such as a photoresist layer 135 (FIG. 5), and the phase shift mask pattern 115 is recorded and projected onto the substrate 20.

  The photolithographic system 100 is used to combine a photolithographic projection (photolithographic exposure) with photolithographic processing technology to form a relatively large number (eg, thousands) of LEDs 10 on a single substrate 20. . The plurality of layers in which the LED 10 is formed are formed by, for example, step and repeat, step and scan, or a combination thereof. Therefore, prior to projecting the phase shift mask pattern 115 onto the photoresist layer 135 to form the array 70 of exposure fields EF, the phase shift mask pattern 115 is more specifically a layer formed in advance. Should be properly positioned in the pre-formed exposure field EF. This is accomplished by positioning the substrate 20 with respect to the phase shift mask 112 using one or more of the aforementioned substrate positioning reference marks 136 and positioning references. In the optical positioning system 150, the positioning reference is one or more mask positioning reference marks 116.

  Accordingly, in the operation of the optical positioning system 150, the positioning light 153 from the light source 152 travels along the axis A2, and after being reflected by the beam splitter 154, travels toward the lens 156 along the axis A3. The positioning light 153 passes through the lens 156, is reflected by the fold mirror 158, passes through the phase shift mask 112 and the projection lens 120, and further, part of the surface 22 of the substrate 20 including the substrate positioning reference mark 136. Irradiate. A part 153R of the positioning light 153 is reflected by the surface 22 of the substrate 20 and the substrate positioning reference mark 136, and travels backward through the projection lens 120 and the phase shift mask 112. In particular, the reflected positioning light 153 passes through the mask positioning reference mark 116. When the substrate positioning reference mark 136 has diffractive properties, the diffracted light 153S from the substrate positioning reference mark 136 is collected.

  By the combination of the projection lens 120 and the lens 156, the reflected light 153R forms an image on the image sensor 160 in which the substrate positioning reference mark 136 and the mask positioning reference mark 116 are superimposed. Here, the mask positioning reference mark 116 serves as a reference for positioning. The positioning reference in another type of optical positioning system, such as an off-axis system, is the optical axis of the optical positioning system adjusted based on the origin of the lithographic system.

  The image sensor 160 generates an electrical signal S 1 representing the captured digital image and sends it to the image processing unit 164. The image processing unit 164 is optimized so that it can process the received digital image. For example, it is conceivable to use image processing software stored in a computer readable medium such as the memory unit 165. In particular, the image processing unit 164 measures the relative displacement between the superimposed substrate and mask positioning reference mark images, recognizes these patterns, and further transmits a corresponding stage control signal S2 transmitted to the movable substrate stage 130. Optimized to produce The image processing unit 164 further sends an image signal S3 to the display unit 170 that displays a superimposed image of the substrate and the mask positioning reference mark.

  In response to the stage control signal S2, the movable substrate stage 130 remains on the XY plane until the images of the mask positioning reference mark 116 and the substrate positioning reference mark 136 are positioned (that is, completely overlapped) ( If necessary, the Z-plane may be added to the XY plane for focus adjustment processing), and the phase shift mask 112 and the substrate 20 are correctly positioned.

  Referring again to FIG. 5, the projection of the phase shift mask pattern 115 includes a diffraction process in which light 108 incident on the phase shift mask 112 is diffracted by the phase shift mask pattern 115 to form a (diffracted) exposure 121. Can be considered. As a result of this diffraction process, the (diffracted) exposure 121 (ie, the lowest diffraction order [zero order or plus or minus first order]) is captured by the projection lens 120 and projected onto the surface of the photoresist layer 135. . The quality of the image formed by the projection lens 120 is directly related to the aberration of the projection lens 120, as is the number of diffraction orders. Zero-order diffracted rays are linear components that contribute to the “DC” background intensity of image brightness, and as such are generally not desirable.

  Thus, if the photolithographic projection process is considered a diffraction process, the photolithographic system 100 may be configured to optimize the diffraction process to form a desired image. In particular, by appropriately designing the phase shift mask 112 and the phase shift region R in the mask, zero-order diffracted rays can be eliminated. Furthermore, by properly selecting the aperture size of the aperture stop AS in the projection lens 120, it is possible to select the diffraction orders that contribute to the photolithographic projection process. Specifically, the size of the aperture stop AS can be adjusted by taking only two first-order diffracted light beams by the projection lens 120.

  More specifically, a two-dimensional periodic phase shift mask pattern 115 is formed on the phase shift mask so that the first-order diffracted light is generated in both the X-direction and the Y-direction. The lattice or checkerboard pattern described above can be formed. However, it should be noted that the zero order light is substantially removed and the electric field magnitude of the transmitted zero order light is substantially zero. This can be achieved by one embodiment in which the phase shift mask 112 is configured such that different phase shift regions R have the same area.

(Example of phase shift mask)
FIG. 8A is a schematic diagram illustrating an example of a phase shift mask 112 in which the phase shift mask pattern 115 has a translucent phase shift structure or region R. FIG. The translucent phase shift region R ₀ has a phase shift of 0 degree. Further, the translucent phase shift region R _π has a phase shift of 180 (π) degrees.

FIG. 8B is an enlarged view showing four phase shift regions R in the phase shift mask 112 shown in FIG. 8A. The phase shift regions R ₀ and R _π are squares having a dimension (length of one side) of L. Each phase shift region R has the same area and is formed in a checkerboard pattern or an array. The phase shift region R can take any reasonable shape. In particular, it may include at least one circle, ellipse, or polygon.

  The photolithographic system 100 including the phase shift mask 112 having the checkerboard-like phase shift mask pattern 115 has a size of about L / 2 (that is, a substantial size L of the phase shift region R in the phase shift mask 112). Photolithographic projection to form a periodic (eg, checkerboard like) structure on the photoresist layer 135. Specifically, there is a doubling of the spatial period during the projection process. This doubling of the spatial period substantially doubles the spatial period of the phase shift mask pattern 115 at the surface 22 of the substrate 20. As a result, twice as many dark regions and bright regions are formed in the substrate 20. This is because the zero-order diffracted rays have been removed, allowing a combination of each first-order ray and zero-order ray to regenerate the original spatial period in the phase shift mask 112. By removing this zero order ray, only two first order rays are projected. When these two primary rays are combined, a sine pattern having a spatial period twice that of the original phase shift mask pattern 115 is generated. Thus, when L is 1 micron, a photoresist structure with an L / 2 dimension of 0.5 microns is formed.

As a rule of thumb in photolithographic projection, the smallest feature size FS that can be printed by the photolithographic system 100 having projection wavelengths λ _I and NA is expressed as FS = k ₁ · λ _I / NA. Here, k ₁ is a constant generally estimated to be between 0.5 and 1, depending on the individual photolithographic process. The DOF (depth of focus) is given by k ₂ · λ _I / NA ² . Here, k ₂ is another process-based constant that varies depending on the individual photolithographic process, and is often about 1.0. Therefore, the dimension FS and the DOF are in a trade-off relationship.

  The board | substrate 20 used for LED manufacture does not reach the board | substrate used for manufacture of a semiconductor integrated circuit at the flatness. In fact, most LED substrates 20 have warpage due to the MOCVD process on the surface 22 of the substrate 20 that exceeds tens of microns (from peaks to valleys). Further, the surface of each exposure field EF has a warp of about 5 microns (from a mountain to a valley). Since DOF is limited with respect to the non-smoothness (warp depth) of the substrate, this degree of non-smoothness is considered to be a major problem when using a photolithographic projection process for manufacturing LEDs. Has been.

In a traditional photolithographic process using a conventional photolithographic photoresist, the minimum feature size (line width) that can be formed in the photoresist is given by 0.7 × λ _I / NA. (Ie, k ₁ is 0.7.) Under conditions where a print characteristic of 1 micron in size is desired, using a mapping wavelength of λ _I = 365 nm, the required NA is 0.255. When this NA is used, the DOF of the temporary mapping system is 5.6 microns, which corresponds to the non-flatness required for the general LED substrate 20. This means that it is difficult to make the entire exposure field EF within the DOF. For this reason, the pins 72 formed outside the DOF will not match the required size and required shape.

However, when using the phase shift mask 112 and a conventional photolithographic photoresist, the minimum feature size that can be printed is given by 0.3 × λ _I / NA (ie, k ₁ is 0.3). It is done. This has the practical effect of reducing the required NA by about half and increasing the DOF by about 4 times compared to the conventional mask. Therefore, when the pin diameter D is given, NA = k ₁ × λ _I / D, and DOF is given by the following equation.
DOF = k ₂ × λ _I / NA ² = k ₂ × λ _I / [k ₁ × λ _I / D] ² = k ₂ × D ² / k ₁ ² × λ _I

As a means of the embodiment, when the photoresist is exposed by photolithography for the purpose of obtaining a pin 72 having a diameter D = 1 micron using a projection wavelength λ _I = 365 nm, the required NA is only 0.11. Also, in order to allow each exposure field EF of the non-flat LED substrate to be within the DOF, the DOF exceeds 30 microns.

In certain embodiments, the photolithographic system 100 used to implement the methods described herein is relatively in comparison to today's critical level projection lens NAs values (eg, 0.5 or greater). It has a low projection lens NA value (for example, 0.5 or less). The photolithographic system 100 also has a relatively long mapping wavelength (eg, approximately λ _I = 365 nm, or other mercury lines compared to today's critical level mapping wavelength (eg, deep ultraviolet light having a wavelength of 193 nm). Either). The small-NA, long-wavelength photolithographic system 100 is more expensive than the large-NA, short-wavelength advanced photolithographic system used at the critical level in semiconductor integrated circuit manufacturing in most cases. And maintenance costs are very low.

FIG. 9A is a schematic diagram illustrating another example of a phase shift mask 112 that may be used to form an array 70 with sub-micron pins 72. The phase shift mask 112 of FIG. 9A is similar to that of FIGS. 8A and 8B, except that the opaque background 117 is present, the dimensions of the phase shift regions R ₀ and R _π are L / 2, and It is different that they are separated. As the phase shift regions R ₀ and R _π , octagonal ones are shown as examples of polygon phase shift regions. FIG. 9B is similar to FIG. 9A, but shows an example of a phase shift mask 112 having a circular phase shift region R.

The opaque background 117 may be coated with a shock absorbing layer such as chrome or aluminum. The phase shift regions R ₀ and R _π are printed on the photoresist layer 135 with substantially the same dimension L / 2. This exceeds the conventional resolution limit in the photolithographic system 100 designed at 1 micron. The advantage of the configuration of the phase shift mask 112 shown in FIGS. 9A and 9B is that the placement and spacing of the final photolithographic image forming the array 70 of pins 72 is simple.

FIG. 10 illustrates an array 70 ′ of photoresist pins 72 ′ formed using a 3 μm thick negative photoresist layer 135 and using a phase shift mask 112 similar to that shown in FIG. 8A. It is a scanning electron microscope (SEM) image of an Example. Note that the phase shift regions R ₀ and R _π are L / 2 = 0.6. Each photoresist pin 72 'has a diameter (width) D of about 0.6 microns. As shown in the figure, the shape of the photoresist pin 72 ′ may take various shapes as shown by two circles drawn by broken lines as an estimate of the actual size and shape of the photoresist pin 72 ′. For example, the bottom part is cut off, or the side surface is inclined.

(Phase shift mask with assist phase region)
FIG. 11A is a plan view showing an example of a chromeless phase shift mask 112 similar to that shown in FIG. 8A. FIG. 11B is an enlarged view of a portion indicated by “AA” in FIG. 11A. The phase shift mask 112 of FIG. 11A includes a phase shift mask pattern 115 (similar to that shown in FIG. 8A) supported on the surface 114 of the phase shift mask 112. The phase shift mask pattern 115 has a central (or inner or main) checkerboard array 115C in which phase shift (or “phase”) regions R ₀ and R _π are alternately arranged. The checkerboard array 115C includes a peripheral edge 115P having a side 115E and four corners 115PC. The phase shift region R needs to have a phase shift different from each other by π (180 degrees) or a combination of phase regions R satisfying this condition (for example, R _{π / 2} and R _{3π / 2} ). It is. The phase shift region R is usually the same size or larger than the resolution limit of the particular photolithographic system 100 in which the phase shift mask 112 is used. That is, the phase shift region R is sized to form a configuration suitable for the photoresist layer 135 or the like or suitable for use.

  The phase shift mask pattern 115 further includes an assist pattern or array 115A that surrounds the central checkerboard array 115C at the side 115E. The assist pattern or array 115A has a sub-resolution assist phase region R 'disposed adjacent to at least a part of the peripheral edge 115P, which is one or more sides 115E. Here, the sub-resolution is considered to be an appropriate or useful configuration originally such as a resist structure such as a photoresist pin 72 'when projected by a photolithographic projection system having a resolution limit. It means an assist phase region R ′ that does not result in formation of a thing. Each assist phase region R ′ has a phase opposite to the phase of the adjacent phase shift region R of the checkerboard array 115C. The assist phase region R ′ defines the peripheral edge 118 of the assist pattern 115A.

  In one embodiment, the determination as to whether or not the given assist phase region R ′ is a sub-resolution is performed by specifically photolithography projection on the phase shift mask 112 in a photosensitive material such as a photoresist layer. This is done by examining whether one of the assist phase regions R ′ formed in the photoresist layer 135 is optimal and useful based on the phase shift mask 112 used for printing.

  In one embodiment, some assist phase regions R 'have the same size as adjacent phase shift regions R in the checkerboard array 115C. Also, some assist phase regions R ′ are substantially smaller than the dimensions of adjacent phase shift regions R.

  In one embodiment, the outer surface 114 of the phase shift mask pattern 115 (ie, the portion adjacent to the periphery 118 of the assist phase region) has an opaque background portion so that the exposure field EF has a clear periphery (see FIG. 11A). 117.

  In one embodiment, the assist phase region R ′ is located outside the stepping area of the phase shift mask pattern 115. In other words, only the checkerboard array 115C falls within the area that is actually exposed in the exposure field EF. When a plurality of exposure fields EF are joined together, the non-printing region related to the assist phase region R ′ is overlapped with the pattern in the next exposure field EF.

  FIG. 11C is similar to FIG. 11B but shows another embodiment of the phase shift mask pattern 115, wherein the assist phase region R ′ is further one or more disposed in each of the one or more corners 115PC. Assist phase region R ′. The assist phase region R ′ at the corner shown in FIG. 11B is shifted by π phase in order to maintain the checkerboard-like array pattern. In addition, in some embodiments, the corner assist phase region R 'is smaller than the non-corner assist phase region R' disposed adjacent to the side 115E. Therefore, in an embodiment, the assist phase region R ′ is configured to surround (for example, close to) the peripheral edge 115P. In another embodiment, the assist phase region R ′ is configured to surround at least a part of the peripheral edge 115P.

  A plurality of exposure fields EF can be joined together to form a large array 70 'of photoresist pins 72'. This is because the formation of the LED 10 includes forming an array 70 of pins 72 on the substrate 20 as the first pattern layer in the LED process. By using the photolithographic system 100 between the exposure fields EF, it is possible to configure a process that incorporates a scribing line. However, this is not how a conventional LED manufacturing process has been developed using a full wafer aligner. Currently, in LED manufacturing, a scribing area (also called a scribing line) 137 does not exist anywhere on the wafer (substrate 20). Rather, substantially the entire wafer has the array 70 ′ of photoresist pins 72 ′ with no substantial breakage (ie, substantially continuous array 70 ′ and thereby substantially continuous array 70). It is formed to include.

  Such a structure of pins 72 is feasible because subsequent layers used in the manufacture of LED 10 need not be positioned relative to array 70. This allows the wafer containing the array 70 to be generic that can be used for all LED devices, regardless of die size. Because the array 70 thus formed is not a specific device, the array 70 can be formed by a wafer supplier rather than a device manufacturer. Since only one phase shift mask 112 is required for each type of array 70 (eg, each pin size of pin 72), the cost of phase shift mask 112 is divided across all devices using the same array 70. Can bear.

  The checkerboard array 115C in the phase shift mask 112 effectively serves as an infinite array for the inner side of the exposure field EF. In practice, for example, the phase shift mask 112 is used to form thousands of LEDs. Each LED includes thousands of pins 72 (see FIG. 1). For this reason, there are more than several thousand phase shift regions R and assist phase regions R ′ forming the checkerboard array 115C and the assist pattern 115A. However, when the phase shift mask pattern 115 is formed only by the checkerboard array 115C and its peripheral edge 115P ends at the boundary of the corresponding lithographic exposure field EF, the shape of the pin at the peripheral edge 118 of the exposure field EF is It is distorted due to the lack of phase interference exceeding 115E.

  FIG. 12A schematically illustrates formation of a (negative) array 70 'of photoresist pins 72' using a phase shift mask 112 that includes a phase shift mask pattern 115 having only a checkerboard array 115C. The array 70 'has a peripheral pin 72'P formed at the peripheral edge of the exposure field EF and an inner (center) pin 72'C formed inside the peripheral pin 72'P. The peripheral pin 72'P has a distorted shape as compared with the inner pin 72'C. To facilitate the distinction between these two types of pins, the peripheral pin 72'P and the inner (center) pin 72'C are separated using a broken line.

  FIG. 12B is similar to FIG. 12A, but uses a phase shift mask 112 further including an assist phase region R ′ surrounding the periphery, as shown in FIG. 11B. The resulting array 70 'of photoresist pins 72' has peripheral pins 72'P that are substantially the same shape as the inner pins 72'C due to the effect of the assist phase region R '. This configuration of the phase shift mask 112 reduces (or minimizes) the exposure of adjacent photoresist areas and subsequently exposes the exposed photoresist pattern of adjacent exposure fields EF to be stitched together without gaps. Allows exposure.

  FIG. 13 is a cross-sectional view of a 2D model of an array 70 ′ of (positive) photoresist pins 72 ′ formed in the photoresist layer 135, and a PROLITHR photolithographic image that can be used at KLA-Tencor, Milpitas, Calif. It is based on data generated using simulation software. The phase shift mask 112 used in the photolithographic exposure simulation has an assist phase region R ′ having a width of 0.4 μm disposed only on the left side of the phase shift mask 112 and has a checkerboard (alternate) pattern. It has several 1.6 micron square phase shift regions R arranged. In this photolithographic exposure simulation, an i-line wavelength of 365 nm is used with a numerical aperture (NA) of the projection lens of 0.28 and a partial coherent coefficient σ of 0.57. The resolution limit of a photolithographic projector is given by (0.7) × λ / NA to 1 micron.

  In the structure that continues all the way to the left end of the exposure field EF, the shape of the wall W72 'of the leftmost resist wall W135L in the photoresist layer 135 is very similar to the shape of the leftmost photoresist pin 72'. This leftmost photoresist pin 72 'is, in turn, very similar to the adjacent pin (indicated by 72'C on the center or inside). On the other hand, when the non-optical characteristic configuration at the right end of the exposure field EF is shown, the resist wall W135R of the photoresist layer 135 related to the right end of the phase shift mask 112 is distorted as compared with other photoresist walls.

The number N of phase shift regions R and the number N ′ of assist phase regions R ′ in a given phase shift mask 112 depend on the size of the exposure field EF and the spacing of the pins 72 in the array 70. In the exposure field dimension S _EF and the distance P ₇₂ between the pins 72, the number N of the phase shift regions R is given by N = (S _EF / P ₇₂ ) ² . As an example, when S _EF = 10 mm and P ₇₂ = 0.0016 mm, N = (10 / 0.0016) ² = 3.9 × 10 ⁷ . The number N ′ of assist phase regions R ′ arranged at all four corners of the phase shift mask 112 is given by N ′ = 4 × (10 / 0.0016) = 2.5 × 10 ⁴ . This number N increases by four when the assist phase region R ′ is added to the four corners of the checkerboard array 115C.

(Example of a method for forming a rough substrate surface)
Accordingly, one aspect of the present invention is an array of pins 72 during the manufacture of LED 10 using photolithographic projection and photolithographic process techniques using phase shift mask 112 including assist phase region R ′ as described above. A method of forming a roughened substrate surface 22 having 70 is included. An example of a method for forming the array 70 of pins 72 will be described below with reference to FIGS. 6 and 14A to 14E.

  Referring initially to FIG. 14A, the method includes providing a substrate 20 having a photoresist layer 135 coated on the surface 22 of the substrate 20. Next, the coated substrate 20 is placed on the movable substrate stage 130 of the photolithography system 100 (FIG. 6). The phase shift mask 112 (see, for example, FIGS. 11A to 11C) having the checkerboard array 115C and the assist pattern 115A is disposed on the mask stage 110 of the photolithographic system 100. Next, the method performs the following photolithographic projection using the photolithographic system 100. That is, an array 70 ′ of photoresist pins 72 ′ is formed over substantially the entire exposure field EF, and the exposure lens 108 is used to expose the photoresist layer 135 on the exposure field EF. The exposure of the phase shift mask 112 and the passing (diffracted) exposure light 121 from the phase shift mask pattern 115 are captured and projected. This is illustrated in FIG. 14B.

  Referring to FIG. 7, a number of LED regions 10 'are formed in the photoresist layer 135 of each exposure field EF. Therefore, in the example where the phase shift mask pattern 115 has an area of 15 mm × 30 mm and each LED 10 is 1 mm square, there are 450 LED regions 10 ′ in each exposure field EF. When the photolithographic system 100 operates at unit magnification, each exposure field EF is also 15 mm × 30 mm. Inset B of FIG. 7 shows an array 10A 'of LED regions 10' in the configuration of LEDs 10. Each LED region 10 ′ is separated by a scribe region 11. However, an array 70 'of photoresist pins 72' is formed on the entire surface of the exposure field EF including the scribing area 137 shown in the inset A (see inset C in FIG. 7). The connection between the exposure fields may be performed at each exposure field boundary. The phase shift mask 112 is configured to relieve distortion of the components formed at the periphery of the exposure field EF, thereby facilitating the joining process, and the exposure field EF existing in the scribing area 137. The necessity to prepare a part (for example, the periphery of the exposure field) is avoided.

  Referring to FIG. 14C, the exposed photoresist layer 135 of FIG. 14B removes unexposed resist (negative photoresist) or is complementary to an array 70 ′ of photoresist pins 72 ′ or a complementary relationship thereto. It is processed to remove the exposed resist (positive photoresist) to form a hole. The photoresist array 70 ′ is then etched using a general photolithography etching technique as shown by an arrow 200, and a photoresist pattern is projected onto the substrate 20. This forms an array 70 of pins 72 on the surface 22 of the substrate, as shown in FIG. 14D.

  FIG. 14E is similar to FIG. 14D and shows an example in which the pins 72 of the array 70 are non-cylindrical (ie, pyramidal as shown). The shape of such pins 72 on the surface 22 of the substrate 20 can be obtained from the non-pyramid shaped photoresist pins 72 'using the etching technique described above.

  Since the substrate 20 is composed of a plurality of LED regions 10 ′ having a suitably roughened substrate surface 22, the LEDs 10 can be manufactured using general photolithographic based LED manufacturing techniques. . This technique further includes, for example, constructing a GaN multilayer structure 30 on the roughened surface 22 of the substrate 20, and then replacing the p-contact 90p or n-contact 90n with the layer 50 or 40, respectively, shown in FIG. The process of adding is included.

  It will be apparent to those skilled in the art that various modifications can be made on the basis of the invention without departing from the spirit and scope of the invention. Therefore, the present invention is also protected with respect to those modifications as described in the claims or equivalents thereof.

Claims (20)

A phase shift mask for use in a photolithographic projection system having a resolution limit,
A checkerboard array having a peripheral edge, which is composed of a plurality of phase shift regions that are larger than the resolution limit, and
A plurality of assist phase regions arranged so as to be adjacent to at least a part of the peripheral edge,
The plurality of phase shift regions have a phase difference of 180 degrees between the adjacent phase shift regions,
Each assist phase region is smaller than the resolution limit, and has a phase difference of 180 degrees between adjacent phase shift regions. The peripheral edge has four sides;
The phase shift mask according to claim 1, wherein the phase shift region is arranged next to each of these sides.   The phase shift mask according to claim 2, wherein the peripheral edge has four corners defined by the four sides, and the assist phase region is arranged next to the four corners.   4. The phase shift mask according to claim 1, wherein the assist phase region is disposed adjacent to an entire periphery of the checkerboard array. 5.   5. The phase shift mask according to claim 1, further comprising an opaque layer disposed so as to be adjacent to a peripheral edge defined by the assist phase region. 6. A phase shift mask used in a photolithographic projection system having a resolution limit and a wavelength,
A mask body that transmits the wavelength of the photolithographic projection system and has a surface;
A checkerboard array that is supported by the surface of the mask body, is composed of a plurality of phase shift regions that are larger than the resolution limit, and has a plurality of sides and a peripheral edge with four corners; ,
A plurality of assist phase regions supported by the surface and arranged adjacent to the plurality of sides and four corners so as to surround the periphery;
The plurality of phase shift regions have a phase difference of 180 degrees between the adjacent phase shift regions,
Each of the assist phase regions is smaller than the resolution limit, and has a phase difference of 180 degrees between the adjacent phase shift region and the adjacent assist phase region.   The phase shift mask according to claim 6, further comprising an opaque layer disposed so as to be adjacent to a peripheral edge defined by the assist phase region. A method of performing photolithographic patterning on a semiconductor substrate,
Preparing a semiconductor substrate having a surface supporting the photoresist layer;
A plurality of phase shift areas, the plurality of phase shift areas having a phase difference of 180 degrees between the adjacent phase shift areas, and a checkerboard array having a peripheral edge; A plurality of assist phase regions that are smaller than the limit and are arranged adjacent to at least a part of the peripheral edge, and each assist phase region is 180 degrees between the adjacent phase shift regions. Photolithographic projection of a phase shift mask pattern on the photoresist layer, which has a phase difference,
A method of processing the photoresist layer to form an intermittent array of photoresist. Processing the photoresist to form an array of substrate pins defining a roughened substrate surface;
The method of claim 8, further comprising forming a pn junction multilayer structure on the roughened substrate surface.   The method according to claim 8, wherein the semiconductor substrate is made of sapphire.   11. A method according to any one of claims 8 to 10, wherein the photolithographic projection is a unit magnific- tion with a nominal wavelength of 365nm. The substrate pins have dimensions of 1 micron or less;
The method according to claim 9, wherein the photolithographic projection is performed with a numerical aperture of 0.5 or less.   13. The method according to any one of claims 8 to 12, wherein the phase shift mask further comprises an opaque layer adjacent to a periphery defined by the assist phase region.   14. The photolithographic projection includes splicing exposure fields to form a substantially continuous array of photoresist pins on a substantially entire photoresist layer on the substrate. 2. The method according to item 1. Illuminating light is transmitted through a phase shift mask having a checkerboard phase shift pattern having a periphery surrounded by an array of sub-resolution assist phase regions, and a photoresist pin is exposed by photolithography exposure to the photoresist on the semiconductor substrate. An array of
Processing the array of photoresist pins to form an array of substrate pins defined by a roughened substrate surface;
A pn junction multilayer structure is formed on the roughened substrate surface, and the roughened substrate surface scatters the light generated in the pn junction multilayer structure, thereby emitting light compared to a smooth substrate surface LED. A method of manufacturing a light emitting diode (LED) of increasing quantity.   The method of claim 15, wherein the phase shift mask further comprises an opaque layer adjacent to a periphery defined by the sub-resolution assist phase region.   The method according to claim 15 or 16, wherein the photolithographic exposure of the photoresist is performed with a numerical aperture of 0.5 or less.   The method of claim 17, wherein the photolithographic exposure of the photoresist is performed in unit magnification with a nominal wavelength of 365 nm.   19. The photolithographic exposure of the photoresist includes the step of stitching exposure fields to form a substantially continuous array of photoresist pins over substantially the entire substrate. The method described in 1.   The method of claim 19, further comprising an exposure field overlap corresponding to the assist phase region of the phase shift mask.