JP2012226409A - Multi-core processor - Google Patents

Abstract

An object of the present invention is to improve the reliability of alternative processing performed when an abnormality occurs in any of processor cores.
A plurality of processor cores capable of executing a plurality of functions, a correspondence relationship between the plurality of functions and the plurality of processor cores are determined, and at least a part of the plurality of processor cores is provided with a function. A control unit that designates a standby core that is not to be executed, and the control unit changes the designation of the spare core every time a predetermined switching timing arrives. Processor.
[Selection] Figure 1

Description

  The present invention relates to a multi-core processor that has a plurality of processor cores and each processor core can execute an independent function.

  2. Description of the Related Art Conventionally, a multi-core processor is known in which a plurality of processor cores (CPU cores) are enclosed in one package and each processor core can perform processing in parallel and independently. Since the multi-core processor can perform parallel processing, for example, in the field of in-vehicle control devices, it is expected to be used to integrate a plurality of control devices having different functions into one control device. .

  The multi-core processor has an advantage that, when an abnormality occurs in any one of the processor cores, another processor core can perform an alternative process.

  Patent Document 1 describes that, in a processor having a plurality of processor cores, the processor cores are divided into an operating core group and a spare core group, and when the operating core fails, replacement processing is performed with the spare core. .

Special table 2009-524863

  However, in the technique described in the above-described conventional patent document 1, the reliability that the spare core can normally perform the substitute process when the operating core fails is low.

  This is because there is a possibility that the spare core does not perform any processing for a long time, and the alternative processing may not be performed normally due to aging degradation during that time. In addition, there is a high possibility that the spare core has not performed the function of the failed operating core in the past, which also causes a decrease in reliability.

  The present invention is intended to solve such a problem, and provides a multi-core processor capable of improving the reliability of alternative processing performed when an abnormality occurs in any of the processor cores. The main purpose.

In order to achieve the above object, one embodiment of the present invention provides:
Multiple processor cores capable of performing multiple functions;
Control means for determining a correspondence relationship between the plurality of functions and the plurality of processor cores and designating at least a part of the plurality of processor cores as standby cores in a standby state in which the functions are not executed;
With
The control means changes the designation of the spare core every time a predetermined switching timing arrives,
It is a multi-core processor.

  According to this aspect of the present invention, since the designation of the spare core is changed every time a predetermined switching timing arrives, the reliability that the processor core waiting as the spare core can operate normally is high. Become. In addition, when performing an alternative process for a processor core in which an abnormality has occurred, there is a high possibility that the process has been performed in the past. For this reason, it is possible to improve the reliability of the alternative process performed when an abnormality occurs in any of the processor cores.

In one embodiment of the present invention,
The control means may be means for cyclically changing a correspondence relationship between the plurality of functions and the plurality of processor cores and designation of the spare core in the plurality of processor cores.

in this case,
When the abnormality occurs in a processor core not designated as the spare core, the control means is a means for substituting the spare core for the function performed by the processor core in which the abnormality has occurred. Also good.

In one embodiment of the present invention,
The control unit is configured such that a specific processor core among the plurality of processor cores sequentially executes the plurality of functions, and a non-specific processor core other than the specific processor core is a specific function assigned to itself among the plurality of functions. It is good also as a means to control to perform only.

in this case,
The control means may be means for designating a non-specific processor core whose function has been moved to the specific processor core at the predetermined switching timing as the spare core.

In one aspect of the invention in which the specific processor core is specified,
The control means is means for substituting the specific processor core for the function being executed by the processor core in which the abnormality occurs when an abnormality occurs in the processor core not designated as the spare core. It is good.

in this case,
The control means assigns a function executed by the specific processor core to a non-specific processor core designated as the spare core when an abnormality occurs in a processor core not designated as the spare core. It may be a means.

  According to the present invention, it is possible to provide a multi-core processor capable of improving the reliability of an alternative process performed when an abnormality occurs in any of the processor cores.

1 is a system configuration example of a multi-core processor 1 according to a first embodiment of the present invention. It is a figure which shows the state by which several functions were allocated to processor core 20 # 0-20 # 7 at a certain time. FIG. 3 is a diagram illustrating a correspondence relationship between a plurality of functions and processor cores 20 # 0 to 20 # 7 and a designation of a spare core when a predetermined switching timing arrives in the state illustrated in FIG. It is a figure which shows the correspondence of a some function and processor core 20 # 0-20 # 7, and designation | designated of a reserve core after the predetermined switching timing has arrived 4 times from the state shown in FIG. FIG. 5 is a diagram illustrating correspondence between a plurality of functions and processor cores 20 # 0 to 20 # 7 and designation of spare cores after an abnormality has occurred in the processor core 20 # 7 in the state illustrated in FIG. It is a flowchart which shows the flow of a process of the master control function performed by processor core 20 # 1 which concerns on 1st Example. It is explanatory drawing for demonstrating operation | movement of the multi-core processor of a conventional structure. FIG. 3 is a diagram illustrating a correspondence relationship between a plurality of functions and processor cores 20 # 0 to 20 # 7 and a designation of a spare core when a predetermined switching timing arrives in the state illustrated in FIG. FIG. 8 is a diagram illustrating correspondence between a plurality of functions and processor cores 20 # 0 to 20 # 7 and designation of a spare core after four predetermined switching timings have arrived from the state illustrated in FIG. 7. FIG. 9 is a diagram illustrating a correspondence relationship between a plurality of functions and processor cores 20 # 0 to 20 # 7 and designation of a spare core after an abnormality occurs in the processor core 20 # 3 in the state illustrated in FIG. It is a flowchart which shows the flow of a process of the master control function performed by processor core 20 # 1 which concerns on 2nd Example. It is explanatory drawing for demonstrating the other embodiment of this invention. It is explanatory drawing for demonstrating the other embodiment of this invention.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the accompanying drawings.

  The multi-core processor of the present invention is suitably applied to an in-vehicle control device that is mounted on a vehicle and performs various arithmetic processes for controlling in-vehicle devices. In particular, the present invention is suitably applied to a device that simultaneously executes a plurality of functions, such as an in-vehicle control device in which a plurality of functions are integrated. Note that the present invention is not limited to this, and the present invention can also be applied to a control device that controls other moving objects such as airplanes and ships, and a structure such as a plant, a home personal computer, and a server device.

<First embodiment>
The multi-core processor 1 according to the first embodiment of the present invention will be described below with reference to the drawings.

[Constitution]
FIG. 1 is a system configuration example of a multi-core processor 1 according to the first embodiment of the present invention. The multi-core processor 1 includes a program memory 10, processor cores 20 # 0 to 20 # 7, a working memory 30, and I / O means 40 as main components. In this embodiment, the number of processor cores is eight, but any number of processor cores of two or more may be provided. Hereinafter, the numbers after “#” of the processor cores 20 # 0 to 20 # 7 are referred to as ID numbers.

  The program memory 10 is a non-volatile memory such as a ROM (Read Only Memory), a flash ROM, and an EEPROM (Electrically Erasable and Programmable Read Only Memory). The program memory 10 includes a plurality of functions that can be executed by each of the processor cores 20 # 0 to 20 # 7 (in this embodiment, function A, function B, function C, function D, function E, function F, function G, And a program (instruction sequence) corresponding to the master control function. Then, the program memory 10 outputs the instruction stored at the address input from each of the processor cores 20 # 0 to 20 # 7 to the processor cores 20 # 0 to 20 # 7 via the instruction fetch bus 15.

  The processor cores 20 # 0 to 20 # 7 include, for example, a program counter, an instruction fetch unit, an instruction queue, an instruction issuing unit, a general-purpose register, an ALU (Arithmetic Logic Unit), a MUL (multiplier), a DIV (divider), and an LSU. (Load Store Unit) A computer unit equipped with other arithmetic units.

  The working memory 30 is, for example, a RAM (Random Access Memory), and can exchange data with the processor cores 20 # 0 to 20 # 7 via the data bus 35.

  The I / O unit 40 performs transmission / reception with an external device of the multi-core processor 1. When the multi-core processor 1 is an in-vehicle control device, the external device is an A / D converter that converts the output value of the sensor into a digital value and outputs the digital value. Such an A / D converter digitally converts the output value of the sensor every predetermined period, and sends an interrupt notification to the corresponding processor core of the multi-core processor 1. The processor core performs necessary processing among the functions executed by itself by detecting the interrupt notification.

[Decision of correspondence and designation of spare core]
FIG. 2 is a diagram illustrating a state in which a plurality of functions are assigned to the processor cores 20 # 0 to 20 # 7 at a certain point in time. At this time, the processor core 20 # 0 is designated as a spare core, the function A and the master control function are assigned to the processor core 20 # 1, the function B is assigned to the processor core 20 # 2, and the processor core 20 # 3 is assigned. Function C is assigned, function D is assigned to the processor core 20 # 4, function E is assigned to the processor core 20 # 5, function F is assigned to the processor core 20 # 6, and function G is assigned to the processor core 20 # 7. Is assigned.

  Here, the spare core refers to a processor core that is maintained in a standby state in which a specific function is not executed and an alternative process of another core can be performed.

  The processor core 20 # 1 to which the master control function is assigned changes the correspondence between the plurality of functions and the processor cores 20 # 0 to 20 # 7 and the designation of the spare core each time a predetermined switching timing arrives. .

  The “predetermined switching timing” may be arbitrarily determined according to the function executed by the multi-core processor 1, but when the multi-core processor 1 is an in-vehicle control device, for example, it is synchronized with IG on, ACC on, etc. It is conceivable to set the timing. In addition, the present invention is not limited to this, and it may be arbitrarily determined every predetermined time, once a day, once a week, or the like.

  In the case of the present embodiment, the correspondence between the plurality of functions and the processor cores 20 # 0 to 20 # 7 and the designation of the spare core are changed “cyclically” as described below. In the present invention, “cyclically” means that the designation of each function and spare core is carried up by 1 (by 2 or 3 or so) as shown below. (Or by lowering) means that the core 20 # 7 is changed to return to the core 20 # 0.

Spare core: Processor core 20 # 0 → 20 # 1 → 20 # 2 → 20 # 3 → 20 # 4 → 20 # 5 → 20 # 6 → 20 # 7 → 20 # 0 →
Function A: Processor core 20 # 1-> 20 # 2-> 20 # 3-> 20 # 4-> 20 # 5-> 20 # 6-> 20 # 7-> 20 # 0-> 20 # 1-> ...
Function B: Processor core 20 # 2-> 20 # 3-> 20 # 4-> 20 # 5-> 20 # 6-> 20 # 7-> 20 # 0-> 20 # 1-> 20 # 2-> ...
Function C: Processor core 20 # 3-> 20 # 4-> 20 # 5-> 20 # 6-> 20 # 7-> 20 # 0-> 20 # 1-> 20 # 2-> 20 # 3-> ...
(Hereafter omitted)

  The above change rule can also be expressed as follows. The number N indicates the ID number of the processor core designated as the spare core, the number i indicates the ID number of the processor core to which a certain function is assigned (thus, there are seven types), and “mod "Indicates a remainder.

Change of spare core designation: N → (N + 1) mod8
Change of function assignment (A to G): i → (i + 1) mod 8

  FIG. 3 is a diagram illustrating the correspondence between a plurality of functions and the processor cores 20 # 0 to 20 # 7 and the designation of a spare core when a predetermined switching timing arrives in the state illustrated in FIG.

  FIG. 4 is a diagram showing the correspondence between a plurality of functions and the processor cores 20 # 0 to 20 # 7 and the designation of a spare core after four predetermined switching timings have arrived from the state shown in FIG. It is.

[Processing when an error occurs]
As described above, when an abnormality occurs in any of the processor cores while the functions and spare cores are cyclically assigned, the processor core 20 # 1 to which the master control function is assigned first has an abnormality. Stop the processor core.

  Then, the processor core 20 # 1 substitutes the processor core designated as the spare core for the processing of the processor core in which the abnormality has occurred.

  Whether or not an abnormality has occurred in the processor core is detected by a known method. For example, SUM check based on data read from the ROM, calculation value check of ALU or the like, determination of coincidence between the calculation value and the sensor output value input from the I / O unit 40, and the like are performed.

  FIG. 5 is a diagram showing correspondence between a plurality of functions and processor cores 20 # 0 to 20 # 7 and designation of spare cores after an abnormality occurs in the processor core 20 # 7 in the state shown in FIG. It is. As shown in the drawing, the function B assigned to the processor core 20 # 7 is assigned to the processor core 20 # 5 designated as the spare core.

  If an abnormality occurs in any of the cores, the user is notified by a buzzer, a display, or the like. As for the subsequent control, if there is a surplus in the number of processor cores to the extent that a spare core can be specified, the above cyclic change may be performed. If there is no surplus, the process is performed as it is. At the same time, a comment urging the user to repair / inspect may be output.

[Processing flow]
FIG. 6 is a flowchart showing the flow of processing of the master control function executed by the processor core 20 # 1 according to the first embodiment.

  First, the processor core 20 # 1 determines whether or not a predetermined switching timing has arrived (S100).

  When the predetermined switching timing has arrived, the ID number N of the processor core designated as the spare core is acquired (S102).

  Then, it is determined whether or not the ID number N is the maximum value (7 in this embodiment) (S104). It is assumed that the number of the processor core designated as the spare core and the number of the processor core to which a function described later is assigned are stored in the general-purpose register of the processor core 20 # 1.

  If the ID number N is not the maximum value, the processor core 20 # N + 1 is designated as a spare core (S106). On the other hand, if the ID number N is the maximum value, the processor core 20 # 0 is designated as a spare core (S108).

  Next, the following processing is executed for each of the functions A to F. First, the ID number i of the processor core to which the function X (A to F is generalized is referred to as X) is acquired (S110). Then, it is determined whether or not the ID number i is the maximum value (7 in this embodiment) (S112).

  If the ID number i is not the maximum value, the function X is assigned to the processor core 20 # i + 1 (S114). On the other hand, if the ID number i is the maximum value, the function X is assigned to the processor core 20 # 0 (S116).

  Subsequently, the processor core 20 # 1 determines whether or not an abnormality has occurred in any of the processor cores (S118). If an abnormality occurs in any of the processor cores, the function assigned to the processor core is assigned to the processor core designated as the backup core (S120).

[Comparison with conventional configuration, summary]
Here, a comparison with a conventional multi-core processor in a mode in which the function assignment and the specification of the spare core are not changed will be described.

  FIG. 7 is an explanatory diagram for explaining the operation of the conventional multi-core processor. As shown in the figure, in the conventional multi-core processor, since the spare core is fixed, for example, when an alternative process is performed when an abnormality occurs in the processor core 3 executing the function C, the function C The reliability of whether or not it can be executed normally was low. This is because there is a possibility that no processing is performed before the spare core performs the substitution processing, and there is a possibility that the function C is not executed at all in the past.

  On the other hand, in the multiprocessor 1 of the present embodiment, since functions and spare cores are allocated cyclically, the processor core designated as the spare core has already executed all (or many) functions. ing. As a result, it is possible to improve the reliability that the function related to the substitute process can be normally executed.

  Further, since the abnormality check is performed in the process of executing the function by the processor core, the reliability that each processor core is normal can be improved.

  Therefore, it is possible to improve the reliability of the alternative process performed when an abnormality occurs in any of the processor cores.

  According to the multi-core processor 1 of the present embodiment described above, it is possible to improve the reliability of alternative processing performed when an abnormality occurs in any of the processor cores.

<Second embodiment>
The multi-core processor 2 according to the second embodiment of the present invention will be described below.

  Since [Configuration] is the same as that in the first embodiment, reference is made to FIG. 1, the same reference numerals are given to the respective components, and the description of the basic functions is omitted.

[Decision of correspondence and designation of spare core]
Also in the multi-core processor 2 according to the present embodiment, the processor core 20 # 1 to which the master control function is assigned has a plurality of functions and the processor cores 20 # 0 to 20 # 7 each time a predetermined switching timing arrives. The correspondence relationship and the spare core designation are changed.

  In the present embodiment, a part of the processor cores 20 # 0 to 20 # 7 is handled as a specific processor core that sequentially executes a plurality of functions. This specific processor core is assigned an alternative process when an abnormality occurs in another core.

  In other words, the processor core 20 # 1 to which the master control function is assigned has a specific processor core (in this case, the processor core 20 # 0 is selected from the processor cores 20 # 0 to 20 # 7 each time a predetermined switching timing arrives. A specific processor core is assumed to execute a plurality of functions in order, and other processor cores (hereinafter referred to as non-specific processor cores) are specific functions assigned to themselves (hereinafter referred to as non-specific processor cores). (Referred to as self-function).

  However, a processor core whose function has been moved to a specific processor core among non-specific processor cores is designated as a reserve core.

  As a result, the function assigned to each processor core or the designation of the spare core transitions as follows. In the initial state, it is assumed that the processor core 20 # 0 is a specific processor core and designated as a spare core.

Processor core 20 # 0 (specific): Spare core → Function A → Function B → Function C → Function D → Function E → Function F → Function G → Spare core →
Processor core 20 # 1 (non-specific): Function A → Spare core → Function A → Function A → Function A → Function A → Function A → Function A → Function A →
Processor core 20 # 2 (unspecified): Function B → Function B → Spare core → Function B → Function B → Function B → Function B → Function B → Function B → ...
Processor core 20 # 3 (unspecified): Function C → Function C → Function C → Spare core → Function C → Function C → Function C → Function C → Function C →
(Hereafter omitted)

  The above change rule can also be expressed as follows. “Mod” indicates a remainder.

Change of spare core designation: N → (N + 1) mod8
Change of function assignment: Function assigned to core 20 # 0 → core 20 # N
Functions assigned to the core 20 # (N + 1) mod8 → core 20 # 0

  FIG. 8 is a diagram illustrating correspondence between a plurality of functions and processor cores 20 # 0 to 20 # 7 and designation of spare cores when a predetermined switching timing arrives in the state illustrated in FIG.

  FIG. 9 is a diagram showing the correspondence between a plurality of functions and the processor cores 20 # 0 to 20 # 7 and the designation of a spare core after four predetermined switching timings have arrived from the state shown in FIG. It is.

[Processing when an error occurs]
As described above, when an abnormality occurs in any of the processor cores while the functions and spare cores are cyclically assigned, the processor core 20 # 1 to which the master control function is assigned first has an abnormality. Stop the processor core.

  Then, the processor core 20 # 1 substitutes the processor core 20 # 0, which is a specific processor core, for the function executed by the processor core in which the abnormality has occurred.

  Whether or not an abnormality has occurred in the processor core is detected by a known method as in the first embodiment.

  FIG. 10 is a diagram showing correspondence between a plurality of functions and processor cores 20 # 0 to 20 # 7 and designation of spare cores after an abnormality occurs in the processor core 20 # 3 in the state shown in FIG. It is.

  As illustrated, the function F assigned to the processor core 20 # 3 is assigned to the processor core 20 # 0, which is a specific processor core. The function executed by the processor core 20 # 0, which is a specific processor core, is assigned to the processor core 20 # 5, which is a spare core.

  If an abnormality occurs in any of the cores, the user is notified by a buzzer, a display, or the like. As for the subsequent control, if there is a surplus in the number of processor cores to the extent that a spare core can be specified, the above cyclic change may be performed. If there is no surplus, the process is performed as it is. At the same time, a comment urging the user to repair / inspect may be output.

[Processing flow]
FIG. 11 is a flowchart showing the flow of processing of the master control function executed by the processor core 20 # 1 according to the second embodiment.

  First, the processor core 20 # 1 determines whether or not a predetermined switching timing has arrived (S200).

  If the predetermined switching timing has arrived, the ID number N of the processor core designated as the spare core is acquired (S202). Then, the processor core 20 # N is returned to the state of executing the “self function” of the processor core (S204), and it is determined whether or not the ID number N is the maximum value (7 in this embodiment) (S206). ).

  If the ID number N is not the maximum value, the processor core 20 # N + 1 is designated as a spare core, and the function executed by the processor core 20 # N + 1 is assigned to the processor core 20 # 0 (S208). On the other hand, if the ID number N is the maximum value, the processor core 20 # 0 is designated as a spare core (S210).

  Subsequently, the processor core 20 # 1 determines whether or not an abnormality has occurred in any of the processor cores (S212). If an abnormality occurs in any of the processor cores, the function assigned to the processor core is assigned to the processor core 20 # 0 (S214), and the function assigned to the processor core 20 # 0 is assigned to the spare core. Is assigned to the processor core specified in (S216; return to “self function”).

[Summary]
According to the multi-core processor 2 of the present embodiment described above, the reliability of the alternative process performed when an abnormality occurs in any of the processor cores can be improved as in the first embodiment.

  Further, the movement of functions between processor cores can be reduced as compared with the first embodiment. Non-specific processor cores that are not specific processor cores are controlled by two choices of executing a self-function or being designated as a spare core. As a result, the software load can be reduced.

  The best mode for carrying out the present invention has been described above with reference to the embodiments. However, the present invention is not limited to these embodiments, and various modifications can be made without departing from the scope of the present invention. And substitutions can be added.

  In both the first and second embodiments, the subject executing the master control function can be changed as follows.

  For example, not only the processor core 20 # 1, but any processor core may execute the master control function.

  Further, as shown in FIG. 12, the master control function may be moved between the processor cores in association with any one of the functions A to F. FIG. 12 is an explanatory diagram for explaining another embodiment of the present invention.

  Also, as shown in FIG. 13, the master control function may be executed by hardware that does not belong to any core (denoted as the master control circuit 50 in the figure), or any core. It may be executed by another CPU that does not belong. FIG. 13 is an explanatory diagram for explaining another embodiment of the present invention.

  Further, a dedicated processor core that executes only the master control function may be provided.

1, 2 Multi-core processor 10 Program memory 15 Instruction fetch bus 20 # 0-20 # 7 Processor core 30 Working memory 35 Data bus 40 I / O means 50 Master control circuit

Claims (7)

Multiple processor cores capable of performing multiple functions;
Control means for determining a correspondence relationship between the plurality of functions and the plurality of processor cores and designating at least a part of the plurality of processor cores as standby cores in a standby state in which the functions are not executed;
With
The control means changes the designation of the spare core every time a predetermined switching timing arrives,
Multi-core processor. The multi-core processor according to claim 1, comprising:
The control means is means for cyclically changing the correspondence relationship between the plurality of functions and the plurality of processor cores, and designation of the spare core in the plurality of processor cores.
Multi-core processor. A multi-core processor according to claim 2, comprising:
The control means is means for substituting the spare core for the function that the processor core in which the abnormality occurred when an abnormality occurs in a processor core that is not designated as the spare core.
Multi-core processor. The multi-core processor according to claim 1, comprising:
The control unit is configured such that a specific processor core among the plurality of processor cores sequentially executes the plurality of functions, and a non-specific processor core other than the specific processor core is a specific function assigned to itself among the plurality of functions. Is a means to control to execute only,
Multi-core processor. A multi-core processor according to claim 4,
The control means is means for designating, as the spare core, a non-specific processor core whose function has been moved to the specific processor core at the predetermined switching timing.
Multi-core processor. A multi-core processor according to claim 4 or 5,
The control means is means for substituting the specific processor core for the function that the processor core in which the abnormality occurred when an abnormality occurs in a processor core that is not designated as the spare core.
Multi-core processor. The multi-core processor according to claim 6, wherein
The control means assigns a function executed by the specific processor core to a non-specific processor core designated as the spare core when an abnormality occurs in a processor core not designated as the spare core. Means,
Multi-core processor.

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