JP2012221149A - Reconfigurable integrated circuit device - Google Patents

Abstract

A reconfigurable integrated circuit device that optimally constructs a network connection between processor elements is provided.
A reconfigurable integrated circuit device includes a first processor element PE1_1 in a first locally connected processor group LC1 and a processor element PE that does not share a processor element PE with the first locally connected processor LC1 group. It has a plurality of global connection networks GN1 that select and supply any one of the outputs of the plurality of processor elements PE0_l and the like in the two locally connected processor groups LC2.
[Selection] Figure 5

Description

  The present invention relates to a reconfigurable integrated circuit device.

  The reconfigurable integrated circuit device has a plurality of processor elements (PE) and a network connecting the processor elements. An integrated circuit device that can be reconfigured can arbitrarily calculate the configuration of the processor elements and the network configuration between the processor elements based on configuration data set by the control circuit that is a sequencer in response to an external or internal event. Build in state or arithmetic circuit.

  Reconfigurable integrated circuit devices include multiple arithmetic processors (ALU: Arithmetic and Logic Unit (ALU) having functions such as adders, multipliers, and comparators, delay circuits, counters, selectors, and registers. A plurality of elements are provided in advance, and a network for connecting the processor elements is provided. The reconfigurable integrated circuit device reconstructs the processor element and the network into a desired configuration based on the configuration data from the reconfiguration control unit including the sequencer, and performs a predetermined operation in the reconstructed state. Execute.

  In a reconfigurable integrated circuit device, if a plurality of arithmetic circuits are constructed by a plurality of processor elements, these arithmetic circuits can simultaneously perform data processing. When the data processing in one calculation state is completed, the reconfigurable integrated circuit device constructs another calculation state with different configuration data, and performs different data processing in that state.

  In this way, the reconfigurable integrated circuit device can dynamically reconstruct different operation states, thereby improving the data processing capability for a large amount of data and increasing the overall processing efficiency.

JP 2009-266021 A

  In such a reconfigurable integrated circuit device, it is ideal that all the processor elements are freely connected to the network via signal lines, and the data processing is executed by the freely connected processor elements. It is. However, if all the processor elements are connected to the network in this way, the network resources become enormous and the circuit scale of the LSI increases.

  Accordingly, an object of the present invention is to provide a reconfigurable integrated circuit device that optimally constructs a network connection between processor elements.

A first aspect of a reconfigurable integrated circuit device that is dynamically constructed in an arbitrary computation state based on configuration data is arranged in an array, and each includes a plurality of processor elements each having a computing unit,
A plurality of locally connected processor groups included in the plurality of processor elements, each provided in each of the plurality of locally connected processor groups having a predetermined number of processor elements adjacent to each other; A plurality of local connection networks that select and supply one of the outputs of a plurality of second processor elements adjacent to the first processor element based on the configuration data to an input of the first processor element; ,
The input of the first processor element in the first locally connected processor group is the output of a plurality of processor elements in the second locally connected processor group that does not share the processor element with the first locally connected processor group. A plurality of global connection networks that are selected and supplied based on the configuration data.

  According to the first aspect, the network connection between the processor elements can be optimally constructed.

It is a schematic block diagram of the reconfigurable integrated circuit device relevant to this Embodiment. It is a figure which shows the specific example of the reconfiguration array relevant to this Embodiment. It is another figure which shows the specific example of the reconfiguration array relevant to this Embodiment. It is a figure which shows the example of arrangement | positioning of the processor element in this Embodiment. It is a circuit diagram explaining an example of the connection method of a local connection processor group. It is the figure which showed the local connection network and the global connection network. It is a circuit diagram explaining the other example of the connection method of a local connection processor group. It is the figure which showed the local connection network and the global connection wiring. It is a circuit diagram explaining the specific example of a global connection network. It is a circuit diagram explaining the specific example of a global connection network. It is a circuit diagram explaining the specific example of a global connection network. It is a figure explaining the arrangement | positioning between local connection processor groups, and a connection relationship. It is another figure explaining the arrangement | positioning between local connection processor groups, and a connection relationship. It is a circuit diagram explaining a local connection network. It is another circuit diagram explaining a local connection network. It is another circuit diagram explaining a local connection network. It is another circuit diagram explaining a local connection network. It is another circuit diagram explaining a local connection network. It is another circuit diagram explaining a local connection network. It is another circuit diagram explaining a local connection network. It is another circuit diagram explaining a local connection network. It is another circuit diagram explaining a local connection network. It is an example of the circuit diagram of a processor element. It is a circuit diagram of the processor element of this Embodiment. FIG. 24 is a circuit diagram in the case where an arithmetic circuit for addition is constructed using the processor element of FIG. FIG. 25 is a circuit diagram when an arithmetic circuit for addition is constructed using the processor element of FIG. 24. It is a flowchart explaining the creation process of the configuration data in the reconfigurable integrated circuit device of the present embodiment. It is a flowchart figure which shows the starting sequence of the reconfigurable integrated circuit in this Embodiment. It is an example of an RTL description file. FIG. 30 is a diagram of a logic circuit that realizes the RTL description file of FIG. FIG. 31 is a diagram showing an example in which the processor elements of the logic circuit shown in FIG. 30 are connected using a local connection network and a global connection network in the present embodiment. FIG. 32 is a diagram for explaining a processor element to be tightly coupled in FIG.

  FIG. 1 is a schematic configuration diagram of a reconfigurable integrated circuit device related to the present embodiment. The reconfigurable (reconfigurable) integrated circuit device R_LSI includes a plurality of reconfiguration arrays R_ARRAY having a plurality of processor elements PE and an inter-processor element network NW for connecting the input and output thereof, and the processor elements PE. And an input / output port 10 for outputting data from the PE.

  The plurality of processor elements PE are an ALU having functions such as an adder, a multiplier, and a comparator, and a plurality of types of processor elements such as a delay circuit, a counter, and a selector. The processor element PE is constructed in an arbitrary state based on the configuration data. The inter-processor element network NW is constructed in an arbitrary connection state based on the configuration data. Therefore, by setting the configuration data, the reconfiguration array R_ARRAY can be reconfigured to an arbitrary data processing circuit by connecting a plurality of processor elements to an arbitrary state.

  In the reconfiguration array R_ARRAY in FIG. 1, a processor element PE having an ALU function, a processor element PE having a multiplier MPY function, a processor element PE having a memory RAM function, and a processor having a register file RegFile function Element PE etc. are included. The memory processor element stores, for example, table data.

  The reconfigurable integrated circuit device R_LSI further includes a configuration data memory 14 for storing a plurality of types of configuration data, and a reconfiguration for reading predetermined configuration data from the memory 14 and setting it in the reconfiguration array R_ARRAY. And a control circuit 12. The reconfiguration control circuit 12 is a group of registers having instruction codes for instructing, for example, reading data into a memory and setting configuration data, and corresponding instruction codes in response to events such as interrupt signals and status signals. Execute. By executing the instruction code, the corresponding configuration data is read from the configuration data memory 14 and set in the reconfiguration array R_ARRAY.

  The reconfigurable integrated circuit device R_LSI reads information including configuration data stored in an external memory 1 such as a flash memory, and via a decoder 18, the reconfiguration control circuit 12 and the configuration data memory 14 and the processor element are sorted and stored in either the register file RegFile or the memory RAM.

  Here, a logically designed file is logically synthesized by the RTL language, which is one of the hardware description languages, and information RD including configuration data generated by the logical synthesis is stored in the memory 1 outside the chip. . In the reconfigurable integrated circuit device R_LSI, for example, when the power is turned on, the built-in loader 16 reads the information RD from the external memory 1 and loads it into the reconfiguration array R_ARRAY or the configuration data memory 14. After the initial load, when the loader 16 outputs a ready signal to the reconfiguration control circuit 12, the reconfiguration control circuit 12 executes a predetermined instruction code, and stores the reconfiguration array R_ARRAY according to the configuration data. Build in the processing circuit. Note that the reconfigurable integrated circuit device R_LSI can also input configuration data from the CPU via the BUS without depending on the loader 16. When initialization is completed, the processing circuit built in the reconfiguration array processes input data from the input / output port 10 and outputs processed output data from the input / output port 10.

  FIG. 2 is a diagram showing a specific example of the reconfiguration array R_ARRAY related to the present embodiment. The processor elements PE0 to PE3, the memory processor element PE5, and the other processor elements PE4 are configured to be connectable via a selector 21 that is a switch in the inter-processor element network NW. Each processor element PE0 to PE5 can be constructed in an arbitrary configuration based on the configuration data CD0 to CD5. The selector 21 (21a, 21b, 21c) in the network NW can also be constructed in an arbitrary configuration based on the configuration data CDs.

  Each processor element PE outputs end signals CS0 to CS3 upon completion of the respective arithmetic processing. This end signal is given as an event to the reconfiguration control circuit 12, and the next configuration data CD is supplied to the processor element PE at an appropriate timing, and is constructed in another arithmetic circuit.

  The selector 21 includes a register 22 that stores configuration data CD and a selector circuit 23 that selects an input according to the data in the register 22, as shown as an example in the lower right of the figure. Further, a flip-flop 24 that latches the output of the selector circuit 23 in synchronization with the clock CK may be provided. The network NW also enables desired connection to the data input port 10 (IN) and the output port 10 (OUT) via a selector.

  FIG. 3 is another diagram showing a specific example of the reconfiguration array R_ARRAY related to the present embodiment. As illustrated, the processor element PE receives data from the inter-processor element network NW, the processing unit 32 processes the data, and the output unit 33 outputs the data to the network NW. Each processor element PE has a configuration data register 30 in which information including configuration data CD is set and held from the configuration data memory 14.

  Based on the information, the calculation unit 32 in the processor element PE has a predetermined function built in the calculation circuit. Similarly, the output unit 33 is constructed based on the information. Further, the information is stored in the RAM / REGFile 34 as table data or register values in the processor element PE of the memory or register file. The network NW is also constructed in an arbitrary connection state based on the configuration data CD.

(Embodiment)
FIG. 4 is a diagram showing an arrangement example of the processor elements PE in the present embodiment. As shown in the figure, a plurality of processor elements PE are arranged in an array in the reconfiguration array R_ARRAY in FIG. Note that broken lines in FIG. 4 indicate omitted processor elements.

  A group of processor elements included in the plurality of processor elements PE shown in FIG. 4 and having a predetermined number of processor elements PE adjacent to each other is referred to as a locally connected processor group. Here, a part of the locally connected processor group is denoted by reference numerals LC1 to LC3. In the example shown in FIG. 4, the predetermined number of processor elements PE is 9 (3 vertical × 3 horizontal), and adjacent to the eight vertical and horizontal diagonals around the central processor element PE in the locally connected processor group. Eight processor elements PE are provided. The processor elements PE in the locally connected processor group can be connected to each other via a local connection network described later.

  In the present embodiment, a reconfigurable integrated circuit device having a local connection network for connecting processor elements in a locally connected processor group and a global connection network for connecting locally connected processor groups will be described. According to this reconfigurable integrated circuit device, network resources, that is, the number of wires can be reduced. In the following example, the locally connected processor group LC1 is connected to the locally connected processor groups LC2 and LC3 via the global connection network. Here, the locally connected processor group LC1 does not share the processor element PE with the locally connected processor groups LC2 and LC3.

  FIG. 5 is a circuit diagram illustrating an example of a method for connecting the locally connected processor groups LC1 to LC3. FIG. 5 shows the connection of a plurality of processor elements PE arranged in an n × n matrix. The locally connected processor group LC1 includes a first processor element PE1_1 and eight second processor elements PE0_0, PE0_1, PE0_2, PE1_0, PE1_2, P2_0, PE2_1, PE2_2 adjacent to eight locations around the processor element PE1_1. Have The local connection networks LN1a and LN1b provided in the locally connected processor group LC1 have eight processor elements PE0_0, PE0_1, PE0_2, PE1_0, PE1_2, P2_0, and PE2_1 adjacent to the processor element PE1_1 at two inputs of the processor element PE1_1. , One of the outputs of PE2_2 is selected and supplied based on the configuration data CD.

  For this supply, the local connection networks LN1a and LN1b are provided corresponding to the respective input terminals of the processor element PE1_1, two input terminals in the illustrated example, and the eight second processor elements PE0_0 adjacent thereto are provided. There are local connection selectors SEL1_1a and SEL1_1b which select one of the outputs based on the configuration data CD and supply it to the two input terminals of the processor element PE1_1. With this configuration, the processor element PE1_1 can be connected to eight adjacent processor elements PE.

  Similarly, local connection networks similar to the local connection networks LN1a and LN1b are also provided in the locally connected processor groups LC2 and LC3, respectively.

  Any connection is possible if all the processor elements PE have an input selector that selects the output of all the processor elements PE based on the configuration data CD. However, this increases the number of network wires. Therefore, in the present embodiment, a local connection network LN1a, LN1b is provided for each local connection processor group including a limited number, for example, nine processor elements PE, and the remote processor elements PE are separated from each other. Signals selected from a plurality of processor elements PE in the locally connected processor group are connected by a global connection network. By using such a global connection network, the total number of network wires can be reduced.

  The global connection network GN1 provided for connecting the locally connected processor group LC1 and the locally connected processor group LC2 includes a plurality of processor elements PE0_l, PE0_m, PE0_n, PE1_l, PE1_n, in the second locally connected processor group LC2. One of the outputs of PE2_l, PE2_m, and PE2_n is selected based on the configuration data CD and supplied to the local connection networks LN1a and LN1b. Note that l is an integer of 3 or more, m is l + 1, n is l + 2, and m is 30 in the example of FIG.

  In order to supply signals from the locally connected processor group LC2 to the locally connected processor group LC1, the global connection network GN1 uses one of the outputs of the plurality of processor elements PE0_l in the locally connected processor group LC2 based on the configuration data CD. The global connection selector SEL1_mg is selected. The outputs of the eight processor elements PE0_l adjacent to the processor element 1_m in the locally connected processor group LC2 are input to the input terminal of the global connection selector SEL1_mg. Furthermore, the global connection network GN1 includes a global connection wiring Lg1 that connects the output of the global connection selector SEL1_mg and the input terminals of the local connection selectors SEL1_1a and SEL1_1b.

  Similarly, in order to supply signals from the locally connected processor group LC3 to the locally connected processor group LC1, the global connection network GN2 also has a global connection selector SELm_1g that connects the outputs of the eight processor elements PE in the locally connected processor group LC3, A global connection wiring Lg2 is provided for connecting the output of the global connection selector SELm_1g and the input terminals of the local connection selectors SEL1_1a and SEL1_1b in the local connection processor group LC1.

  In other words, the inputs of the local connection selectors SEL1_1a and SEL1_1b in the locally connected processor group LC1 are connected to other separated local connections in addition to the outputs of the eight second processor elements PE0_0 in the locally connected processor group LC1. The outputs (global connection networks GN1 and GN2) of the eight processor elements PE in the processor groups LC2 and LC3 are connected through global connection wirings Lg1 and Lg2. The local connection selectors SEL1_1a and SEL1_1b in the locally connected processor group LC1 are connected to the outputs of the processor elements PE0_0 and the like in the locally connected processor group LC1 and the globally connected networks GN1 and GN2 from the other locally connected processor groups LC2 and LC3. One of the outputs of the global connection selectors SEL1_mg and SEL1mg_2 is selected based on the configuration data CD and supplied to the input terminal of the processor element PE1_1.

  Note that one global connection network GN1 may be connected to the inputs of the local connection selectors SEL1_1a and SEL1_1b, instead of the plurality of global connection networks GN1 and GN2.

  FIG. 6 shows the local connection network LN1 and the global connection network GN1. In this example, the local connection selector SEL1_1a has a global connection selected from the outputs of the eight processor elements PE in the locally connected processor group LC1 and the outputs of the eight processor elements PE in the locally connected processor group LC2. The output of the wiring Lg1 is input.

  FIG. 7 is a circuit diagram illustrating another example of a method for connecting the locally connected processor groups LC1 to LC3. FIG. 7 illustrates an example of configuring a global connection network without providing a global connection selector.

  The global connection network GN11 connects the output of the first processor element PE1_m in the locally connected processor group LC2 and the input terminals of the local connection selectors SEL1_1a and SEL1_1b provided in the processor element PE1_1 in the locally connected processor group LC1. A global connection wiring Lg11 is provided.

  By connecting the global connection wiring Lg11 in this way, the local connection selectors SEL1_ma and SEL1_mb and the processor element PE1_m in the locally connected processor group LC2 can function as the global connection selector SEL1_mg. At this time, the processor element PE1_m in the locally connected processor group LC2 selects either the output of the arithmetic unit provided therein or the input of the processor element PE1_m based on the configuration data CD and outputs it to the output terminal. An output selector is preferably provided inside. With this configuration, the delay due to the processor element is reduced.

  Similarly, the global connection network GN12 of the locally connected processor group LC3 connects the output of the processor element PEm_1 in the locally connected processor group LC3 and the input terminals of the local connection selectors SEL1_1a and SEL1_1b in the locally connected processor group LC1. Connection wiring Lg12 is provided.

  In other words, the inputs of the local connection selectors SEL1_1a and SEL1_1b in the locally connected processor group LC1 are connected to other separated local connections in addition to the outputs of the eight second processor elements PE0_0 in the locally connected processor group LC1. The outputs of the eight processor elements PE in the processor groups LC2 and LC3 are connected via the global connection wirings Lg11 and Lg12 of the plurality of global connection networks GN1 and GN2.

  The local connection selectors SEL1_1a and SEL1_1b in the locally connected processor group LC1 are connected to the outputs of the processor element PE0_0 in the locally connected processor group LC1 and the globally connected networks GN11 and GN12 from the other locally connected processor groups LC2 and LC3 (processors). One of the outputs of the elements PE1_m and PEm_1) is selected based on the configuration data CD and supplied to the input terminal of the processor element PE1_1.

  FIG. 8 is a diagram showing the local connection network LN1 and the global connection wirings Lg11 and Lg12. In this example, the local connection selector SEL1_1a includes the outputs of the eight processor elements PE in the locally connected processor group LC1, and the global connection wiring Lg11 of the processor element PE1_m in the locally connected processor group LC2 shown in FIG. , The global connection wiring Lg12 of the processor element PEm_1 in the locally connected processor group LC3 is input.

  According to the present embodiment, since the locally connected processor group is connected using the global connection network, the number of wirings can be reduced. When connecting the processor element PE1_1 in the locally connected processor group LC1 and the eight processor elements PE of the locally connected processor group LC2 without using the global connection network, eight wires are required. However, if a global connection network is used, only one wire is required, and the number of wires can be greatly reduced. In this way, by connecting a large number of processor elements PE with a small number of wires, in the example of FIGS. 5 and 7, the processor element PE1_1 can be connected to 8 × 3 processor elements PE. Is greatly improved. In addition, since the connection is made using a dedicated global connection network, the delay time in signal transmission / reception can be greatly reduced.

  Further, when a logic circuit is configured using a plurality of processor elements PE, the plurality of processor elements PE can be locally concentrated and connected by a local connection network, so that network resources are not insufficient. On the other hand, local connection processors that are not frequently connected are connected via the global connection wiring, so that the placement and routing can be prevented from being crowded.

  9 to 11 are circuit diagrams illustrating specific examples of the global connection network. 9 to 11 correspond to the global connection network described in FIG.

  FIG. 9 is a circuit diagram in which the processor elements PE0_30, PE0_31, PE0_32, PE1_30, PE1_32, PE2_30, PE2_31, and PE2_32 of the global connection network shown in FIG. 6 are replaced with immediate value registers REG0 to REG7. Since there is little need to consider the output delay for the immediate value register, the register REG0 and the like are connected to the processor element PE1_1 using the global connection network.

  FIG. 10 is a circuit diagram in which the processor element PE2_2 shown in FIG. 9 is replaced with a processor element REG0 having a register function. In order to reduce the output delay of the register REG0, the register REG0 is connected to the processor element PE1_1 using a local connection network.

  FIG. 11 is obtained by adding a selector SELr that selects the output of REG0 and the output of SEL1_mg based on the configuration data CD and supplies the output to SEL1_1a to the configuration of FIG.

  In this way, the processor element PE that executes processing whose timing is critical is connected to the processor element PE1_1 using the local connection network, and the processor element PE that executes processing whose timing is not critical is connected to the processor element PE1_1 and the global connection network. By using and connecting, it is possible to construct a flexible network connection.

  FIG. 12 is a diagram for explaining the arrangement and connection relationship between locally connected processor groups. Assume that a plurality of processor elements PE are arranged in an array of 20 vertically and 20 horizontally, and a locally connected processor group is included in the plurality of processor elements.

  Here, a region including five vertical and five horizontal processor elements PE is referred to as a region A1. A local connection processor group is included in this area A1. The locally connected processor group may have three vertical and three horizontal processor elements PE like the locally connected processor group LC21, or four vertically and four horizontally like the locally connected processor group LC22. The processor element PE may be included. Further, the number of vertical processor elements PE and the number of horizontal processor elements PE may be different.

  For example, the locally connected processor group LC21, which is one of the locally connected processor groups, can be connected to the locally connected processor group LC23 using a global connection network. The locally connected processor group LC21 can be connected to the locally connected processor groups LC24, LC22, LC26, LC27, and LC28 separated by one or more locally connected processor groups using a global connection network. The locally connected processor group may share some processor elements with other locally connected processor groups. In FIG. 12, the locally connected processor group LC21 and the locally connected processor group LC29 share some processor elements PE21.

  The locally connected processor group LC21 is connected to the locally connected processor group LC24 using a global connection network to form a first globally connected processor. Similarly, the locally connected processor group LC25 is connected to the locally connected processor group LC26 using the global connection network to form a second globally connected processor. Then, the locally connected processor group LC21 may be connected to the locally connected processor group LC25 using a global connection network, and may be connected to the first and second global connection processors using a global connection network.

  FIG. 13 is another diagram for explaining the arrangement and connection relationship between locally connected processor groups. In FIG. 12, the area A1 has five vertical and horizontal processor elements PE. However, in FIG. 13, the area A2 has four vertical and four horizontal processor elements PE. This area A2 includes a group of locally connected processors.

  In FIG. 13, as described with reference to FIG. 12, the locally connected processor group LC31 can be connected to the locally connected processor groups LC32 and LC33 using a global connection network. Further, the locally connected processor group LC31 can be connected to the locally connected processor group LC34 separated by one or more locally connected processor groups using a global connection network.

  As described above, in the reconfigurable integrated circuit device according to the present embodiment, a plurality of locally connected processor groups can be arbitrarily arranged, and each locally connected processor group can be connected via a globally connected network. Therefore, the network connection of the processor element PE can be flexibly configured according to the circuit configuration.

  The local connection network in the local connection processor group will be described with reference to FIGS.

  FIG. 14 is a circuit diagram illustrating a local connection network. The input terminals of the local connection selectors SEL1_1a and SEL1_1b include the output signal lines L0_0, L0_1, L0_2, L1_0, L1_2 of the processor elements PE0_0, PE0_1, PE0_2, PE1_0, PE1_2, P2_0, PE2_1, and PE2_2 adjacent to the processor element PE1_1, L2_0, L2_1, and L2_2 are connected. Further, as described with reference to FIGS. 6 and 8, the global connection wiring Lg1 and the like are connected. The connection of the global connection wiring Lg2, etc. is omitted from the configuration of the drawing.

  The output signal line Ls1_1a of the selector SEL1_1a and the output signal line Ls1_1b of the selector SEL1_1b are connected to the input terminal of the processor element PE1_1, and the output signal line L1_1 is connected to the output terminal. The output signal line L1_1 is connected to an input terminal of a local connection selector provided in another adjacent processor element.

  With the above configuration, the local connection selectors SEL1_1a and SEL1_1b select the output of the adjacent processor element PE0_0 and the like and the output of the global connection selector SEL1_mg and the like based on the configuration data CD, and supply them to the input terminal of the processor element PE1_1 .

  FIG. 15 is another circuit diagram illustrating the local connection network. The processor element PE1_2 of the locally connected processor group LC41 also selects one of the eight processor elements PE0_1, PE0_2, PE0_3, PE1_1, PE1_3, PE2_1, PE2_2, and PE2_3 adjacent to it based on the configuration data CD Local connection selectors SEL1_2a and SEL1_2b are provided to input terminals of the processor element PE1_2. Although the connection of the global connection wiring Lg1 etc. is omitted in the configuration of the drawing, it is connected to the input terminals of the selectors SEL1_1a and SEL1_1b as described in FIG.

  The locally connected processor group LC1 and the other locally connected processor group LC41 share some processor elements PE0_1, PE0_2, PE1_1, PE1_2, PE2_1, and PE2_2. Thus, by arranging the locally connected processor groups in an overlapping manner, the size of the locally connected processor group can be freely changed. As a result, the network connection between the processor elements PE can be flexibly constructed.

  FIG. 16 is another circuit diagram illustrating the local connection network. The processor element PE2_1 in the locally connected processor group LC42 also selects one of the outputs of the adjacent processor elements PE1_0, PE1_1, PE1_2, PE2_0, PE2_2, PE3_0, PE3_1, and PE3_2 based on the configuration data CD. It has local connection selectors SEL2_1a and SEL2_1b that are supplied to the input terminals of PE2_1. Although the connection of the global connection wiring Lg1 etc. is omitted in the configuration of the drawing, it is connected to the input terminals of the selectors SEL1_1a and SEL1_1b as described in FIG.

  Also in FIG. 16, as described in FIG. 15, the locally connected processor group LC1 and the other locally connected processor groups LC41, LC42 share some processor elements PE1_1, PE1_2, PE2_1, PE2_2.

  17 and 18 are other circuit diagrams illustrating the local connection network. 17 and 18, the local connection of the processor element PE connected to the input / output port 10 shown in FIG. 1 will be described. The processor elements PE connected to the input / output port 10 correspond to the processor elements PE0_0 to PE0_33, PE0_0 to PE33_0, PE0_33 to PE33_33, and PE33_0 to PE33_33, which are the outer peripheral processor elements shown in FIG.

  The processor element PE0_0 in FIG. 17 selects one of the outputs of the four ports 10 (IN) and the outputs of the adjacent processor elements PE0_1, PE1_0, and PE1_1 based on the configuration data CD. It has local connection selectors SEL0_0a and SEL0_0b supplied to the input terminals.

  The processor element PE0_1 in FIG. 18 selects one of the outputs of the three ports 10 (IN) and the outputs of the adjacent processor elements PE0_0, PE0_2, PE1_0, PE1_1, and PE1_2 based on the configuration data CD. It has local connection selectors SEL0_1a and SEL0_1b that are supplied to the input terminals of the processor element PE0_1.

  Note that the outputs of the processor elements PE0_0, PE1_0, PE0_1, and PE0_2 can be connected to an output port.

  19 and 20 are other circuit diagrams illustrating the local connection network. In FIG. 5 and the like, the processor element PE is locally connected to all the adjacent processor elements PE, but an example in which the processor element PE is locally connected to some adjacent processor elements PE will be described.

  The local connection selectors SEL1_1a and SEL1_1b provided in the processor element PE1_1 in FIG. 19 configure the configuration data of one of the outputs of the adjacent processor elements PE0_0, PE0_2, PE1_0, PE1_2, PE2_0, and PE2_2 of the processor element PE1_1. Select based on CD and supply to the input terminal of the processor element PE1_1. The outputs of the processor elements PE0_1 and PE2_1 are not supplied to the input terminal of the processor element PE1_1.

  The local connection selectors SEL1_1a and SEL1_1b provided in the processor element PE1_1 in FIG. 20 are configured based on the configuration data CD, based on the configuration data CD. Is selected and supplied to the input terminal of the processor element PE1_1. The outputs of the processor elements PE1_0 and PE1_2 are not supplied to the input terminal of the processor element PE1_1.

  As described with reference to FIGS. 19 and 20, the local connection selectors SEL1_1a and SEL1_1b can connect the global connection wiring to the vacant input terminals by not locally connecting the adjacent processor elements PE. Therefore, the locally connected processor group LC1 can be connected to a plurality of locally connected processor groups as described with reference to FIGS.

  21 and 22 are other circuit diagrams illustrating the local connection network. 21 and 22, the connection of the processor element PE that feeds back the output of the processor element PE to its own input will be described. As shown in FIGS. 21 and 22, the output signal wiring L1_1 of the processor element PE1_1 is connected to the input terminals of the local connection selectors SEL1_1a and SEL1_1b provided in the processor element PE1_1.

  By feeding back the output in this way, the processor element PE1_1 can function as a selector that holds the output value (holds the previous value) depending on conditions, for example.

  Next, the processor element will be described with reference to FIGS. If the processor element PE can be used as simple wiring, the number of wirings for network connection can be reduced.

  FIG. 23 is an example of a circuit diagram of the processor element. The processor element PE50 includes an arithmetic unit 50a that executes predetermined arithmetic processing on the input signal INa and the input signal INb, and a register REGo that is provided in a subsequent stage of the arithmetic unit 50a and holds and outputs the output of the arithmetic unit 50a. Have.

  The register REGo provided in the output stage is a retiming register provided for reconfigurable integrated circuit devices to perform a large amount of arithmetic processing and data processing with a circuit structure suitable for pipeline and parallel processing. is there. The registers REGa and REGb provided in the input stage are also retiming registers, but are not necessarily required registers.

  The processor element PE50 outputs an output signal via such a retiming register. For this reason, it takes more than one cycle from when a signal is input until this signal is output. When such a processor element is used as a wiring, a delay occurs. That is, when such a processor element PE is used as a wiring, a latency of one cycle or more occurs every time a signal passes through the processor element PE.

  FIG. 24 is a circuit diagram of the processor element of the present embodiment. The processor element PE60 includes output selectors SELa and SELb that select one of the input terminal of the processor element PE60, the output of the arithmetic unit 60a, and the output of the register REGo based on the configuration data CD and output (OUT) to the output terminal. Have.

  That is, the first output selector SELa selects one of the input terminal of the processor element PE60 and the arithmetic unit 60a connected to this input terminal based on the configuration data CD, the register REGo, the second output Supply to selector SELb. The register REGo holds the output of the output selector SELa. The second output selector SELb selects either the output of the register REGo or the output selector SELa based on the configuration data CD and outputs it to the output terminal of the processor element PE60.

  With this configuration, the input signal INa is bypassed (through) the arithmetic unit 60a by the wiring L1, and is input to the output selector SELa. The input signal INa is input to the output selector SELb by bypassing the register REGo by the wiring L2. Further, the output of the arithmetic unit 60a bypasses the register REGo by the wiring L2 and is input to the output selector SELb.

  When the processor element PE60 is used as a wiring, the input signal INa can pass only through the output selectors SELa and SELb and pass through the processor element PE60, so that the output delay can be reduced.

  Further, when the output delay due to the register REGo is eliminated, the output signal of the arithmetic unit 60a can be output through the register REGo, so that the output delay of the output signal can be reduced.

  Here, an addition arithmetic circuit that adds the number A, the number B, and the number C and outputs the operation result X is constructed using an integrated circuit device that can be reconfigured.

  FIG. 25 is a circuit diagram in the case where the arithmetic circuit for addition is constructed using the processor element PE50 of FIG. The processor element PE51 adds (ADD) the numbers A and B and outputs the operation result to the processor element PE53.

  The processor element Delay52 is a delay adjustment processor element provided to cope with the output delay of the processor element PE51.

  The processor element PE53 adds the operation result of the processor element PE51 (added value of the number A and the number B) and the number C, and outputs the operation result X.

  In FIG. 25, a processor element Delay 52 for delay adjustment is provided. Therefore, the designer can simply rewrite the instruction that adds the number A, number B, and number C and outputs the operation result X in the RTL language as X = A + B + C. Cannot be executed by a simple integrated circuit device. This is because the above-described delay adjustment instruction is not described.

  Therefore, the processor element PE60 of FIG. 24 is used.

  FIG. 26 is a circuit diagram in the case where the arithmetic circuit for addition is constructed using the processor element PE60 of FIG. As shown in FIG. 26, a processor element PE61 is provided in place of the processor element PE51 of FIG. The processor element PE61 corresponds to the processor element PE60 in FIG. 24, and the addition result by the arithmetic unit 60a is input to the processor element PE53 through a register (register REGo in FIG. 24) provided therein. Further, the processor element for delay adjustment shown in FIG. 25 is eliminated, and a signal corresponding to the number C is directly input to the processor element PE53. As described above, such an arithmetic circuit can be constructed because the addition result of the arithmetic unit passes through the register and is input to the processor element PE53, so that the delay due to this register is eliminated and the processor element PE for delay adjustment is provided. This is because it becomes unnecessary.

  In this way, using a reconfigurable integrated circuit device having the processor element PE60 of FIG. 24, the designer simply describes the above instruction in the RTL language as X = A + B + C, and this instruction It can be executed by a reconfigurable integrated circuit device.

  The processor element PE61 in FIG. 26 corresponds to, for example, the processor element PE0_0 in FIG. Since the processor element PE0_0 has two or more input terminals as described with reference to FIG. 17, signals corresponding to the numbers A and B are input from these two input terminals. The processor element PE53 in FIG. 26 corresponds to the processor element PE3_0 in FIG. Since the processor element PE3_0 has one or more input terminals, a signal corresponding to several C is input from this input terminal. In addition, the processor element PE53 of FIG. 26 may correspond to, for example, the processor element PE3_1. At this time, if the processor elements PE1_0 and PE2_0 are used as wirings that pass through the arithmetic units and registers provided therein as described with reference to FIG. 24, the output delay described above does not occur.

  FIG. 27 is a flowchart for explaining a configuration data creation process in the reconfigurable integrated circuit device according to the present embodiment. First, the creation process using a tool will be described. First, the designer creates a circuit configuration and algorithm, and generates a circuit description file that describes the circuit configuration and algorithm in the RTL language. Furthermore, in addition to the circuit description file in the RTL language, the designer generates a circuit description file that combines the circuit cells in the library. This circuit description file becomes data of the logic circuit.

  Then, the designer compiles these circuit description files using a development tool (S10). By this compilation, logic synthesis is performed, and further placement and routing are performed (S11). In this placement and routing process, network connection information is determined. When a development tool is used, compilation is automatically executed by the development tool (S12). Then, configuration data is created by the development tool (S13). This configuration data is written into the flash memory 1 shown in FIG.

  Next, the process of creating configuration data by manual input will be described. First, the designer constructs a data flow based on a circuit configuration and algorithm created in advance (S14). Next, an instruction is set to the processor element PE (S15). Then, the designer manually performs placement and routing (S11, S16), and creates configuration data (S13).

  As described above, the reconfigurable integrated circuit device according to the present embodiment can be configured to have an arbitrary circuit configuration based on configuration data information obtained by logically synthesizing a circuit description file logically designed in the RTL language. It is possible to build.

  FIG. 28 is a flowchart showing a startup sequence of the reconfigurable integrated circuit device according to the present embodiment. When the power of the integrated circuit is turned on (S20), the built-in loader 16 instructs to read the flash memory 1 outside the chip (S21). As a result, reading of information including configuration data in the flash memory 1 starts (S22). The decoder 18 in the integrated circuit interprets the configuration information sequentially read from the flash memory 1, and reconfigures the control unit 12, the configuration data memory 14, the memory processor element RAM (PE), and the register file processor element RegFile. Distribute to (PE) etc. and install (S23).

  When the writing of the data is finished, for example, the loader 16 outputs a ready signal indicating that the setting of the configuration data is finished to the reconfiguration control unit 12. As a result, the reconfigurable integrated circuit device becomes operable (S24). In response to this ready signal, the reconfiguration control circuit 12 reads the first configuration data from the configuration data memory 14, loads it to the processor element PE or network NW in the reconfiguration array R_ARRAY, and performs the first processing. Build a circuit. Then, the constructed processing circuit performs signal processing of the constructed function on the input data (S25).

  FIG. 29 is an example of an RTL description file. Line 100 operates at the rising edge of CLK or the falling edge of RESET, and lines 101-103 are! If RESET = 1, it indicates that LO and HI are reset to 0. Lines 104-114 are LO = 0 if LO = 9, otherwise LO = LO + 1, and when LO = 9, HI = 0 if HI = 5 and HI = HI otherwise. It shows that it increments with +1. That is, the counter LO of the lower digits 0-9 and the counter HI of the upper digits 0-5 are shown.

  FIG. 30 is a diagram in which the logic circuit for realizing the RTL description file of FIG. 29 and the logic circuit are constructed in a reconfiguration array group. The comparator 81 determines whether LO is equal to the constant “4′h9”. If the determination result is YES = 1, the selector 83 selects the constant “4′h0” of the register 82 and the determination result is NO. If = 0, the selector 83 selects the LO + 1 of the adder 85, and if the selector 84 is COUNTON = 1, selects the output of the selector 83 as a new counter value. It shows holding. The above configuration is the lower counter.

  Further, the register 86, the comparator 87, the register 88, the selector 89, the adder 90, and the selector 92 have the same configuration as the above-described lower counter. Then, when the selector 91 is LO = 4, the output of the selector 89 is selected. When the selector 91 is other than LO = 4, the output is held and the output is not changed. These configurations are the upper counters.

  FIG. 31 is a diagram showing an example in which the processor elements of the logic circuit shown in FIG. 30 are connected using the local connection network and the global connection network in the present embodiment. The processor element indicated by reference numeral (80 to 92) in FIG. 30 and the processor element PE indicated by reference numeral (80 to 92) in FIG. 31 are the same.

  The left processor element PE group centering on the processor element PE2_1 corresponds to the LO counter of FIG. 30, and the right processor element PE group centering on the processor element PE2_31 corresponds to the HI counter of FIG.

  The processor element PE2_1 and the eight processor elements PE1_0, PE1_1, PE1_2, PE2_0, PE2_2, PE3_0, PE3_1, and PE3_2 centering on the processor element PE2_1 constitute a locally connected processor group. Furthermore, the processor element PE2_31 and the processor Assume that eight processor elements PE1_30, PE1_31, PE1_32, PE2_30, PE2_32, PE3_30, PE3_31, and PE3_32 centering on the element PE2_31 constitute a locally connected processor group.

  In the figure, the local connection selector is not shown, but is provided in each processor element PE.

  In FIG. 31, the processor element PE1_3 and the processor element PE1_30 are connected by the global connection wiring Lg21 as described in FIGS. 7 and 8, and the processor element PE3_1 and the processor element PE2_31 are as described in FIGS. Are connected by a global connection wiring Lg22.

  The signal COUNTON passes through the processor elements PE0_3 and PE1_3 (through) and is supplied to the processor element PE2_2. The signal COUNTON is supplied to the processor element PE1_30 via the global connection wiring Lg21, and further supplied to the processor element PE2_30 through the processor element PE1_30.

  The output of the processor element PE2_2 passes through the processor elements PE1_2 and PE0_2 and is output (LO). The output of the processor element PE2_30 passes through the processor elements PE1_31 and PE0_31 and is output (HI). As described with reference to FIG. 24, the processor elements PE0_3, PE1_3, PE1_2, PE1_30, and PE1_31 are processor elements that function as wiring, and output signals through the internal registers and arithmetic units.

  The COUNTON signal is a 1-bit signal. Therefore, the processor elements PE0_3, PE1_3, and PE1_30 that pass this signal are configured to have a 1-bit signal wiring.

  FIG. 32 is a diagram for explaining the processor elements PE2_1 and PE2_2 that are tightly coupled in FIG. Here, since the processor element PE that is tightly coupled functions as a selector, the tight coupling of the processor elements PE2_1 and PE2_2 is referred to as SEL connection.

  The signal lines Ls2_1a and Ls2_1b correspond to the output signal lines Ls1_1a and Ls1_1b in FIG. 14, and a local connection selector is provided above each of the signal lines Ls2_1a and Ls2_1b. Similarly, a local connection selector is provided above each of the signal lines Ls2_2a and Ls2_2b.

  Tightly coupled selectors SELc1 and SELc2 provided between the processor elements PE2_1 and PE2_2 connected in SLE supply the output of the processor element PE2_1 to the input of the processor element PEPE2_2. The selector SLEc1 selects and supplies either the output of the processor element PE2_1 or the output of the signal line Ls2_2a to the processor element PE2_2 based on the configuration data CD. The selector SLEc2 selects and supplies either the output of the processor element PE2_1 or the output of the signal line Ls2_2b to the processor element PE2_2 based on the configuration data CD. Note that the processor elements PE2_30 and PE2_31 in FIG. 31 are also SEL-connected in the same manner.

  By connecting frequently used processor elements PE using a selector for tight coupling, wiring delay can be minimized. In addition, if processor elements PE are tightly coupled, deep if-else statements, case statements, and combinational logic can be implemented efficiently. In particular, the tight coupling of the processor elements is suitable when configuring processor elements for selector and subtraction.

  According to the reconfigurable integrated circuit device of the present embodiment described above, the network connection between the processor elements can be optimally constructed.

  The above embodiment is summarized as follows.

(Appendix 1)
A reconfigurable integrated circuit device that is dynamically constructed in an arbitrary computation state based on configuration data,
A plurality of processor elements arranged in an array, each having a computing unit;
A plurality of locally connected processor groups included in the plurality of processor elements, each provided in each of the plurality of locally connected processor groups having a predetermined number of processor elements adjacent to each other; A plurality of local connection networks that select and supply one of the outputs of a plurality of second processor elements adjacent to the first processor element based on the configuration data to an input of the first processor element; ,
The input of the first processor element in the first locally connected processor group is the output of a plurality of processor elements in the second locally connected processor group that does not share the processor element with the first locally connected processor group. A reconfigurable integrated circuit device comprising a plurality of global connection networks that are selected and supplied based on the configuration data.

(Appendix 2)
In Appendix 1,
The reconfigurable integrated circuit device wherein the second locally connected processor group is located apart from the first locally connected processor group by one or more locally connected processor groups.

(Appendix 3)
In Appendix 1,
A reconfigurable integrated circuit device in which a plurality of locally connected processor groups each having the locally connected network share a part of processor elements with other locally connected processor groups.

(Appendix 4)
In any one of appendices 1 to 3,
The locally connected processor group includes the first processor element and eight second processor elements adjacent to the first processor element and eight diagonally upward, downward, leftward and rightward directions around the first processor element. A network is a reconfigurable integrated circuit device that selects either all eight or some second processor element outputs.

(Appendix 5)
In any one of appendices 1 to 4,
The local connection network is provided corresponding to each input terminal of the first processor element, and selects any one of the outputs of the second processor element based on the configuration data. A reconfigurable integrated circuit device having a selector for local connection supplied to the input terminal of the processor element.

(Appendix 6)
In Appendix 5,
The global connection network includes a global connection selector that selects any one of outputs of a plurality of processor elements in the second locally connected processor group based on the configuration data, an output of the global connection selector, A reconfigurable integrated circuit device comprising a global connection wiring that connects an input terminal of the local connection selector provided in a first processor element in the first local connection processor group.

(Appendix 7)
In Appendix 5,
The global connection network includes an output of a first processor element in the second locally connected processor group and an input of the local connection selector provided in the first processor element in the first locally connected processor group. A reconfigurable integrated circuit device having global connection wiring for connecting terminals.

(Appendix 8)
In Appendix 7,
The reconfigurable integrated circuit, wherein the first processor element includes an output selector that selects either the output of the arithmetic unit or the input terminal based on the configuration data and outputs the selected output terminal to the output terminal.

(Appendix 9)
In Appendix 5,
The input of the selector for local connection in the first locally connected processor group is supplied from the second locally connected processor group in addition to the output of the second processor element in the first locally connected processor group. Reconfigurable integrated circuit device to which a global connection network is connected.

(Appendix 10)
In Appendix 5,
The input of the selector for local connection in the first locally connected processor group includes a plurality of second locally connected processor groups in addition to the output of the second processor element in the first locally connected processor group. A reconfigurable integrated circuit device to which a plurality of global connection networks supplied from is connected.

(Appendix 11)
In any one of appendices 1 to 4,
The first processor element is further provided at a subsequent stage of the arithmetic unit, a register for holding the output of the arithmetic unit, an input terminal of the first processor element, an output of the arithmetic unit, and an output of the register A reconfigurable integrated circuit comprising: an output selector that selects any of the above based on the configuration data and outputs the selected data to an output terminal.

(Appendix 12)
In any one of appendices 1 to 4,
The first processor element further includes a first output selector that selects one of the input terminal of the first processor element and the arithmetic unit connected to the input terminal based on the configuration data. And a register for holding the output of the first output selector, and an output of the first processor element that selects either the output of the register or the output of the first output selector based on the configuration data A reconfigurable integrated circuit having a second output selector that outputs to a terminal.

PE ... Processor element, LC1 to LC3 ... Locally connected processor group, LN1a, LN1b ... Locally connected network, GN1, GN2, GN11, GN12 ... Globally connected network, SEL1_mg, SELmg_1 ... Globally connected selector, Lg1, Lg2, Lg11, Lg12 ... Global connection wiring, 60a ... Calculator, REGo ... Register, SELa, SELb ... Output selector

Claims (6)

A reconfigurable integrated circuit device that is dynamically constructed in an arbitrary computation state based on configuration data,
A plurality of processor elements arranged in an array, each having a computing unit;
A plurality of locally connected processor groups included in the plurality of processor elements, each provided in each of the plurality of locally connected processor groups having a predetermined number of processor elements adjacent to each other; A plurality of local connection networks that select and supply one of the outputs of a plurality of second processor elements adjacent to the first processor element based on the configuration data to an input of the first processor element; ,
The input of the first processor element in the first locally connected processor group is the output of a plurality of processor elements in the second locally connected processor group that does not share the processor element with the first locally connected processor group. A reconfigurable integrated circuit device comprising a plurality of global connection networks that are selected and supplied based on the configuration data. In claim 1,
The local connection network is provided corresponding to each input terminal of the first processor element, and selects any one of the outputs of the second processor element based on the configuration data. A reconfigurable integrated circuit device having a selector for local connection supplied to the input terminal of the processor element. In claim 2,
The global connection network includes a global connection selector that selects any one of outputs of a plurality of processor elements in the second locally connected processor group based on the configuration data, an output of the global connection selector, A reconfigurable integrated circuit device comprising a global connection wiring that connects an input terminal of the local connection selector provided in a first processor element in the first local connection processor group. In claim 2,
The global connection network includes an output of a first processor element in the second locally connected processor group and an input of the local connection selector provided in the first processor element in the first locally connected processor group. A reconfigurable integrated circuit device having global connection wiring for connecting terminals. In claim 2,
The input of the selector for local connection in the first locally connected processor group is supplied from the second locally connected processor group in addition to the output of the second processor element in the first locally connected processor group. Reconfigurable integrated circuit device to which a global connection network is connected. In claim 1,
The first processor element is further provided at a subsequent stage of the arithmetic unit, a register for holding the output of the arithmetic unit, an input terminal of the first processor element, an output of the arithmetic unit, and an output of the register A reconfigurable integrated circuit comprising: an output selector that selects any of the above based on the configuration data and outputs the selected data to an output terminal.

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