JP2012209297A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the same capable of suppressing reduction in an electron mobility and enhancing confinement of a two-dimensional electron gas.SOLUTION: A first nitride semiconductor layer 2 formed of AlInGaN (0≤a, b≤1, 0≤a+b≤1) and having a bandgap larger than that of a second nitride semiconductor layer 3, the second nitride semiconductor layer 3 formed of AlInGaN (0≤c, d≤1, 0≤c+d≤1), a back barrier layer 4 formed of InGaN (0<e≤1) and having a bandgap smaller than that of the second nitride semiconductor layer 3, a channel layer 5 formed of AlInGaN (0≤f, g≤1, 0≤f+g≤1) and having a bandgap equivalent to that of the second nitride semiconductor layer 3, and a barrier layer 6 formed of AlInGaN (0≤h, i≤1, 0≤h+i≤1) and having a bandgap larger than that of the channel layer 5, are laminated in this order on a substrate 1.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device such as a heterojunction field effect transistor using a nitride semiconductor and a manufacturing method thereof.

  A heterojunction field effect transistor using a nitride semiconductor is known as a high electron mobility transistor (abbreviation: HEMT). The HEMT has features such as a high breakdown electric field and high electron mobility compared to a transistor using silicon (Si) and a transistor using gallium arsenide (GaAs), and thus operates at high frequency and high output. Expected as a device.

  As the frequency increases, the gate length needs to be reduced. In the conventional HEMT, when the gate length is miniaturized, a so-called short channel effect occurs in which the modulation effect of the two-dimensional electron gas by the gate electrode is reduced. In order to suppress the occurrence of the short channel effect, it is effective to have a structure that enhances confinement of the two-dimensional electron gas.

  Non-Patent Document 1 discloses a back barrier structure in which a back barrier layer having a smaller band gap and a smaller thickness than the channel layer is inserted in the channel layer as a structure that enhances confinement of the two-dimensional electron gas. . Specifically, Non-Patent Document 1 discloses a HEMT in which an indium gallium nitride (InGaN) back barrier layer is inserted into an AlGaN / GaN channel layer composed of an aluminum gallium nitride (AlGaN) layer and a gallium nitride (GaN) layer. Is disclosed.

  The channel layer divided into two as an upper layer and a lower layer of the back barrier layer has a notch in the conduction band due to the polarization effect of the back barrier layer even if the band gap is the same. As a result, the conduction band of the channel layer under the back barrier layer is lifted to form a barrier. This barrier enhances the confinement of the two-dimensional electron gas.

  Patent Document 1 discloses a back barrier structure in which a plurality of back barrier layers are inserted in a channel layer. Specifically, Patent Document 1 discloses a structure in which a plurality of conduction channels made of InGaN are provided in a GaN channel layer to enhance carrier confinement in the conduction channel. The conduction channel corresponds to the back barrier layer.

Special table 2007-535138

T.A. T. Palacios, five others, “AlGaN / GaN High Electron Mobility Transistors with InGaN Back-Barriers”, IEEE ELECTRON DEVICE LETTERS), January 2006, Vol. 27 (Vol. 27), No. 1 (No. 1), p. 13-15

  In the technique disclosed in Non-Patent Document 1 described above, an InGaN back barrier layer having a small band gap and a relatively small thickness is formed in the GaN channel layer, and conduction of the GaN buffer layer, which is the lower layer of the back barrier layer, is performed. By lifting the band, the confinement of the two-dimensional electron gas is improved, and the problem that the short channel effect described above occurs is improved.

FIG. 2A of Non-Patent Document 1 discloses the gate voltage dependence of the mutual conductance g _{m in} a structure without an InGaN back barrier layer. Further, FIG. 2B of Non-Patent Document 1 discloses that the rise of the mutual conductance g _m is improved and the value of the mutual conductance g _m is increased by adopting the above-described InGaN back barrier structure. ing.

  However, in the InGaN back barrier structure disclosed in Non-Patent Document 1, the two-dimensional electron gas spreads not only to the channel layer but also to the lower layer of the channel layer. Therefore, it is required to further enhance the confinement of the two-dimensional electron gas.

  A semiconductor layer constituting a semiconductor device such as a HEMT is formed by crystal growth using, for example, a metal organic chemical vapor deposition (abbreviation: MOCVD) method. In MOCVD, a growth temperature of 1000 ° C. or higher is required to form a semiconductor layer with good crystallinity.

  However, when forming a nitride semiconductor layer containing In as disclosed in Non-Patent Document 1 and Patent Document 1 described above, in order to suppress In segregation due to a low melting point of In, for example, about Crystal growth is performed at a low temperature of 900 ° C.

  Further, Non-Patent Document 1 discloses that in order to sufficiently exhibit the effect of enhancing the confinement of the two-dimensional electron gas in the InGaN back barrier structure, the thickness of the GaN channel layer may be made relatively thin, such as about 10 nm to 20 nm. Preferred is disclosed. When such a relatively thin GaN channel layer is formed, crystal growth is performed at a low temperature.

  When crystal growth is performed at such a low temperature, there is a problem that the crystallinity of the GaN channel layer and the AlGaN channel layer is lowered, and the electron mobility is lowered.

  When the thickness of the GaN channel layer is relatively thin as described above, the two-dimensional electron gas distributed in the GaN channel layer is scattered by alloy scattering by the InGaN back barrier layer, which is a ternary alloy, and the electron mobility. There is a problem that decreases.

  An object of the present invention is to provide a semiconductor device in which a decrease in electron mobility is suppressed and confinement of a two-dimensional electron gas is enhanced, and a method for manufacturing the same.

The semiconductor device of the present invention is provided on a substrate and the substrate, and has a composition formula Al _a In _b Ga _{1-(a + b)} N (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, 0 ≦ a + b ≦ 1). a first nitride semiconductor layer made of nitride semiconductor represented by), the provided first nitride semiconductor layer, the composition formula _{Al c in d Ga 1- (c} + d) N (0 ≦ c ≦ 1, 0 ≦ d ≦ 1, 0 ≦ c + d ≦ 1), a second nitride semiconductor layer made of a nitride semiconductor, and a composition formula In _a third nitride semiconductor layer made of a nitride semiconductor represented by _e Ga _1-e N (0 <e ≦ 1); and a composition formula Al _f In _g provided on the third nitride semiconductor layer. A fourth nitride semiconductor layer made of a nitride semiconductor represented by Ga _{1- (f + g)} N (0 ≦ f ≦ 1, 0 ≦ g ≦ 1, 0 ≦ f + g ≦ 1); Provided on nitride semiconductor layer Is a composition formula _{Al h In i Ga 1- (h} + i) N (0 ≦ h ≦ 1,0 ≦ i ≦ 1,0 ≦ h + i ≦ 1) fifth nitride of a nitride semiconductor represented by A band gap of the first nitride semiconductor layer is larger than a band gap of the second nitride semiconductor layer, and a band gap of the third nitride semiconductor layer is the second gap semiconductor layer. The band gap of the fourth nitride semiconductor layer is equal to the band gap of the second nitride semiconductor layer, and the band gap of the fifth nitride semiconductor layer is smaller than the band gap of the fifth nitride semiconductor layer. Is larger than the band gap of the fourth nitride semiconductor layer.

In the method for manufacturing a semiconductor device of the present invention, a compositional formula Al _a In _b Ga _{1- (a + b)} N (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, 0 ≦ a + b ≦ 1) is formed on a substrate. A first layer forming step of forming a first nitride semiconductor layer with the represented nitride semiconductor, and a composition formula Al _c In _d Ga _{1- (c + d)} on the first nitride semiconductor layer; A second layer forming step of forming a second nitride semiconductor layer from a nitride semiconductor represented by N (0 ≦ c ≦ 1, 0 ≦ d ≦ 1, 0 ≦ c + d ≦ 1); A third layer forming step of forming a third nitride semiconductor layer on the nitride semiconductor layer with a nitride semiconductor represented by a composition formula In _e Ga _1-e N (0 <e ≦ 1); A nitride represented by the composition formula Al _f In _g Ga _{1− (f + g)} N (0 ≦ f ≦ 1, 0 ≦ g ≦ 1, 0 ≦ f + g ≦ 1) is formed on the third nitride semiconductor layer. By the semiconductor, the fourth A fourth layer forming step of forming a compound semiconductor layer, the fourth semiconductor layer, the composition formula _{Al h In i Ga 1- (h} + i) N (0 ≦ h ≦ 1,0 ≦ i ≦ A fifth layer forming step of forming a fifth nitride semiconductor layer with a nitride semiconductor represented by 1, 0 ≦ h + i ≦ 1), wherein in the first layer forming step, the first nitride The first nitride semiconductor layer is formed such that the band gap of the semiconductor layer is larger than the band gap of the second nitride semiconductor layer. In the third layer forming step, the third nitride is formed. Forming the third nitride semiconductor layer so that the band gap of the semiconductor semiconductor layer is smaller than the band gap of the second nitride semiconductor layer, and in the fourth layer forming step, The band gap of the nitride semiconductor layer is the band gap of the second nitride semiconductor layer. The fourth nitride semiconductor layer is formed so as to be equal to the step, and in the fifth layer forming step, the band gap of the fifth nitride semiconductor layer is the band of the fourth nitride semiconductor layer. The fifth nitride semiconductor layer is formed so as to be larger than the gap.

  According to the semiconductor device of the present invention, the first nitride semiconductor layer having a band gap larger than the band gap of the second nitride semiconductor layer is provided between the second nitride semiconductor layer and the substrate. It has been. Thereby, confinement of the two-dimensional electron gas at the interface between the fifth nitride semiconductor layer 6 functioning as a barrier layer and the fourth nitride semiconductor layer 5 functioning as a channel layer is improved, and good pinch-off characteristics are obtained. Can be obtained.

  In addition, the distribution of the two-dimensional electron gas does not collapse greatly even if the thickness of the fourth nitride semiconductor layer that is the channel layer is increased. Therefore, the influence of the alloy scattering of the third nitride semiconductor layer made of InGaN and functioning as the back barrier layer can be reduced, so that a decrease in electron mobility can be suppressed.

  In addition, since the thickness of the fourth nitride semiconductor layer that is the channel layer can be increased without increasing the confinement width of the two-dimensional electron gas, the crystallinity of the channel layer can be improved. As a result, the crystallinity and surface morphology of the heterointerface between the fourth nitride semiconductor layer as the channel layer and the fifth nitride semiconductor layer as the barrier layer can be improved, so that the electron mobility is improved. Can be made. Therefore, even if the gate length is shortened, the short channel effect can be suppressed, so that high-frequency characteristics can be improved, efficiency can be improved, and output can be increased by improving electron mobility.

  According to the method for manufacturing a semiconductor device of the present invention, the semiconductor device of the present invention having excellent effects as described above can be manufactured.

It is sectional drawing which shows the structure of the semiconductor device 100 which is one Embodiment of this invention. It is a graph which shows the band structure and carrier distribution of two-dimensional electron gas in the epitaxial structure of the semiconductor device of a prior art. It is a graph which shows the band structure and carrier distribution of two-dimensional electron gas in the epitaxial structure of the semiconductor device 100 which is one Embodiment of this invention. It is sectional drawing which shows the semiconductor device 101 which is another example of a semiconductor device. It is sectional drawing which shows the semiconductor device 102 which is another example of a semiconductor device. It is sectional drawing which shows the semiconductor device 103 which is another example of a semiconductor device. It is sectional drawing which shows the semiconductor device 104 which is another example of a semiconductor device. It is sectional drawing which shows the semiconductor device 105 which is another example of a semiconductor device. It is sectional drawing which shows the semiconductor device 106 which is another example of a semiconductor device. It is sectional drawing which shows the semiconductor device 107 which is another example of a semiconductor device. FIG. 6 is a cross-sectional view showing a state where the stacking of first to fifth nitride semiconductor layers 2 to 6 on substrate 1 is completed. It is sectional drawing which shows the state of the stage which completed formation of the source electrode 8a and the drain electrode 8b. FIG. 6 is a cross-sectional view showing a state where the formation of the element isolation region 9 is completed. It is sectional drawing which shows the state of the stage which completed formation of the gate electrode. It is sectional drawing which shows the state of the stage which the formation of the insulating film 10 was complete | finished. FIG. 6 is a cross-sectional view showing a state at a stage where the formation of the high concentration n-type impurity region 12 is completed. It is sectional drawing which shows the state of the stage which completed formation of the source electrode 8a and the drain electrode 8b. FIG. 6 is a cross-sectional view showing a state where the formation of the element isolation region 9 is completed. It is sectional drawing which shows the state in the stage where formation of the hole part 13 was complete | finished. It is sectional drawing which shows the state of the stage which the formation of the recess 14 was complete | finished. 7 is a cross-sectional view showing a state in which the removal of the insulating film 10 in the gate electrode formation region S has been completed. FIG. 7 is a cross-sectional view showing a state at a stage where the removal of the insulating film 70 in the gate electrode formation region S is completed. FIG. It is sectional drawing which shows the semiconductor device 108 which is another example of a semiconductor device. It is sectional drawing which shows the semiconductor device 109 which is another example of a semiconductor device.

  FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device 100 according to an embodiment of the present invention. Semiconductor device 100 in the present embodiment is a heterojunction field effect transistor (hereinafter sometimes simply referred to as “transistor”) using a nitride semiconductor.

  The semiconductor device 100 includes a substrate 1, a first nitride semiconductor layer 2, a second nitride semiconductor layer 3, a third nitride semiconductor layer 4, a fourth nitride semiconductor layer 5, and a fifth nitride semiconductor. A layer 6, a gate electrode 7, a source electrode 8a, a drain electrode 8b, an element isolation region 9 and an insulating film 10 are provided. The substrate 1 is a semi-insulating silicon carbide (SiC) substrate.

  A first nitride semiconductor layer 2 is provided on the surface on one side in the thickness direction of the substrate 1. A second nitride semiconductor layer 3 is provided on the surface of one side in the thickness direction of the first nitride semiconductor layer 2. A third nitride semiconductor layer 4 is provided on the surface of one side in the thickness direction of second nitride semiconductor layer 3. A fourth nitride semiconductor layer 5 is provided on the surface of one side in the thickness direction of the third nitride semiconductor layer 4. A fifth nitride semiconductor layer 6 is provided on the surface of one side in the thickness direction of the fourth nitride semiconductor layer 5.

  The first to fifth nitride semiconductor layers 2 to 6 are epitaxial crystal layers and are formed by epitaxial growth as will be described later. In the following description, the first to fifth nitride semiconductor layers 2 to 6 may be referred to as “epitaxial crystal layers”. The structure of the epitaxial crystal layer, that is, the structure of the first to fifth nitride semiconductor layers 2 to 6 may be referred to as an “epitaxial structure”. Further, the surface on one side in the thickness direction of the epitaxial crystal layer, that is, the surface on one side in the thickness direction of the fifth nitride semiconductor layer 6 may be referred to as “semiconductor surface”.

The first nitride semiconductor layer 2 is a nitride represented by the composition formula Al _a In _b Ga _{1− (a + b)} N (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, 0 ≦ a + b ≦ 1). Made of semiconductor. In the present embodiment, the first nitride semiconductor layer 2 is made of Al _0.03 Ga _0.97 N.

The second nitride semiconductor layer 3, the composition formula _{Al c In d Ga 1- (c} + d) N (0 ≦ c ≦ 1,0 ≦ d ≦ 1,0 ≦ c + d ≦ 1) nitride represented by Made of semiconductor. More specifically, the second nitride semiconductor layer 3, a composition formula _{Al c In d Ga 1- (c} + d) N (0 ≦ c ≦ 1,0 ≦ d ≦ 1,0 ≦ c + d ≦ 1) The nitride semiconductor is represented by a nitride semiconductor having a smaller band gap than the first nitride semiconductor layer 2. In the present embodiment, the second nitride semiconductor layer 3 is made of GaN having a smaller band gap than the first nitride semiconductor layer 2. Therefore, the band gap of the second nitride semiconductor layer 3 is smaller than the band gap of the first nitride semiconductor layer 2. In other words, the band gap of the first nitride semiconductor layer 2 is larger than the band gap of the second nitride semiconductor layer 3.

The third nitride semiconductor layer 4 is made of a nitride semiconductor represented by a composition formula In _e Ga _1-e N (0 <e ≦ 1). More specifically, the third nitride semiconductor layer 4 is a nitride semiconductor represented by the composition formula In _e Ga _1-e N (0 <e ≦ 1), and the second nitride semiconductor layer 3 It is made of a nitride semiconductor having a smaller band gap. In the present embodiment, the third nitride semiconductor layer 4 is made of In _0.15 Ga _0.85 N having a smaller band gap than the second nitride semiconductor layer 3. Therefore, the band gap of the third nitride semiconductor layer 4 is smaller than the band gap of the second nitride semiconductor layer 3.

The fourth nitride semiconductor layer 5, the composition formula _{Al f In g Ga 1- (f} + g) N (0 ≦ f ≦ 1,0 ≦ g ≦ 1,0 ≦ f + g ≦ 1) nitride represented by Made of semiconductor. More specifically, the fourth nitride semiconductor layer 5, by a composition formula _{Al f In g Ga 1- (f} + g) N (0 ≦ f ≦ 1,0 ≦ g ≦ 1,0 ≦ f + g ≦ 1) The nitride semiconductor is a nitride semiconductor having a band gap equal to that of the second nitride semiconductor layer 3. In the present embodiment, the fourth nitride semiconductor layer 5 is made of GaN having a band gap equal to that of the second nitride semiconductor layer 3. Therefore, the band gap of the fourth nitride semiconductor layer 5 is equal to the band gap of the second nitride semiconductor layer 3.

The fifth nitride semiconductor layer 6 is a nitride represented by the composition formula Al _h In _i Ga _{1− (h + i)} N (0 ≦ h ≦ 1, 0 ≦ i ≦ 1, 0 ≦ h + i ≦ 1). Made of semiconductor. More specifically, the fifth nitride semiconductor layer 6 has a composition formula Al _h In _i Ga _{1− (h + i)} N (0 ≦ h ≦ 1, 0 ≦ i ≦ 1, 0 ≦ h + i ≦ 1). The nitride semiconductor is represented by a nitride semiconductor having a larger band gap than the fourth nitride semiconductor layer 5. In the present embodiment, the fifth nitride semiconductor layer 6 is made of Al _0.2 Ga _0.8 N having a larger band gap than the fourth nitride semiconductor layer 5.

  Therefore, the band gap of the fifth nitride semiconductor layer 6 is larger than the band gap of the fourth nitride semiconductor layer 5. As described above, since the band gap of the fourth nitride semiconductor layer 5 is equal to the band gap of the second nitride semiconductor layer 3, the band gap of the fifth nitride semiconductor layer 6 is the second nitride. This is larger than the band gap of the semiconductor layer 3.

  Gate electrode 7 is provided on the surface of one side in the thickness direction of fifth nitride semiconductor layer 6. The gate electrode 7 functions as a Schottky electrode. The gate electrode 7 is composed of, for example, a nickel / gold (Ni / Au) bilayer film.

  The source electrode 8a and the drain electrode 8b are provided on the surface of one side in the thickness direction of the fifth nitride semiconductor layer 6 so as to face each other with the gate electrode 7 interposed therebetween. Both the source electrode 8 a and the drain electrode 8 b are provided at a distance from the gate electrode 7. The source electrode 8a and the drain electrode 8b function as ohmic electrodes. The source electrode 8a and the drain electrode 8b are made of, for example, a titanium / aluminum (Ti / Al) bilayer film.

  Of the surface on one side in the thickness direction of the fifth nitride semiconductor layer 6, at least a portion where the gate electrode 7, the source electrode 8 a and the drain electrode 8 b are not provided is covered with the insulating film 10. In other words, at least the exposed portion of the semiconductor surface is covered with the insulating film 10. Thus, the insulating film 10 is provided so as to cover the exposed part of the semiconductor surface at the minimum. However, the insulating film 10 may be provided so as to cover the exposed portion of the semiconductor surface and a part of each of the gate electrode 7, the source electrode 8a, and the drain electrode 8b.

  The element isolation region 9 isolates the transistor from other semiconductor elements provided on the substrate 1. In FIG. 1, the transistor is described as the semiconductor device 100. However, when a semiconductor element other than the transistor is provided over the substrate 1, the semiconductor device 100 includes the transistor and another semiconductor element. Also good.

  The element isolation region 9 is formed in the epitaxial crystal layer in a region other than the region where the transistor is formed. Specifically, the element isolation region 9 is formed in an epitaxial crystal layer between a region where a transistor is formed and a region where another semiconductor element is formed. In the present embodiment, element isolation region 9 is formed from the surface on one side in the thickness direction of fifth nitride semiconductor layer 6, which is the semiconductor surface, to the inside of fourth nitride semiconductor layer 5.

  Thus, the element isolation region 9 is formed from the surface on one side in the thickness direction of the fifth nitride semiconductor layer 6 to the inside of the fourth nitride semiconductor layer 5, but is not limited thereto. The nitride semiconductor layer 4 may be formed over the second nitride semiconductor layer 3, or the second nitride semiconductor layer 3 may be formed over the first nitride semiconductor layer 2. . In other words, the depth of the element isolation region 9 may be from the surface of the fifth nitride semiconductor layer 6 to the inside of the fourth nitride semiconductor layer 5, or inside the third nitride semiconductor layer 4. Up to the inside of the second nitride semiconductor layer 3 or up to the inside of the first nitride semiconductor layer 2.

  As described above, semiconductor device 100 of the present embodiment has a band gap larger than the band gap of second nitride semiconductor layer 3 between substrate 1 and second nitride semiconductor layer 3. A first nitride semiconductor layer 2 is provided. As a result, almost the entire two-dimensional electron gas 11 can be confined near the interface between the fifth nitride semiconductor layer 6 serving as a barrier layer and the fourth nitride semiconductor layer 5 serving as a channel layer. This will be specifically described below.

FIG. 2 is a graph showing a band structure and a carrier distribution of a two-dimensional electron gas in an epitaxial structure of a conventional semiconductor device. FIG. 3 is a graph showing the band structure and the carrier distribution of the two-dimensional electron gas in the epitaxial structure of the semiconductor device 100 according to the embodiment of the present invention. 2 and FIG. 3, the horizontal axis represents the distance [nm] from the surface on one side of the thickness direction of the semiconductor device, the left vertical axis represents energy [eV], and the right vertical axis represents the carrier concentration [cm]. ^-3 ].

  2 and 3, the line indicated by the symbol GC indicates the two-dimensional electron gas concentration, the line indicated by the symbol Ec indicates the energy level of the conduction band, and the line indicated by the symbol Ef. Indicates the Fermi level, and the line indicated by the symbol Ev indicates the energy level of the valence band. The graphs shown in FIGS. 2 and 3 show the results of calculating the band structure and the carrier distribution of the two-dimensional electron gas in the epitaxial structure of the semiconductor device using the one-dimensional band calculation simulator software.

FIG. 3 shows a band structure in an Al _0.2 Ga _0.8 N / GaN / In _0.15 Ga _0.85 N / GaN / Al _0.03 Ga _0.97 N structure, which is an epitaxial structure in the semiconductor device 100 of the present embodiment shown in FIG. And the carrier distribution of the two-dimensional electron gas are calculated using a one-dimensional band calculation simulator software. Here, “Al _0.2 Ga _0.8 N / GaN / In _0.15 Ga _0.85 N / GaN / Al _0.03 Ga _0.97 N” means that the nitride semiconductor constituting the first to fifth nitride semiconductor layers 2 to 6 is a semiconductor. In order from the surface side, that is, the fifth nitride semiconductor layer 6, the fourth nitride semiconductor layer 5, the third nitride semiconductor layer 4, the second nitride semiconductor layer 3, and the first nitride semiconductor layer 2. It shows in order.

In the calculation using the one-dimensional band calculation simulator software, the semiconductor device 100 shown in FIG. 1 includes a first nitride semiconductor layer 2 made of Al _0.03 Ga _0.97 N, a thickness of 200 nm, and a second nitride. The semiconductor layer 3 is made of GaN, the thickness is 50 nm, the third nitride semiconductor layer 4 as the back barrier layer is made of In _0.15 Ga _0.85 N, the thickness is 2 nm, and the channel layer A certain fourth nitride semiconductor layer 5 is made of GaN and has a thickness of 50 nm, and a fifth nitride semiconductor layer 6 which is a barrier layer is made of Al _0.2 Ga _0.8 N and has a thickness of 15 nm. Yes. The carrier concentration of each layer is 1 × 10 ¹⁶ cm ^−3, and the surface pinning energy of the fifth nitride semiconductor layer 6 that is a barrier layer is 1.42 eV.

FIG. 2 shows the results of calculating the band structure in the epitaxial structure and the carrier distribution of the two-dimensional electron gas in the conventional semiconductor device using the one-dimensional band calculation simulator software. As an epitaxial structure in a conventional semiconductor device, the barrier layer 56 is made of Al _0.2 Ga _0.8 N, its thickness is 15 nm, the channel layer 55 is made of GaN, its thickness is 15 nm, and the back barrier layer 54 _Is made of In _0.15 Ga _0.85 N, and its thickness is 2 nm. A GaN buffer layer is provided between the back barrier layer 54 and the substrate, and its thickness is 200 nm. The carrier concentration of each layer is 1 × 10 ¹⁶ cm ^−3, and the surface pinning energy of the barrier layer 56 is 1.42 eV.

The epitaxial structure in the conventional semiconductor device used for the calculation in FIG. 2 corresponds to the epitaxial structure disclosed in Non-Patent Document 1 described above. FIG. 1 of Non-Patent Document 1 shows a band structure of a valence band in an InGaN back barrier structure. Further, FIG. 2 of Non-Patent Document 1 shows a result calculated using a one-dimensional band calculation simulator software in order to examine the carrier concentration distribution. From FIG. 2 of Non-Patent Document 1, it can be seen that the two-dimensional electron gas distributed with a high carrier concentration of 1 × 10 ¹⁷ cm ⁻³ or more is distributed throughout the GaN channel layer.

  The results shown in FIG. 1 and FIG. 2 of Non-Patent Document 1 are the same as the results shown in FIG. That is, as shown in FIG. 2, in the epitaxial structure in the conventional semiconductor device, the distribution of the two-dimensional electron gas 11 extends not only to the channel layer 55 but also to the lower layer of the channel layer 55. Therefore, even if the thickness of the channel layer 55 is changed, the distribution of the two-dimensional electron gas 11 can be seen throughout the channel layer 55.

  On the other hand, in the case of the semiconductor device 100 of the present embodiment, as shown in FIG. 3, the distribution of the two-dimensional electron gas 11 is independent of the thickness of the fourth nitride semiconductor layer 5 that is the channel layer. The entire structure is confined near the interface between the fifth nitride semiconductor layer 6 serving as a barrier layer and the fourth nitride semiconductor layer 5 serving as a channel layer. This is considered to be because the first nitride semiconductor layer 2 having a band gap larger than the band gap of the second nitride semiconductor layer 3 is provided.

  That is, as in the present embodiment, by providing the first nitride semiconductor layer 2 having a band gap larger than the band gap of the second nitride semiconductor layer 3, the two-dimensional electron gas 11 is caused to flow into the barrier layer. 6 and the channel layer 5 can be confined near the interface.

  As described above, since the confinement of the two-dimensional electron gas 11 can be enhanced in this embodiment, even when the gate length of the gate electrode 7 is shortened, the modulation of the two-dimensional electron gas 11 is controlled by the gate electrode 7. be able to. In other words, the short channel effect can be suppressed. Therefore, it is possible to improve transistor characteristics in a high frequency region including efficiency improvement.

  As described above, according to the present embodiment, the second nitride semiconductor layer 3 is disposed between the second nitride semiconductor layer 3 and the substrate 1, that is, below the second nitride semiconductor layer 3 immediately below the back barrier layer 4. A first nitride semiconductor layer 2 having a band gap larger than that of the nitride semiconductor layer 3 is provided. As a result, the confinement of the two-dimensional electron gas 11 at the interface between the barrier layer 6 and the channel layer 5 can be improved, and good pinch-off characteristics can be obtained.

  Further, the distribution of the two-dimensional electron gas 11 does not collapse greatly even if the thickness of the channel layer 5 is increased as shown in FIG. Therefore, the influence of the alloy scattering of the back barrier layer 4 made of InGaN can be reduced, so that the decrease in electron mobility can be suppressed.

  Moreover, since the thickness of the channel layer 5 can be increased without increasing the confinement width of the two-dimensional electron gas 11, the crystallinity of the channel layer 5 can be improved. Thereby, the crystallinity and surface morphology of the hetero interface between the channel layer 5 and the barrier layer 6 can be improved, so that the electron mobility can be improved. Therefore, even if the gate length is shortened, the short channel effect can be suppressed, so that high frequency characteristics can be improved, efficiency can be improved, and output can be increased by improving electron mobility.

  As described above, in this embodiment, it is possible to realize the semiconductor device 100 in which the decrease in the electron mobility is suppressed and the confinement of the two-dimensional electron gas is increased, so that the high frequency characteristics of the semiconductor device 100 can be improved. Higher output can be achieved by increasing efficiency and improving electron mobility.

  The epitaxial structure is not limited to the configuration of the present embodiment, and an epitaxial structure having the following configuration may be used.

For example, a structure in which the band gap is equal to each layer of the epitaxial structure in the present embodiment, and the lattice constant of the third nitride semiconductor layer 4 that is the back barrier layer is equal to the lattice constant of each of the other layers. . Such epitaxial structures, for example, a _{Al 0.489 In 0.26 Ga 0.215 N /} Al 0.242 In 0.247 Ga 0.511 N / In 0.15 Ga 0.85 N / Al 0.242 In 0.247 Ga 0.511 N / Al 0.279 In 0.255 Ga 0.466 N structure.

In this epitaxial structure, the lattice constants of the nitride semiconductor layers 2, 3, 5, 6 other than the third nitride semiconductor layer 4 are lattices of In _0.15 Ga _0.85 N constituting the third nitride semiconductor layer 4. It is equal to a constant. The band gap of each layer of this epitaxial structure is the band gap of each layer of the Al _0.2 Ga _0.8 N / GaN / In _0.15 Ga _0.85 N / GaN / Al _0.03 Ga _0.97 N structure, which is the epitaxial structure in the present embodiment. It is equal to.

Thereby, the same effect as that obtained with the Al _0.2 Ga _0.8 N / GaN / In _0.15 Ga _0.85 N / GaN / Al _0.03 Ga _0.97 N structure, which is the epitaxial structure in the present embodiment, can be obtained. Further, since a lattice matching system in which the lattice constants of the respective layers are matched is obtained, a structure in which no distortion occurs in the epitaxial crystal can be configured. Therefore, the reliability of the transistor can be improved.

  That is, the composition of aluminum (Al), indium (In), and gallium (Ga) in each of the first, second, fourth, and fifth nitride semiconductor layers 2, 3, 5, and 6 is changed to the first, second, and second compositions. The semiconductor device 100 is configured by selecting the lattice constants of the fourth and fifth nitride semiconductor layers 2, 3, 5, and 6 and the lattice constant of the third nitride semiconductor layer 4 to coincide with each other. The lattice constant of the nitride semiconductor layer to be matched can be matched. Accordingly, it is possible to prevent distortion from occurring in the epitaxial crystal, so that the reliability of the semiconductor device 100 can be improved.

  A heterojunction field effect transistor using a nitride semiconductor has a higher breakdown voltage as the breakdown electric field of the semiconductor material used for the channel layer 5 is higher. In the present embodiment, from the viewpoint of increasing the breakdown voltage, the band gap of each of the first to fifth nitride semiconductor layers 2 to 6 satisfies the above relationship, and the fourth nitride which is a channel layer The semiconductor layer 5 and the second nitride semiconductor layer 3, which is immediately below the back barrier layer, are made of a nitride semiconductor having the same composition, and the band gap of the second and fourth nitride semiconductor layers 3 and 5. Is 3.47 eV or more.

Specifically, the fourth nitride semiconductor layer 5 that is the channel layer and the second nitride semiconductor layer 3 that is the immediately lower layer of the back barrier layer are composed of the composition formula Al _c In _d Ga _{1-(c + d).} It is composed of a nitride semiconductor represented by N, and the compositions d and c of aluminum (Al) and indium (In) are selected so as to satisfy d ≧ {(2.73 / 2.67) × c}.

  Thereby, the band gap of the fourth nitride semiconductor layer 5 that is the channel layer can be set to 3.47 eV or more that is the band gap of GaN. Therefore, in addition to the above-described effects, the breakdown voltage can be improved, and a high breakdown voltage can be realized.

  In the present embodiment described above, only the minimum necessary elements that operate as a transistor are described, but the semiconductor device 100 finally has a structure in which a protective film, a wiring, a via hole, and the like are formed. Used as a device.

  In the present embodiment, the substrate 1 is a semi-insulating SiC substrate, but is not limited to this, and is a substrate made of, for example, silicon (Si), sapphire, gallium nitride (GaN), or aluminum nitride (AlN). It may be.

  Further, the source electrode 8a and the drain electrode 8b are not necessarily composed of a Ti / Al bilayer film. The source electrode 8a and the drain electrode 8b only have to have ohmic characteristics. Titanium (Ti), aluminum (Al), niobium (Nb), hafnium (Hf), zirconium (Zr), strontium (Sr), nickel (Ni ), Tantalum (Ta), gold (Au), platinum (Pt), vanadium (V), molybdenum (Mo) or tungsten (W), or a multilayer film composed of these metals. .

Further, the gate electrodes 7 and 71 are not necessarily formed of a nickel / gold (Ni / Au) bilayer film. The gate electrodes 7 and 71 are made of metal such as titanium (Ti), aluminum (Al), platinum (Pt), gold (Au), nickel (Ni), palladium (Pd), iridium silicide (IrSi), platinum silicide (PtSi). ), A silicide such as nickel silicide (NiSi ₂ ), or a single layer film made of a nitride metal such as titanium nitride (TiN), tungsten nitride (WN), or tantalum nitride (TaN), or these single layer films It may be formed of a multilayer film composed of

  The insulating film 10 includes at least one of aluminum (Al), gallium (Ga), silicon (Si), hafnium (Hf), titanium (Ti), zirconium (Zr), tantalum (Ta), vanadium (V), and the like. It may be formed of a single layer film composed of oxide, nitride, oxynitride or the like of one or more kinds of atoms, or may be formed of a multilayer film composed of these single layer films.

  The semiconductor device may have the configuration shown in FIGS. FIG. 4 is a cross-sectional view showing a semiconductor device 101 as another example of the semiconductor device. As shown in FIG. 4, in the nitride semiconductor layer on the lower side of the source electrode 8a and the drain electrode 8b, that is, on the substrate 1 side, a high concentration which is a region doped with an n-type impurity at a high concentration. An n-type impurity region 12 may be formed.

  With such a structure, the contact resistance between the source electrode 8a and the drain electrode 8b and the nitride semiconductor layer in contact with them can be reduced. In addition, the resistance between the two-dimensional electron gas 11 generated on the barrier layer 6 side of the channel layer 5 and the source electrode 8a and the drain electrode 8b can be reduced. Therefore, the structure shown in FIG. 4 is more preferable than the structure shown in FIG. 1 because it is advantageous in increasing the efficiency of the semiconductor device as a transistor and increasing the output power by increasing the current.

  High-concentration n-type impurity region 12 is formed by injecting, for example, Si into the nitride semiconductor layer as an n-type impurity. The high-concentration n-type impurity region 12 is not necessarily formed by implanting Si, and it is sufficient that the n-type impurity is doped at a high concentration. Specifically, the high-concentration impurity region 12 is doped with a material that forms an n-type impurity level in a nitride semiconductor, such as Si, oxygen atoms (O), and carbon atoms (C), at a high concentration. Just do it. As described above, the high-concentration impurity region 12 can be formed by doping with a material that forms an n-type impurity level in the nitride semiconductor, but is not limited thereto, and is formed by forming a nitrogen vacancy, for example. May be. In this case, nitrogen vacancies need only be formed in the high concentration impurity region 12 at a high concentration.

  In FIG. 4, the high-concentration n-type impurity region 12 is formed from the surface of the fifth nitride semiconductor layer 6 that is the semiconductor surface to the region that reaches the fourth nitride semiconductor layer 5 that is the channel layer. Yes. The region where the high-concentration n-type impurity region 12 is formed is not necessarily limited to the region shown in FIG. 4, and may be larger or smaller than the region shown in FIG. That is, the high-concentration n-type impurity region 12 may be formed in at least a part of the nitride semiconductor layer below the source electrode 8a and the drain electrode 8b. As described above, if the high-concentration n-type impurity region 12 is formed in at least part of the nitride semiconductor layer below the source electrode 8a and the drain electrode 8b, the above-described effect can be obtained.

  FIG. 5 is a cross-sectional view showing a semiconductor device 102 which is still another example of the semiconductor device. A portion of the nitride semiconductor layer below the source electrode 8a and the drain electrode 8b in the semiconductor device 100 shown in FIG. 1, that is, on the substrate 1 side, may be removed as shown in FIG. In this case, the removed portion of the nitride semiconductor layer is filled with the source electrode 18a and the drain electrode 18b. In FIG. 5, a part of the fifth nitride semiconductor layer 6 is removed to form a hole 13, and the hole 13 is filled with a part of the source electrode 18 a and the drain electrode 18 b.

  By adopting the structure shown in FIG. 5, the resistance between the two-dimensional electron gas 11 generated on the barrier layer 6 side of the channel layer 5 and the source electrode 18a and the drain electrode 18b can be reduced. Therefore, the structure shown in FIG. 5 is more preferable than the structure shown in FIG. 1 because it is more advantageous for higher efficiency of the semiconductor device as a transistor and higher output by increasing current.

  In FIG. 5, the nitride semiconductor layers 2 to 6 below the source electrode 18 a and the drain electrode 18 b are formed from the surface of the fifth nitride semiconductor layer 6 that is the semiconductor surface, that is, the surface of the barrier layer 6. The region up to the lower layer is removed. The limit of the depth direction in which the nitride semiconductor layers 2 to 6 are removed is limited to the interface between the fourth nitride semiconductor layer 5 that is a channel layer and the fifth nitride semiconductor layer 6 that is a barrier layer. If at least a part of the nitride semiconductor layer below the source electrode 18a and the drain electrode 18b is removed, the above-described effect can be obtained.

  FIG. 6 is a cross-sectional view showing a semiconductor device 103 which is still another example of the semiconductor device. The gate electrode may be provided so as to be embedded in the recess 14 like the gate electrode 17 shown in FIG. The bottom portion of the gate electrode 17 shown in FIG. 6 is buried in a recess 14 formed in the fifth nitride semiconductor layer 6 that is a barrier layer. The recess 14 is formed by removing a part of the barrier layer 6 by etching or the like. Therefore, the bottom surface of the gate electrode 17 is not in contact with the surface formed by epitaxial growth of the barrier layer 6.

  As shown in FIG. 1 described above, when the bottom surface of the gate electrode 7 is in contact with the surface formed by epitaxial growth of the barrier layer 6, current coplus may be generated. Here, “current coplus” refers to a phenomenon in which the on-resistance value in a high-voltage operation becomes higher than the on-resistance value of a transistor in a low-voltage operation. The current coplus is considered to be caused by the fact that the electric field concentrates on the edge of the gate electrode during high voltage operation and the electrons are accelerated, and the electrons are trapped in defects on the surface of the epitaxial crystal layer and interface states.

  As shown in FIG. 1 described above, when the bottom surface of the gate electrode 7 is in contact with the surface formed by epitaxial growth of the barrier layer 6, the semiconductor surface between the gate electrode 7 and the drain electrode 8b and the vicinity thereof are disposed. A virtual gate is formed due to the influence of electrons trapped in the formed defects and interface states. This makes it difficult to control the two-dimensional electron gas 11 by controlling the potential of the original gate electrode 7 and causes current collapse.

  On the other hand, if the bottom surface of the gate electrode 17 is not in contact with the surface formed by epitaxial growth of the barrier layer 6, as shown in FIG. The distance to the electron gas 11 is shortened. This facilitates the control of the two-dimensional electron gas 11 by controlling the potential of the gate electrode 17 and reduces the influence of electron traps on the semiconductor surface. Therefore, current collapse can be suppressed and mutual conductance can be increased.

  FIG. 7 is a cross-sectional view showing a semiconductor device 104 which is still another example of the semiconductor device. In FIGS. 1 and 4 to 6 described above, the gate electrode 7 has a square cross-sectional shape. The cross-sectional shape of the gate electrode is not necessarily a square shape. The gate electrode may be, for example, a T-type gate electrode (hereinafter also referred to as “T-type gate electrode”) 71 as shown in FIG. 7 or a Y-type gate electrode. Thus, by making the cross-sectional shape of the gate electrode 71 a T-type structure or a Y-type structure, the gate resistance can be reduced while maintaining the area where the gate electrode 71 is in contact with the semiconductor. Specifically, the gate electrode 71 can maintain an area in contact with the fifth nitride semiconductor layer 6 that is a barrier layer, and the gate resistance can be reduced.

  FIG. 8 is a cross-sectional view showing a semiconductor device 105 which is still another example of the semiconductor device. In FIG. 7 described above, the structure in which the part of the T-type gate electrode 71 is not in contact with the insulating film 10 is shown. However, as shown in FIG. 8, the structure in which the part of the T-type gate electrode 72 is in contact with the insulating film 10. It may be. By adopting a structure in which the subordinate portion of the T-type gate electrode 72 is in contact with the insulating film 10, the electric field concentrated on the edge portion on the drain electrode 8 b side of the gate electrode 72 can be reduced during high voltage operation. As a result, current collapse can be suppressed and the breakdown voltage can be increased.

  FIG. 9 is a cross-sectional view showing a semiconductor device 106 which is still another example of the semiconductor device. In FIG. 8 described above, the insulating film 10 is formed on the entire surface of the barrier layer 6 on one side in the thickness direction where at least the gate electrode 72, the source electrode 8a, and the drain electrode 8b are not formed. However, the present invention is not limited to this, and the insulating film 70 may be formed only on the part under the gate electrode 71 as shown in FIG. Thus, by forming the insulating film 70 only in the part under the gate electrode 71, the capacitance generated between the source electrode 8a and the gate electrode 71 and between the gate electrode 71 and the drain electrode 8b can be reduced. Can do. As a result, the gain and efficiency during high-frequency operation can be improved.

  FIG. 10 is a cross-sectional view showing a semiconductor device 107 which is still another example of the semiconductor device. The above-described structures shown in FIGS. 4 to 9 do not have to be individually adopted, and may be combined as shown in FIG. 10, for example. In the semiconductor device 107 shown in FIG. 10, the bottom of the T-type gate electrode 73 is embedded in the recess 14.

  Next, a method for manufacturing the semiconductor device 100 according to the embodiment of the present invention shown in FIG. 1 will be described. 11 to 20 are views for explaining a method of manufacturing the semiconductor device 100 according to the embodiment of the present invention.

  FIG. 11 is a cross-sectional view showing a state where the stacking of the first to fifth nitride semiconductor layers 2 to 6 on the substrate 1 has been completed. First, for example, a substrate 1 made of sapphire, silicon carbide (SiC), gallium nitride (GaN), Si, or the like is prepared. In the present embodiment, a SiC substrate is prepared as the substrate 1.

  Next, the first nitridation is performed on the surface on one side in the thickness direction of the substrate 1 by, for example, a molecular beam epitaxy (abbreviation: MBE) method or a chemical vapor deposition (abbreviation: CVD) method. The semiconductor layer 2, the second nitride semiconductor layer 3, the third nitride semiconductor layer 4, the fourth nitride semiconductor layer 5, and the fifth nitride semiconductor layer 6 are stacked in this order. As described above, the third nitride semiconductor layer 4 functions as a back barrier layer. The fourth nitride semiconductor layer 5 functions as a channel layer. The fifth nitride semiconductor layer 6 functions as a barrier layer.

In the present embodiment, a structure of Al _0.2 Ga _0.8 N / GaN / In _0.15 Ga _0.85 N / GaN / Al _0.03 Ga _0.97 N is epitaxially grown on the SiC substrate as the first to fifth nitride semiconductor layers 2 to 6. The case where it is made to explain is demonstrated.

  The band gap of the first nitride semiconductor layer 2 affects the confinement of the two-dimensional electron gas 11 distributed at a high concentration in the fourth nitride semiconductor layer 5 that is the channel layer. Therefore, the band gap of the first nitride semiconductor layer 2 is desirably larger than that of the second nitride semiconductor layer 3 having a band gap equal to that of the channel layer 5. From this, the composition of Al, In and Ga in the nitride semiconductor constituting the first nitride semiconductor layer 2 is such that the band gap of the first nitride semiconductor layer 2 is that of the second nitride semiconductor layer 3. It is desirable to choose so as to be larger than the band gap.

The thickness dimension of the first nitride semiconductor layer 2 (hereinafter sometimes referred to as “thickness”) is preferably a thickness that does not affect the upper epitaxial crystal layer due to lattice mismatch with the substrate 1. Specifically, the thickness of the first nitride semiconductor layer 2 is desirably 100 nm or more and 1000 nm or less. Thus, by increasing the thickness of the first nitride semiconductor layer 2 to 100 nm or more and 1000 nm or less, the crystallinity of the first nitride semiconductor layer 2 is improved, and the second nitride semiconductor layer 3 and subsequent layers to be stacked thereafter are formed. The crystallinity of the nitride semiconductor layer can be improved. In the present embodiment, the first nitride semiconductor layer 2 is made of Al _0.03 Ga _0.97 N and has a thickness of 200 nm.

  In the present embodiment, the second nitride semiconductor layer 3 and the fourth nitride semiconductor layer 5 that is the channel layer are made of GaN and have a thickness of 50 nm. The thickness of the second and fourth nitride semiconductor layers 3 and 5 is not limited to this, but is smaller than the thickness of the first nitride semiconductor layer 2 and the third nitride semiconductor layer. A thickness greater than 4 is selected. Specifically, the thickness of the second and fourth nitride semiconductor layers 3 and 5 is desirably 10 nm or more and 200 nm or less. Within this range, it is desirable that the thickness of the second nitride semiconductor layer 3 is particularly thick. By increasing the thickness of the second nitride semiconductor layer 3 to, for example, about 200 nm, the crystallinity of the second nitride semiconductor layer 3 is improved, and the third nitride semiconductor layer 4 stacked thereafter is used. The crystallinity of a certain InGaN layer can be improved.

As described above, the third nitride semiconductor layer 4 serving as the back barrier layer is made of a nitride semiconductor represented by the composition formula In _e Ga _1-e N (0 <e ≦ 1). The band gap of the third nitride semiconductor layer 4 is made smaller than the band gap of the second nitride semiconductor layer 3 and the fourth nitride semiconductor layer 5.

  The second nitride semiconductor layer 3 and the fourth nitride semiconductor layer 5 are upper and lower layers of the third nitride semiconductor layer 4 and have the same band gap. By making the band gap of the third nitride semiconductor layer 4 smaller than the band gap of the second and fourth nitride semiconductor layers 3 and 5 as described above, An energy difference (hereinafter sometimes referred to as “notch”) can be generated in the fourth nitride semiconductor layer 5. This energy difference becomes a barrier against electrons, that is, a back barrier.

  Therefore, it is desirable that the thickness of the third nitride semiconductor layer 4 serving as the back barrier layer be as small as about 5 nm or less because a steep band gap difference can be generated. However, when the band gap of the third nitride semiconductor layer 4 is made smaller than the band gaps of the second and fourth nitride semiconductor layers 3 and 5 as described above, formation of holes, that is, holes, is not possible. It is desirable that the band gap is such that it does not occur.

From the above, in the present embodiment, the third nitride semiconductor layer 4 that is the back barrier layer is made of In _0.15 Ga _0.85 N and has a thickness of 2 nm. The thickness of the third nitride semiconductor layer 4 is not limited to this, but is desirably 5 nm or less as described above, and more desirably 1 nm or more and 5 nm or less. The thickness of the third nitride semiconductor layer 4 is selected to be smaller than the thickness of the second and fourth nitride semiconductor layers 3 and 5.

In the present embodiment, the fifth nitride semiconductor layer 6 that is a barrier layer is made of Al _0.2 Ga _0.8 N and has a thickness of 15 nm. The thickness of the fifth nitride semiconductor layer 6 is not limited to this. In view of the desired two-dimensional electron gas concentration and breakdown voltage, the band gap difference between the fifth nitride semiconductor layer 6 and the fourth nitride semiconductor layer 5 is determined, and based on this, the fifth nitride semiconductor is determined. The composition of the constituent elements of the layer 6 and the thickness of the fifth nitride semiconductor layer 6 are determined. That is, the composition and thickness of the fifth nitride semiconductor layer 6 are determined based on the desired two-dimensional electron gas concentration and breakdown voltage. Specifically, the thickness of the fifth nitride semiconductor layer 6 is preferably 5 nm or more and 50 nm or less.

The impurity concentration of the first to fifth nitride semiconductor layers 2 to 6 may be 1 × 10 ¹⁸ cm ⁻³ or less. In particular, the impurity concentration of the fifth nitride semiconductor layer 6 serving as the barrier layer is set to 1 × 10 ¹⁸ cm ⁻³ or less in order to make the barrier layer 6 a high breakdown voltage layer. In the present embodiment, the conductivity type of the impurity is always n-type. In a nitride semiconductor, even when impurities are not intentionally introduced, that is, in the case of non-doping, impurities enter the nitride semiconductor from a growth furnace or atmospheric gas, and include n-type impurities. Therefore, even if the first to fifth nitride semiconductor layers 2 to 6 are non-doped in crystal growth, the actual impurity concentration only needs to be 1 × 10 ¹⁸ cm ⁻³ or less. Is desirable.

  FIG. 12 is a cross-sectional view showing a state where the formation of the source electrode 8a and the drain electrode 8b has been completed. After the formation of the first to fifth nitride semiconductor layers 2 to 6, a conductive film to be the source electrode 8a and the drain electrode 8b is deposited by using, for example, a vapor deposition method or a sputtering method, and the source electrode 8a is formed by a lift-off method or the like. And the drain electrode 8b is formed. As the conductive film to be the source electrode 8a and the drain electrode 8b, for example, titanium (Ti), aluminum (Al), niobium (Nb), hafnium (Hf), zirconium (Zr), strontium (Sr), nickel (Ni), A single layer film made of a metal such as tantalum (Ta), gold (Au), platinum (Pt), vanadium (V), molybdenum (Mo) or tungsten (W), or a multilayer film composed of these single layer films Is used.

  Heat treatment may be performed after the formation of the source electrode 8a and the drain electrode 8b. By performing heat treatment, the metal layer constituting the source electrode 8a and the drain electrode 8b and the fifth nitride semiconductor layer 6 which is the semiconductor surface layer are reacted to form an alloy layer as a reaction layer. it can. Thereby, contact resistance and access resistance can be further reduced.

  FIG. 13 is a cross-sectional view showing a state in which the formation of the element isolation region 9 has been completed. After the formation of the source electrode 8a and the drain electrode 8b, the element isolation region 9 is formed in the epitaxial crystal layer in a region other than the region for forming the transistor, using the resist pattern or the like as a mask 31. In the present embodiment, the element isolation region 9 is formed from the surface of the fifth nitride semiconductor layer 6 to the inside of the fourth nitride semiconductor layer 5 toward the substrate 1. The element isolation region 9 is not limited to this, and the fifth to first nitride semiconductor layers which are epitaxial crystal layers from the surface of the fifth nitride semiconductor layer 6 toward the substrate 1. It is formed over any one of 6-2.

  In the present embodiment, the element isolation region 9 is formed by an ion implantation method in which the ions 32 are irradiated. Examples of the ions 32 to be irradiated include helium (He), nitrogen (N), oxygen (O), magnesium (Mg), argon (Ar), calcium (Ca), iron (Fe), zinc (Zn), and strontium. And ions such as (Sr) and barium (Ba). The method for forming the element isolation region 9 is not limited to the ion implantation method. For example, part of the first to fifth nitride semiconductor layers may be removed using etching or the like to form the element isolation region 9.

FIG. 14 is a cross-sectional view showing a state in which the formation of the gate electrode 7 has been completed. After the element isolation region 9 is formed, a conductive film to be the gate electrode 7 is deposited by using, for example, an evaporation method or a sputtering method, and the gate electrode 7 is formed by a lift-off method or the like. Examples of the conductive film to be the gate electrode 7 include titanium (Ti), aluminum (Al), platinum (Pt), gold (Au), nickel (Ni), palladium (Pd), and other metals, iridium silicide (IrSi), and the like. , Single layer films made of silicide such as platinum silicide (PtSi), nickel silicide (NiSi ₂ ), or nitride metal such as titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), or the like A multilayer film composed of a single layer film is used.

  FIG. 15 is a cross-sectional view showing a state in which the formation of the insulating film 10 has been completed. After the formation of the gate electrode 7, the fifth nitride semiconductor layer 6 is insulated so as to cover at least a portion where the gate electrode 7, the source electrode 8 a and the drain electrode 8 b are not formed on the surface on one side in the thickness direction. A film 10 is formed. Specifically, for example, a plasma CVD method, a catalytic chemical vapor deposition (abbreviation: Cat-CVD) method, an atomic growth (Atomic Layer Deposition; abbreviation: ALD) method, an MOCVD method, an MBE method, or a sputtering method. Thus, the insulating film 10 is formed.

  Examples of the insulating film 10 include aluminum (Al), gallium (Ga), silicon (Si), hafnium (Hf), titanium (Ti), zirconium (Zr), tantalum (Ta), and vanadium (V). A single-layer film made of an oxide, nitride, or oxynitride of at least one kind of atom or a multilayer film composed of these single-layer films is formed.

  According to the semiconductor device manufacturing method described above, it is possible to manufacture the semiconductor device 100 which is the heterojunction field effect transistor having the structure shown in FIG. 1 and having excellent effects as described above. . In this embodiment, only the minimum necessary elements that operate as a transistor are described, but the semiconductor device 100 is finally used as a device through a formation process of a protective film, a wiring, a via hole, and the like.

  In the present embodiment, after the formation of the first to fifth nitride semiconductor layers 6 that are epitaxial crystal layers, the source electrode 8a and the drain electrode 8b are formed, the element isolation region 9 is formed, the gate electrode 7 is formed, Each process of forming the insulating film 10 is performed in this order. These steps are not necessarily performed in this order, and the order of the steps may be changed.

  For example, the element isolation region 9 may be formed before forming the source electrode 8a and the drain electrode 8b. The element isolation region 9 may be formed after the gate electrode 7 is formed. Alternatively, the gate electrode 7 may be formed after forming the insulating film 10 and removing the insulating film 10 in the region where the gate electrode 7 is to be formed in the formed insulating film 10. Alternatively, the element isolation region 9 may be formed after the insulating film 10 is formed, and then the gate electrode 7 may be formed after the insulating film 10 in the gate forming region is removed.

In the present embodiment, the first to fifth nitride semiconductor layers 2 to 6 shown in FIG. 11 are made of Al _0.2 Ga _0.8 N / GaN / In _0.15 Ga _0.85 N / GaN / Al _0.03 Ga _0.97 N. Although the case where the structure is epitaxially grown on the SiC substrate has been described, the same effects as those of the embodiment are achieved by appropriately changing the conditions for forming the first to fifth nitride semiconductor layers 2 to 6. Various heterojunction field effect transistors can be manufactured as a semiconductor device.

  Specifically, when the epitaxial structure shown in FIG. 11 is epitaxially grown on the substrate 1 using the MOCVD method, trimethylammonium, trimethylgallium, trimethylindium, ammonia, or n, which is a material gas for a nitride semiconductor, is used. The flow rate, pressure, temperature, and time of silane that is a source gas of the type dopant are adjusted, and each layer has a desired composition, film thickness, and doping concentration. Accordingly, various nitride semiconductor heterojunction field effect transistors can be manufactured as semiconductor devices.

  Further, other semiconductor devices 101 to 107 shown in FIGS. 4 to 10 are manufactured by appropriately changing each step in the manufacturing method of the semiconductor device 100 of the present embodiment shown in FIGS. can do. For example, the semiconductor device 101 shown in FIG. 4 can be manufactured as follows.

  FIG. 16 is a cross-sectional view showing a state where the formation of the high-concentration n-type impurity region 12 has been completed. First, as in the above-described embodiment, first to fifth nitride semiconductor layers 2 to 6 are formed on the substrate 1 as shown in FIG.

Next, as shown in FIG. 16, the resist pattern or the like is used as an implantation mask 33, and at least part of the nitride semiconductor layers 2 to 6 below the region where the source electrode 8a and the drain electrode 8b are formed, that is, on the substrate 1 side. Next, an impurity such as Si that becomes n-type in the nitride semiconductor is implanted. Specifically, the impurity ions 34 are implanted into a desired region by using an ion implantation method or the like. Next, a high concentration n-type impurity region 12 is formed by heat treatment. In this embodiment, the conditions for implanting ions 34 are an implantation dose of 1 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁷ cm ⁻² and an implantation energy of 10 keV to 1000 keV.

The impurity concentration of the high-concentration n-type impurity region 12 is preferably equal to or higher than the impurity concentration used when intentionally forming n-type GaN or AlGaN during crystal growth. Specifically, the impurity concentration of the high-concentration n-type impurity region 12 is preferably 1 × 10 ¹⁸ cm ⁻³ or more, more preferably 1 × 10 ¹⁹ cm ⁻³ or more.

One desirable distribution of impurities in the high-concentration n-type impurity region 12 is a region from the semiconductor surface under the source electrode 8a and the drain electrode 8b to the interface between the barrier layer 6 and the channel layer 5 through which electrons flow. Examples include a structure having a high impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or more in both the region from the interface to the channel layer 5 side up to about 10 nm. As a method for determining the implantation dose and the implantation energy for forming such an impurity distribution, there is a method of simulating the ion range by Monte Carlo calculation using the implantation energy and the structure of the irradiation object as parameters. By this method, the implantation energy and the implantation dose satisfying the above conditions can be determined.

When a resist pattern is used as the implantation mask 33, the resist pattern may be formed after forming a nitride film or an oxide film on the barrier layer 6. By forming a nitride film or an oxide film on the barrier layer 6 in this way, the implanted ions 34 are atoms constituting the barrier layer 6, specifically, aluminum (Al), gallium (Ga), indium ( In), nitrogen (N), and the like can be prevented from jumping into the vacuum. Examples of the nitride film or oxide film formed on the barrier layer 6 include a nitride film such as a silicon nitride (SiN _x ) film or an aluminum nitride (AlN) film, a silicon dioxide (SiO ₂ ) film, or an aluminum oxide (Al _2). An oxide film such as O ₃ ) is formed with a thickness of about 10 nm to 100 nm.

  As described above, after the ions 34 are implanted using the implantation mask 33, heat treatment is performed and the implanted ions 34 are activated, whereby the high-concentration n-type impurities below the source electrode 8a and the drain electrode 8b are activated. The resistance of the region 12 is reduced. This heat treatment may be performed after covering the surface of the nitride semiconductor with a nitride film or an oxide film. By performing the heat treatment after covering the surface of the nitride semiconductor with the nitride film or the oxide film in this way, it is possible to prevent nitrogen atoms from escaping from the semiconductor surface during the heat treatment.

As the nitride film or oxide film covering the surface of the nitride semiconductor, for example, a nitride film such as a silicon nitride (SiN _x ) film or an aluminum nitride (AlN) film, or a silicon dioxide (SiO ₂ ) film on the barrier layer 6. Alternatively, an oxide film such as aluminum oxide (Al ₂ O ₃ ) is formed with a thickness of about 10 nm to 100 nm. Thus, after covering the surface of the nitride semiconductor with a nitride film or an oxide film, heat treatment may be performed.

  FIG. 17 is a cross-sectional view showing a state where the formation of the source electrode 8a and the drain electrode 8b has been completed. After the high-concentration n-type impurity region 12 is formed, the source electrode 8a and the drain electrode 8b are formed by a lift-off method or the like, similar to the case shown in FIG.

  FIG. 18 is a cross-sectional view showing a state where the formation of the element isolation region 9 is completed. After the formation of the source electrode 8a and the drain electrode 8b, the element isolation region 9 is formed in the epitaxial crystal layer in a region other than the region where the transistor is manufactured using the resist pattern as a mask 31 in the same manner as shown in FIG. Form. Thereafter, the gate electrode 7 and the insulating film 10 are formed in the same manner as shown in FIGS. Through the above steps, the semiconductor device 101 shown in FIG. 4 can be manufactured.

  In the manufacturing method of the semiconductor device 101 described above, the step of forming the high concentration n-type impurity region 12 shown in FIG. 16, the step of forming the source electrode 8a and the drain electrode 8b shown in FIG. 17, and the element isolation region shown in FIG. 9 are performed in this order. These three steps are not necessarily performed in this order, and the order of the steps may be changed. For example, the element isolation region 9 may be formed before forming the source electrode 8a and the drain electrode 8b.

  FIG. 19 is a cross-sectional view showing a state in which the formation of the hole 13 has been completed. When manufacturing the semiconductor device 102 shown in FIG. 5, the source electrode 8a shown in FIG. 12 is formed after the formation of the first to fifth nitride semiconductor layers 2 to 6 shown in FIG. Before forming the drain electrode 8b, the hole 13 is formed as shown in FIG.

Specifically, the source of the first to fifth nitride semiconductor layers 2 to 6 is etched by dry etching using chlorine (Cl ₂ ) gas or the like using the resist pattern as a mask 35. At least a part of the semiconductor layer under the region where the electrode 8a and the drain electrode 8b are to be formed is removed. When the semiconductor device 102 shown in FIG. 5 is manufactured, a part of the fifth nitride semiconductor layer 6 is removed as shown in FIG. As a result, a hole 13 is formed in the fifth nitride semiconductor layer 6. Next, similarly to the case shown in FIG. 12 described above, the source electrode 18a and the drain electrode 18b are formed so as to fill the hole of the hole 13.

  Thereafter, the element isolation region 9, the gate electrode 7 and the insulating film 10 are formed in the same manner as shown in FIGS. Through the above steps, the semiconductor device 102 shown in FIG. 5 can be manufactured.

  Before or after the etching step shown in FIG. 19, the step of forming the high concentration n-type impurity region 12 shown in FIG. 16 may be performed. Thus, a semiconductor device in which the semiconductor device 101 shown in FIG. 4 and the semiconductor device 102 shown in FIG. 5 are combined, that is, the high concentration n-type impurity region 12 is provided and a part of the high concentration n-type impurity region 12 is removed. A semiconductor device in which the holes 13 formed in this way are filled with the source electrode 18a and the drain electrode 18b can be manufactured.

  FIG. 20 is a cross-sectional view showing a state in which the formation of the recess 14 is completed. When the semiconductor device 103 shown in FIG. 6 is manufactured, after forming the element isolation region 9 shown in FIG. 13 and before forming the gate electrode 7 shown in FIG. The recess 14 is formed as shown in FIG.

Specifically, the resist pattern or the like is used as a mask 36, and etching is performed by a dry etching method using chlorine (Cl ₂ ) gas or the like through an opening 36a of the mask 36, thereby forming a region (hereinafter referred to as “a gate electrode 7”). Part of the S barrier layer 6 (referred to as “gate electrode formation region”) is removed. As a result, the recess 14 is formed in the fifth nitride semiconductor layer 6 which is a barrier layer. When etching is performed, the etching can be performed to a desired depth by adjusting the etching time and the gas flow rate, so that the recess 14 having a desired depth can be formed.

  After that, after the gate electrode 17 is formed so as to fill the recess 14 as in the case shown in FIG. 14, the insulating film 10 is formed as in the case shown in FIG. Through the above steps, the semiconductor device 103 having a structure in which the gate electrode 17 is embedded in the recess 14 as shown in FIG. 6 can be manufactured.

  FIG. 21 is a cross-sectional view showing a state at the stage where the removal of the insulating film 10 in the gate electrode formation region S is completed. When the semiconductor device 105 shown in FIG. 8 is manufactured, after the formation of the element isolation region 9 shown in FIG. 13 and before the formation of the gate electrode 7 shown in FIG. In the same manner as shown in FIG. 15, the insulating film 10 is formed on the semiconductor surface, that is, the surface of the fifth nitride semiconductor layer 6. Specifically, the insulating film 10 is deposited on the semiconductor surface by using, for example, an evaporation method, a plasma CVD method, a Cat-CVD method, an MOCVD method, an MBE method, or an ALD method.

  Since the insulating film 10 formed on the semiconductor surface also serves as a protective film, it is desirable that the insulating film 10 be a high-quality film. As such an insulating film 10, for example, aluminum (Al), gallium (Ga), silicon (Si), hafnium (Hf), titanium (Ti), zirconium (Zr), tantalum (Ta), vanadium (V), etc. An insulating film made of oxide, nitride, oxynitride or the like containing at least one kind of atoms is deposited.

  Next, the insulating film 10 in the gate electrode formation region S is removed by dry etching or wet etching through the mask 37 in which the opening 37a is formed in the gate electrode formation region S. For example, a resist mask or an oxide film mask is used as the mask 37.

  After removing the mask 37, an electrode metal to be a gate metal is deposited by an evaporation method using a resist pattern having an opening wider than the opening of the insulating film 10 formed by etching, and a gate electrode is formed by a lift-off method or the like. 72 is formed. Thereby, the semiconductor device 105 having the structure shown in FIG. 8 can be manufactured.

  By using the method for manufacturing the semiconductor device 105 shown in FIG. 8 described above, the semiconductor device 106 having the structure shown in FIG. 9 can be manufactured. Specifically, first, as in the case of manufacturing the semiconductor device 105 shown in FIG. 8, after the formation of the element isolation region 9 shown in FIG. 13, the fifth nitride semiconductor layer 6, which is a semiconductor surface, is formed. An insulating film is formed on the surface. At this time, the insulating film 70 having a thickness equal to the distance between the portion under the gate electrode 71 shown in FIG. 9 and the semiconductor surface is formed as the insulating film. Next, as in the case of manufacturing the semiconductor device 105 shown in FIG. 8, the insulating film 70 in the gate electrode formation region S is removed and the gate electrode 71 is formed as shown in FIG.

  Next, the insulating film 70 is removed by wet etching using an etching solution such as buffered hydrofluoric acid, that is, a hydrofluoric acid buffer solution. At this time, the insulating film 70 can be left in a desired region by adjusting the processing conditions of the wet etching, for example, the processing time and the concentration of the etching solution. As a result, as shown in FIG. 9, a shape is obtained in which the insulating film 70 remains only in the part under the gate electrode 71.

  As described above, the semiconductor device 106 having a structure in which the insulating film 70 remains only in the part under the gate electrode 71 as shown in FIG. 9 can be manufactured.

  FIG. 22 is a cross-sectional view showing a state where the removal of the insulating film 70 in the gate electrode formation region S is completed. The semiconductor device 104 shown in FIG. 7 can be manufactured in the same manner as the semiconductor device 105 shown in FIG. Specifically, after the formation of the element isolation region 9 shown in FIG. 13 and before the formation of the gate electrode 7 shown in FIG. 14, a semiconductor is formed in the same manner as shown in FIG. An insulating film 10 is formed on the surface of the fifth nitride semiconductor layer 6 that is the surface.

  In order to finally use the semiconductor device 104 as a device, a part of the insulating film 10 covering the source electrode 8a and the drain electrode 8b is removed by wet etching using, for example, hydrofluoric acid, and then the wiring electrode Need to form. Therefore, as the insulating film 10, an insulating film that can be removed by wet etching using, for example, hydrofluoric acid is formed.

  Next, the second insulating film 40 is formed on the surface on one side in the thickness direction of the insulating film 10. As a result, an insulating film 70 composed of the two insulating films of the insulating film 10 and the second insulating film 40 is formed. As the second insulating film 40, an insulating film that can be easily removed by wet etching, for example, a silicon oxide film (SiO), is formed as compared with the insulating film 10.

  Next, the second insulating film 40 and the insulating film 10 in the gate electrode formation region S are sequentially removed by dry etching or wet etching through the mask 38 in which the opening 38a is formed in the gate electrode formation region S. For example, a resist mask or an oxide film mask is used as the mask 38.

  After removing the mask 38, an electrode metal to be a gate metal is deposited by vapor deposition using a resist pattern in which an opening wider than the opening of the second insulating film 40 and the insulating film 10 formed by etching is formed. Then, the gate electrode 71 is formed by a lift-off method or the like.

  Of the insulating film 70, the second insulating film 40, which is the insulating film that is more easily wet-etched, is removed by wet etching using an etching solution such as buffered hydrofluoric acid, ie, a hydrofluoric acid buffer solution. As a result, the semiconductor device 104 having the structure shown in FIG. 7, which has a structure in which the subordinate portion of the gate electrode 71 is not in contact with the insulating film 10, can be manufactured.

  Further, the second insulating film 40 in a desired region can be left by adjusting the wet etching processing conditions of the second insulating film 40, for example, the processing time and the concentration of the etching solution. Thereby, for example, the semiconductor device 108 having the structure shown in FIG. 23 can be manufactured. FIG. 23 is a cross-sectional view showing a semiconductor device 108 which is still another example of the semiconductor device. By adjusting the wet etching process conditions of the second insulating film 40 as described above, the insulating film 10 covers the semiconductor surface and the second insulating film 40 is formed on the gate electrode 71 as shown in FIG. It is possible to obtain a shape that remains only in the part under the umbrella.

  The semiconductor device manufacturing methods described above do not have to be employed individually and can be combined as appropriate. For example, the semiconductor device 107 shown in FIG. 10 can be manufactured by appropriately combining the above-described manufacturing methods of the semiconductor device.

  Specifically, first, as in the case of manufacturing the semiconductor device 100 shown in FIG. 1, the first to fifth nitride semiconductor layers 2 to 2 are formed on the substrate 1 as shown in FIG. 6 is formed. Next, as in the case of manufacturing the semiconductor device 101 shown in FIG. 4, the high concentration impurity region 12, the source electrode 8a, the drain electrode 8b, and the element isolation region 9 are formed as shown in FIGS. Form.

  Next, in the same manner as in the case of manufacturing the semiconductor device 105 shown in FIG. 8, as shown in FIG. 21 described above, at least the source electrode 8a in the surface of the fifth nitride semiconductor layer 6 which is the semiconductor surface. An insulating film is formed so as to cover the portion where the drain electrode 8b is not formed. At this time, the insulating film 70 having a thickness equal to the distance between the portion under the gate electrode 73 shown in FIG. 10 and the semiconductor surface is formed as the insulating film.

  Thereafter, as in the case of manufacturing the semiconductor device 103 shown in FIG. 6, the recess 14 is formed in the gate electrode formation region S as shown in FIG. Next, the gate electrode 73 having the same shape as the gate electrodes 71 and 72 shown in FIGS. 7 to 9 is formed so as to fill the recess 14.

  Next, the insulating film 70 is removed with an etchant such as buffered hydrofluoric acid. At this time, the insulating film 70 can be left in a desired region by adjusting the wet etching process conditions. As a result, as shown in FIG. 10 described above, a shape is obtained in which the insulating film 70 remains only in the portion under the gate electrode 73.

  As described above, as shown in FIG. 10 described above, the semiconductor device 107 having a shape in which the insulating film 70 remains only in the subordinate portion of the T-type gate electrode 73 with the bottom embedded in the recess 14 can be manufactured. it can.

  Further, for example, the semiconductor device 109 shown in FIG. 24 can be manufactured by appropriately combining the above-described semiconductor device manufacturing methods. FIG. 24 is a cross-sectional view showing a semiconductor device 109 which is still another example of the semiconductor device. In the semiconductor device 109, like the semiconductor device 108 shown in FIG. 23 described above, the insulating film 10 covers the semiconductor surface and the second insulating film 40 remains only in the part under the gate electrode 73.

  The manufacturing method of the semiconductor device 109 shown in FIG. 24 will be specifically described. First, the first to fifth nitride semiconductors are formed on the substrate 1 in the same manner as in the case of manufacturing the semiconductor device 107 shown in FIG. After the layers 2 to 6 are formed, the high concentration impurity region 12, the source electrode 8a, the drain electrode 8b, and the element isolation region 9 are formed.

  Next, in the same manner as in the case of manufacturing the semiconductor device 104 shown in FIG. 7, as shown in FIG. 22 described above, at least the source electrode 8a in the surface of the fifth nitride semiconductor layer 6 which is the semiconductor surface. And the insulating film 10 is formed so that the part in which the drain electrode 8b is not formed may be covered. Next, the second insulating film 40 is formed on the surface on one side in the thickness direction of the insulating film 10, and the insulating film 70 composed of the two insulating films of the insulating film 10 and the second insulating film 40 is formed. To do.

  Then, after forming the recess 14 in the gate electrode formation region S in the same manner as shown in FIG. 20, the gate electrode 73 having the same shape as the gate electrodes 71 and 72 shown in FIGS. Then, the second insulating film 40 is removed with an etching solution such as buffered hydrofluoric acid. At this time, it is possible to leave the second insulating film 40 in a desired region by adjusting the processing conditions of the wet etching. As a result, as shown in FIG. 24, a shape is obtained in which the second insulating film 40 remains only in the part under the gate electrode 73.

  As described above, as shown in FIG. 24, the second insulating film 40 is formed only on the part of the T-type gate electrode 73 where the insulating film 10 covers the semiconductor surface and the bottom is buried in the recess 14. The remaining semiconductor device 109 can be manufactured.

  1 substrate 2 first nitride semiconductor layer 3 second nitride semiconductor layer 4 third nitride semiconductor layer (back barrier layer) 5 fourth nitride semiconductor layer (channel layer) 6 second 5, nitride semiconductor layer (barrier layer), 7, 17, 71 to 73 gate electrode, 8a, 18a source electrode, 8b, 18b drain electrode, 9 element isolation region, 10, 70 insulating film, 11 two-dimensional electron gas, 12 High-concentration n-type impurity region, 40 Second insulating film, 100 to 109 Semiconductor device.

Claims (4)

A substrate,
The nitride semiconductor is provided on the substrate and is represented by the composition formula Al _a In _b Ga _{1− (a + b)} N (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, 0 ≦ a + b ≦ 1). A first nitride semiconductor layer;
Provided on the first nitride semiconductor layer and represented by the composition formula Al _c In _d Ga _{1-(c + d)} N (0 ≦ c ≦ 1, 0 ≦ d ≦ 1, 0 ≦ c + d ≦ 1). A second nitride semiconductor layer comprising a nitride semiconductor;
A third nitride semiconductor layer formed on the second nitride semiconductor layer and made of a nitride semiconductor represented by a composition formula In _e Ga _1-e N (0 <e ≦ 1);
Provided on the third nitride semiconductor layer and represented by the composition formula Al _f In _g Ga _{1-(f + g)} N (0 ≦ f ≦ 1, 0 ≦ g ≦ 1, 0 ≦ f + g ≦ 1). A fourth nitride semiconductor layer comprising a nitride semiconductor;
Provided on the fourth nitride semiconductor layer and represented by the composition formula Al _h In _i Ga _{1-(h + i)} N (0 ≦ h ≦ 1, 0 ≦ i ≦ 1, 0 ≦ h + i ≦ 1). And a fifth nitride semiconductor layer made of a nitride semiconductor,
The band gap of the first nitride semiconductor layer is larger than the band gap of the second nitride semiconductor layer,
The band gap of the third nitride semiconductor layer is smaller than the band gap of the second nitride semiconductor layer,
The band gap of the fourth nitride semiconductor layer is equal to the band gap of the second nitride semiconductor layer,
A semiconductor device, wherein a band gap of the fifth nitride semiconductor layer is larger than a band gap of the fourth nitride semiconductor layer.   The composition of aluminum (Al), indium (In), and gallium (Ga) in each of the first, second, fourth, and fifth nitride semiconductor layers is the first, second, fourth, and fifth. 2. The semiconductor device according to claim 1, wherein a lattice constant of each nitride semiconductor layer and a lattice constant of the third nitride semiconductor layer are selected to coincide with each other. The second nitride semiconductor layer and the fourth nitride semiconductor layer are made of a nitride semiconductor having the same composition,
The semiconductor device according to claim 1, wherein a band gap of the second and fourth nitride semiconductor layers is 3.47 eV or more. The nitride semiconductor represented by the composition formula Al _a In _b Ga _{1- (a + b)} N (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, 0 ≦ a + b ≦ 1) is formed on the substrate by the first A first layer forming step of forming a nitride semiconductor layer;
On the first nitride semiconductor layer, nitride represented by the composition formula Al _c In _d Ga _{1-(c + d)} N (0 ≦ c ≦ 1, 0 ≦ d ≦ 1, 0 ≦ c + d ≦ 1) A second layer forming step of forming a second nitride semiconductor layer with a physical semiconductor;
Forming a third layer on the second nitride semiconductor layer by forming a third nitride semiconductor layer from a nitride semiconductor represented by the composition formula In _e Ga _1-e N (0 <e ≦ 1) Process,
On the third nitride semiconductor layer, a nitride represented by the composition formula Al _f In _g Ga _{1-(f + g)} N (0 ≦ f ≦ 1, 0 ≦ g ≦ 1, 0 ≦ f + g ≦ 1). A fourth layer forming step of forming a fourth nitride semiconductor layer with a physical semiconductor;
On the fourth nitride semiconductor layer, a nitride represented by the composition formula Al _h In _i Ga _{1− (h + i)} N (0 ≦ h ≦ 1, 0 ≦ i ≦ 1, 0 ≦ h + i ≦ 1) A fifth layer forming step of forming a fifth nitride semiconductor layer with a physical semiconductor,
In the first layer forming step, the first nitride semiconductor layer is formed such that a band gap of the first nitride semiconductor layer is larger than a band gap of the second nitride semiconductor layer. ,
In the third layer forming step, the third nitride semiconductor layer is formed so that a band gap of the third nitride semiconductor layer is smaller than a band gap of the second nitride semiconductor layer. ,
In the fourth layer forming step, the fourth nitride semiconductor layer is formed so that a band gap of the fourth nitride semiconductor layer is equal to a band gap of the second nitride semiconductor layer,
In the fifth layer forming step, the fifth nitride semiconductor layer is formed such that a band gap of the fifth nitride semiconductor layer is larger than a band gap of the fourth nitride semiconductor layer. A method for manufacturing a semiconductor device.

Images