JP2012190956A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of a lead frame type semiconductor device.SOLUTION: An encapsulant 5 which encapsulates a semiconductor chip 2 forms a quadrilateral in a plan view, the four sides of which each have a plurality of leads 10 disposed thereon. Also, a tab (chip mounting part) 3 is supported by a plurality of suspension leads 6 which are formed integrally with the tab 3. The plurality of suspension leads 6 each extend along a first diagonal line (virtual line) DL1 of the encapsulant 5 forming the quadrilateral, while the plurality of suspension leads 6 are not disposed on a second diagonal line (virtual line) DL2 side differing from the first diagonal line DL1. Here, the bonding regions located at tips on the tab 3 side of the plurality of leads 10 each are arranged closer to the second diagonal line DL2 side.

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technology effective when applied to a lead frame type semiconductor device in which a plurality of external terminals are arranged along each of four sides of a quadrilateral sealing body. Is.

  Japanese Patent Laying-Open No. 2005-354115 (Patent Document 1) describes a QFP (Quad Flat Package) type semiconductor device in which a semiconductor chip is mounted on a die pad having an outer dimension smaller than that of the semiconductor chip. Patent Document 1 describes a lead frame in which a downset process is applied to each of a plurality of suspension leads formed integrally with a die pad.

  In Japanese Patent Application Laid-Open No. 2004-56136 (Patent Document 2), a semiconductor chip is mounted on a support lead extending from a first corner of a resin sealing body toward a second corner on the opposite side. A QFP type semiconductor device is described.

JP 2005-354115 A JP 2004-56136 A

When the package mode of the semiconductor device is roughly classified according to the type of base material on which the semiconductor chip is mounted,
There are a lead frame type semiconductor device using a lead frame as a base material and a wiring board type semiconductor device using a wiring board (interposer substrate) as a base material. In the lead frame type semiconductor device, the lead frame as the base material in the lead frame type semiconductor device is less expensive than the wiring substrate as the base material in the wiring board type semiconductor device. The manufacturing cost can be reduced as compared with the apparatus.

  Among lead frame semiconductor devices, QFP type semiconductor devices and QFN (Quad Flat Non-Leaded Package) type semiconductor devices have a plurality of external terminals along each of the four sides of the quadrilateral semiconductor device. Since the semiconductor device is arranged, it is a semiconductor device that can suppress an increase in mounting area and reduce manufacturing costs even if the number of external terminals increases.

  The inventor of the present application has further studied the above-described QFP type or QFN type semiconductor device and found the following problems. With the recent demand for miniaturization of semiconductor devices, the planar size of semiconductor chips mounted on lead frames is being reduced. However, there is a limit to the microfabrication of a plurality of leads, which are a plurality of external terminals arranged around the semiconductor chip, and it is difficult to miniaturize the leads as the miniaturization technology of the semiconductor chip advances. It has become. For this reason, it is difficult to bring a plurality of leads close to a miniaturized semiconductor chip, and the distance between the bonding pad formed on the semiconductor chip and the lead tends to be long. In other words, the length of the wire that electrically connects the bonding pad and the lead of the semiconductor chip tends to increase.

  Here, the length of the wire is an important factor that affects the reliability of the semiconductor device. For example, if the length of the wire is increased, the wire is easily deformed during the manufacturing process, which causes a short circuit failure between adjacent wires. Moreover, since the impedance component of a wire will increase if the length of a wire becomes long, a predetermined electrical characteristic may not be acquired. Moreover, since the usage-amount of the material (metal) which comprises a wire will increase when the length of a wire becomes long, it will cause the increase in manufacturing cost.

  The present invention has been made in view of the above problems, and an object thereof is to provide a technique for improving the reliability of a lead frame type semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, in a semiconductor device according to an aspect of the present invention, a plurality of leads electrically connected to the semiconductor chip via a plurality of wires are arranged around a chip mounting portion on which the semiconductor chip is mounted. The bonding regions of the plurality of wires and the plurality of leads are sealed with a sealing body. Further, the sealing body has a quadrilateral shape in plan view, and the plurality of leads are arranged along each of the four sides. The chip mounting portion is supported by a plurality of suspension leads formed integrally with the chip mounting portion. Each of the plurality of suspension leads extends along a first diagonal line (imaginary line) of the sealing body forming a quadrilateral, and on a second diagonal line (virtual line) side different from the first diagonal line, The plurality of suspension leads are not arranged. Here, the bonding areas of the plurality of leads are arranged close to the second diagonal line.

  The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to one embodiment of the present invention, the reliability of a lead frame semiconductor device can be improved.

It is a top view which shows the upper surface side of the semiconductor device which is one embodiment of this invention. It is sectional drawing along the AA line of FIG. It is sectional drawing along the BB line of FIG. FIG. 2 is a perspective plan view showing a planar structure inside a sealing body of the semiconductor device shown in FIG. 1. FIG. 5 is an enlarged plan view showing the periphery of the semiconductor chip shown in FIG. 4 in an enlarged manner. FIG. 6 is an enlarged plan view of a D part in FIG. 5. FIG. 6 is an enlarged plan view of an E part in FIG. 5. FIG. 6 is an enlarged plan view of a portion F in FIG. 5. FIG. 6 is an enlarged plan view of a G part in FIG. 5. It is explanatory drawing which shows the assembly flow of the semiconductor device which is one embodiment of this invention. FIG. 11 is a plan view showing the overall structure of the lead frame prepared in the lead frame preparation step shown in FIG. 10. FIG. 12 is an enlarged plan view around one product formation region among the plurality of product formation regions shown in FIG. 11. FIG. 13 is an enlarged cross-sectional view schematically showing an offset process for forming the inclined portion of the suspension lead shown in FIG. 12. FIG. 13 is an enlarged cross-sectional view schematically showing an offset process for forming the inclined portion of the suspension lead shown in FIG. 12. FIG. 13 is an enlarged cross-sectional view schematically showing an offset process for forming the inclined portion of the suspension lead shown in FIG. 12. FIG. 13 is an enlarged cross-sectional view schematically showing an offset process for forming the inclined portion of the suspension lead shown in FIG. 12. FIG. 17 is an enlarged plan view showing a planar positional relationship between the pressing portion of the upper mold shown in FIGS. 13 to 16 and the lead frame shown in FIG. 12. It is an enlarged plan view which shows the state which mounted the semiconductor chip on the tab shown in FIG. 12 via the bonding material. It is an expanded sectional view along the HH line of FIG. It is an expanded sectional view along the KK line of FIG. FIG. 19 is an enlarged plan view showing a state where electrode pads and leads of the semiconductor chip shown in FIG. 18 are electrically connected via wires. It is an expanded sectional view along the HH line of FIG. FIG. 22 is an enlarged plan view showing a state in which a sealing body is formed in the product formation region of the lead frame shown in FIG. 21. It is an expanded sectional view along the AA line of FIG. FIG. 24 is an enlarged cross-sectional view showing a state in which a sealing resin is supplied into the cavity of the molding die in the cross section along the line AA shown in FIG. 23. FIG. 24 is an enlarged cross-sectional view showing a state in which the sealing resin is supplied into the cavity of the molding die in the cross section along the line BB shown in FIG. 23. It is explanatory drawing which shows typically a mode that resin for sealing is supplied to the area | region where the wire is arrange | positioned in the sealing process shown in FIG. It is explanatory drawing which shows typically the cross section along the LL line | wire of FIG. It is explanatory drawing which shows typically the cross section along the MM line | wire of FIG. It is an enlarged plan view which shows the state which cut | disconnected the dam part shown in FIG. FIG. 31 is an enlarged cross-sectional view showing a state in which an exterior plating film is formed on the exposed surfaces of a plurality of leads exposed from the sealing body in the cross section taken along the line AA shown in FIG. 30. FIG. 32 is an enlarged plan view showing a state where the outer lead portion shown in FIG. 31 is cut and molded. FIG. 33 is an enlarged plan view showing a state in which the product forming region shown in FIG. 32 is separated from the frame portion of the lead frame and separated into pieces. FIG. 7 is a plan view showing a lower surface (mounting surface) side of a semiconductor device which is a modified example of the semiconductor device shown in FIG. 1. FIG. 35 is a cross-sectional view corresponding to FIG. 2 in the semiconductor device shown in FIG. 34. FIG. 35 is a perspective plan view corresponding to FIG. 4 in the semiconductor device shown in FIG. 34. FIG. 5 is a perspective plan view showing a semiconductor device which is another modified example with respect to FIG. 4.

(Description format, basic terms, usage in this application)
In the present application, the description of the embodiment will be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Regardless of the front and rear, each part of a single example, one is a part of the other, or a part or all of the modifications. In principle, repeated description of similar parts is omitted. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It does not exclude things that contain. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but includes a SiGe (silicon-germanium) alloy, other multi-component alloys containing silicon as a main component, and other additives. Needless to say, it is also included. Moreover, even if it says gold plating, Cu layer, nickel / plating, etc., unless otherwise specified, not only pure materials but also members mainly composed of gold, Cu, nickel, etc. Shall be included.

  In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  Moreover, in each figure of embodiment, the same or similar part is shown with the same or similar symbol or reference number, and description is not repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, hatching or a dot pattern may be added in order to clearly indicate that it is not a void or to clearly indicate the boundary of a region.

  In this embodiment, as an example of a lead frame type semiconductor device in which a plurality of external terminals are arranged along each of the four sides of a quadrilateral sealing body, an embodiment applied to a QFP type semiconductor device is taken up. I will explain.

<Appearance structure of semiconductor device>
First, the external structure of the semiconductor device of this embodiment will be described. FIG. 1 is a plan view showing the upper surface side of the semiconductor device of the present embodiment. 2 is a cross-sectional view taken along line AA in FIG. 1, and FIG. 3 is a cross-sectional view taken along line BB in FIG. 4 is a perspective plan view showing a planar structure inside the sealing body of the semiconductor device shown in FIG. 1, and FIG. 5 is an enlarged plan view showing the periphery of the semiconductor chip shown in FIG. 4 and 5 are perspective plan views showing the internal structure of the semiconductor device, the plan view showing the internal structure through the sealing body 5 shown in FIG.

  The semiconductor device 1 of the present embodiment includes a sealing body (resin body) 5 that seals the semiconductor chip 2 (see FIGS. 2 to 4), and a plurality of leads 10 that are external terminals exposed from the sealing body 5. have. 2 and 3, the sealing body 5 has an upper surface 5a, a lower surface 5b located on the opposite side of the upper surface 5a, and a side surface 5c that surrounds the peripheral portions of the upper surface 5a and the lower surface 5b. Moreover, as shown in FIG. 1, the planar shape of the sealing body 5 consists of a quadrangle (rectangle). Specifically, the sealing body 5 is positioned next to the first corner C1, the second corner C2, and the first corner C1 that face each other via the chip mounting portion on which the semiconductor chip 2 is mounted. A third corner C3, and a fourth corner C4 opposed to the third corner via the chip mounting portion. The sealing body 5 includes a first side S1 located between the first corner C1 and the fourth corner C4, a second side S2 located between the second corner C2 and the third corner C3, It has a third side S3 located between the second corner C2 and the fourth corner C4, and a fourth side S4 located between the first corner C1 and the third corner C3. In addition, the sealing body 5 includes a first diagonal line (virtual line) DL1 connecting the first corner part C1 and the second corner part C2, and a second diagonal line (virtual line connecting the third corner part C3 and the fourth corner part C4. ) It has DL2. Strictly speaking, as shown in FIG. 1, each corner of the sealing body 5 is chamfered to prevent or suppress damage such as chipping of the sealing body 5, but the first side S1. Since each side (each side) of the fourth side S4 is sufficiently longer than the sides constituting the chamfered portion and can be regarded as a quadrilateral (or a quadrangle), in the present embodiment, The description will be made as a quadrilateral having four main sides excluding the side of the chamfered portion.

  A plurality of leads 10 that are external terminals of the semiconductor device 1 are arranged along each of the first side S1 to the fourth side S4. That is, the semiconductor device 1 is a QFP type semiconductor device 1 in which a plurality of leads 10 are arranged along each of the four sides of the semiconductor device 1 forming a quadrilateral. The semiconductor device 1 is a so-called multi-pin type semiconductor device in which the number of external terminals is increased by arranging a plurality of leads 10 on each of the four sides. For example, in the example shown in FIG. 1, as an example of a multi-pin type, there are 36 leads 10 arranged in total along each side. However, the number of leads 10 is not limited to the mode shown in FIG. 1 and can be further increased according to the required number of external terminals. For example, as a modified example with respect to FIG. 1, a semiconductor device in which a total of 256 leads 10 are arranged along each side can be provided.

  Further, as shown in FIG. 2, each of the plurality of leads 10 has a part (inner lead part 12) sealed with the sealing body 5 and the other part (outer lead part 11) exposed from the sealing body 5. Yes. The outer lead portion 11 is a terminal for electrically connecting to a terminal on the mounting board side when the semiconductor device 1 is mounted on a mounting board (not shown). In the present embodiment, the outer lead portion 11 is a side surface 5c of the sealing body 5. It is exposed so as to protrude outward from the outer periphery, and is formed in a gull wing shape on the outer side of the sealing body 5. In addition, on the surface (upper surface, lower surface, and side surface) of the outer lead portion 11, for example, an exterior plating film made of solder is used in order to improve the wettability of solder as a bonding material when electrically connected to the terminals of the mounting substrate. 13 is formed.

  Further, as shown in FIG. 1, the plurality of outer lead portions 11 arranged along each side (first side S1 to fourth side S4) of the sealing body have an equal number of arrangements from the center of each side ( The same number) is arranged at equal intervals. Specifically, among the plurality of outer lead portions 11, the plurality of first outer lead portions OL1 arranged along the first side S1 has the other arrangement number from the center of the first side S1 to one end. It arrange | positions at equal intervals so that it may become equal to the arrangement | positioning number between ends (18 each in FIG. 1). Similarly, among the plurality of outer lead portions 11, the plurality of second outer lead portions OL2 arranged along the second side S2 has the other arrangement number from the center of the second side S2 to one end portion. It arrange | positions at equal intervals so that it may become equal to the arrangement | positioning number between ends (18 each in FIG. 1). Further, among the plurality of outer lead portions 11, the plurality of third outer lead portions OL3 arranged along the third side S3 has the number of arrangements from the center of the third side S3 to one end portion at the other end. They are arranged at equal intervals so as to be equal to the number of arrangements up to the part (18 pieces in FIG. 1). In addition, among the plurality of outer lead portions 11, the plurality of fourth outer lead portions OL4 arranged along the fourth side S4 has the arrangement number from the center of the fourth side S4 to one end portion on the other end. They are arranged at equal intervals so as to be equal to the number of arrangements up to the part (18 pieces in FIG. 1). In other words, the plurality of outer lead portions 11 are arranged so as to be symmetrical with respect to the center of each side. The outer lead portion 11 is disposed so as to be symmetrical with respect to the first diagonal line DL1 and the second diagonal line DL2. Since the layout of the outer lead portion 11 is generally performed, in the present embodiment, by arranging the outer lead portion 11 in a general layout, no special terminal arrangement is required for the mounting board. It has a configuration. That is, the versatility of the semiconductor device 1 can be improved.

<Internal structure of semiconductor device>
Next, the internal structure of the semiconductor device 1 will be described.

  As shown in FIG. 2, the semiconductor device 1 includes a semiconductor chip 2, a tab (chip mounting portion, die pad) 3 on which the semiconductor chip 2 is mounted, a plurality of leads 10 arranged around the tab 3, and a semiconductor chip. 2 and a plurality of wires 4 that electrically connect the plurality of leads 10, and a sealing body 5 that seals the semiconductor chip 2 and the plurality of wires 4. As shown in FIG. 3, the semiconductor device 1 has two suspension leads 6 formed integrally with the tab 3. Hereinafter, details of each component will be described.

  The semiconductor chip 2 disposed in the sealing body 5 is located between the front surface (main surface) 2a, the back surface (main surface) 2b located on the opposite side of the front surface 2a, and between the front surface 2a and the back surface 2b, It has a side surface 2c surrounding the periphery of the front surface 2a and the back surface 2b. As shown in FIG. 5, the planar shape (shape of the front surface 2a and the back surface 2b) of the semiconductor chip 2 is a quadrangle. A plurality of pads (bonding pads, chip electrodes, electrode pads) 2d which are external connection terminals of the semiconductor chip 2 are formed on the surface 2a. The plurality of pads 2d are arranged on the peripheral edge side on the surface 2a along each side of the semiconductor chip 2.

  The semiconductor chip 2 includes a semiconductor substrate made of, for example, silicon, and a plurality of wiring layers stacked on the semiconductor substrate. A plurality of semiconductor elements (circuit elements) such as diodes and transistors are formed on the surface 2a side of the semiconductor chip 2 (specifically, the element formation surface (main surface) of the semiconductor substrate), and the semiconductor chip 2 is formed on the semiconductor element. A plurality of pads 2d are electrically connected to each other through a wiring (wiring layer) that is not connected. Thus, the semiconductor chip 2 constitutes an integrated circuit by a plurality of semiconductor elements formed on the surface 2a and wirings for electrically connecting the plurality of semiconductor elements. In addition, the base material (semiconductor substrate) having the surface 2a which is a semiconductor element formation surface of the semiconductor chip 2 is made of, for example, silicon (Si). Further, a passivation film (not shown) that is an insulating film is formed on the surface 2a, and each surface of the plurality of pads 2d is exposed from the insulating film in the opening formed in the passivation film. Yes. The pad 2d is made of metal, and in the present embodiment, is made of, for example, aluminum (Al). Further, a plating film is formed on the surface of the pad 2d. In the present embodiment, a multilayer plating film having a multilayer structure in which a gold (Au) film is formed through, for example, a nickel (Ni) film is provided. Is formed.

  The semiconductor chip 2 is mounted on the tab 3 which is a chip mounting portion via an adhesive (die bond material) 7. In the present embodiment, the semiconductor chip 2 is mounted by a so-called face-up mounting method in which the semiconductor chip 2 is mounted on the tab 3 with the back surface 2b facing the upper surface 3a of the tab 3. The adhesive 7 is not particularly limited as long as it can firmly fix the semiconductor chip 2 on the tab 3. In the present embodiment, for example, an epoxy-based thermosetting resin is used.

  Moreover, the tab 3 has the lower surface 3b located in the other side of the upper surface 3a and the upper surface 3a, as shown in FIG. 2 and FIG. The tab 3 is made of a metal material, and is made of, for example, copper (Cu) in the present embodiment. Specifically, a thin plated conductor film (not shown) made of, for example, nickel (Ni) is formed on the surface of a base material made of copper (Cu). Moreover, the planar shape of the tab 3 is circular as shown in FIG. 5, for example, and has a smaller area than the back surface 2b of the semiconductor chip 2 (see FIG. 2). For this reason, the entire upper surface 3 a of the tab 3 is covered with the semiconductor chip 2. In FIG. 5, as an example of the planar shape of the tab 3, a circular shape capable of mounting the semiconductor chips 2 having various planar sizes is shown. However, depending on the shape and planar size of the semiconductor chip 2 to be mounted. Various modifications can be applied.

  As shown in FIGS. 3 and 5, the tab 3 is supported by the suspension leads 6. The suspension lead 6 has an upper surface 6a and a lower surface 6b located on the opposite side of the upper surface 6a. The suspension lead 6 is made of the same metal material as that of the tab 3, and is made of, for example, copper (Cu) in the present embodiment. Specifically, a thin plated conductor film (not shown) made of, for example, nickel (Ni) is formed on the surface of a base material made of copper (Cu). In the present embodiment, two suspension leads 6 are connected to the tab 3 and are integrally formed with the tab 3. As shown in FIG. 3, among the two suspension leads 6, the first suspension lead SL1 extends from the tab 3 toward the first corner C1 of the sealing body 5 along the first diagonal line DL1 shown in FIG. Extend. Of the two suspension leads 6, the second suspension lead SL2 extends from the tab 3 toward the second corner C2 of the sealing body 5 along the first diagonal line DL1 shown in FIG. On the other hand, as shown in FIG. 4, the suspension leads 6 are not arranged in the direction along the second diagonal line DL2. That is, the support structure of the tab 3 of the present embodiment supports the tab 3 by the two suspension leads 6 (the first suspension lead SL1 and the second suspension lead SL2) extending along the first diagonal line DL1. Has a suspended structure.

  Further, as shown in FIG. 3, each of the two suspension leads 6 has an inclined portion (offset) between the tab 3 and the corner portion (first corner portion C1 or second corner portion C2) of the sealing body 5. Part, bending part) 6c. The suspension lead 6 of the present embodiment is subjected to a so-called downset process in which the height of the end portion on the tab 3 side of the inclined portion 6c is lower than the end portion on the opposite side. By performing downset processing on the plurality of suspension leads 6, the height of the tab 3 is arranged at a position lower than the height of the lead 10 as shown in FIG. 2. As a result, the plurality of wires 4 connected to the semiconductor chip 2 can be sealed, and the entire thickness of the sealing body 5 can be reduced. That is, the semiconductor device 1 can be thinned. Further, as shown in FIG. 5, the inclined portion 6 c is disposed between the leads 10 in a plan view. By arranging the inclined portion 6 c between the leads 10, the height of the upper surface 6 a (see FIG. 3) of the suspension lead 6 in the region inside the lead 10 is the same height as the upper surface 3 a (see FIG. 3) of the tab 3. Can be. As a result, the semiconductor chip 2 having an arbitrary size can be stably mounted on the tab 3 within a range that fits inside the lead 10.

  Further, as shown in FIGS. 2 and 5, a plurality of leads 10 are arranged around the tab 3 (in other words, around the semiconductor chip 2). As shown in FIG. 2, the plurality of leads 10 have an upper surface 10a and a lower surface 10b positioned on the opposite side of the upper surface 10a. The lead 10 is made of the same metal material as that of the tab 3 and the suspension lead 6, and is made of, for example, copper (Cu) in the present embodiment. Specifically, a thin plated conductor film (not shown) made of, for example, nickel (Ni) is formed on the surface of a base material made of copper (Cu). Further, the inner lead portion 12 of the lead 10 extends from the side surface 5c of the sealing body 5 toward the tab 3 (semiconductor chip 2), and bonding for bonding the wire 4 to the tip portion of the tab 3 (semiconductor chip 2). A region 12a is provided. Further, in the present embodiment, particularly the tip portions of the plurality of leads 10 are arranged at a narrow pitch in a narrow region, and therefore an insulating adhesive (adhesive tape) 8 is attached to the plurality of leads 10. Thus, contact between adjacent leads 10 is suppressed. In the manufacturing process of the semiconductor device 1, the adhesive 8 is preferably bonded to the vicinity of the tip portion of the lead 10, particularly at the tip portion of the lead 10, because contact due to the displacement of the lead 10 is likely to occur. Further, as shown in FIG. 5, from the viewpoint of suppressing the contact between the lead 10 and the suspension lead 6, by arranging the adhesive 8 so as to surround the periphery of the tab 3, the plurality of leads 10 and the suspension leads 6. It is preferable to fix the plane position. Although details will be described later, in the wire bonding step of bonding the wire 4 to the lead 10, the adhesive 8 is preferably bonded to the upper surface 10 a side of the lead 10 in order to support the bonding region 12 a from the lower surface 10 b side. Other structural features of the lead 10 will be described in detail later.

  The semiconductor chip 2 and the plurality of leads 10 are electrically connected via a plurality of wires 4. Specifically, one end of the plurality of wires 4 is bonded to the plurality of pads 2d of the semiconductor chip, and the other end of the plurality of wires 4 is bonded to the bonding regions 12a of the plurality of leads 10, thereby The pad 2d and the lead 10 are electrically connected. The wire 4 is made of a metal material. In the present embodiment, the wire 4 is made of gold (Au) that has high electrical conductivity and can be easily processed. In addition, as a material which comprises a wire, you may use not only this but copper (Cu), for example. In this embodiment, the bonding portion between the wire 4 and the pad 2d is the first bond side, and the bonding portion between the bonding region 12a of the wire 4 and the lead 10 is the second bond side, and the bonding is performed by a so-called positive bonding method. An example is shown. However, the bonding method of the wire 4 is not limited to the positive bonding method. As a modification, the bonding portion of the bonding region 12a of the wire 4 and the lead 10 is the first bonding side, and the bonding portion of the wire 4 and the pad 2d is the first bonding method. A so-called reverse bonding method in which two bonds are used can also be used.

  The semiconductor chip 2, the plurality of wires 4, and the inner lead portions 12 of the plurality of leads 10 are sealed with a sealing body 5 made of resin. For this reason, the inner leads 12 of the plurality of wires 4 and the plurality of leads 10 are fixed and protected in the sealing body 5.

<Detailed structure of lead>
Next, the detailed structure of the plurality of leads 10 and the suspension leads 6 shown in FIGS. 6 to 9 are enlarged plan views of a D part, an E part, an F part, and a G part in FIG. 5, respectively.

  In the case of the multi-pin type semiconductor device 1 as in the present embodiment, the arrangement pitch between the plurality of leads 10 can be widened at the peripheral portion of the sealing body 5 like the outer lead portion 11 shown in FIG. it can. On the other hand, as shown in FIG. 5, since the leads 10 are densely arranged at the tip portion on the tab 3 side of the plurality of leads 10, the interval between the adjacent leads 10 is narrower than the interval at the peripheral portion. Become. When the arrangement interval of the leads 10 becomes narrow, there is a possibility that adjacent leads 10 come into contact with each other. As a method of preventing contact between the adjacent leads 10, the length of each lead 10 is shortened, and the position of the tip of the lead 10 is arranged close to the peripheral edge side of the sealing body 5 (see FIG. 4). Thus, a mode in which the space for arranging the leads 10 is ensured is conceivable.

  However, if the position of the tip of the lead 10 is arranged close to the peripheral edge side of the sealing body 5 (see FIG. 4), the length of the wire 4 connected to the lead 10 becomes long. In particular, in recent years, the semiconductor chip has been miniaturized, and the length of the wire 4 is further increased if the tip of the lead 10 cannot be brought closer to the semiconductor chip 2 side. The length of the wire 4 is an important factor that affects the reliability of the semiconductor device 1. For example, if the length of the wire 4 is increased, the wire 4 is easily deformed during the manufacturing process, which causes a short circuit failure between adjacent wires 4. In addition, if the length of the wire 4 is increased, the impedance component of the wire 4 increases, so that predetermined electrical characteristics may not be obtained. Further, when the wire 4 is formed of an expensive material such as gold in order to reduce the impedance component of the wire 4, the manufacturing cost increases if the length of the wire 4 is increased. Therefore, the inventor of the present application has studied a technique for suppressing the length of the wire 4 from increasing, and found the configuration of the present embodiment.

  That is, in the present embodiment, the tab 3 shown in FIG. 5 is supported by the two suspension leads 6 (the first suspension lead SL1 and the second suspension lead SL2) extending along the first diagonal line DL1 (see FIG. 4). Therefore, the suspension leads along the second diagonal line DL2 shown in FIG. 1 are not arranged. And the front-end | tip part of the some lead | read | reed 10 is arranged near the 2nd diagonal DL2 side. Specifically, in the present embodiment, the first lead group disposed along the first side S1 shown in FIG. 4, the second lead group disposed along the second side S2, and the third side S3. The third lead group to be arranged and the fourth lead group arranged along the fourth side S4 each include a plurality of leads 10. The tip portions of the plurality of leads 10 constituting each lead group have a certain width and are arranged at certain intervals. For example, the width (the width in plan view) of the tip portions of the leads 10 shown in FIG. 5 is 90 μm, and the distance between the tip portions of adjacent leads 10 is 60 μm. The term “constant” includes those that are strictly constant, but does not exclude those that are slightly deviated due to problems such as processing accuracy. Hereinafter, when the expression “constant” is used, the same meaning is used.

  On the other hand, the distance between the tips of the leads 10 arranged at the end of each lead group is not constant. That is, the distance between the tips of adjacent leads 10 across the suspension lead 6 (interval W3 between the corner lead pair CLD1 shown in FIG. 6 and interval W3 between the corner lead pair CLD2 shown in FIG. The gap between the tips of the adjacent leads 10 is not larger than the gap (the gap W4 between the corner lead pair CLD3 shown in FIG. 8 and the gap W4 between the corner lead pair CLD4 shown in FIG. 9). Specifically, among the plurality of leads 10 constituting the first lead group, the lead 10 arranged closest to the first corner C1 and the plurality of leads 10 constituting the fourth lead group are the first corners. The lead 10 arranged on the part C1 side constitutes a corner lead pair CLD1 shown in FIG. In addition, among the plurality of leads 10 constituting the second lead group, the lead 10 arranged closest to the second corner C2 and the second corner among the plurality of leads 10 constituting the third lead group. The leads 10 arranged on the C2 side constitute a corner lead pair CLD2 shown in FIG. In addition, among the plurality of leads 10 constituting the second lead group, the lead 10 arranged closest to the third corner C3 and the third corner among the plurality of leads 10 constituting the fourth lead group. The leads 10 arranged on the C3 side constitute a corner lead pair CLD3 shown in FIG. Further, among the plurality of leads 10 constituting the first lead group, the lead 10 arranged closest to the fourth corner C4 and the fourth corner among the plurality of leads 10 constituting the third lead group. The leads 10 arranged on the C4 side constitute a corner lead pair CLD4 shown in FIG. Here, the interval between the tip portions on the tab 3 side of the corner lead pair CLD1 shown in FIG. 6 and the corner lead pair CLD2 shown in FIG. 7 is wide because the suspension lead 6 is disposed therebetween. For example, in the present embodiment, the width (width in plan view) W1 of the suspension lead 6 is 300 μm. Further, the interval W2 between the suspension leads 6 and the tips of the leads 10 arranged next to the suspension leads 6 is 250 μm. For this reason, the distance W3 between the tips on the tab 3 side of the corner lead pair CLD1 shown in FIG. 6 and the corner lead pair CLD2 shown in FIG. 7 is 800 μm. On the other hand, the interval lead (distance between the end portions) W4 on the tab 3 side of the corner lead pair CLD3 shown in FIG. 8 and the corner lead pair CLD4 shown in FIG. It can be made narrower than the corner lead pair CLD1, CLD2. For example, in this embodiment, it is 100 μm.

  Here, between the corner lead pair CLD1 and CLD2 in which the suspension leads 6 are arranged as shown in FIGS. 6 and 7, in addition to 300 μm of the width W1 of the suspension leads 6, 250 μm is provided on both sides thereof. There is a gap. This is to prevent the lead 10 disposed next to the suspension lead 6 and the molding die from coming into contact when the inclined portion 6c of the suspension lead 6 is formed, for example, by press working using a molding die. Is the clearance. When the inclined portion 6c is not formed in the suspension lead 6, the gap (interval W2) on both sides of the suspension lead 6 can be set to about 100 μm, for example. Further, as shown in FIGS. 8 and 9, a gap (interval) that is larger than the distance (for example, 60 μm) between the leads 10 constituting each lead group is formed between the pair of corner leads CLD3 and CLD4 in which no suspension leads are arranged. W4 (for example, 100 μm) is vacant for the following reason. That is, when the tip portions of the plurality of leads 10 are formed by, for example, pressing using a punching die, the tip portions of the leads 10 tend to be displaced toward the diagonal line connecting the corner portions. This is because in the press working using the punching die, the press working is sequentially performed from the center lead of each lead group toward both ends. In order to prevent the tip of the lead 10 located at the end of each lead group from contacting, a gap of 100 μm is opened in this embodiment. However, as a modification, when the tip portions of the plurality of leads 10 are formed by, for example, etching, it can be set to 60 μm similarly to the arrangement interval of each lead group.

  Further, in the present embodiment, since the suspension leads along the second diagonal line DL2 (see FIG. 4) are not disposed, the tip portion on the tab 3 side of the lead 10 can be disposed in the space around the diagonal line. And the front-end | tip part of the some lead | read | reed 10 which comprises each lead group is located in a line from the 2nd diagonal line DL2 side toward the 1st diagonal line DL1 (refer FIG. 4) at the substantially fixed space | interval. Therefore, the planar arrangement of the tip portions of the plurality of leads 10 constituting each lead group can be expressed as follows. That is, when the line connecting the center of the first side S1 and the center of the second side S2 shown in FIG. 4 is the first center line (virtual line) CL1 (see FIG. 4), a plurality of lines constituting the first lead group The tip of the lead (first lead) 10 is arranged in a region between the first center line CL1 and the first diagonal line DL1 in the number of regions arranged between the first center line CL1 and the second diagonal line DL2. More than the number placed. In addition, the number of first tip lines of the plurality of leads (second leads) 10 constituting the second lead group is arranged in the region between the first center line CL1 and the second diagonal line DL2. More than the number arranged in the region between CL1 and the first diagonal DL1. Further, when the line connecting the center of the third side S3 and the center of the fourth side S4 shown in FIG. 4 is the second center line (virtual line) CL2 (see FIG. 4), a plurality of lines constituting the third lead group The tip of the lead (third lead) 10 is arranged in the region between the second center line CL2 and the first diagonal line DL1 in the number arranged in the region between the second center line CL2 and the second diagonal line DL2. More than the number to be. In addition, the number of the tip portions of the plurality of leads (fourth leads) 10 constituting the fourth lead group is arranged in the region between the second center line CL2 and the second diagonal line DL2 is the second center line. More than the number arranged in the region between CL2 and the first diagonal DL1. That is, in the present embodiment, the tips of the leads 10 are arranged close to the second diagonal line DL2 shown in FIG.

  For this reason, even if the positions of the tips of the leads 10 are close to the semiconductor chip 2, the leads 10 can be arranged at an arrangement interval that can suppress contact between the tips of the adjacent leads 10. Further, in each lead 10, the bonding region 12 a for connecting the wire 4 is located at the tip of the lead 10 on the tab 3 side. Therefore, if the position of the tip of the lead 10 is close to the semiconductor chip 2, the wire 4 Can be shortened. For this reason, in the semiconductor device 1 of the present embodiment, it is possible to suppress a short circuit failure between the adjacent wires 4 due to the deformation of the wires 4 during the manufacturing process. In addition, since the impedance component of the wire 4 can be kept to a minimum, predetermined electrical characteristics can be easily obtained. Moreover, in this Embodiment, although the wire 4 consists of gold | metal | money, since the length of the wire 4 can be shortened, manufacturing cost can be reduced. In particular, in the case of the semiconductor device 1 having an offset structure in which the suspension lead 6 includes the inclined portion 6c (see FIG. 3) as in the present embodiment, the suspension lead along the second diagonal line DL2 (see FIG. 4) is removed. As a result, a wide space for arranging the tip of the lead 10 can be secured. For example, in the example described above, a width of 700 μm (800 μm-100 μm) can be secured. Therefore, by removing the suspension leads and arranging the tip portions of the leads 10 close to the diagonal line from which the suspension leads are removed, the distance between the tip portions of the leads 10 and the semiconductor chip 2 can be reduced. large.

  Moreover, in this Embodiment, as shown in FIG. 4, the some outer lead part 11 arrange | positioned along each edge | side (1st edge | side S1-4th edge | side S4) of a sealing body is respectively the center of each edge | side. Are arranged at equal intervals so that the number of arrangements from each other becomes equal (the same number). Specifically, among the plurality of outer lead portions 11, the plurality of first outer lead portions OL1 arranged along the first side S1 has the arrangement number from the first center line CL1 to one end portion on the other end. They are arranged at equal intervals so as to be the same as the number of arrangements up to the part (18 pieces in FIG. 4). Similarly, among the plurality of outer lead portions 11, the plurality of second outer lead portions OL2 arranged along the second side S2 are arranged at the other end from the first center line CL1 to one end portion. They are arranged at equal intervals so as to be the same as the number of arrangements up to the part (18 pieces in FIG. 4). Further, among the plurality of outer lead portions 11, the plurality of third outer lead portions OL3 arranged along the third side S3 has the number of arrangements from the second center line CL2 to one end portion on the other end portion. It arranges at equal intervals so that it may become the same number as the number of arrangements until (18 in FIG. 4 each). Further, among the plurality of outer lead portions 11, the plurality of fourth outer lead portions OL4 arranged along the fourth side S4 has the number of arrangements between the second center line CL2 and one end portion on the other end portion. It arranges at equal intervals so that it may become the same number as the number of arrangements until (18 in FIG. 4 each). For this reason, as described above, in the present embodiment, the outer lead portion 11 is arranged in a general layout so that a special terminal arrangement is not required for the mounting board. That is, the versatility of the semiconductor device 1 can be improved.

  In the present embodiment, the tip portions of the plurality of leads 10 are arranged close to the second diagonal line DL2 shown in FIG. 1, and therefore, adjacent corner lead pairs CLD3 (see FIG. 8) across the second diagonal line DL2. ), The distance between the wires 4 connected to the CLD4 (see FIG. 9) is connected to the corner lead pair CLD1 (see FIG. 6) and CLD2 (see FIG. 7) adjacent to each other across the first diagonal line DL1, respectively. The distance between the wires 4 is narrower. For this reason, in the manufacturing process of the semiconductor device described later, in particular, deformation of the wire 4 in the sealing process can be suppressed. The detailed reason for suppressing the deformation of the wire 4 in the sealing step will be described later.

<Manufacturing process of semiconductor device>
Next, a manufacturing process of the semiconductor device 1 shown in FIGS. 1 to 9 will be described. The semiconductor device 1 is manufactured along the assembly flow shown in FIG. FIG. 10 is an explanatory diagram showing an assembly flow of the semiconductor device of the present embodiment. Details of each step will be described below with reference to FIGS.

1. Lead frame preparation process;
FIG. 11 is a plan view showing the overall structure of the lead frame prepared in the lead frame preparation step shown in FIG. 10, and FIG. 12 is an enlarged plan view around one product formation region among the plurality of product formation regions shown in FIG. FIG.

  First, as a lead frame preparation step shown in FIG. 10, a lead frame 20 as shown in FIG. 11 is prepared. The lead frame 20 is made of, for example, copper (Cu). Specifically, a thin plated conductor film (not shown) made of, for example, nickel (Ni) is formed on the surface of a base material made of copper (Cu). The thickness of the constituent members of the lead frame 20 is, for example, 125 μm. Further, the lead frame 20 includes a plurality of product formation regions 20a arranged in a matrix, for example. The plurality of product formation regions 20a are each surrounded by and supported by a frame portion (frame body) 20b. As shown in FIG. 12, which is a partially enlarged view of FIG. 11, each product formation region 20a has a tab 3, a plurality of suspension leads 6 that support the tab 3, and a tab 3 described with reference to FIGS. A plurality of leads 10 are formed around the periphery of each other. The tab 3, the plurality of suspension leads 6, and the plurality of leads 10 are integrally formed and connected to the frame portion 20b. The product formation region 20a includes a first side S1, a second side S2, a third side S3, and a fourth side S4. The product formation region 20a is located between the first corner C1 between the first side S1 and the fourth side S4, and between the second side S2 and the third side S3. It is located between the second corner C2 facing C1, the third corner C3 between the second side S2 and the fourth side S4, and between the first side S1 and the third side S3. A fourth corner C4 that faces the corner C3 is provided.

  The tab 3 which is a chip mounting portion for mounting a semiconductor chip is disposed at the center of the product formation region 20a. The tab 3 is coupled to the plurality of suspension leads 6 described with reference to FIGS. 1 to 9 and supported by the frame portion 20 b via the suspension leads 6. The plurality of suspension leads 6 are respectively disposed along the first diagonal line DL1, and the suspension leads along the second diagonal line DL2 are not disposed. Each suspension lead 6 has an inclined portion 6c. That is, the lead frame 20 prepared in this step has been previously subjected to offset processing (downset processing). In FIG. 12, the suspension lead is bifurcated at the first corner portion C1 or the second corner portion C2 and connected to the frame portion 20b. This is for enlarging the flow path of the sealing resin in the sealing step shown in FIG. However, the shape of each suspension lead 6 is not limited to the embodiment shown in FIG. 12. For example, as a modified example, the shape is extended without branching to the first corner portion C1 or the second corner portion C2 and connected to the frame portion 20b. It can be.

  A plurality of leads 10 are arranged around the tab 3. Specifically, a plurality of leads 10 are arranged along the first side S1, the second side S2, the third side S3, and the fourth side S4 of the product formation region 20a. A dam part (dam bar, tie bar) 21 extending so as to intersect (orthogonal) the plurality of leads 10 is disposed between the plurality of leads 10, and the plurality of leads 10 are connected to the lead frame via the dam part 21. 20 is formed integrally. The dam portion 21 is arranged so as to surround the tab 3. In a sealing step (see FIG. 10) to be described later, a sealing resin is supplied to the inside of the region surrounded by the dam portion 21 to form the sealing body 5 shown in FIG. In addition, bonding regions 12a are provided at the tips of the plurality of leads 10 on the tab 3 side. The bonding region 12a is a region where one end of the wire is bonded in a wire bonding step (see FIG. 10) described later. An insulating adhesive material (adhesive tape) 8 is attached to the plurality of leads 10 so as to surround the tab 3. The adhesive 8 is disposed on the tip side from the middle of the lead 10. Thereby, in the area | region where the some lead | read | reed 10 is arrange | positioned with a narrow pitch, it can suppress that the adjacent leads 10 contact. The adhesive 8 is disposed on the outer peripheral side with respect to the bonding region 12a. In other words, the adhesive 8 is disposed on the tip end side of the lead 10 so that the bonding region 12a provided at the tip end of the plurality of leads 10 is exposed. In addition, the respective leading ends of the plurality of leads 10 are arranged closer to the second diagonal line DL2 where the suspension lead 6 is not disposed than the first diagonal line DL1 where the suspension lead 6 is disposed.

  The lead frame 20 shown in FIGS. 11 and 12 is formed as follows, for example. First, a metal plate (for example, a copper plate formed by plating a nickel film) is prepared, and the pattern shown in FIGS. 11 and 12 is formed by pressing or etching. At this time, in order to suppress deformation of the tip portion of the lead 10 during processing, patterning is performed in a state where the tip portion of the lead 10 is connected, and after the pattern is formed, the tips of the plurality of leads 10 are formed. It is preferable to separate the part by, for example, pressing or etching.

  Next, as an offset process, the suspension lead 6 is offset to form the inclined portion 6c. In this offset process, as shown in FIGS. 13 to 16, the inclined lead 6 c is formed on the suspension lead 6 by pressing using a molding die 27 including an upper die 25 and a lower die 26. 13 to 16 are enlarged sectional views schematically showing an offset process for forming the inclined portion of the suspension lead shown in FIG. FIG. 17 is an enlarged plan view showing a planar positional relationship between the pressing portion of the upper mold shown in FIGS. 13 to 16 and the lead frame shown in FIG. The molding die 27 used in the offset process includes an upper die 25 and a lower die 26 as shown in FIGS. The upper mold 25 includes a pressing portion 25 a that protrudes toward the lower mold 26 on the lower surface side. On the other hand, the lower mold 26 includes a recessed portion 26 a at a position facing the pressing portion 25 a of the upper mold 25. Then, when the lower surface of the upper die 25 and the upper surface of the lower die 26 are brought close to each other and the suspension lead 6 disposed between the pressing portion 25a and the depression portion 26a is pressed, as shown in FIG. 15 and FIG. The inclined portion 6c is formed following the shape of the pressing portion 25a and the recessed portion 26a. When the inclined portion 6c is formed by press working as described above, the width of the pressing portion 25a of the molding die 27 is as shown in FIG. 17 in consideration of the alignment accuracy between the molding die 27 and the lead frame 20. It is preferable to make it thicker than the width of the suspension lead 6. However, when the width of the pressing portion 25a is increased, it is necessary to prevent the lead 10 disposed in the vicinity of the suspension lead 6 from contacting the pressing portion 25a. For this reason, in this embodiment, the interval W2 between the suspension lead 6 and the tip of the lead 10 arranged next to the suspension lead 6 is set to 250 μm. Thereby, it can suppress that the press part 25a and the lead | read | reed 10 contact and the lead | read | reed 10 deform | transforms at the time of press work.

  Next, as shown in FIG. 12, as the lead tip portion fixing step, the tip portion of the lead 10 is fixed by applying and curing the adhesive 8 in the vicinity of the tip portion of the lead 10 on the tab 3 side. In the present embodiment, the adhesive material 8 is applied after the offset process so that the adhesive material 8 is not sandwiched between the molding dies 27 shown in FIGS. 13 to 16 in the offset process. However, the timing for fixing the tip portion of the lead 10 is not limited to the above, and for example, the lead tip portion fixing step can be performed before the offset step. In this case, since the adhesive 8 is disposed between the molding dies 27, the adhesive 8 and the molding dies 27 are not in contact with each other from the viewpoint of reducing the influence on the shape and moldability of the inclined portion 6c. Is preferred. However, the shape of each suspension lead 6 is not limited to the aspect shown in FIG. 16, and for example, as a modification, it is not necessary to perform press working. In this case, the distance between the suspension lead and the lead adjacent to the suspension lead can be further reduced.

2. Die bonding process;
18 is an enlarged plan view showing a state in which a semiconductor chip is mounted on the tab shown in FIG. 12 via a bonding material, FIG. 19 is an enlarged cross-sectional view taken along the line HH of FIG. 18, and FIG. It is an expanded sectional view along the KK line of FIG.

  Next, as a die bonding step shown in FIG. 10, the semiconductor chip 2 is mounted on the tab 3 via the adhesive 7 as shown in FIGS. 18 to 20. In this embodiment, as shown in FIGS. 19 and 20, mounting is performed by a so-called face-up mounting method in which the back surface 2 b of the semiconductor chip 2 is mounted facing the top surface 3 a of the tab 3. In the present embodiment, for example, the semiconductor chip 2 is mounted via an adhesive 7 that is an epoxy-based thermosetting resin. The adhesive 7 is a paste that has fluidity before being cured (thermoset). It is a material. When the paste material is used as the adhesive material 7 in this way, first, the adhesive material 7 is applied onto the tab 3, and then the back surface 2 b of the semiconductor chip 2 is bonded to the upper surface 3 a of the tab 3. Then, after bonding, when the adhesive 7 is cured (for example, heat treatment is performed), the semiconductor chip 2 is fixed on the tab 3 via the adhesive 7 as shown in FIGS. 19 and 20. In the present embodiment, an embodiment in which a paste material made of a thermosetting resin is used for the adhesive material 7 has been described, but various modifications can be applied. For example, instead of a paste material, an adhesive material that is a tape material (film material) having an adhesive layer on both sides is attached in advance to the back surface 2b of the semiconductor chip 2, and the semiconductor chip 2 is placed on the tab 3 via the tape material. May be installed.

  Further, in the present embodiment, by arranging the inclined portion 6 c of the suspension lead 6 between the leads 10, the region inside the tip portion on the tab 3 side of the lead 10 has the same height. For this reason, the semiconductor chip 2 having an arbitrary size can be mounted as long as it has a planar size that fits inside the tip of the lead 10 on the tab 3 side. That is, the versatility of the lead frame 20 can be improved.

3. Wire bonding process;
21 is an enlarged plan view showing a state in which the electrode pads and leads of the semiconductor chip shown in FIG. 18 are electrically connected via wires, and FIG. 22 is an enlarged cross-sectional view taken along line HH in FIG. is there.

  Next, as a wire bonding step shown in FIG. 10, as shown in FIGS. 21 and 22, the plurality of pads 2 d of the semiconductor chip 2 and the plurality of leads 10 are electrically connected through the plurality of wires 4, respectively. In this step, for example, as shown in FIG. 22, a heat stage 30 in which a recess 30a is formed is prepared, and the lead frame 20 on which the semiconductor chip 2 is mounted is heat stage so that the tab 3 is positioned in the recess 30a. 30. Then, the pads 2 d of the semiconductor chip 2 and the leads 10 are electrically connected via the wires 4. Here, in the present embodiment, the wire 4 is supplied through the capillary 31, and the wire 4 is bonded by a so-called nail head bonding method using both ultrasonic waves and thermocompression bonding. In the present embodiment, after one end of the wire 4 is connected to the pad 2d of the semiconductor chip 2, the other end of the wire 4 is connected to the bonding region 12a of the lead 10 (inner lead portion 12). The wire 4 is joined by a so-called positive bonding method. In this step, the lead 10 is heated via the heat stage 30. From the viewpoint of suppressing the adhesive 8 bonded to the lead 10 from inhibiting the adhesion between the heat stage 30 and the lead 10, the adhesive 8 is used. Is disposed on the upper surface 10 a side of the lead 10, and the lower surface 10 b side is preferably exposed from the adhesive 8.

  Further, since the wire 4 connects the pad 2 d and the lead 10, the interval between the adjacent wires 4 is defined by the arrangement of the pad 2 d and the lead 10. Therefore, in the present embodiment, the interval between the wires 4 connected to the corner lead pairs CLD1, CLD2, CLD3, and CLD4 is connected to the leads 10 other than the corner lead pairs CLD1, CLD2, CLD3, and CLD4. It is wider than the distance between the wires 4. The distance between the wires 4c connected to the corner lead pair CLD3 and the distance between the wires 4d connected to the corner lead pair CLD4 are the same as the distance between the wires 4a connected to the corner lead pair CLD1 and the corners. It becomes narrower than the interval between the wires 4b connected to the lead pair CLD2. In other words, the arrangement interval of the wires 4c and 4d arranged adjacent to each other across the second diagonal line DL2 (see FIG. 12) is equal to the wire 4a arranged adjacent to each other across the first diagonal line DL1 (see FIG. 12). 4b becomes narrower than the arrangement interval.

4). Sealing step;
23 is an enlarged plan view showing a state in which a sealing body is formed in the product formation region of the lead frame shown in FIG. 21, and FIG. 24 is an enlarged cross-sectional view taken along line AA of FIG. FIG. 25 is an enlarged cross-sectional view showing a state in which the sealing resin is supplied into the cavity of the molding die in the cross section along the line AA shown in FIG. FIG. 26 is an enlarged cross-sectional view showing a state in which the sealing resin is supplied into the cavity of the molding die in the cross section taken along line BB shown in FIG.

  Next, as a sealing step shown in FIG. 10, as shown in FIGS. 23 and 24, the sealing body 5 is formed, and the semiconductor chip 2, the plurality of wires 4, and a part of the plurality of leads 10 (inner leads). Part 12) is sealed. When the sealing body 5 is formed, the plurality of wires 4 and the plurality of leads 10 in the sealing body 5 are fixed, and contact between adjacent wires 4 or leads 10 can be prevented.

  In this embodiment, the semiconductor chip 2 mounted on the lead frame 20 is fixed in the cavities 43 and 44 of the upper mold 41 and the lower mold 42 of the molding die 40 as shown in FIGS. In this state, a so-called transfer mold method is used in which a softened (plasticized) thermosetting resin (sealing resin 5d) is press-fitted into the cavities 43 and 44, and then heated and cured. The transfer mold method is preferable in that the sealing body 5 can be collectively formed in the plurality of product formation regions 20a, and thus the manufacturing can be performed efficiently.

  In this step, first, a molding die 40 shown in FIGS. 25 and 26 is prepared. The molding die 40 includes an upper die (first die) 41 that covers the upper surface (surface on which the semiconductor chip is mounted) side of the lead frame 20, and a lower surface (opposite surface of the surface on which the semiconductor chip is mounted). A lower mold (first mold) 42 covering the side is provided. The upper mold 41 has a cavity (concave part) 43, and the lower mold 42 has a cavity (concave part) 44, and the cavities 43 and 44 are overlapped to form the sealing body 5 shown in FIG. To create a space for Further, as shown in FIG. 25, a mold surface (clamp surface) 41 a is disposed around the cavity 43 of the upper mold 41. A mold surface (clamp surface) 42a is disposed around the cavity 44 of the lower mold 42, and is disposed opposite to the mold surface 41a. The molding die 40 fixes the lead frame 20 between the upper die 41 and the lower die 42 by sandwiching and holding the lead frame 20 between the opposing die surfaces 41a and 42a. The mold surfaces 41a and 42a extend to the inside of the dam portion 21 shown in FIG. 25 (the side close to the tab 3). In other words, the cavities 43 and 44 are respectively disposed inside the dam portion 21 shown in FIG. Thus, the sealing resin 5d shown in FIGS. 25 and 26 does not spread outside the dam portion 21 (see FIG. 25), and the sealing body 5 having the shape shown in FIGS. 25 and 26 is formed.

  Further, as shown in FIG. 26, the molding die 40 has a gate part 45 which is a supply part of the sealing resin 5d, and gas (air) in the cavities 43 and 44 and discharge of excess sealing resin 5d. It has the vent part 46 which is a part. In the present embodiment, the cavities 43 and 44 have four corners (the first corner C1, the second corner C2, the third corner C3, and the fourth corner C4 shown in FIG. 23). The gate portion 45 is disposed at the first corner C1, and the vent portion 46 is disposed at the remaining three corners. As shown in FIG. 26, the method of disposing the gate portion 45 on the side surface 43b of the cavity 43 is called a side gate method. The side gate method is advantageous in that the mold structure can be simplified as compared with a so-called top gate method in which the sealing resin 5d is supplied from above the cavity 43.

  Next, the flow direction of the sealing resin 5d will be described. The sealing resin 5d is supplied from the gate portion 45 into the cavities 43 and 44, and the gas (air) in the cavities 43 and 44 and the excess sealing resin 5d are pushed out by the supply pressure of the sealing resin 5d. And is discharged from the vent portion 46. In this embodiment, as shown in FIG. 26, the tab 3 is supported by the two suspension leads 6 along the first diagonal line DL1 (see FIG. 23) connecting the first corner C1 and the second corner C2. For this reason, although it is hard to deform | transform with respect to the external force from the direction along the extension direction of the suspension lead 6, it is orthogonal to the extension direction of the suspension lead 6 (along the 2nd diagonal line DL2 shown in FIG. 23). It is easy to be deformed with respect to an external force from the other direction. That is, when the supply pressure of the sealing resin 5d is applied along the second diagonal line DL2 shown in FIG. 23, the tab 3 and the semiconductor chip 2 mounted on the tab 3 are easily deformed by the pressure. Therefore, in the present embodiment, the gate portion 45 is disposed at the first corner portion C1 where the suspension lead 6 is disposed among the four corner portions of the sealing body forming region. Further, the vent portion 46 is disposed at the second corner portion C2 located on the opposite side of the first corner portion C1 via the tab 3. Thereby, the supply pressure of the sealing resin 5 d is applied along the extending direction of the suspension leads 6. As a result, it is possible to prevent or suppress the deformation of the tab 3 and the semiconductor chip 2 mounted on the tab 3 in the sealing step. That is, in the present embodiment, the gate 3 and the vent 46 are disposed along the first diagonal line DL1 (see FIG. 23) where the suspension leads 6 are disposed, so that the tab 3 is formed by the two suspension leads 6. In the manufacturing process of the semiconductor device having the supporting structure, the deformation of the tab 3 and the semiconductor chip 2 can be suppressed, and the decrease in the reliability of the semiconductor device due to the deformation can be suppressed. In the present embodiment, the vent portion 46 is also formed in the third corner portion C3 and the fourth corner portion C4 shown in FIG. 23 from the viewpoint of suppressing gas from staying in the corner portion and forming voids. is doing. Even in this case, if the vent portion 46 is disposed at the second corner portion C2, the supply pressure of the sealing resin 5d is applied along the extending direction of the suspension lead 6.

  In the present embodiment, in the wire bonding step described above, as shown in FIG. 21, the interval between the wires 4c connected to the corner lead pair CLD3 and the interval between the wires 4d connected to the corner lead pair CLD4 By narrowing, the so-called wire flow phenomenon in which the wire 4 is deformed by the supply pressure of the sealing resin 5d can be suppressed. The reason will be described below. FIG. 27 is an explanatory view schematically showing a state where the sealing resin is supplied to the region where the wires are arranged in the sealing step shown in FIG. 28 is an explanatory view schematically showing a cross section taken along line LL in FIG. 27, and FIG. 29 is a cross section taken along line MM in FIG. In FIG. 27, the supply direction of the sealing resin 5d is schematically shown.

  The wire flow phenomenon is a phenomenon in which the wire 4 is deformed by the supply pressure of the sealing resin in the sealing process. Specifically, it is a phenomenon in which the wire 4 is deformed so as to fall toward the adjacent wire 4 when the supply pressure of the sealing resin is applied from a direction intersecting (orthogonal) with respect to the extending direction of the wire 4. is there. For this reason, depending on the degree of deformation due to the wire flow phenomenon, the adjacent wires 4 come into contact with each other, which causes a decrease in the reliability of the semiconductor device. The inventor of the present application has studied the wire flow phenomenon and obtained the following knowledge. That is, as shown in FIG. 27, when supplying the sealing resin to a wire group composed of a plurality of wires 4 densely arranged at a narrow pitch, among the plurality of wires 4, the sealing resin 5d A wire flow phenomenon is likely to occur in the wire 4e arranged at a position closest to the supply side, and almost no wire flow phenomenon occurs in the other wires 4f and 4g. In addition, when the arrangement pitch with the wire 4g arranged on the supply side of the sealing resin 5d is wide like the wire 4h shown in FIG. 27, the wire flow phenomenon easily occurs.

  As shown in FIG. 28, in the region where the wires 4 are arranged at a narrow pitch, the sealing resin 5 d is divided into an upper part and a lower part by the wires 4 and then embedded in a gap between the adjacent wires 4. For this reason, the supply pressure of the sealing resin 5d is dispersed, and the force component in the traveling direction of the sealing resin 5d causing the wire flow phenomenon is reduced. On the other hand, as shown in FIG. 29, when the wire 4h having a wide arrangement pitch with the wire 4g is sealed, the sealing resin 5d divided into the upper part and the lower part comes into contact with the wire 4h again in an integrated state. To do. For this reason, the supply pressure of the sealing resin 5d applied to the wire 4h is not dispersed, and the force component in the traveling direction of the sealing resin 5d causing the wire flow phenomenon increases. As a result, it is considered that the wire flow phenomenon easily occurs in the wire 4h.

  Next, the principle of the above-described wire flow phenomenon will be described by applying it to the present embodiment. In this embodiment, since the sealing is performed by the side gate method, for example, as shown with an arrow in FIG. 23, the gate portion 45 (see FIG. 26) is arranged in a part of the sealing resin 5d. From the first corner portion C1, the tab 3 (see FIG. 26) and the semiconductor chip 2 (see FIG. 26) are wrapped around the periphery and proceed toward the second corner portion C2. The other part of the sealing resin 5d is also supplied on the semiconductor chip 2 and below the tab 3. However, the region where the semiconductor chip 2 and the tab 3 are arranged has resistance to the flow of the sealing resin 5d. Therefore, the sealing resin 5d that goes around the tab 3 and the semiconductor chip 2 is more common. The sealing resin 5d that wraps around the tab 3 and the semiconductor chip 2 proceeds in a direction intersecting the extending direction of the plurality of wires 4 shown in FIG. For this reason, if the arrangement pitch of the plurality of wires 4 is increased, the wire flow phenomenon is likely to occur.

  Therefore, in the present embodiment, as shown in FIG. 21, the interval between the wires 4c connected to the corner lead pair CLD3 and the interval between the wires 4d connected to the corner lead pair CLD4 are reduced. For this reason, a wire flow phenomenon can be suppressed. In this embodiment, the length of the wire 4 can be shortened by reducing the distance between the plurality of leads 10 and the semiconductor chip 2. This configuration can also suppress the wire flow phenomenon. Incidentally, the distance between the wires 4a connected to the corner lead pair CLD1 and the distance between the wires 4b connected to the corner lead pair CLD2 shown in FIG. 21 are wider than the distance between the wires 4c and 4d. Yes. However, the wire 4a is the wire 4 disposed at a position closest to the first corner C1 where the gate portion 45 (see FIG. 26) is disposed among the plurality of wires 4. For this reason, when the wire 4a is sealed, a wide space that is not filled with the sealing resin 5d (see FIG. 26) remains in the cavities 43 and 44 (see FIG. 26). The supply pressure of the applied sealing resin 5d can be relaxed. For this reason, generation | occurrence | production of a wire flow phenomenon can be suppressed in the wire 4a. Moreover, the wire 4b is the wire 4 arrange | positioned in the position furthest away from the 1st corner | angular part C1 which is the supply side of sealing resin 5d. Further, when the wire 4b is sealed, the other wires 4 are arranged at a narrow pitch next to the supply side of the sealing resin 5d, so that even if the supply pressure of the sealing resin 5d increases, the wire Flow phenomenon is unlikely to occur.

  As described above, according to the present embodiment, the wire flow phenomenon can be suppressed by narrowing the interval between the wires 4c and the wire 4d where the wire flow phenomenon is most likely to occur. As a result, contact between adjacent wires 4 can be suppressed, and a decrease in reliability of the semiconductor device 1 shown in FIGS. 1 to 9 can be suppressed.

  As described above, the cavities 43 and 44 are filled with the sealing resin 5d, and after the bubbles (voids) are removed, the sealing resin 5d is cured by heating to be sealed as shown in FIGS. Form body 5. In this heating step (baking step), for example, the sealing resin 5d is temporarily cured in the molding die 40 (see FIG. 25) (the entire sealing resin 5d is not cured, but is taken out from the molding die 40). Even if the shape can be maintained). Thereafter, the lead frame 20 is taken out from the molding die 40 and transferred to a heating furnace (not shown) to fully cure the sealing resin 5d (a state where the entire sealing resin 5d is cured). When this heating step is completed, the sealing body 5 shown in FIGS. 25 and 26 is formed.

5. Dam cut process;
FIG. 30 is an enlarged plan view showing a state where the dam portion shown in FIG. 23 is cut. Next, as a dam cutting step shown in FIG. 10, as shown in FIG. 30, dam portions 21 formed between the plurality of leads 10 (outer lead portions 11) and connecting the plurality of leads 10 are removed. In this step, for example, the dam portion 21 is removed by performing press working using a punch (cutting blade) and a die (support jig) (not shown). At this time, a part of the resin body (resin within the dam) formed inside the dam portion 21 is also removed together with the dam portion 21. In this step, the ends of the outer lead portions 11 of the plurality of leads 10 are connected to the frame portion 20b of the lead frame. In other words, even after the dam portion 21 is removed, the plurality of leads 10 are integrally formed via the frame portion 20 b of the lead frame 20.

6). Plating process;
FIG. 31 is an enlarged cross-sectional view showing a state in which an exterior plating film is formed on the exposed surfaces of a plurality of leads exposed from the sealing body in the cross section taken along the line AA shown in FIG.

  Next, as a plating step shown in FIG. 10, an exterior plating film 13 is formed on the plurality of leads 10 (outer lead portions 11) exposed from the sealing body 5 as shown in FIG. The exterior plating film 13 is made of, for example, solder. By forming the exterior plating film 13 on the lead 10 that is an external terminal, the exterior plating film 13 is a solder that is a bonding member when the semiconductor device 1 shown in FIG. The wettability of the material can be improved. In this step, the lead frame 20 that is a workpiece to be plated is placed in a plating tank (not shown) containing a plating solution (not shown), and the exterior plating film 13 is formed by, for example, electrolytic plating. To do. According to this electrolytic plating method, the exterior plating film 13 can be collectively formed in the region exposed from the sealing body 5. Therefore, the exterior plating film 13 is formed on the upper surface, the lower surface, and the side surfaces of the plurality of outer lead portions 11.

7). Lead Molding FIG. 32 is an enlarged plan view showing a state where the outer lead part shown in FIG. 31 is cut and molded. Note that an enlarged cross-sectional view along line AA shown in FIG. 32 is the same as FIG.

  Next, as a lead molding step shown in FIG. 10, the outer lead portion 11 of the lead 10 is cut and separated from the frame portion 20b as shown in FIG. Thereafter, as shown in FIG. 2, each of the outer lead portions 11 of the plurality of leads 10 is formed into a gull wing shape. The method of cutting the outer lead portions 11 of the plurality of leads 10 is, for example, arranged by pressing a punch (cutting blade) (not shown) on the upper surface side of the lead frame 20 and a die (support jig) (not shown) on the lower surface side. Cut by. Moreover, the method of shape | molding the outer lead part 11 of the lead | read | reed 10 can be shape | molded by pressing using the punch and die | dye for shaping | molding. By this step, the plurality of leads 10 are separated from each other and become separate bodies. In addition, the plurality of leads 10 are separated from the lead frame 20 by this step. For this reason, if each member in the product formation region 20a is not supported by the frame portion 20b of the lead frame 20, it is difficult to mold. Therefore, in the present embodiment, as shown in FIG. 12, the suspension leads 6 are arranged in an area where the plurality of leads 10 are not arranged, and for example, the suspension leads 6 are sealed with a sealing body 5 as shown in FIG. ing. As a result, the product formation region 20a is connected to and supported by the frame portion 20b of the lead frame 20 through the suspension leads 6 (see FIG. 12) until the individualization process described later is completed.

8). FIG. 33 is an enlarged plan view showing a state where the product formation region shown in FIG. 32 is separated from the frame portion of the lead frame and separated into pieces.

  Next, as shown in FIG. 33, the product forming region 20a is separated from the frame portion 20b of the lead frame 20 and separated into pieces as shown in FIG. In this step, the suspension lead 6 (see FIG. 12), which is a connecting portion between the product forming region 20a and the frame portion 20b, is pressed using, for example, a punch (cutting blade) and a die (support jig) (not shown). To cut. At this time, the gate resin formed on the gate portion 45 and the vent resin formed on the vent portion 46 shown in FIG. 26 are respectively removed by punching.

  Through the above steps, the semiconductor device 1 shown in FIGS. 1 to 9 is obtained. Although not shown, in addition to the above steps, a mark step for forming a product identification symbol of the semiconductor device 1 is performed. Further, since the lead frame 20 of the present embodiment uses the lead frame 20 having a plurality of product formation regions 20a as shown in FIG. 11, a plurality of semiconductor devices 1 are obtained from one lead frame 20. can do. Thereafter, necessary inspections and tests such as an appearance inspection and an electrical test are performed and shipped or mounted on a mounting board (not shown).

<Modification>
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the embodiment applied to the QFP semiconductor device 1 and the manufacturing method thereof has been described. However, as a modification, the embodiment is applied to the QFN semiconductor device 50 as shown in FIGS. be able to. 34 is a plan view showing a lower surface (mounting surface) side of a semiconductor device which is a modification of the semiconductor device shown in FIG. 1, and FIG. 35 is a cross-sectional view corresponding to FIG. 2 in the semiconductor device shown in FIG. 36 is a perspective plan view corresponding to FIG. 4 in the semiconductor device shown in FIG. The semiconductor device 50 shown in FIGS. 34 to 36 is different from the semiconductor device 1 shown in FIG. 1 in that it is a QFN type semiconductor device.

  In the QFN type semiconductor device 50, when the semiconductor device 1 is mounted on a mounting substrate (not shown), the outer lead portion 11 that is a terminal for electrically connecting to a terminal on the mounting substrate side is formed on the lower surface ( The mounting surface 5b is exposed. In other words, the sealing body 5 is formed such that the outer lead portions 11 of the plurality of leads 10 are exposed from the lower surface 5 b of the sealing body 5. The semiconductor device 50 is disposed and electrically connected so that the outer lead portion 11 faces a terminal on the mounting substrate side (not shown). For this reason, as shown in FIG. 35, the lead 10 can be prevented from projecting from the side surface 5c of the sealing body 5, or the projecting length can be shortened, so that the semiconductor device 1 described in the first embodiment can be reduced. Further, the mounting area can be reduced. It is preferable that the exposed area of the outer lead portion 11 be as small as possible within a range in which electrical connection reliability with a terminal on the mounting substrate side can be secured during mounting. By reducing the exposed area, the lead 10 can be prevented from dropping or oxidized. For this reason, the semiconductor device 50 performs etching processing (half etching processing) from the lower surface 10 b side of the inner lead portion 12 of the lead 10 and seals the inner lead portion 12 with the sealing body 5. For this reason, as shown in FIG. 35, the lower surface 10b side of the bonding region 12a to which the wire 4 is bonded is also sealed. Therefore, the joint between the wire 4 and the lead 10 can be reliably protected.

  The semiconductor device 50 is different from the semiconductor device 1 described in the above-described embodiment in the above point, but includes a sealing body 5 having a quadrilateral shape in plan view, and a plurality of leads 10 along each of the four sides. Is the same as the semiconductor device 1 in that. Therefore, reliability can be improved by applying the technique described in the above embodiment. Since the semiconductor device 50 is the same as the semiconductor device 1 except for the above-described differences, a duplicate description is omitted.

  Further, for example, in the above-described embodiment, from the viewpoint of shortening the length of the wire 4, the tip portion on the tab 3 side of the lead 10 is used as a semiconductor by utilizing the space obtained by removing the suspension lead 6 along the second diagonal line DL 2. The mode of approaching the chip 2 has been described, but as a modification, it can be applied to a semiconductor device 55 having an increased number of external terminals as shown in FIG. FIG. 37 is a perspective plan view showing a semiconductor device which is another modification example of FIG. In FIG. 37, a modified example of the semiconductor device 1 described in the above embodiment will be described. However, the technique described below may be applied in combination with the QFN type semiconductor device 50 shown in FIGS. it can.

  The semiconductor device 55 shown in FIG. 37 has the above-described implementation in that a total of four leads 10 are added, two on each of the third corner C3 and the fourth corner C4 along the second diagonal line DL2. Different from the semiconductor device 1 described in the embodiment. In other words, in the semiconductor device 1 shown in FIGS. 1 to 9, the tips of the leads 10 arranged along each side are arranged close to the second diagonal line DL <b> 2 where the suspension leads 6 are not arranged. The outer lead portion 11 is arranged not symmetrically on one diagonal side but symmetrically with respect to the centers of the respective sides (the first side S1, the second side S2, the third side S3, and the fourth side S4). . On the other hand, the semiconductor device 55 shown in FIG. 37 is different from the semiconductor device 1 in that the tips of the plurality of leads 10 arranged along each side are arranged close to the second diagonal line DL2 where the suspension leads 6 are not arranged. It is the same. In addition to this, in the semiconductor device 55, the outer lead portion 11 is also arranged close to the second diagonal line DL2 side with respect to the center of each side. In other words, the semiconductor device 55 has a quadrilateral shape in plan view, and a plurality of leads 10 are arranged along each side (the first side S1, the second side S2, the third side S3, and the fourth side S4). Is done. And as for the some outer lead part 11 arrange | positioned along each edge | side (1st edge | side S1-4th edge | side S4) of the sealing body 5, the arrangement | positioning number from the center of each edge | side is respectively 1st from the center of each edge | side. It arrange | positions at equal intervals so that the arrangement | positioning number by the side of the 1st diagonal line DL1 may increase from the center of each edge | side rather than the arrangement | positioning number by the side of 1 diagonal line DL1. Specifically, among the plurality of outer lead portions 11, the plurality of first outer lead portions OL1 arranged along the first side S1 is the end of the second diagonal line DL2 from the center (first center line CL1) of the first side S1. Are arranged at equal intervals so that the number of arrangements up to the portion (19 in FIG. 37) is larger than the number of arrangements up to the end on the first diagonal line DL1 (18 in FIG. 37). Yes. Similarly, among the plurality of outer lead portions 11, the plurality of second outer lead portions OL2 arranged along the second side S2 extends from the center (first center line CL1) of the second side S2 to the end of the second diagonal line DL2. Are arranged at equal intervals so that the number of arrangements up to the portion (19 in FIG. 37) is larger than the number of arrangements up to the end on the first diagonal line DL1 (18 in FIG. 37). Yes. In addition, among the plurality of outer lead portions 11, the plurality of third outer lead portions OL3 arranged along the third side S3 are end portions of the second diagonal line DL2 from the center (second center line CL2) of the third side S3. Are arranged at equal intervals so that the number of arrangements up to (19 in FIG. 37) is larger than the number of arrangements up to the end on the first diagonal line DL1 (18 in FIG. 37). . In addition, among the plurality of outer lead portions 11, the plurality of fourth outer lead portions OL4 arranged along the fourth side S4 are end portions of the second diagonal line DL2 from the center (second center line CL2) of the fourth side S4. Are arranged at equal intervals so that the number of arrangements up to (19 in FIG. 37) is larger than the number of arrangements up to the end on the first diagonal line DL1 (18 in FIG. 37). . Thus, by adding the leads 10 along the second diagonal line DL2 where the suspension leads 6 are not disposed, the semiconductor device 55 can increase the number of external terminals as compared with the semiconductor device 1. In the example shown in FIG. 37, corner lead pairs CLD3 and CLD4 are added along the second diagonal line DL2, and a total of 148 leads 10 are provided.

  Further, when the leads 10 are added along the second diagonal line DL2 as in the semiconductor device 55, the arrangement pitch of the leads 10 around the second diagonal line DL2 is as shown in a comparison between FIG. 4 and FIG. Narrower than 1. In other words, the leads 10 (inner lead portions) are spread around the semiconductor chip 2. For this reason, in the sealing step described in the above embodiment, the supply pressure can be stabilized when the sealing resin is supplied, so that the retention of gas in the cavity can be suppressed. As a result, it is possible to suppress voids (bubbles) from remaining in the sealing body 5. Further, since the tips of the plurality of leads 10 on the tab 3 side of the semiconductor device 55 are arranged close to the second diagonal line DL2 similarly to the semiconductor device 1, the wires 4 connected to the corner lead pairs CLD3 and CLD4 are arranged. The wire flow phenomenon can be suppressed.

  However, since the semiconductor device 55 adds the lead 10 using the space from which the suspension leads 6 are removed, the tip portion of the lead 10 cannot be brought closer to the semiconductor chip 2 than the semiconductor device 1. In other words, in the semiconductor device 55, the length of the lead 10 is shorter than that of the semiconductor device 1, and the distance between the tip portion of the lead 10 and the semiconductor chip 2 is longer than that of the semiconductor device 1. For this reason, the length of each of the plurality of wires 4 of the semiconductor device 55 is longer than the length of the wires 4 of the semiconductor device 1. Therefore, from the viewpoint of obtaining the effect by shortening the length of the wire 4 (for example, reduction of the impedance component of the wire 4, deformation during the manufacturing process of the wire 4, or reduction of the manufacturing cost), the above embodiment is described. The semiconductor device 1 described in the above or the semiconductor device 50 described in the modification are more preferable. Further, since the external layout of the semiconductor device 55 is a special layout, the semiconductor devices 1 and 50 are preferable from the viewpoint of versatility with respect to the mounting substrate.

  As another difference, in the semiconductor device 55, since the length of the lead 10 is shortened, the adhesive 8 shown in FIG. 5 is not disposed. However, since the presence or absence of the adhesive 8 can be determined in accordance with the ease of deformation of the lead 10 (particularly around the tip), the bonding region of the lead 10 and the outer lead portion 11 also in the semiconductor device 55. An adhesive material 8 as shown in FIG. 4 may be disposed between them. Except for the differences described above, the semiconductor device 55 is the same as the semiconductor device 1 described in the above-described embodiment, and thus a duplicate description is omitted.

  Moreover, in the said embodiment, although the tab mounting part which has a planar area smaller than the back surface 2b of the semiconductor chip 2 and formed circular planar shape was demonstrated as an example as a chip mounting part which mounts the semiconductor chip 2, a chip mounting part The shape is not limited to the above, and various sizes and shapes can be applied. Further, it is possible to apply a mode in which the semiconductor chip 2 is simply mounted on the suspension lead 6 without forming a chip mounting portion wider than the suspension lead 6. In this case, the region where the semiconductor chip 2 of the suspension lead 6 is mounted can be considered as a chip mounting portion.

  In the above embodiment, the example in which the lower surface 3b of the tab 3 is sealed by the sealing body 5 has been described. However, as a modification, the tab 3 is exposed from the lower surface 5b side of the sealing body 5. Can do.

  The present invention is applicable to semiconductor devices such as QFP and QFN.

1, 50, 55 Semiconductor device 2 Semiconductor chip 2a Surface (main surface)
2b Back side (main surface)
2c Side surface 2d Pad (bonding pad, chip electrode, electrode pad)
3 Tab (chip mounting part, die pad)
3a upper surface 3b lower surface 4, 4a, 4b, 4c, 4d, 4e, 4f, 4g, 4h wire 5 sealing body 5a upper surface 5b lower surface 5c side surface 5d sealing resin 6 suspension lead 6a upper surface 6b lower surface 6c inclined portion 7 adhesive 8 Adhesive 10 Lead 10a Upper surface 10b Lower surface 11 Outer lead portion 12 Inner lead portion 12a Bonding region 13 Exterior plating film 20 Lead frame 20a Product forming region 20b Frame portion 21 Dam portion 25 Upper die 25a Pressing portion 26 Lower die 26a Recessed portion 27 Molding Mold 30 Heat stage 30a Recess 31 Capillary 32 Wire 40 Mold 41 Mold 41a, 42a Mold surface (clamp surface)
42 Lower mold 43, 44 Cavity 43b Side 45 Gate part (supply part)
46 Vent part (discharge part)
C1 First corner C2 Second corner C3 Third corner C4 Fourth corner CL1 First center line (virtual line)
CL2 Second center line (virtual line)
CLD1, CLD2 Corner lead pair (first corner lead pair)
CLD3, CLD4 Corner lead pair (second corner lead pair)
DL1 First diagonal (imaginary line)
DL2 Second diagonal (virtual line)
OL1 1st outer lead part OL2 2nd outer lead part OL3 3rd outer lead part OL4 4th outer lead part S1 1st edge S2 2nd edge S3 3rd edge S4 4th edge SL1 1st suspension lead SL2 2nd suspension lead W1 width W2, W3, W4 interval

Claims (11)

A chip mounting portion;
A first suspension lead formed integrally with the chip mounting portion;
A second suspension lead formed integrally with the chip mounting portion;
A plurality of leads arranged around the chip mounting portion;
A semiconductor chip mounted on the chip mounting portion, having a front surface, a plurality of bonding pads formed on the front surface, and a back surface opposite to the front surface;
A plurality of wires for electrically connecting the plurality of bonding pads and the plurality of leads of the semiconductor chip,
A sealing body for sealing the semiconductor chip and the plurality of wires;
Including
The planar shape of the sealing body includes a first corner, a second corner facing the first corner and the chip mounting portion, a third corner located next to the second corner, A fourth corner facing the third corner via the chip mounting portion, a first side located between the first corner and the fourth corner, the second corner, and the third corner A second side located between, a third side located between the second corner and the fourth corner, and a fourth side located between the first corner and the third corner. Consisting of a square with
When a virtual line connecting the first corner and the second corner is a first diagonal line, and a virtual line connecting the third corner and the fourth corner is a second diagonal,
The first suspension lead extends from the chip mounting portion toward the first corner portion of the sealing body and along the first diagonal line in a plan view.
The second suspension lead extends from the chip mounting portion toward the second corner portion of the sealing body and along the first diagonal line in plan view,
A plurality of leads are arranged along each of the first to fourth sides, and in each of the plurality of leads, a bonding region for joining the plurality of wires to a tip portion located on the chip mounting portion side With
The plurality of leads are arranged adjacent to each other with two pairs of first corner leads arranged adjacent to each other with the first diagonal line in plan view, and with the second diagonal lines arranged in plan view. Two pairs of second corner lead pairs, and
The first or second suspension lead is disposed between the two pairs of first corner lead pairs,
No suspension leads are arranged between the two pairs of second corner lead pairs,
The arrangement interval of the tip portions of the two pairs of second corner lead pairs on the chip mounting portion side is narrower than the arrangement interval of the tip portions of the two pairs of first corner lead pairs on the chip mounting portion side. A semiconductor device characterized by the above. In claim 1,
Among the plurality of wires, the interval between the second wires connected to the two pairs of second corner lead pairs is the interval between the first wires connected to the two pairs of first corner lead pairs, respectively. A semiconductor device characterized by being narrower than that. In claim 1,
The first suspension lead includes a first inclined portion between the chip mounting portion and the first corner of the sealing body,
The second suspension lead includes a second inclined portion between the chip mounting portion and the second corner of the sealing body,
The first and second inclined portions are each disposed between the plurality of leads in a plan view. In claim 1,
The plurality of leads include a plurality of first leads constituting a first lead group disposed along the first side and a plurality of second leads constituting a second lead group disposed along the second side. Two leads, a plurality of third leads constituting a third lead group arranged along the third side, and a plurality of fourth leads constituting a fourth lead group arranged along the fourth side. Included,
When a virtual line connecting the center of the first side and the second side is a first center line, and a virtual line connecting the third side and the fourth side is a second center line,
The tip portions of the plurality of first leads on the chip mounting portion side are arranged in a region between the first center line and the second diagonal line so that the number of the first center line and the first diagonal line is greater. More than the number placed in the area between
The tip portions of the plurality of second leads on the chip mounting portion side are arranged in a region between the first center line and the second diagonal line so that the number of the first center line and the first diagonal line is greater. More than the number placed in the area between
The tip portions of the plurality of third leads on the chip mounting portion side are arranged in a region between the second center line and the second diagonal line so that the number of the first center line and the first diagonal line is greater. More than the number placed in the area between
The tip portions of the plurality of fourth leads on the chip mounting portion side are arranged in a region between the second center line and the second diagonal line so that the number of the first center line and the first diagonal line is greater. There are more semiconductor devices than the number arranged in the region between. In claim 4,
The plurality of leads are composed of a plurality of outer lead portions exposed from the sealing body, a plurality of inner lead portions formed integrally with the plurality of outer lead portions, and sealed to the sealing body,
The plurality of outer lead portions include a plurality of first outer lead portions constituting a first lead group disposed along the first side and a plurality of second lead groups disposed along the second side. A second outer lead portion, a plurality of third outer lead portions constituting a third lead group disposed along the third side, and a plurality of fourth lead groups disposed along the fourth side. A fourth outer lead portion is included,
The number of the first outer lead portions is the same as the number arranged between the first center line and one end, and the number arranged between the first center line and the other end. Yes,
The plurality of second outer lead portions is the same number as the number arranged between the first center line and one end, and the number arranged between the first center line and the other end. Yes,
The number of the third outer lead portions is the same as the number arranged between the second center line and one end, and the number arranged between the second center line and the other end. Yes,
The number of the fourth outer lead portions is the same as the number arranged between the second center line and one end, and the number arranged between the second center line and the other end. There is a semiconductor device. A method for manufacturing a semiconductor device comprising the following steps:
(A) a chip mounting portion, a first suspension lead formed integrally with the chip mounting portion, a second suspension lead formed integrally with the chip mounting portion, and a plurality of disposed around the chip mounting portion Preparing a lead frame with leads;
(B) mounting a semiconductor chip having a surface, a plurality of bonding pads formed on the surface, and a back surface opposite to the surface on the chip mounting portion;
(C) electrically connecting the plurality of bonding pads of the semiconductor chip and the plurality of leads via a plurality of wires;
(D) After the step (c), a sealing resin is supplied in a state where the semiconductor chip and the plurality of wires are arranged in the cavity of the molding die, and the semiconductor chip and the plurality of wires are sealed. The step of:
here,
In each of the plurality of leads, a bonding region for bonding the plurality of wires in the step (c) is disposed at a tip portion located on the chip mounting portion side.
The planar shape of the cavity includes a first corner, a second corner facing the first corner through the chip mounting portion, a third corner located next to the second corner, and the third corner. A fourth corner that faces the corner through the chip mounting portion, a first side located between the first corner and the fourth corner, and between the second corner and the third corner A quadrangle having a second side located at the second side, a third side located between the second corner and the fourth corner, and a fourth side located between the first corner and the third corner Consisting of
When a virtual line connecting the first corner and the second corner is a first diagonal line, and a virtual line connecting the third corner and the fourth corner is a second diagonal,
In the step (d),
The first suspension lead is disposed so as to extend from the chip mounting portion toward the first corner of the cavity and along the first diagonal line in plan view,
The second suspension lead is disposed so as to extend from the chip mounting portion toward the second corner of the cavity and along the first diagonal line in plan view,
The plurality of leads are disposed along each of the first to fourth sides,
The plurality of leads are arranged adjacent to each other with two pairs of first corner leads arranged adjacent to each other with the first diagonal line in plan view, and with the second diagonal lines arranged in plan view. Two pairs of second corner lead pairs, and
The first or second suspension lead is disposed between the two pairs of first corner lead pairs,
No suspension leads are arranged between the two pairs of second corner lead pairs,
The arrangement interval of the tip portions on the chip mounting portion side of the two pairs of second corner lead pairs is narrower than the arrangement interval of the tip portions on the chip mounting portion side of the two pairs of first corner lead pairs. In claim 6,
The molding die includes a supply part and a discharge part of the sealing resin on a side surface of the cavity,
The method of manufacturing a semiconductor device, wherein the supply unit is disposed at the first corner of the cavity, and the discharge unit is disposed at the second corner. In claim 7,
Among the plurality of wires, the interval between the second wires connected to the two pairs of second corner lead pairs is the interval between the first wires connected to the two pairs of first corner lead pairs, respectively. A method for manufacturing a semiconductor device, characterized by being narrower than the above. In claim 7,
The first suspension lead includes a first inclined portion between the chip mounting portion and the first corner of the cavity,
The second suspension lead includes a second inclined portion between the chip mounting portion and the second corner of the cavity,
The method of manufacturing a semiconductor device, wherein the first and second inclined portions are respectively disposed between the plurality of leads in a plan view. In claim 7,
The plurality of leads include a plurality of first leads constituting a first lead group disposed along the first side and a plurality of second leads constituting a second lead group disposed along the second side. Two leads, a plurality of third leads constituting a third lead group arranged along the third side, and a plurality of fourth leads constituting a fourth lead group arranged along the fourth side. Included,
When a virtual line connecting the center of the first side and the second side is a first center line, and a virtual line connecting the third side and the fourth side is a second center line,
The tip portions of the plurality of first leads on the chip mounting portion side are arranged in a region between the first center line and the second diagonal line so that the number of the first center line and the first diagonal line is greater. More than the number placed in the area between
The tip portions of the plurality of second leads on the chip mounting portion side are arranged in a region between the first center line and the second diagonal line so that the number of the first center line and the first diagonal line is greater. More than the number placed in the area between
The tip portions of the plurality of third leads on the chip mounting portion side are arranged in a region between the second center line and the second diagonal line so that the number of the first center line and the first diagonal line is greater. More than the number placed in the area between
The tip portions of the plurality of fourth leads on the chip mounting portion side are arranged in a region between the second center line and the second diagonal line so that the number of the first center line and the first diagonal line is greater. A method for manufacturing a semiconductor device, characterized in that the number of the semiconductor devices is larger than the number arranged in a region between. In claim 7,
In the step (d), a plurality of inner lead portions constituting the plurality of leads are disposed in the cavity, and a plurality of outer lead portions formed integrally with the plurality of inner lead portions are disposed outside the cavity. And
The plurality of outer lead portions include a plurality of first outer lead portions constituting a first lead group disposed along the first side and a plurality of second lead groups disposed along the second side. A second outer lead portion, a plurality of third outer lead portions constituting a third lead group disposed along the third side, and a plurality of fourth lead groups disposed along the fourth side. A fourth outer lead portion is included,
The number of the first outer lead portions is the same as the number arranged between the first center line and one end, and the number arranged between the first center line and the other end. Yes,
The plurality of second outer lead portions is the same number as the number arranged between the first center line and one end, and the number arranged between the first center line and the other end. Yes,
The number of the third outer lead portions is the same as the number arranged between the second center line and one end, and the number arranged between the second center line and the other end. Yes,
The number of the fourth outer lead portions is the same as the number arranged between the second center line and one end, and the number arranged between the second center line and the other end. A method for manufacturing a semiconductor device, comprising:

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