JP2012186279A - Laminated print circuit board incorporating electronic component and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable an electronic component 12a to be mounted in multiple layers.SOLUTION: A laminated print circuit board 3a includes: a first wiring board 11a; a second wiring board 11c laminated on the first wiring board 11a; an electronic component 12a placed between the first wiring board 11a and the second wiring board 11c; and a spacer 11b disposed around the electronic component 12a. A single-sided board which is the type similar to the first wiring board 11a and the second wiring board 11c and has a wiring circuit 23b formed only on its one surface, is used as the spacer 11b.

Description

  The present invention relates to a laminated printed wiring board incorporating electronic components and a method for manufacturing the same.

  As electronic devices become smaller and more functional, electronic components built into the devices are also becoming smaller, and printed circuit boards on which electronic components are mounted are becoming increasingly indispensable and multi-layered. ing. In addition, the frequency of signals handled by electronic devices is increased, and in addition to higher density, improvement in high-speed transmission characteristics is required.

  As a technique for meeting these requirements, there is a packaging technique called EWLP (Embedded Wafer Level Package) (see, for example, Patent Document 1). EWLP is a technique for incorporating a semiconductor structure such as a WLCSP (Wafer Level Chip Size Package) in a printed wiring board. According to EWLP, the mounting density of the semiconductor elements can be greatly improved, the wiring length between the semiconductor elements can be shortened, and the high-speed transmission characteristics can be improved. However, since EWLP uses a build-up method by repetitive processes such as resist mask fabrication and plating, the number of manufacturing steps is large, manufacturing time is long, and manufacturing cost is high. Furthermore, since a heat press process is required for multilayering, there is a problem that a plurality of thermal histories are applied to some insulating resin layers, and the resin is likely to deteriorate.

  On the other hand, a technique for manufacturing a laminated wiring board with a built-in semiconductor element by embedding WLCSP between layers of a plurality of printed wiring boards and collectively performing a thermocompression treatment (see, for example, Patent Document 2). By adopting the batch lamination method of Patent Document 2, it is possible to reduce the number of manufacturing steps as compared with EWLP, and the heat press treatment is applied only once to the insulating resin layer. Deterioration can be suppressed.

JP 2004-95836 A JP 2009-146940 A

  However, the multilayer wiring board disclosed in Patent Document 2 includes two single-sided wiring boards that are arranged to face each other so that the conductor circuit is exposed to the outside, and a semiconductor element disposed between the two wiring boards. And a spacer disposed around the semiconductor element. A wiring circuit is formed on both surfaces of the spacer, and the wiring circuit is electrically connected by a through wiring.

  For this reason, it is impossible to further stack a plurality of laminated wiring boards disclosed in Patent Document 2 and incorporate a plurality of semiconductor elements in a plurality of wiring layers. This is because, in order to further stack a plurality of multilayer wiring boards, one conductor circuit exposed on the multilayer wiring board and a conductor circuit on a different multilayer wiring board are joined and laminated, but the conductor circuits are joined together. Because you can't. As described above, there is a problem that it is difficult to incorporate semiconductor elements in a plurality of layers.

  In view of the above problems, an object of the present invention is to provide a laminated printed wiring board capable of incorporating electronic components in a plurality of layers and a method for manufacturing the same.

  To achieve the above object, according to a first aspect of the present invention, there is provided a laminated printed wiring board incorporating electronic components, the first insulating layer, and a first conductor circuit formed on one surface of the first insulating layer. The first insulating layer is formed through the first insulating layer, one end of which contacts the first conductor circuit, and the other end of the first insulating layer is exposed from the other surface facing the first insulating layer. A wiring board, a second insulating layer, a second conductor circuit formed on one surface of the second insulating layer, and formed through the second insulating layer, one end of which contacts the second conductor circuit, and the other end Is disposed between the first wiring board and the second wiring board, the second wiring board having a second interlayer conductive portion exposed from the other surface facing the one surface of the second insulating layer, and the other of the first interlayer conductive portion An electronic component having an electrode connected to the end; a third insulating layer disposed around the electronic component; and one surface of the third insulating layer A wiring circuit formed and in contact with the first interlayer conductive portion; and a third interlayer conductive portion formed through the third insulating layer and having one end in contact with the wiring circuit and the other end in contact with the second conductor circuit. It is a summary to provide the spacer which has.

  In the first aspect of the present invention, the second wiring board may further include a third conductor circuit formed on the other surface of the second insulating layer and in contact with the other end of the second interlayer conductive portion. By bringing the third conductor circuit into contact with bumps or other protruding electrodes, the laminated printed wiring board with the built-in electronic components can be mounted on a larger wiring board.

  In the first aspect of the present invention, a plurality of combinations of electronic components and spacers may be arranged in different layers between the first wiring board and the second wiring board. By using a spacer in which a wiring circuit is formed only on one surface, a plurality of electronic components can be embedded at high density.

  A laminated printed wiring board obtained by laminating a plurality of laminated printed wiring boards according to the first aspect of the present invention, wherein the other laminated printed wiring board has the other end of the second interlayer conductive portion of one laminated printed wiring board. A plurality of laminated printed wiring boards may be laminated so as to be in contact with the first conductor circuit of the.

  According to a second aspect of the present invention, there is provided a method for manufacturing a laminated printed wiring board including the electronic component according to the first aspect, wherein the first interlayer conductive portion is in contact with an electrode of the electronic component. A first step of connecting an electronic component to the wiring board; and a first wiring board, a spacer, and a first wiring board so that the wiring circuit is in contact with the first interlayer conduction portion and the second conductor circuit is in contact with the third interlayer conduction portion. And a second step of joining the two wiring boards in alignment with each other.

  According to a third aspect of the present invention, there is provided a method for manufacturing a laminated printed wiring board incorporating the electronic component according to the first aspect, wherein the second surface is opposite to the one surface on which the electrodes of the electronic component are formed. A first wiring board, a spacer, and a second wiring so that the electrode and the wiring circuit are in contact with the first interlayer conductive portion, and the second conductor circuit is in contact with the third interlayer conductive portion. And a second step of joining together by aligning the positions of the plates.

  As described above, according to the multilayer printed wiring board incorporating the electronic component of the present invention and the method for manufacturing the same, the second interlayer conductive portion is exposed on either surface of the multilayer printed wiring board. A plurality of laminated printed wiring boards can be further laminated without bonding. Therefore, it is possible to incorporate electronic components in a plurality of layers.

It is sectional drawing which shows the whole structure of the multilayer printed wiring board 3a incorporating the electronic component 12a in connection with the 1st Embodiment of this invention. It is sectional drawing for demonstrating the effect by the laminated printed wiring board 3a in connection with 1st Embodiment. 3A is a cross-sectional view showing the first wiring board in a state where the electronic component 12a is flip-chip bonded, FIG. 3B is a cross-sectional view showing the spacer, and FIG. FIG. 3 is a cross-sectional view showing a second wiring board. 4A is a cross-sectional view showing the first wiring board, FIG. 4B is a cross-sectional view showing the spacer, and FIG. 4C is a state in which the electronic component is face-up bonded. It is sectional drawing which shows a 2nd wiring board. It is sectional drawing which shows the whole structure of the laminated printed wiring board which incorporated the electronic component concerning 2nd Embodiment. It is sectional drawing which shows the whole structure of the lamination printed wiring board which incorporated the electronic component concerning a comparative example. It is sectional drawing for demonstrating the problem in the laminated printed wiring board of FIG.

  Embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings, the same parts are denoted by the same reference numerals.

(First embodiment)
First, the overall configuration of the laminated printed wiring board 3a according to the first embodiment of the present invention will be described with reference to FIG.

  The laminated printed wiring board 3a according to the first embodiment of the present invention includes a first wiring board 11a, a second wiring board 11c laminated on the first wiring board 11a, a first wiring board 11a, and a second wiring. The electronic component 12a arrange | positioned between the board | substrates 11c, and the spacer 11b arrange | positioned around the electronic component 12a are provided.

  The first wiring board 11a includes a first insulating layer 21a, a first conductor circuit 23a formed on one surface of the first insulating layer 21a, and an adhesive layer formed on the other surface corresponding to one surface of the first insulating layer 21a. 22a and a first interlayer conductive portion 24a formed through the first insulating layer 21a and the adhesive layer 22a. One end of the first interlayer conductive portion 24a is in contact with the first conductor circuit 23a.

The second wiring board 11c includes a second insulating layer 21c, a second conductor circuits 23c ₁ formed on one surface of the second insulating layer 21c, a formed on the other surface facing the one surface of the second insulating layer 21c a third conductor circuit 23c _2, and a second interlayer conductive portion 24c which is formed through the second insulating layer 21c. One end of the second interlayer conductive portion 24c is in contact with the second conductor circuits 23c _1, the other end of the second interlayer conductive portion 24c is in contact with the third conductive circuit 23c _2.

  The electronic component 12a is disposed between the first wiring board 11a and the second wiring board 11c. The electronic component 12a has an electrode 26 connected to the other end of the first interlayer conductive portion 24a. Here, the “electronic component” 12a is a concept including both passive components such as resistors and capacitors, and active components such as ICs, diodes, and transistors. For example, as the electronic component 12a, a semiconductor (bare) chip on which a semiconductor element is formed, or a WLCSP packaged in the same size as the semiconductor chip can be used. Furthermore, it is desirable from the viewpoint of quality improvement to use WLCSP capable of KGD (Known Good Die) as the electronic component 12a.

The spacer 11b is formed on the other surface corresponding to one surface of the third insulating layer 21b, the third insulating layer 21b disposed around the electronic component 12a, the wiring circuit 23b formed on one surface of the third insulating layer 21b. And the third insulating layer 21b and the third interlayer conductive portion 24b formed through the adhesive layer 22b. The wiring circuit 23b is in contact with the other end of the first interlayer conductive portion 24a. One end of the third interlayer conductive portion 24b is in contact with the wiring circuit 23b, the other end of the third interlayer conductive portion 24b is in contact with the second conductor circuits 23c _1.

  The first insulating layer 21a is bonded to the electronic component 12a and the third insulating layer 21b by the adhesive layer 22a. The second insulating layer 21c is bonded to the third insulating layer 21b by the adhesive layer 22b, and is bonded to the electronic component 12a by the element adhesive 25a.

Thus, the first conductor circuit 23a is formed only on one surface of the first insulating layer 21a. The second conductor circuits 23c ₁ and the third conductor circuit 23c ₂ are formed on both surfaces of the second insulating layer 21c. A wiring circuit 23b is formed only on one side of the third insulating layer 21b. The first side of the direction of the first insulating layer 21a of the first conductor circuit 23a is formed, a surface direction of the second insulating layer 21c in which the second conductor circuit 23c ₁ is formed, and the wiring circuit 23b is formed The direction of one surface of the three insulating layers 21b is equal. Thus, the conductor circuits 23a, is 23c ₁ and the wiring circuit 23b, can be connected via the without first interlayer conductive portion 24a, the third interlayer conductive portion 24b in direct contact with each other.

In the first embodiment, the second wiring board 11c is, the case is a double-sided substrate provided with a third conductor circuit 23c ₂ formed on the other surface of the second insulating layer 21c. Thus, the third conductor circuit 23c ₂ by contacting the bump electrode such as bump, a laminated printed wiring board 3a with a built-in electronic component 12a, can be further mounted on the large wiring substrate.

However, the present invention is not limited thereto, the second wiring board 11c may be a single-sided board which is not provided with a third conductor circuit 23c _2. In this case, the second interlayer conductive portion 24c is exposed on any one surface of the multilayer printed wiring board 3a. Therefore, as shown in FIG. 2, a plurality of laminated printed wiring boards 3a and 3b can be further laminated without joining the conductor circuits. Therefore, it is possible to incorporate a plurality of electronic components 12a and 12b in a plurality of layers.

  As the materials of the first insulating layer 21a, the second insulating layer 21c, and the third insulating layer 21b, the purpose and use of the laminated printed wiring board 3a to be manufactured from various insulating materials known in the manufacturing field of printed wiring boards and the like. It can be appropriately selected and used depending on the situation. For example, when manufacturing a flexible laminated printed wiring board, a single-sided copper-clad laminate (single-sided CCL) having a structure in which a copper foil is bonded to a flexible resin sheet such as a thin polyimide sheet can be used.

  As a material for the adhesive layers 22a and 22b, various kinds of adhesives known in the field of manufacturing printed wiring boards can be used. For example, a polyimide-type adhesive, an epoxy-type adhesive, etc. are mentioned. Further, as the element adhesive 25a, a groove portion of DAF (Die Attached Film) can be used. When the wafer on which the DAF is attached to the back surface is separated into pieces and the separated electronic component 12a is peeled off from the DAF, a groove portion of the DAF adheres to the back surface of the electronic component 12a. This groove corresponds to the element adhesive 25a shown in FIG.

  The first interlayer conductive portion 24a, the third interlayer conductive portion 24b, and the second interlayer conductive portion 24c are at least one kind of low electrical resistance metal particles selected from nickel, silver, and copper, and tin, bismuth, indium, lead The conductive paste containing at least one kind of low melting point metal particles selected from is heated and cured.

The first conductor circuit 23a, the second conductor circuit 23c ₁ , the third conductor circuit 23c ₂ and the wiring circuit 23b contain the same metal component. The metal component contained in the first conductor circuit 23a, the second conductor circuit 23c ₁ , the third conductor circuit 23c ₂ and the wiring circuit 23b is at least one kind of low electricity selected from copper, gold, silver and tin. It is a resistance metal. The interface between the first conductor circuit 23a and the first interlayer conductive portion 24a, the interface between the first interlayer conductive portion 24a and the wiring circuit 23b, the interface between the wiring circuit 23b and the third interlayer conductive portion 24b, the third interlayer conductive portion 24b and the second interface of the conductor circuit 23c _1, the interface of the second conductor circuit 23c ₁ and the second interlayer conductive portion 24c, a second interlayer conductive portion 24c on the surface of the third conductive circuit 23c _2, respectively, the conductor circuits 23a, _23c 1, 23c ₂ , an alloy layer (not shown) made of an alloy of the low electrical resistance metal in the wiring circuit 23b and the low melting point metal in the conductive paste may be formed. The first conductor circuit 23a, the second conductor circuit 23c ₁ , the third conductor circuit 23c ₂ and the wiring circuit 23b may contain different metal components.

During the first conductor circuit 23a and the first insulating layer 21a, between the second conductor circuits 23c ₁ and the second insulating layer 21c, and the third conductive circuit 23c ₂ between the second insulating layer 21c, and a wiring circuit 23b first A seed layer may be disposed between each of the three insulating layers 21b. Here, the material of the seed layer includes at least one metal selected from nickel, chromium, titanium, tungsten, and an alloy of titanium and tungsten. The seed layer absorbs the surface roughness of one surface and the other surface of the first insulating layer 21a, the second insulating layer 21c, and the third insulating layer 21b. Thus, the first conductor circuit 23a, a second conductor circuit 23c _1, flatness is improved in the third conductor circuit 23c ₂ and the wiring circuit 23b, the electrical characteristics are improved. Further, when the plurality of wiring boards 11a to 11c are laminated, the flatness when the plurality of laminated printed wiring boards 3a are laminated is also improved. Further, between the first conductor circuit 23a and the first insulating layer 21a, between the second conductor circuits 23c ₁ and the second insulating layer 21c, between the third conductor circuit 23c ₂ and the second insulating layer 21c, and the wiring circuit 23b And the third insulating layer 21b can be increased in adhesion strength.

Although not shown in FIGS. 1 and 2, the interface of the first conductor circuit 23a and the first interlayer conductive portion 24a, the interface of the printed circuit 23b and the third interlayer conductive portion 24b, second conductive circuits 23c ₁ and the second interlayer conductive interface parts 24c, and a second interlayer conductive portion 24c interface of the third conductor circuit 23c ₂ may each have an irregular shape. Specifically, the first conductor circuit 23a, the wiring circuit 23b, and the second conductor exposed on the bottom surface of the via hole before the first interlayer conductive portion 24a, the third interlayer conductive portion 24b, and the second interlayer conductive portion 24c are embedded in the via hole. The conductor circuit 23c ₁ has a fine uneven shape formed by a roughening process such as irradiating a laser or the like to damage the conductor circuit 23c1. For example, the arithmetic average roughness Ra of the bottom surface of the via hole may be 0.1 to 0.8 μm, preferably 0.1 to 0.5 μm.

Laminated printed wiring board 3a shown in Figure 1, the first conductor circuit 23a, the wiring circuit 23b, or the second conductor circuits 23c ₁ and the third conductor circuit 23c ₂ shapes arbitrarily set, interlayer conductive portions 24a, 24b, 24c can be arranged at an arbitrary position. Therefore, the structure of the multilayer printed wiring board 3a shown in FIG. 1 is an example, the first conductor circuit 23a, the wiring circuit 23b, the second conductor circuits 23c ₁ and the shape and position of the third conductor circuit 23c _2, and interlayer conduction The positions of the parts 24a, 24b, and 24c can be changed.

  With reference to FIG. 3A to FIG. 3C, an example of a method of manufacturing the laminated printed wiring board 3a incorporating the electronic component 12a shown in FIG. 1 using flip chip bonding will be described. 3A is a cross-sectional view showing the first wiring board 11a in a state where the electronic component 12a is flip-chip bonded, and FIG. 3B is a cross-sectional view showing the spacer 11b, and FIG. ) Is a cross-sectional view showing the second wiring board 11c.

  First, before the electronic component 12a is flip-chip bonded, the first wiring board 11a shown in FIG. 3A, the spacer 11b shown in FIG. 3B, and the second wiring board 11c shown in FIG. Manufacture each.

  Specifically, first, a circuit pattern of the seed layer and the first conductor circuit 23a is formed on one surface of the flexible first insulating layer 21a. Specifically, for example, a surface of the first insulating layer 21a made of a flexible resin sheet such as a polyimide film is roughened, and then a seed layer made of nickel, for example, is formed on the entire surface of the first main surface. It is formed by electroless plating or sputtering. Then, a resist pattern is formed in a region where the first conductor circuit 23a is not formed. The first conductor circuit 23a is formed on the seed layer where the resist pattern is not formed by electrolytic plating. Thereafter, the resist pattern and the seed layer under the resist pattern are selectively removed. Thereby, the circuit pattern of the first conductor circuit 23a of FIG. As a method for forming a circuit pattern, various manufacturing methods using a subtractive method can be used.

  Considering the suppression of film thickness variation and the formation of fine circuit patterns, the thickness of the first conductor circuit 23a is preferably in the range of 3 to 20 μm. Further, as the first insulating layer 21a, a polyimide film having a thickness of 12 to 50 μm or a plastic film such as a liquid crystal polymer is used.

  Next, a thermosetting resin film is attached to the other surface opposite to one surface of the first insulating layer 21a by thermocompression bonding to form the adhesive layer 22a. A thermosetting resin film is attached on the adhesive layer 22a by thermocompression bonding to form a resin film. For thermocompression bonding, a laminating apparatus, for example, a vacuum laminator is used, and in a reduced-pressure atmosphere, pressing and bonding are performed at a temperature lower than the curing temperature of the thermosetting resin film.

  As the material of the adhesive layer 22a, an adhesive such as an epoxy-based thermosetting resin or an acrylic resin, or a thermoplastic adhesive represented by thermoplastic polyimide can be used. The adhesive layer 22a can be formed by applying, for example, a varnish-like resin adhesive on the other surface of the first insulating layer 21a instead of the film-like material.

  The resin film may be a polyimide film, a plastic film such as PET (polyethylene terephthalate) or PEN (polyethylene naphthalate), and the surface of the adhesive layer 22a is covered with a film that can be bonded or peeled off by UV irradiation. You may form.

  A via hole is formed from the other surface of the first insulating layer 21a, and a seed layer is exposed on the bottom surface of the via hole. Specifically, a via hole penetrating the first insulating layer 21a, the adhesive layer 22a, and the resin film is formed. The via hole is formed from the other surface side of the first insulating layer 21a at a position where the first conductor circuit 23a is formed. Therefore, the seed layer is exposed on the bottom surface of the via hole.

Specifically, a via hole having a diameter of 100 μm is formed by perforating the first insulating layer 21a, the adhesive layer 22a, and the resin film with a UV-YAG laser so as to penetrate from the other surface side. Thereafter, in order to remove smear generated during drilling, plasma desmear treatment with a mixed gas of carbon tetrafluoride (CF ₄ ) and oxygen (O ₂ ) is performed.

  The via hole can also be formed by laser processing using a carbon dioxide laser or excimer laser, drill processing, or chemical etching.

In addition, the plasma desmear process is not limited to the mixed gas of CF ₄ and O ₂ as the type of gas used, and other inert gas such as argon (Ar) can be used. You may apply the wet desmear process by a chemical | medical solution.

  The seed layer exposed on the bottom surface of the via hole is selectively removed to expose the first conductor circuit 23a on the bottom surface of the via hole. Specifically, the seed layer is removed by wet etching using a chemical solution such as nitric acid.

  A conductive paste is filled into the via hole where the first conductor circuit 23a is exposed on the bottom surface. Specifically, the via holes are filled with the conductive paste by screen printing until each space is filled. The conductive paste includes at least one low electrical resistance metal particle selected from nickel, silver, and copper, and at least one low melting point metal particle selected from tin, bismuth, indium, and lead, and an epoxy It is composed of a paste in which a binder component mainly composed of a resin is mixed. The conductive paste uses a metal composition that is easy to be alloyed at a low temperature, such as the curing temperature of the adhesive layer 22a, by metal particles being diffusion bonded between the particles or by diffusion bonding with the first conductor circuit 23a. Examples thereof include lead-free solder, anisotropic conductive paste (ACF), silver paste, a mixed material of those pastes, and a paste material mixed with a trace amount of different metals. As a method for filling the conductive paste, a printing method, a spin coating method, a spray coating method, a dispensing method, a laminating method, and a method using them in combination can be used.

  Thereafter, the resin film is peeled off. As a result, the front end (lower surface) portion of the printed conductive paste is exposed with a height corresponding to the thickness dimension of the peeled resin film protruding to the lower surface side of the adhesive layer 22a. Thus, the resin film adjusts the protrusion height of the conductive paste that will later become the first interlayer conductive portion 24a by appropriately selecting the thickness thereof. Through the above steps, the first wiring board 11a is formed.

  As described above, the manufacturing process of the spacer 11b in FIG. 3B is the same process as that of the first wiring board 11a, and thus the description thereof is omitted. Also, the manufacturing process of the second wiring board 11c in FIG. 3C is almost the same process as the first wiring board 11a, and thus the description thereof is omitted.

  Next, as shown in FIG. 3A, an electronic component 12a is prepared in which an element adhesive 25a is bonded to the other surface opposite to the one surface on which the electrode 26 is formed. And the electronic component 12a is connected to the 1st wiring board 11a using a flip chip bonding method so that the electrode 26 which the electronic component 12a contacts the 1st interlayer conduction | electrical_connection part 24a with which the 1st wiring board 11a is equipped.

Next, the first wiring board 11a, the spacer 11b, and the second wiring board 11c on which the electronic component 12a is flip-chip bonded are overlaid. Specifically, as shown in FIG. 3 (a) ~ FIG 3 (c), the first interlayer conductive portion 24a is in contact with the printed circuit 23b, a third interlayer conductive portion 24b is brought into contact with the second conductor circuits 23c ₁ As described above, the first wiring board 11a, the spacer 11b, and the second wiring board 11c are overlapped in an aligned state. In this state, the first wiring board 11a, the spacer 11b, and the second wiring board 11c are temporarily fixed by heating at a temperature lower than the curing temperature of the adhesive layers 22a and 22b and the conductive paste.

  The first wiring board 11a, the spacer 11b, and the second wiring board 11c that are laminated by temporary fastening are collectively used in a reduced pressure atmosphere of 1 kPa or less at a heating temperature of 150 ° C. to 200 ° C. using a vacuum curing press device. Heat-press. This method is called a batch lamination method. At the time of thermocompression bonding, the adhesive layer 22a is thermally cured, the first insulating layer 21a and the third insulating layer 21b are joined, the adhesive layer 22b is thermally cured, and the third insulating layer 21b and the second insulating layer 21c. Are joined. The other surface of the electronic component 12a is bonded to the second insulating layer 21c by the element adhesive 25a. The conductive paste is also thermally cured to form a sintered body, that is, the first interlayer conductive portion 24a, the second interlayer conductive portion 24c, and the third interlayer conductive portion 24b. In this way, the first wiring board 11a, the spacer 11b, and the second wiring board 11c are joined.

At the same time, the interface between the first conductor circuit 23a and the first interlayer conductive portion 24a, the interface between the first interlayer conductive portion 24a and the wiring circuit 23b, the interface between the wiring circuit 23b and the third interlayer conductive portion 24b, and the third interlayer interface conductive portion 24b and the second conductor circuits 23c _1, the interface of the second conductor circuit 23c ₁ and the second interlayer conductive portion 24c, and the second interlayer conductive portion 24c and the third interface of the conductor circuit 23c _2, wherein the alloy A layer is formed. In this way, the laminated printed wiring board 3a shown in FIG. 1 is completed.

  In addition, when the flip chip bonding of FIG. 3 is used, before joining the first wiring board 11a, the spacer 11b, and the second wiring board 11c, the electrode 26 of the electronic component 12a and the first interlayer conductive portion 24a are previously connected. Aligned and connected. However, other manufacturing methods may be used. For example, the first wiring board 11a, the spacer 11b, and the second wiring board 11c may be joined, and at the same time, the electrode 26 of the electronic component 12a and the first interlayer conductive portion 24a may be aligned and connected.

  Next, with reference to FIGS. 4A to 4C, an example of a method for manufacturing the laminated printed wiring board 3a incorporating the electronic component 12a shown in FIG. 1 using face-up bonding will be described. . 4A is a cross-sectional view showing the first wiring board 11a, FIG. 4B is a cross-sectional view showing the spacer 11b, and FIG. 4C is a view in which the electronic component 12a is face-up bonded. It is sectional drawing which shows the 2nd wiring board 11c of the state which was in contact. There is no difference in the final structure of the laminated printed wiring board 3a between the case where face-up bonding is used and the case where flip-chip bonding is used.

  First, as shown in FIGS. 4A to 4C, a method of manufacturing the second wiring board 11c before the first wiring board 11a, the spacer 11b, and the electronic component 12a are face-up bonded, respectively, This is the same as when flip-chip bonding is used, and the description is omitted.

  Next, as shown in FIG. 4C, an electronic component 12a is prepared in which an element adhesive 25a is bonded to the other surface opposite to the one surface on which the electrode 26 is formed. Then, the other surface of the electronic component 12a is bonded to one surface of the second insulating layer 21c included in the second wiring board 11c via the element adhesive 25a.

Next, the first wiring board 11a, the spacer 11b, and the second wiring board 11c to which the electronic component 12a is bonded are overlapped. Specifically, as shown in FIGS. 4A to 4C, the electrode 26 of the electronic component 12a is in contact with the first interlayer conductive portion 24a, and the first interlayer conductive portion 24a is connected to the wiring circuit 23b. contact, the third interlayer conductive portion 24b is in contact with the second conductor circuits 23c _1, the first wiring board 11a, spacers 11b, and superposed in a second state in which the wiring board 11c are aligned. In this state, the first wiring board 11a, the spacer 11b, and the second wiring board 11c are temporarily fixed by heating at a temperature lower than the curing temperature of the adhesive layers 22a and 22b and the conductive paste.

  The first wiring board 11a, the spacer 11b, and the second wiring board 11c laminated by temporary fastening are collectively heat-pressed by the above-described collective laminating method. In this way, the first wiring board 11a, the spacer 11b, and the second wiring board 11c are joined.

  As described above, according to the first embodiment of the present invention, the following operational effects can be obtained.

The other end of the third interlayer conductive portion 24b having spacer 11b is is in contact with the second conductor circuits 23c ₁ of the second wiring board 11c. That is, the spacer 11b is a single-sided wiring board in which the wiring circuit 23b is formed only on one side. Therefore, since the third interlayer conductive portion 24b is exposed on one surface of the laminated printed wiring board 3a, a plurality of laminated printed wiring boards 3a can be further laminated without joining the conductor circuits. Therefore, the electronic component 12a can be built in a plurality of layers. In the example of FIG. 1, without exposing the second interlayer conductive portion 24c on one surface of the laminated printed wiring board 3a, it is connected to the third conductive circuit 23c _2, third conductor circuit 23c ₂ is As will be described later, this is a member that is useful when mounted on another substrate via bumps or the like, and is unnecessary when the laminated printed wiring boards 3a are laminated.

The second wiring board 11c further comprises formed on the other surface of the second insulating layer 21c, the third conductor circuit 23c ₂ in contact with the other end of the second interlayer conductive portion 24c. By forming the protruding electrodes such as bumps third conductor circuit 23c _2, a laminated printed wiring board 3a with a built-in electronic component 12a, can be further mounted on the large wiring substrate.

A plurality of laminated printed wiring boards 3a shown in FIG. 1 can be laminated. What is necessary is just to laminate | stack a some multilayer printed wiring board so that the other end of the 2nd interlayer conduction | electrical_connection part 24c which one laminated printed wiring board has contacts the 1st conductor circuit 23a which the other laminated printed wiring board has. However, in this case, the third conductor circuit 23c ₂ is unnecessary.

  Further, according to the first embodiment of the present invention, as with EWLP, the mounting density of the semiconductor elements can be greatly improved, the wiring length between the semiconductor elements is shortened, and the high-speed transmission characteristics are improved. Can be made. Furthermore, the above-described problems of EWLP can be solved. That is, the batch stacking method is used without using the build-up method by repeating the production of the resist mask and the plating process. Therefore, the number of manufacturing steps can be reduced, the manufacturing time can be shortened, and the manufacturing cost can be kept low. Furthermore, since the heat press process at the time of multilayering may be performed only once, deterioration of the insulating resin layer can be suppressed.

  As shown in FIG. 3A, the first wiring board 11a is formed using a flip chip bonding method so that the electrode 26 of the electronic component 12a contacts the first interlayer conductive portion 24a provided in the first wiring board 11a. The electronic component 12a is connected to. Thereby, since the positional accuracy at the time of joining the electrode 26 of the electronic component 12a and the 1st interlayer conduction | electrical_connection part 24a is high, the connection reliability of the electronic component 12a and the 1st interlayer conduction | electrical_connection part 24a can be improved.

  As shown in FIG. 4C, before connecting the electronic component 12a to the first wiring board 11a, the electronic component is placed on one surface of the second insulating layer 21c provided in the second wiring board 11c via the element adhesive 25a. The other surface of 12a is adhered. Accordingly, when the electronic component 12a is mounted, the second insulating layer 21c and the element adhesive 25a can be bonded quickly, so that it is possible to prevent a decrease in the adhesive strength of the element adhesive 25a due to a thermal process or the passage of time. .

(Second Embodiment)
In the first embodiment, a laminated printed wiring board 3a in which one electronic component 12a is incorporated is shown, and a plurality of laminated printed wiring boards 3a are laminated so that a plurality of electronic components are incorporated in a plurality of layers. It was shown that a printed wiring board can be provided. In the present invention, a plurality of electronic components can be incorporated in a plurality of layers even by a method other than the method of laminating a plurality of laminated printed wiring boards 3a.

  Therefore, in the second embodiment, a multilayer printed wiring board in which a plurality of combinations of electronic components and spacers are arranged in different layers between the first wiring board and the second wiring board will be described. With reference to FIG. 5, the overall configuration of the multilayer printed wiring board incorporating the electronic components according to the second embodiment will be described.

  As shown in FIG. 5, the first wiring board 31a is disposed on the outermost surface side of the multilayer printed wiring board according to the second embodiment, and the second wiring board 31e is disposed on the outermost surface side. Between the 1st wiring board 31a and the 2nd wiring board 31e, the spacer 31b which has the electronic component 32a and the insulating layer 41b arrange | positioned around it is arrange | positioned. Furthermore, between the first wiring board 31a and the second wiring board 31e, a spacer 31d having an electronic component 32b and an insulating layer 41d disposed around the electronic component 32b is arranged in a layer different from the electronic component 32a.

  Further, a third wiring board 31c is disposed between the electronic component 32a and the electronic component 32b.

The first wiring board 31a includes a first insulating layer 41a, a first conductor circuit 43a, a first interlayer conductive portion 44a, and an adhesive layer 42a. The second wiring board 31e has a second insulating layer 41e, and the second conductor circuits 43e ₁ and the third conductor circuit 43e _2, a second interlayer conductive portion 44e. The spacer 31b includes an insulating layer 41b, a wiring circuit 43b, an interlayer conductive portion 44b, and an adhesive layer 42b. The spacer 31d includes an insulating layer 41d, a wiring circuit 43d, an interlayer conductive portion 44d, and an adhesive layer 42d. The third wiring board 31c includes an insulating layer 41c, a conductor circuit 43c, an interlayer conductive portion 44c, and an adhesive layer 42c. The electronic component 32a is bonded to the insulating layer 41c with an element adhesive 45a. The electronic component 32b is bonded to the second insulating layer 41e with an element adhesive 45b.

  As described above, a plurality (two in this case) of combinations of the electronic components 32a and 32b and the spacers 31b and 31d are arranged between the first wiring board 31a and the second wiring board 31e in different layers. As described above, by using the spacers 31b and 31d in which the wiring circuits 43b and 43d are formed only on one surface, a plurality of electronic components 32a and 32b can be embedded at high density.

(Comparative example)
As shown in FIG. 6, the laminated printed wiring board 53a according to the comparative example includes a first wiring board 61a, a second wiring board 61c laminated on the first wiring board 61a, a first wiring board 61a, and a second wiring. An electronic component 62a disposed between the plates 61c and a spacer 61b disposed around the electronic component 62a are provided.

  The first wiring board 61a includes a first insulating layer 71a, a first conductor circuit 73a formed on one surface of the first insulating layer 71a, and an adhesive layer formed on the other surface corresponding to one surface of the first insulating layer 71a. 72a and a first interlayer conductive portion 74a formed through the first insulating layer 71a and the adhesive layer 72a. One end of the first interlayer conductive portion 74a is in contact with the first conductor circuit 73a.

  The second wiring board 61c includes a second insulating layer 71c, a second conductor circuit 73c formed on one surface of the second insulating layer 71c, and an adhesive layer formed on the other surface corresponding to one surface of the second insulating layer 71c. 72c and a second interlayer conductive portion 74c formed through the second insulating layer 71c and the adhesive layer 72c. One end of the second interlayer conductive portion 74c is in contact with the second conductor circuit 73c.

The electronic component 62a has an electrode 76 connected to the other end of the first interlayer conductive portion 74a. The spacer 61b includes a third insulating layer 71b disposed around the electronic component 62a, wiring circuits 73b ₁ and 73b ₂ formed on one surface of the third insulating layer 71b and the other surface facing the one surface, and a third insulating layer. An adhesive layer 72b formed between the layer 71b and the electronic component 62a; Wiring circuit 73b ₁ is in contact with the first interlayer conductive portions 74a. Wiring circuit 73b ₂ is in contact with the second interlayer conductive portion 74c.

Thus, the spacer 61b, the wiring circuit _73b 1 on both surfaces of the third insulating layer 71b, 73b ₂ are formed. For this reason, as shown in FIG. 7, it is not possible to further stack a plurality of laminated printed wiring boards 53a and 53b and incorporate a plurality of electronic components 62a and 62b in a plurality of wiring layers. This is because, in order to further laminate a plurality of laminated printed wiring boards 53a and 53b, one exposed conductive circuit of one laminated printed wiring board 53a cannot be joined to a conductive circuit of a different laminated printed wiring board 53b. Because. Thus, in the multilayer printed wiring board 53a according to the comparative example, it is difficult to incorporate semiconductor elements in a plurality of layers.

  As described above, the present invention has been described by two embodiments and comparative examples. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

3a: Laminated printed wiring board 11a, 31a ... 1st wiring board 11b, 31b, 31d ... Spacer 11c, 31e ... 2nd wiring board 12a, 32a, 32b ... Electronic component 21a, 41a ... 1st insulating layer 21b ... 3rd insulation Layer 21c, 41e ... 2nd insulating layer 23a, 43a ... 1st conductor circuit 23b, 43b, 43d ... Wiring circuit 23c1, 43e1 ... 2nd conductor circuit 23c2, 43e2 ... 3rd conductor circuit 24a, 44a ... 1st interlayer conduction | electrical_connection part 24b ... third interlayer conductive portion 24c, 44e ... second interlayer conductive portion

Claims (6)

A first insulating layer; a first conductor circuit formed on one surface of the first insulating layer; and formed through the first insulating layer, one end of which contacts the first conductor circuit, and the other end of the first insulating layer A first wiring board having a first interlayer conductive portion exposed from the other surface facing one surface of the one insulating layer;
A second insulating layer, a second conductor circuit formed on one surface of the second insulating layer, and formed through the second insulating layer, one end of which contacts the second conductor circuit, and the other end of the second insulating layer A second wiring board having a second interlayer conductive portion exposed from the other surface facing one surface of the two insulating layers;
An electronic component having an electrode disposed between the first wiring board and the second wiring board and connected to the other end of the first interlayer conductive portion;
A third insulating layer disposed around the electronic component; a wiring circuit formed on one surface of the third insulating layer and in contact with the first interlayer conductive portion; and formed through the third insulating layer; A spacer having a third interlayer conductive portion having one end in contact with the wiring circuit and the other end in contact with the second conductor circuit;
A laminated printed wiring board having an electronic component built therein.   2. The electronic component according to claim 1, wherein the second wiring board further includes a third conductor circuit formed on the other surface of the second insulating layer and in contact with the other end of the second interlayer conductive portion. Laminated printed wiring board with built-in.   The electronic component according to claim 1 or 2, wherein a plurality of combinations of the electronic component and the spacer are arranged in different layers between the first wiring board and the second wiring board. Laminated printed wiring board. A laminated printed wiring board obtained by laminating a plurality of laminated printed wiring boards according to claim 1,
A plurality of laminated printed wiring boards are laminated so that the other end of the second interlayer conductive portion of one laminated printed wiring board is in contact with the first conductor circuit of the other laminated printed wiring board. Laminated printed wiring board with built-in electronic components. A method for producing a laminated printed wiring board incorporating the electronic component according to claim 1,
A first step of connecting the electronic component to the first wiring board so that the electrode of the electronic component is in contact with the first interlayer conductive portion;
The first wiring board, the spacer, and the second wiring board are aligned so that the wiring circuit is in contact with the first interlayer conductive portion and the second conductor circuit is in contact with the third interlayer conductive portion. A second step of joining together,
A method for manufacturing a laminated printed wiring board incorporating an electronic component comprising: A method for producing a laminated printed wiring board incorporating the electronic component according to claim 1,
A first step of connecting the other surface opposite to the one surface on which the electrode of the electronic component is formed on the second wiring board;
The first wiring board, the spacer, and the second wiring board are arranged such that the electrode and the wiring circuit are in contact with the first interlayer conductive portion, and the second conductor circuit is in contact with the third interlayer conductive portion. A second step of aligning and joining;
A method for manufacturing a laminated printed wiring board incorporating an electronic component comprising:

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