JP2012179732A - Inkjet printer apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inkjet printer apparatus that can be stably controlled by a later-stage circuit even when a CPU stops unexpectedly in spite of a simple circuit configuration.SOLUTION: The inkjet printer apparatus prints an image on a printing medium using a print head. The inkjet printer apparatus includes: a power source unit for generating a direct voltage from a commercial power source; a capacity unit for storing electric energy for operation of the print head; a switch unit connected to a power line from the power source unit to the capacity unit; a charging unit for charging the capacity unit by the switch unit; and a gate unit for controlling an output of a drive voltage for driving the switch unit based on a pulse that is output from the CPU for outputting a drive permission signal to the print head.

Description

  The present invention is an ink jet printer apparatus that moves a print head in a main scanning direction, moves a print medium in a direction perpendicular to the main scan direction, and records an image on the print medium. The present invention also relates to control of power switch means for controlling a power supply source for driving the print head inside the ink jet printer apparatus.

  In a thermal ink jet printing apparatus, power is changed to heat using a heat conversion means, and ink droplets are ejected onto the paper surface using the pressure of bubbles generated in the ink. In order to stably operate the means for ejecting the ink droplets onto the paper surface, an aluminum electrolytic capacitor capable of accumulating energy equal to or higher than the conversion energy corresponding to the ejection is provided near the ink droplet ejecting means.

  Moreover, the power circuit means for supplying to the discharge means is provided with semiconductor switch means in its transmission path, and opens and closes it as necessary. Further, since the electric power is supplied only when the ink ejection means is active, the electric charge accumulated in the aluminum electrolytic capacitor is discharged to the ground when not in use, thereby changing the circuit system to a sleep state. . These controls are controlled by CPU means included in the apparatus.

JP 2007-62264 A

  However, in the above circuit, for example, when some problem occurs and the CPU stops its operation, or when the drive signal is not transmitted normally, it is difficult to close the voltage source switch means. .

  SUMMARY OF THE INVENTION An object of the present invention is to provide an ink jet printer apparatus having a simple circuit configuration and capable of stably controlling a subsequent circuit even when a CPU means stops unexpectedly.

  An ink jet printer apparatus according to the present invention is an ink jet printer apparatus that records an image on a print medium using a print head, and includes a power supply unit that generates a DC voltage from a commercial power source and electrical energy for the operation of the print head. Capacity means for storing the power, switch means connected to the power line from the power supply unit to the capacity means, charging means for charging the capacity means by the switch means, and CPU for outputting a drive permission signal to the print head And a gate means for controlling the output of the drive voltage for driving the switch means on the basis of the pulse outputted from the control means.

  According to the present invention, although the circuit configuration is simple, there is an effect that the subsequent circuit can be stably controlled even when the CPU means stops unexpectedly.

It is a figure which shows the inkjet printer apparatus PRT1 which is an Example. FIG. 6 is an explanatory diagram of each signal in the print head driving power supply apparatus 100.

  The mode for carrying out the invention is the following embodiment.

  FIG. 1 is a diagram showing an inkjet printer apparatus PRT1 that is an embodiment of the present invention.

  The ink jet printer apparatus PRT1 includes a print head driving power supply apparatus 100, a CPU 200, an AC / DC circuit 300, and a print head H1. That is, the ink jet printer apparatus PRT1 moves the print head H1 in the main scanning direction, moves the print medium in a direction perpendicular to the main scan direction, and records an image on the print medium. And it connects to the power supply unit which generates a DC voltage from the input of commercial AC power, and operates an internal circuit with the said DC voltage. For simplicity of explanation, other circuits such as a motor and a motor driver are omitted in FIG.

  The print head H1 is a head for ejecting ink droplets onto a paper medium in the inkjet printer apparatus PRT1.

  The CPU 200 supplies the voltage VHpls of the input pulse to the print head driving power supply device 100 and supplies a head driving permission signal to the print head H1.

  The AC / DC circuit 300 is a power supply unit that generates a DC voltage from an input of a commercial AC power supply. The AC / DC circuit 300 receives the commercial power supply AC100 volts and generates voltages VH and Vcc. The voltage VH is supplied to the print head driving power supply device 100. The CPU 200 controls the print head driving power supply device 100.

  The aluminum electrolytic capacitor C1 is provided in the vicinity of the print head H1 to stably and reliably perform the ink discharge operation of the print head H1, and accumulates electrical energy required by the print head H1 for at least one discharge. Capacity.

  The FET Q1 is a switch provided on the power line in order to give power energy for stably ejecting ink droplets to the print head H1, and switches power to the print head H1 as necessary. The FET Q1 is a semiconductor switch that intermittently supplies power from the AC / DC circuit 300 to the aluminum electrolytic capacitor C1. The resistors R1 and R2 are bias resistors for applying a necessary driving voltage to the FET Q1.

  A charging circuit is configured by the FET Q1 and the resistors R1, R2, and R12. This charging circuit is provided in a charging unit of the aluminum electrolytic capacitor C1, and charges the aluminum electrolytic capacitor C1 by the FET Q1.

  The transistor switch Q2 has a collector connected to the bias resistors R1 and R2, and generates a voltage as necessary. The transistor switch Q2 and the transistor switch Q3 are Darlington connected via a bias resistor R11. A current limiting resistor R10 is provided at the collector of the transistor switch Q3. In addition, a resistor R4 and a resistor R5 are provided to determine the switch level of the transistor switch Q3 and to discharge electric charges from a circuit having a rectification and DC blocking function. Connected to the base terminal. The circuit having the rectification and DC cutoff functions is composed of a resistor built-in transistor switch Q4, a resistor R3, a capacitor C3, diodes D1 and D2, and a capacitor C2.

  A gate means for driving the FET Q1 is constituted by a circuit centered on the transistor switches Q2 and Q3. The gate means is driven by the CPU 200 and driven by a software timer. Further, the drive port of the CPU 200 and the gate means are non-DC connected by a capacitor C3. The gate means is used as a driving status of the CPU means.

  The resistor built-in transistor switch Q4 is provided to transmit the port output of the CPU 200 to the subsequent circuit. The same power supply voltage Vcc as that of the CPU 200 is connected to the emitter of the resistor built-in transistor switch Q4. Further, a discharge resistor R3 is connected to the collector of the transistor switch Q4 with a built-in resistor, and has a function of releasing the charge accumulated in the DC blocking capacitor C3. The diode D2 has a function of discharging the charge on the counter electrode side to the subsequent circuit when the DC blocking capacitor C3 is charged.

  The diode D1 is connected to the anode terminal of the diode D2 in order to supply the charge to the DC blocking capacitor C3 as the DC blocking capacitor C3 releases the charge to the discharging resistor R3. The capacitor C2 is a smoothing capacitor for storing the charge supplied from the diode D2.

  The resistor R12 is a discharge resistor that is provided in the vicinity of the print head H1 and discharges the electric charge accumulated in the aluminum electrolytic capacitor C1 for stably operating the print head H1 when it is not needed.

  Next, the operation of the above embodiment will be described.

  FIG. 2 is an explanatory diagram of each signal in the print head driving power supply apparatus 100.

  In FIG. 2, “V” for the voltage and “I” for the current are attached to the signal name. The input pulse voltage VHpls starts at time T1 and ends at time T9. The drive signal input period PR1 is a period after the timing when the CPU 200 outputs the voltage VHpls of the input pulse in the above embodiment. The drive signal abnormal stop period PR2 is a period indicating a case where the drive signal is stopped for some reason during driving. The drive signal normal stop period PR3 is a period when the drive signal is normally stopped.

  In FIG. 2, when the voltage VHpls of the input pulse is input from the time of level 202, the transistor switch Q4 is driven, and approximately Vcc appears at the collector thereof. Strictly speaking, it is Vcc-Vce (sat) when used in the saturation region, but does not affect the outline of the operation, so the expression of Vcc will be used in the future.

  An inverted signal 205 of the voltage VHpls shown in FIG. 2 appears at the collector of the transistor switch Q4. This inversion signal 205 of the voltage VHpls is a signal generated at a point P1 where the cathode of the diode D1, the anode of the diode D2 and the capacitor C3 are connected, and a differential signal as shown by a differential signal 206 at the point P1 in FIG. A signal with a component is generated. The differential signal 206 at this point P1 is rectified by the diode D2 or the diode D1, is input to the series circuit of the resistor R4 and the resistor R5, is divided, and drives the transistor switch Q3. The waveform of this drive voltage is the base voltage VQ2B of the transistor switch Q2 shown in FIG. When the emitter output of the transistor switch Q3 driven by the base current reaches a constant voltage (approximately Vbe) as the base current of the transistor switch Q2, an output proportional to the current supplied at that time is output to the collector of the transistor switch Q2. Try to flow into. The timing is time T2, and the collector voltage at this time is the collector voltage VQ2c of the transistor switch Q2 shown in FIG.

  When the transistor switch Q2 is driven, the FET Q1 is driven by a voltage obtained by dividing the voltage approximately equal to the voltage VH by the resistors R2 and R1. Then, the voltage VH1 of the print head H1 shown in FIG. 2 is generated and applied to the power terminal of the print head H1 connected to the drain of the FET Q1.

  At this time, an inrush current such as the drain current IQ1D of the transistor Q1 shown in FIG. 2 is generated at the time T3 in the drain of the FET Q1, but the head drive permission signal VHon is not input to the print head H1. Therefore, the drain current converges directly. The point in time when the drain current surely converges and the point in time when the voltage VH1 of the print head H1 reaches the specified voltage coincide with each other at time T4.

  Next, the situation of the drive signal abnormal stop period PR2 in the above embodiment will be described.

  The drive signal abnormal stop period PR2 is a moment when the voltage VHpls of the input pulse is temporarily stopped for some reason in a situation where a printing operation or the like is being performed. The voltage VHpls of the input pulse is stopped during the stop period PR21, and is logically indicated at the Low level in the above embodiment. However, the voltage VHpls of the input pulse may be fixed at a high level during the stop period PR21, and even in this case, the same operation as described above is performed.

  When the input pulse voltage VHpls stops in the drive signal abnormal stop period PR2, the inverted signal 205 of the voltage VHpls is fixed in its inverted logic state if the input pulse voltage VHpls is at the low level. Along with this state, the differential signal 206 at the point P1 changes while transitioning to an equilibrium state, but since the voltage VHpls of the input pulse is stopped, it immediately converges to the level 202. The level 202 is about Vcc-Vce (sat) Q4-VfD2. In FIG. 2, the solid line at level 202 indicates the potential that has immediately converged, and the broken line indicates the 0V potential. Since the head drive permission signal VHon is constantly applied during the drive signal abnormal stop period PR2, constant pulse drive is performed. With the stop period PR21, the differential voltage 206 at the point P1 causes the base voltage VQ2B of the transistor switch Q2 to release the charge accumulated in the smoothing capacitor C2 via the resistor R5 and to the resistor R11 and the transistor switch Q2. . The voltage drop caused by this is indicated by a characteristic 203 (period from time T6 to T7) in FIG. Further, the collector voltage becomes a characteristic indicated by the characteristic 203 as the signal changes. Since the gate signal of the FET Q3 is driven by this voltage, the voltage VH1 of the print head H1 exhibits the characteristics shown in the period PR22. At the same time, the drive current indicated by the head drive permission signal VHon behaves as indicated by the current IH1 of the head H1 during the period PR22 (period T6 to T8). At this time, the drain current of the FET Q1 that supplies the head driving current is as shown by the drain current IQ1D of the transistor Q1 in FIG. That is, when the CPU 200 stops unexpectedly, the subsequent circuit can be stably controlled.

  The drive signal normal stop period PR3 is a period showing a behavior when the print head drive power supply apparatus 100 stops normally.

  At time T5, when the input pulse voltage VHpls stops at Low logic, the inverted signal 205 of the input pulse voltage VHpls transitions as its inverted signal. Accordingly, the differential signal 206 at the point P1 converges while showing the differential component to the level 202 as in the case of the stop period PR21. Along with this, the head drive permission signal VHon is stopped in advance, and is fixed at the low level. Soon, the resistors R5 and R11 and the emitter Q2E of the transistor switch Q2 are discharged, and as a result, as shown at time T10, the base voltage VQ2B of the transistor switch Q2 decreases, and the collector signal transitions to the VH level. Along with this, the voltage VH1 of the head changes to a disconnected state, and the potential is lowered according to the discharge characteristics of the resistor R12. In this phase, since the head drive permission signal VHon is stopped, the current of the head H1 is not generated, and the current of the drain voltage Q1D of the transistor Q1 is almost only the discharge current flowing through the resistor R12.

PRT1 ... Inkjet printer device,
100: Print head drive power supply device,
H1 ... Print head,
C1 ... Aluminum electrolytic capacitor,
R1, R2: Bias resistors.

Claims (5)

An inkjet printer device that records an image on a print medium using a print head,
A power supply unit that generates a DC voltage from a commercial power supply;
Capacitive means for storing electrical energy for operation of the print head;
Switch means connected to a power line from the power supply unit to the capacity means;
Charging means for charging the capacity means by the switch means;
Gate means for controlling output of a drive voltage for driving the switch means based on a pulse outputted from a CPU for outputting a drive permission signal to the print head;
An ink jet printer apparatus comprising: Claim 1 wherein
An ink jet printer apparatus wherein the CPU drive port means and the gate means are connected by a capacity means. Claim 1 wherein
An ink jet printer apparatus, wherein the gate means is a circuit that rectifies using diode means. Claim 1 wherein
An ink jet printer apparatus, wherein the gate means is means having a Darlington connection of transistors. Claim 1 wherein
An ink jet printer apparatus according to claim 1, wherein the gate means is means used as a driving status of the CPU means.

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