JP2012175598A - Time-to-digital conversion device - Google Patents

Abstract

A dynamic range of a time digital converter is widened.
In response to a first signal, a first pulse train generator for starting generation of a first pulse repeated at a predetermined cycle; and in response to the first signal, the first pulse A counter circuit that starts counting pulses, and a stochastic time-to-digital converter having a plurality of delay flip-flops whose input terminals are connected to each other and whose clock terminals are connected to each other, and when the second signal is input The first time based on the count number of the counter circuit is detected as a time difference between the first signal and the second signal.
[Selection] Figure 1

Description

  The present invention relates to a time digital conversion apparatus.

  A time-to-digital converter (hereinafter referred to as TDC) is a device that converts a time difference between input signals into a digital signal. Various types of such time digital conversion devices have been proposed.

  For example, a time digital conversion device has been proposed that has a pair of delay lines in which a plurality of delay circuits are connected in cascade, and detects a time difference between input signals using a difference in propagation delay between the pair of delay lines. As another time digital conversion device, for example, a Stochastic type TDC having a large number of delay flip-flops connected in parallel and detecting the time difference of the input signal using variation in the response of each delay flip-flop has been proposed. ing.

T. Hashimoto, H. Yamazaki, A. Muramatsu, T. Sato and A. Inoue, "Time-to-Digital Converter with Vernier Delay Mismatch Compensation for High Resolution On-Die Clock Jitter Measurement", Symposium on VLSI Circuits Digest of Technical Papers, pp. 166-167, 2008. S. Pellerano, P. Madoglio, and Y. Palaskas, "A 4.75-GHz Fractional Frequency Divider-by-1.25 With TDC-Based All-Digital Spur Calibration in 45-nm CMOS," IEEE Journal of Solid-State Circuits, Vol 44, No. 12, pp. 3422-3433, Dec. 2009.

  The area of the time difference detected by the time digital converter varies greatly depending on the measurement method. For example, a time digital converter using a pair of delay lines measures a time difference in the picosecond region. On the other hand, Stochastic type time TDC using a delay flip-flop measures the time difference in the femtosecond region.

  These conventional time-to-digital converters have a problem that the dynamic range (ratio between the maximum value and the minimum value of the measurement value) is at most about three digits. Therefore, an object of the present invention is to solve such a problem.

  In order to solve the above problem, according to one aspect of the present apparatus, in response to the first signal, a first pulse train generation unit that starts generating a first pulse repeated at a predetermined period; A stochastic type having a counter circuit that starts counting the first pulse in response to the first signal, and a plurality of delay flip-flops having input terminals connected to each other and clock terminals connected to each other A time-to-digital converter that detects a first time based on a count number of the counter circuit when a second signal is input as a time difference between the first signal and the second signal. An apparatus is provided.

  According to this apparatus, the dynamic range of the time digital conversion apparatus can be widened.

1 is a configuration diagram of a time digital conversion device according to Embodiment 1. FIG. 3 is a flowchart for explaining the operation of the TDC according to the first embodiment. 6 is a flowchart for explaining a time difference measurement procedure based on the count number of the first pulse. It is a time chart for explaining the measurement procedure of the time difference based on the count number of the first pulse. It is a flowchart explaining the detection procedure of the 1st error. It is a time chart for explaining the first error detection procedure (part 1). It is a time chart explaining the detection procedure of the 1st error (the 2). It is a time chart explaining the detection procedure of the 1st error (the 3). It is a time chart explaining the case where a falling edge is detected as an adjacent pulse for error measurement. It is a flowchart explaining the detection procedure of the 2nd error. It is a time chart explaining the detection procedure of the 2nd error. It is a time chart explaining the nearest edge. 6 is a configuration diagram of a TDC according to Embodiment 2. FIG. It is a circuit diagram explaining an example of the 1st and 2nd delay circuit. It is a circuit diagram explaining an example of the variable delay circuit of the first stage of a 1st delay circuit unit. It is a circuit diagram explaining an example of the 1st and 2nd inversion delay circuit. It is a figure explaining the structure of STDC. It is a figure explaining operation | movement of STDC. It is a figure explaining the characteristic of STDC. 10 is a flowchart illustrating a first error detection procedure in the second embodiment. It is a time chart explaining the detection procedure of an adjacent edge. It is a look-up table used for detection of adjacent edges for error detection. 12 is a flowchart for explaining a second error detection procedure in the second embodiment. 10 is a time chart illustrating a second error detection procedure in the second embodiment. 10 is a flowchart for explaining a third error detection procedure in the second embodiment. FIG. 10 is a configuration diagram of a TDC according to a third embodiment. FIG. 6 is a circuit diagram illustrating an example of a first delay circuit (excluding a variable delay circuit) according to a third embodiment. FIG. 10 is a circuit diagram illustrating an example of a normal rotation delay unit included in a first inversion delay circuit according to a third embodiment. FIG. 10 is a configuration diagram of a time digital conversion device according to a third embodiment. 10 is a flowchart for explaining the operation of the TDC according to the third embodiment. It is a time chart explaining the 4th error detection procedure. FIG. 10 is a configuration diagram of a TDC according to a fifth embodiment. 10 is a time chart for explaining an error detection step in the fifth embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof. In addition, the same code | symbol is attached | subjected to the corresponding part even if drawings differ, The description is abbreviate | omitted.

(Embodiment 1)
FIG. 1 is a configuration diagram of a time digital conversion device (TDC) 2 according to the present embodiment. As illustrated in FIG. 1, the TDC 2 includes a first pulse train generation unit 4, a second pulse train generation unit 6, a counter circuit 8, and an error detection unit 10.

  The first pulse train generator 4 is a device that starts generating a first pulse that is repeated at a predetermined period T (for example, 10 to 10,000 ps) in response to a first signal. Furthermore, the first pulse train generation unit 4 is a device that repeatedly generates a plurality of delay pulses that rise with a predetermined delay time from the first pulse together with the first pulse. The second pulse train generator 6 is a device that starts generating a second pulse that is repeated at the predetermined period T (for example, 10 to 10,000 ps) in response to a second signal. The counter circuit 8 is a device that starts counting the first pulse in response to the first signal. The error detection unit 10 detects a time based on the count number of the counter circuit 8 when the second signal is input as a time difference between the first signal and the second signal, and an error between the calculated time difference and the actual time difference. Is a device for detecting

  FIG. 2 is a flowchart for explaining the operation of the TDC 2 of the present embodiment. FIG. 3 is a flowchart for explaining the time difference measurement procedure (S2) based on the count number of the first pulse. FIG. 4 is a time chart for explaining the time difference measurement procedure (S2) based on the count number of the first pulse. In FIG. 4, the level change of the first signal 12 and the second signal 14, the level change of the first pulse 16 and the second pulse 26, and the output change (change in the number of counts) 18 of the counter circuit 8. It is shown. Note that, on the left side of the first pulse 16 and the second pulse 26, reference numerals of signal lines to which the respective pulses are output are shown.

-Time difference measurement based on the first pulse count-
When the first signal 12 is input to the first input terminal 20, the first pulse train generator 4 responds to the rising edge RE12 of the first signal 12 as shown in FIG. The generation of the first pulse 16 repeated in step S12 is started (S12 in FIG. 3). The generated first pulse 16 is output to the first signal line V _S0 . At this time, the head portion H12 of the first signal 12 is output as the head portion H16 of the first pulse 16a generated first. The counter circuit 8 starts counting 18 of the first pulse 16 in response to the head portion H12 of the first signal 12 (S14). The counter circuit 8 counts rising edges of the first pulse 16.

When the second signal 14 is input to the second input terminal 22, the second pulse train generator 6 responds to the rising edge RE 14 of the second signal 14 and substantially has the period of the first pulse 16. The generation of the second pulse 26 repeated at the same period T is started. Second pulse 26 generated is output to the fifth signal line _{V r} (S18). The leading portion H14 of the second signal 14 is output as the leading portion H26 of the second pulse 26a that is generated first. The counter circuit 8 stops counting the first pulse 16 in response to the head portion H14 of the second signal 14 (S16). The counter circuit 8 holds the count number N0 (the count number when the second signal 14 is input) at this time.

Next, the TDC 2 calculates the first time t ₀ (= (N0−1) × T) based on the count number N 0 held in the counter circuit 8 as the time difference between the first pulse 12 and the second pulse 14. (S20). For example, when the count number N0 of the counter circuit 8 is 3 and the period T of the first pulse 16 is 200 ps, the time difference between the first pulse 12 and the second pulse 14 is 400 ps (= (3-1 ) × 200 ps).

The first time t ₀ is calculated using the calculation function of the miscalculation detection unit 10. However, the miscalculation detector 10 separately provided calculation unit having a computing function, it may calculate the first time t _0. The same applies to other arithmetic processing described later. Note that the time difference between signals (or pulses) is the time difference between predetermined points in the rising edge of each signal (for example, an intermediate point where the signal rises 50%). The second signal 14 is a signal that rises after the first signal 12 as shown in FIG.

  In the above example, the count number of the first pulse 12 is one digit. However, the counter circuit 8 can easily count pulses of several digits (for example, four digits or more). Therefore, according to the present embodiment, the dynamic range of the time difference between the first pulse 12 and the second pulse 14 can be easily widened.

Incidentally, as shown in FIG. 4, the time difference Δ between the first pulse 12 and the second pulse 14 and the first time t ₀ are different by the first remaining time t _over1 (Δ = t ₀ + t _over1 ). Next, the error detection unit 10 detects a time substantially equal to the first remaining time t _over1 as a first error.

-First error detection-
FIG. 5 is a flowchart for explaining the first error detection procedure (S4 in FIG. 2). 6 to 8 are time charts illustrating the first error detection procedure (S4). In FIG. 6, a first signal 12, a second signal 14, a first pulse 16, and a second pulse 26 are shown.

As described above, in response to the rising edge RE14 of the first signal 12, the first pulse train generator 4 starts generating the first pulse 16 repeated at a predetermined period T (S12 in FIG. 3). ). Similarly, in response to the rising edge RE14 of the second signal 14, the second pulse train generation unit 6 starts generating the second pulse 26 that is repeated at substantially the same period T as the first pulse 16. (S18 in FIG. 3). Therefore, the time difference t ′ _over1 between the first pulse 16 and the second pulse 26 is the time difference between the first pulse 16b and the second signal 14 that are generated immediately before the second signal 14 rises. It is substantially the same as the remaining time t _{over1 of} 1. The error detection unit 10 detects the first error by using this time difference _t′over1 .

As illustrated in FIG. 7, the first pulse train generation unit 4 repeatedly generates a plurality of delay pulses 28 a to 28 c that rise with a delay time t _d from the first pulse 16 together with the first pulse 16. . The generated first to third delay pulses 28a, 28b, and 28c are output to the second to fourth signal lines V _S1 , V _S2 , and V _S3 , respectively (see FIG. 1). In addition, the signal line which each outputs is shown at the left end of each pulse train of FIG.

  FIG. 8 is an enlarged view of a region surrounded by a broken line in FIG. The error detection unit 10 sets the rising edge RE26 of the second pulse 26 among the rising edges RE0 to RE3 and the falling edges FE0 to FE3 of the first pulse 16 and the first to third delay pulses 28a to 28c. Adjacent adjacent edges are detected (S22). Here, the phrase “the second edge is adjacent to the first edge” means that the third edge does not occur between the occurrence of one edge and the occurrence of the other edge. In the example shown in FIG. 8, the edges adjacent to the rising edge RE26 of the second pulse 26 are the rising edge RE2 of the second delay pulse 28b and the rising edge RE3 of the third delay pulse 28c.

  The error detection unit 10 detects the adjacent edge RE2 that rises first out of the pair of adjacent edges RE2 and RE3 adjacent to the rising edge RE26 of the second pulse 26 as the adjacent edge NE for error measurement (S22 in FIG. 5). ).

Error detecting unit 10, a time difference _{t 1} between the detected and the adjacent edge NE edge RE0 rising of the first pulse 16 is detected as the first error (S24). For example, when the adjacent edge NE is a rising edge, the error detection unit 10 determines the time difference t ₁ between the first pulse 16 and the adjacent edge NE based on the order Nf1 in which the adjacent edge NE rises among the rising edges RE0 to RE3. = (Nf1-1) × t _d ) is calculated. In the example of FIG. 8, the order in which the adjacent edge NE rises is the third. Accordingly, when the delay time t _d is 50 ps, the first error t ₁ is 100 ps (= (3-1) × 50 ps).

FIG. 9 is a time chart for explaining a case where the falling edges FE0 to FE3 are detected as adjacent pulses NE for error measurement. In the example of FIG. 9, the falling edge FE1 of the first delay pulse 28a and the falling edge FE2 of the second delay pulse 28b are adjacent to the rising edge RE26 of the second pulse 26. The error detection unit 10 detects the adjacent edge FE1 that falls first among the pair of edges FE1 and FE2 adjacent to the rising edge RE26 of the second pulse 26 as the adjacent edge NE for error measurement (S22 in FIG. 5). ). Error detecting unit 10, a time difference _{t 1} between the adjacent edges NE rising edge RE0 Toko of the first pulse 16, calculates (detects) that the first error (S24).

By the way, in the present embodiment, the adjacent edge rising first (or falling later) is detected as the adjacent edge NE for error detection. However, an adjacent edge that rises (or falls) after a pair of adjacent edges adjacent to the rising edge RE26 of the second pulse 26 may be used as an error measurement adjacent edge. In this case, the second remaining time t _over2 becomes a negative value.

As shown in FIGS. 8 and 9, the first error _{t 1,} the first remaining time _{t OVER1} and (= _t 'over1) are different from the second remaining time _{t Over2} min (thus, Δ _{= t} 0 + _{t 1} + t _over2 ). Next, the error detection unit 10 detects a time substantially equal to the second remaining time t _over2 as a second error.

-Detection of second error-
FIG. 10 is a flowchart for explaining the second error detection procedure (S6 in FIG. 2). FIG. 11 is a time chart for explaining the second error detection procedure (S6). The error detection unit 10 controls the first pulse train generation unit 4 to shift the adjacent pulse 30 having the error detection adjacent edge NE by a predetermined shift toward the second pulse 26 as shown in FIG. Shift by time tf (S32 in FIG. 10). The error detector 10 measures the time difference between the rising edge RE26 of the second pulse 26 and the adjacent edge NE in parallel with the shift of the adjacent pulse 30.

Next, the error detection unit 10 is based on the number of shifts N2 of the adjacent pulse 31 when the absolute value of the time difference between the rising edge RE26 of the second pulse 26 and the adjacent edge NE is equal to or less than half the predetermined shift time tf. detecting a time _{t 2} as a second error (S34). For example, in the example of FIG. 11, the number of shifts N2 of the adjacent pulse 30 is seven. Therefore, when the shift time tf is 1 ps, the second error t ₂ (= N2 × Tf) is 7 ps.

FIG. 12 is a time chart for explaining an adjacent edge NNE (hereinafter referred to as the nearest edge) in which the absolute value of the time difference 33b from the rising edge RE26 of the second pulse 26 is equal to or less than half of the predetermined shift time tf. . FIG. 12 shows adjacent pulses 30a and 30b immediately before and after the rising edge RE26 of the second pulse 26 is overtaken. Here, the adjacent pulse 30b immediately after overtaking the second pulse 26 is a pulse obtained by shifting the adjacent pulse 30a immediately before overtaking by the shift time tf. Therefore, the absolute value of the time difference (for example, the time difference 33a) between one edge of the pair of adjacent pulses 30a and 30b immediately before and after the second pulse 26 and the rising edge RE26 of the second pulse 26 is tf More than half. On the other hand, the absolute value of the time difference (for example, time difference 33b) between the other edge and the rising edge RE26 of the second pulse 26 is equal to or less than half of tf. Second error t ₂ is detected by using such a nearest edge NNE.

Meanwhile, as shown in FIG. 11, the second error _{t 2} includes a second remaining time _{t Over2} third remaining time _{t Over3} are different (<0) minutes. The error detection unit 10 detects the third remaining time t _over3 as a third error in the third error detection procedure described below.

In the example shown in FIG. 11, the adjacent pulse 28 b (see FIG. 8) having the adjacent edge RE <b> 2 rising first among the pair of adjacent edges RE <b> 2 and RE <b> 3 is shifted toward the second pulse 26. However, the adjacent pulses 28c having adjacent edges RE3 which rises after, is shifted towards the second pulse 26, may be detecting a second error t _2.

  Alternatively, an adjacent pulse having an adjacent edge FE1 (or FE2) falling earlier (or later) among the falling edges FE1 and FE2 adjacent to the rising edge RE26 of the second pulse 26 is set as the second pulse 26. You may shift toward (refer FIG. 9).

-Detection of third error-
Next, the error detector 10 detects the time difference t _over3 between the rising edge RE26 of the second pulse and the nearest edge NNE as a third error (S8 in FIG. 2).

The detection of the third error t _3, for example, Stochastic type TDC such a very short time measuring device (not shown) is used. The width of the measurement range (measurable range) of this very short time measuring device is preferably the shift time tf. However, pole measurement range short measuring instrument may be a delay time of the first to third delay pulse 28a~28c in shift time tf or _{t d} less.

―Calculation of wide range time difference―
Finally, the error detection unit 10 uses the first time t ₀ based on the count number of the counter circuit 8, the first error t ₁ , the second error t ₂ , and the time based on the third error t ₃ (= t ₀ + t ₁ + t ₂ + t ₃ ) is calculated as a time difference between the first signal 12 and the second signal 14 (S10 in FIG. 2).

For example, if the time t ₀ , the first error t ₁ , the second error t ₂ , and the third error t ₃ corresponding to the count number of the counter circuit 8 are 400 ps, 100 ps, 7 ps, and 216 fs, respectively, the error The detection unit 10 calculates 507.216 ps as the time difference Δ between the first signal 12 and the second signal 14. In this case, the dynamic range of the time difference measurement is 10 ⁶ . This dynamic range is much wider than that of a conventional TDC dynamic range (about 10 ³ ). Moreover, it is easy to increase the number of digits of the first time t ₀ by increasing the maximum count number of the counter circuit 8. Therefore, it is easy to further widen the dynamic range of the present TDC2.

By the way, in the above example, the error detection unit 10 determines the time difference Δ between the first signal 12 and the second signal 14 based on all the measured values (t ₀ , t ₁ , t ₂ , and t ₃ ). Is calculated. However, the time difference between the first signal 12 and the second signal 14 may be calculated using a part of the measured value. For example, the first time t ₀ based on the count number of the counter circuit 8 may be calculated as the time difference between the first signal and the second signal. In this case, the second pulse train generation unit 6 may not be provided, and the second input unit 22 to which the second signal 14 is input may be directly connected to the counter circuit 8. Similarly, a second time (= t ₀ + t ₁ ) based on the first time t ₀ and the first error t ₁ may be calculated as a time difference between the first signal and the second signal. Further, a third time (= t ₀ + t ₁ + t ₂ ) based on the second time and the second error may be calculated as a time difference between the first signal and the second signal. The same applies to the following embodiments.

(Embodiment 2)
(1) Structure FIG. 13 is a configuration diagram of the TDC 2a of the present embodiment. As shown in FIG. 13, the TDC 2a includes a first pulse generation unit 4a, a second pulse generation unit 6a, a counter circuit 8, and an error detection unit 10a.

-First pulse generator-
The first pulse generation unit 4a includes a first delay circuit unit 32a, a first inversion delay circuit 34a, and a first gate circuit 36a. The first delay circuit unit 32a includes a predetermined number (for example, 1 to 10) of first delay circuits 38a that output an input signal by delaying the input signal by a predetermined time t _c (for example, 10 to 100 ps). The first delay circuits 38a are connected in a column, and the output section of the preceding stage delay circuit is connected to the input section of the next stage delay circuit. First delay circuit 44a is a variable delay circuit for input signal in response to output delayed longer than the predetermined time t _c to the control signal from the first timing control circuit 42a to be described later.

The first inversion delay circuit 34a inverts the input signal and outputs the input signal with a delay of a predetermined time t _c (for example, 10 to 100 ps) substantially equal to the delay time of the first delay circuit 38a. It is an inverting delay circuit. As shown in FIG. 13, the input section of the first inverting delay circuit 34a is connected to the output section of the delay circuit 45a in the final stage of the first delay circuit unit 32a. As shown in FIG. 13, the input portions of the delay circuits 38a and the first inverting delay circuit 34a of the first delay circuit unit 32a are connected to the first to fourth signal lines V _S0 , V _S1 , V _S2 , respectively. Connected to V _S3 .

  The first gate circuit 36a includes a first switch circuit 40a and a first timing control circuit 42a. The first switch circuit 40a has a pair of input units SWIN1, SWIN2 and an output unit SWOUT, and connects one of the input units to the output unit SWOUT. The input units SWIN1 and SWIN2 are connected to the first input terminal 20a and the output unit of the first inverting delay circuit 34a, respectively. On the other hand, the output unit SWOUT is connected to the input unit of the first delay circuit unit 32a.

  The first timing control circuit 42a monitors the output signals of the first delay circuit 38a and the first inversion delay circuit 34a, and controls the opening and closing of the switches in the first switch circuit 40a. Further, the first timing control circuit 42a controls the first delay circuit (variable delay circuit) 44a and the third switch circuit 48 of the first delay unit 32a in accordance with a command from the arithmetic control unit 54 described later.

  The first timing control circuit 42a is a logic circuit. However, the first timing control circuit 42a may be a circuit having a CPU (Central Processing Unit) and a memory. In that case, a program for causing the CPU to realize the function of the first timing control circuit 42a is recorded in the memory.

-Second pulse generator-
The second pulse generator 6a has substantially the same structure as the first pulse generator 4a. However, the first-stage delay circuit of the second delay circuit unit 32b is not a variable delay circuit.

In other words, the second pulse generator 6a includes a second delay circuit unit 32b, a second inversion delay circuit 34b, and a second gate circuit 36b. The second delay circuit unit 32b has a predetermined number of second delay circuits 38b that delay and output an input signal for a predetermined time t _c substantially equal to the delay time of the first delay circuit 38a. . The number of second delay circuits 38b is the same as the number of first delay circuits 38a. The second delay circuits 38b are connected in a column, and the output section of the preceding delay circuit 38b is connected to the input section of the next delay circuit 38b.

The second inversion delay circuit 34b is an inversion delay circuit that inverts the input signal and delays and outputs the input signal for a predetermined time t _c substantially equal to the delay time of the second delay circuit 38b. As shown in FIG. 13, the input section of the second inversion delay circuit 34b is connected to the output section of the delay circuit 45b at the final stage of the second delay circuit unit 32b. As shown in FIG. 13, the input section of the first delay circuit 44b of the second delay circuit unit 32b is connected to the fifth signal line _Vr .

  The second gate circuit 36b has a second switch circuit 40b and a second timing control circuit 42b. The output section of the second inverting delay circuit 34b is connected to one input section of the second switch circuit 40b. The other input part of the second switch circuit 40b is connected to the second input part 22b of the TDC 2a. The structure and function of the second switch circuit 40b are substantially the same as those of the first switch circuit 40a.

  The second timing control circuit 42b monitors the output signals of the second delay circuit 38b and the second inversion delay circuit 34b, and controls the opening and closing of the switches in the second switch circuit 40b. The structure of the second timing control circuit 42b is substantially the same as that of the first timing control circuit 42a.

-Counter circuit-
The first input section CIN1 of the counter circuit 8 is connected to a first signal line V _S0 connected between the first switch circuit 40a and the first delay circuit unit 32a. On the other hand, the second input CIN2 of the counter circuit 8 is connected to the fifth signal line V _r connected between the second switch circuit 40b and the second delay circuit unit 32b. The counter circuit 8 starts counting the pulse in response to the pulse input to the first input unit CIN1. Further, the counter circuit 8 stops counting pulses input to the first input unit CIN1 in response to a signal input to the second input unit CIN2.

―Error detection part―
The error detection unit 10 a includes a third switch circuit 48, a Stochastic-type time digital conversion device 50 (hereinafter referred to as STDC), and an arithmetic control unit 54. Input portions of the third switch circuit 48 are connected to signal lines V _{S0 to} V _S3 , respectively. The output section SOUT of the third switch circuit 48 is connected to the first input section STIN1 of the STDC 50. On the other hand, the second input STIN2 of STDC50 the fifth signal line _{V r} which is connected to the second pulse generating unit 6a is connected.

  The arithmetic control unit 54 has, for example, a CPU and a memory. In this memory, a program for causing the CPU to realize the function of the arithmetic control unit 54 is recorded. This memory is also used for calculations performed by the CPU. The arithmetic control unit 54 may be a logic circuit such as an FPGA (Field Programmable Gate Array).

  The output COUT of the counter 8 and the output SOUT of the STDC 50 are transmitted to the arithmetic control unit 54. The arithmetic control unit 54 controls the first timing control circuit 42a and the second timing control circuit 42b.

―Delay circuit―
Various logic circuits can be used as the first and second delay circuits 38a and 38b. For example, a pair of inverter circuits or an exclusive logic circuit can be used. The same applies to the first and second inversion delay circuits 34a and 34b.

  FIG. 14 is a circuit diagram illustrating an example of the first and second delay circuits 38a and 38b (excluding the variable delay circuit 44a). As shown in FIG. 14, the delay circuits 38a and 38b have, for example, a pair of CMOS (Complementary Metal Oxide Semiconductor) inverter circuits 56a and 56b connected in cascade. The delay times of the pair of CMOS inverter circuits 56a and 56b are substantially the same.

  The input signal input to the input terminal DIN1 is delayed and inverted by the first-stage inverter circuit 56a and transmitted to the second-stage inverter circuit 56b. The input signal transmitted to the second-stage inverter circuit 56b is further delayed and inverted and output from the output terminal DOUT1. Accordingly, the signals input to the delay circuits 38a and 38b are delayed by twice the delay time of the CMOS inverter circuits 56a and 56b, and then output at the original level (normal rotation).

-Variable delay circuit-
FIG. 15 is a circuit diagram illustrating an example of the variable delay circuit 44a in the first stage of the first delay circuit unit 32a. The delay circuit 44a shown in FIG. 15 includes a pair of CMOS inverter circuits 56c and 56d, a capacitor 58, and a switch 60 that are connected in cascade. The delay time of the CMOS inverter circuits 56c and 56d is a predetermined time substantially the same as the delay time of the CMOS inverter circuits 56a and 56b included in the first and second delay circuits 38a and 38b.

  Both ends of the capacitor 58 are connected to a wiring 57 and a switch (transistor) 60 for connecting the CMOS inverter circuits 56a and 56b, respectively. The arithmetic control unit 54 sends a control signal to the gate terminal 62 of the switch 60 via the first timing control circuit 42 a to open and close the switch 60. The variable delay circuit 44a operates in substantially the same manner as the delay circuits 38a and 38b of FIG. 14 while the switch 60 is open. On the other hand, the variable delay circuit 44a charges or discharges the capacitor 58 while the switch 60 is closed. Therefore, the variable delay circuit 44a outputs the signal input to the input terminal DIN2 from the output terminal DOUT2 over a longer time than when the switch 60 is open. Therefore, the delay time becomes long.

―Inversion delay circuit―
FIG. 16 is a circuit diagram illustrating an example of the first and second inversion delay circuits 34a and 34b. The inverting delay circuits 34a and 34b shown in FIG. 16 have one CMOS inverter 56e and a capacitor 64 connected to the output portion of the CMOS inverter 56e. The delay time of the CMOS inverter 56e is substantially the same as the delay times of the CMOS inverter circuits 56a and 56b included in the first and second delay circuits 38a and 38b.

  The input signal input to the input terminal DIN3 is delayed and inverted by the CMOS inverter 56e, and then output from the output terminal DOUT3. The delay time of the input signal is the sum of the delay time of the CMOS inverter 56e and the charging time of the capacitor 64. The charging time of the capacitor 64 is set to substantially the same time as the delay time of the CMOS inverter 56e. Accordingly, the delay times of the first and second inversion delay circuits 34a and 34b are substantially the same as the delay times of the first and second delay circuits 38a and 38b.

―STDC―
FIG. 17 is a diagram for explaining the structure of the STDC 50. FIG. 18 is a diagram for explaining the operation of the STDC 50. As shown in FIG. 17, the STDC 50 has a plurality of delay flip-flops (D flip-flops) 66 and an encoder 68. The input terminals X of the delay flip-flop 66 are connected to each other and connected to the first input section STIN1 of the STDC 50. Similarly, the clock terminals Y of the delay flip-flop 66 are connected to each other and connected to the second input section STIN2 of the STDC 50.

  On the other hand, the plurality of output terminals Q of the delay flip-flop 66 are respectively connected to the input section of the encoder 68. The encoder 68 counts the number of delay flip-flops 66 in the on state, and outputs the count number from the output unit STOUT. The delay flip-flop 66 is a flip-flop that is turned on when the clock terminal Y changes from a low level to a high level when the input terminal X is at a high level, and outputs a high level signal.

  FIG. 18 shows a first input signal 70a input to the first input unit STIN1 and a second input signal 70b input to the second input unit STIN2. The vertical axis is voltage, and the horizontal axis is time. The time on the horizontal axis is the time in the fs (femtosecond) region. In such a time domain, the signal levels of the first input signal 70a and the second input signal 70b gradually change from the low level to the high level. The STDC 50 detects, for example, the time difference Δt between the intermediate point 74a of the rising edge 72a of the first input signal 70a and the intermediate point 74b of the rising edge 72b of the second input signal 70b.

  Each delay flip-flop 66 does not have a function of detecting a time difference between input signals. However, as shown in FIG. 18, when the rising edge 72a of the first input signal 70a and the rising edge 72b of the second input signal 70b overlap, a plurality of delay flip-flops are caused due to variations in characteristics of the delay flip-flops 66. Only a part of 66 is turned on. At this time, the number of delay flip-flops 66 that are turned on increases as the time difference Δt between the first input signal 70a and the second input signal 70b increases. The STDC 50 uses this property to detect the time difference Δt of the input signal.

FIG. 19 is a diagram for explaining the characteristics of the STDC 50. The horizontal axis represents the time difference Δt (= t ₂ −t ₁ ) between the input time t ₁ of the first input signal 70 a and the input time t ₂ of the second input signal 70 b. The vertical axis represents the output D _{tdc of STDC 50} (the number of delay flip-flops 66 in the on state). As shown in FIG. 19, the output D _tdc of the _{STDC 50} varies substantially linearly with respect to the time difference Δt within a certain range 76 centered on 0 fs. Therefore, if the time difference Δt is within this range 76 (hereinafter referred to as a measurement range), the time difference Δt can be easily obtained from the output of the STDC 50. The time difference Δt of the input signals obtained in this way is the time in the fs (femtosecond) region. The measurement range 76 is a range of −σ or more and σ or less, where σ is a standard deviation regarding the time difference Δt.

Outside the measurement range 76, the output D _tdc of the _{STDC 50} is substantially 0 or the maximum value of the output. Based on this characteristic, the signal level of the first input signal 70a at the rising edge of the second input signal 70b can be detected. For example, if the output D _{tdc of the STDC 50} is substantially 0, the signal level of the first input signal 70a at the rising edge of the second input signal 70b is low. On the other hand, if the output of the STDC 50 is substantially the maximum value (for example, 255), the signal level of the first input signal 70a at the rising edge of the second input signal 70b is high.

(2) Operation The operation of the TDC 2a is substantially the same as the TDC 2 of the first embodiment described with reference to FIGS. Therefore, the operation of the TDC 2a will be described with reference to the circuit diagrams of FIGS. 2 to 12 and FIG.

-Time measurement based on pulse count (S2 in Fig. 2)-
Until the first signal 12 is input, the first input terminal 20a of the TDC 2a is connected to the input portion of the first delay circuit unit 32a by the first gate circuit 36a. On the other hand, the input section of the first delay circuit unit 32a and the output section of the first inverting delay circuit 34a are separated. In this state, the outputs of the delay circuits 38a included in the first delay circuit unit 32a are all at a low level, and the outputs of the first inversion delay circuit 34a are at a high level.

Now, when the first signal 12 is input to the first input terminal 20a, the first signal 12 is supplied to the first delay circuit unit 32a via the first switch circuit 40a. At this time, the head portion H12 of the first signal 12 is output to the first signal line _{V S0,} the first signal line _{V S0} to the high level (see FIG. 4). Thereby, the first generation of the first pulse 16 output to the first signal line V _S0 is started.

When the first signal 12 is supplied to the first delay circuit unit 32a, each delay circuit 38a of the first delay circuit unit 32a sequentially changes from the off state to the on state. According to this change, the second to fourth signal lines V _{S1 to} V _S3 sequentially change from the low level to the high level (see FIG. 7). Thereby, the first generation of the first to third delay pulses 28a to 28c starts sequentially.

For example, in response to a level change of the first signal line V _S1 , the first gate circuit 36a disconnects the input portion of the first delay circuit unit 32a from the first input terminal 20a, and the first inversion delay circuit. Connect to the output of 34a. At this time, the output of the first inversion delay circuit 34a is at a high level. Therefore, the input section of the first delay circuit unit 32a is kept at the high level by the output of the first inverting delay circuit 34a even after being disconnected from the first input section 20a.

When the final delay circuit 45a of the first delay circuit unit 32a is turned on, the first inversion delay circuit 34a inverts its output V _S3 (high level) and inputs the first delay circuit unit 32a. Return to the department. By this feedback, the level of the first signal line V _S0 changes from the high level to the low level, and the first generation of the first pulse 16 is completed.

Each delay circuit 38a of the first delay circuit unit 32a sequentially changes from an on state to an off state in response to the fed back inverted output. Therefore, the signal levels of the second to fourth signal lines V _{S1 to} V _S3 sequentially change from the high level to the low level. Thereby, the first generation of the first to third delay pulses 28a to 28c is sequentially completed.

When the generation of the third delay pulse 28c ends and the final delay circuit 45a of the first delay circuit unit 32a is turned off, the first inversion delay circuit 34a inverts its output V _S3 (low level). Then, the feedback is made to the input section of the first delay circuit unit 32a. By this feedback, the level of the first signal line V _S0 changes to a high level, and the generation of the first pulse 16 is resumed. Thereafter, the generation of the first pulse 16 and the first to third delay pulses 28a to 28c is repeated.

As is clear from the above description, the pulse width PW (see FIG. 8) of the first pulse 16 is the total number M of delay circuits 38a and inversion delay circuits 34a (4 in the example of FIG. 13), the delay circuits 38a and This is the product M × t _c of the delay time t _c of the inverting delay circuit 34a. The pulse interval PD of the first pulse 16 is also M × t _c . Therefore, the period T in which the generation of the first pulse 16 is repeated is 2M × t _c (8t _{c in the} present TDC 2a).

That is, the present TDC2a in response to the rising edge of the first signal 12, starts generating the first pulse 16 that is repeated at a predetermined cycle 8t _c (S12 in FIG. 3). As is apparent from the above description, the time interval (delay time t _d ) when the first pulse 16 and the first to third delay pulses 28a to 28c sequentially rise is determined by the delay circuit 38a and the inversion delay circuit 34a. it is the delay time _{t c.}

By the way, when the first signal 12 is input to the first input terminal 20a, the first signal line _VSO changes from the low level to the high level. In response to this change, the counter circuit 8 starts counting the first pulse 16 (S14 in FIG. 3).

  On the other hand, when the second signal 14 is input to the second input terminal 22b, the second pulse train generator 6a starts generating the second pulse 26 repeated at a predetermined cycle (S18 in FIG. 3). The procedure in which the second pulse train generator 6a generates the second pulse 26 is substantially the same as the procedure in which the first pulse train generator 6a generates the first pulse 16. Therefore, the cycle in which the generation of the second pulse 26 is repeated is substantially equal to the cycle in which the generation of the first pulse 16 is repeated.

When the second signal 14 to the second input terminal 22b is inputted, the fifth signal line V _r is output leading portion of the second signal 14, the fifth signal line V _r of a high level from a low level To change. In response to this change, the counter circuit 8 stops counting the first pulse 16 (S16 in FIG. 3).

The arithmetic control unit 54 calculates a time based on the count number of the counter circuit 8 at this time as a time difference between the first signal 12 and the second signal 14 (S20 in FIG. 3). For example, when the output of the counter circuit 8 is 4 and the delay time t _c is 50 ps, the calculated time is 1200 ps (= 8 × (4-1) × 50 ps).

-First error detection (S4 in Fig. 2)-
FIG. 20 is a flowchart for explaining a first error detection procedure in the present embodiment. The arithmetic control unit 54 first controls the third switch circuit 48 via the first timing control circuit 42a, and sequentially supplies the first to fourth signal lines V _{S0 to} V _S3 to the first input unit of the STDC 50. Connect to STIN1. On the other hand, a fifth signal line V _r is connected to the second input section STIN2 of the STDC 50. The arithmetic control unit 54 sequentially reads the output of the STDC 50 and sequentially detects and records the signal levels of the first to fourth signal lines V _{S0 to} V _S3 when the signal output to the fifth signal line V _r rises. (S42 in FIG. 20).

  For example, when the detected signal level is a low level, the arithmetic control unit 54 records the level value “0” together with the identifier of the signal line from which the signal level is detected. Similarly, when the detected signal level is high, the arithmetic control unit 54 records the level value “1” together with the identifier of the signal line from which the signal level is detected.

Next, the arithmetic control unit 54 generates a level matrix Vs <N: 0> from the recorded level values (S44 in FIG. 20). N is an integer smaller than the number of elements of the matrix. Each element of the level matrix Vs <N: 0> is a signal level recorded in association with the output signal line. For example, in the TDC 2a shown in FIG. The first element Vs <0> is a level value of the first signal line V _S0 when a signal output to the fifth signal line V _r rises. The second to fourth elements Vs <1> to Vs <3> are the level values of the second to fourth signal lines V _{S1 to} V _S3 when the signal output to the fifth signal line V _r rises. It is.

  Based on the level matrix Vs <N: 0>, the arithmetic control unit 54 raises the rising edge RE26 of the second pulse 26 from the edges of the first pulse 16 and the first to third delay pulses 28a to 28c. One of the pair of adjacent edges adjacent to is detected (S46 in FIG. 20).

The arithmetic control unit 54 detects the first to third errors using the detected adjacent edge. FIG. 21 is a time chart for explaining a procedure for detecting an adjacent edge for error detection. FIG. 21 shows pulses output to the first to fifth signal lines V _{S0 to} V _S3 and V _r . As shown in FIG. 21, the first pulse 16 and the first to third delay pulses 28a to 28c are output to the first to fourth signal lines V _{S0 to} V _S3 , respectively. On the other hand, the second pulse 26 is output to the fifth signal line _Vr . Therefore, the level matrix Vs <3: 0> indicates the signal levels of the first pulse 16 and the first to third delay pulses 28a to 28c when the second pulse 26 rises.

As shown in the upper part of FIG. 21, one cycle of the first pulse 16 is divided into a plurality of periods (hereinafter referred to as delay periods) by the edges of the first pulse 16 and the first to third delay pulses 28a to 28c. ) 78a to 78h. The length of each of the delay periods 78a to 78h is the delay time t _c of the first delay circuit 38a and the first inversion delay circuit 34a. The upper part of FIG. 21 shows a level matrix Vs <3: 0> that is generated when the second pulse 26 rises within each delay period.

  For example, as shown in FIG. 21, when the second pulse 26 rises in the third delay period 78c, the first pulse 16 at the rising edge RE26 of the second pulse 26 is at a high level. Similarly, the first delay pulse 28a and the second delay pulse 28b are also at a high level. On the other hand, the third delay pulse 28c is at a low level. Therefore, the level matrix Vs <3: 0> is “0111”.

  As shown in FIG. 21, the level matrix Vs <3: 0> and the delay periods 78a to 78h have a one-to-one correspondence. Therefore, by referring to the level matrix Vs <3: 0>, it is possible to detect the delay periods 78a to 78h in which the second pulse 26 rises. Further, as shown in FIG. 21, each of the delay periods 78a to 78h is divided by the edge of the first pulse 16 or the first to third delay pulses 28a to 28c. Therefore, an adjacent edge adjacent to the rising edge RE26 of the second pulse 26 can be detected from the delay periods 78a to 78h in which the second pulse 26 rises.

  For example, the third delay period 78c corresponds to the level matrix “0111” as described above. The edges that delimit the delay period 78c are the rising edges RE2 and RE3 of the second delay pulse 28b and the third delay pulse 28c. Therefore, the pair of edges RE 2 and RE 3 are adjacent edges of the second pulse 26. The arithmetic control unit 54 detects one of the pair of adjacent edges as an error detection adjacent edge NE. A lookup table is used to detect adjacent edges.

  FIG. 22 is a look-up table (hereinafter referred to as Table 1) used for detecting adjacent edges for error detection. In the first row of Table 1, the level matrix Vs <3: 0> is shown. The third line of Table 1 shows a signal line from which an adjacent edge NE for error detection is output. “Rise” and “fall” in the third row indicate whether the adjacent edge NE shown in each cell is a rising edge or a falling edge. The adjacent edge NE shown in Table 1 is a front adjacent edge that rises first among a pair of adjacent edges.

Second row of Table 1 shows the time difference t ₁ between adjacent edges NE rising edge RE16 and for error measurement of the first pulse 16.

Assume that the error detection unit 10a detects the edge matrix “0111”. In this case, the arithmetic control circuit 54 refers to this lookup and detects the rising edge RE2 of the second delay pulse 28b output to the third signal line V _S2 as an adjacent edge NE for error detection (FIG. 20 S46). Further, with reference to this lookup, the arithmetic control circuit 54 detects the time difference 2t _c between the rising edge RE16 of the first pulse 16 and the detected adjacent edge NE as a first error (S48). The actual look-up table shows the actual time difference, not the variable 2t _c . For example, when the delay time t _c is 50 ps, the first error t ₁ is 100 ps (= 2 × 50 ps).

  Note that steps S42 to S46 of the present embodiment correspond to S22 (FIG. 5) of the first embodiment. Further, step S48 in the present embodiment corresponds to S24 in the first embodiment.

-Second error measurement (S6 in Fig. 2)-
FIG. 23 is a flowchart for explaining a second error detection procedure in the present embodiment. FIG. 24 is a time chart for explaining a second error detection procedure in the present embodiment.

  FIG. 24 shows the adjacent pulse 30 and the second pulse 26 having the adjacent edge NE for error detection. An adjacent pulse is a pulse having an adjacent edge.

The arithmetic control unit 54 controls the third switch circuit 48 to connect the signal line (for example, V _S2 ) from which the adjacent pulse 30 is output to the first input unit STIN1 of the STDC 50 (S52). The first input unit STIN1 and the third switch circuit 48 are connected by a signal line Vs as shown in FIG. On the other hand, the second input section STIN2 of the STDC 50 is connected to the fifth signal line Vr from which the second pulse 26 is output. On the left side of each pulse train in FIG. 24, the reference numerals of signal lines to which the respective pulses are transmitted are shown.

Next, the arithmetic control unit 54 reads the output code D _tdc of the _{STDC 50} (S54). The arithmetic control unit 54 determines whether the absolute value of the time difference Δt of the input signal corresponding to the read output code D _tdc is less than or equal to half of a predetermined shift time tf described later (S56).

As shown in FIG. 19, the output code D _tdc of the STDC 50 changes substantially linearly with respect to the time difference Δt of the input signal within the measurement range 76 centered on 0 fs. In the example illustrated in FIG. 19, the measurement range 76 is −1000 to 1000 fs. As shown in FIG. 19, when the output code D _tdc is 59 or more and 133 or less, the time difference Δt of the input signal is −1000 to 0 fs. When the output code D _tdc is 133 or more and 212 or less, the time difference Δt of the input signal is 0 to 1000 fs.

Now, it is assumed that the shift time tf is 2000 fs which is the same as the width of the measurement range. When the output code D _{tdc of the STDC 50} is 59 or more and 133 or less, the arithmetic control circuit 54 determines that the absolute value of the time difference Δt of the input signals is less than half of the shift time tf. Similarly, when the output code D _{tdc of the STDC 50} is 133 or more and 212 or less, the arithmetic control circuit 54 determines that the absolute value of the time difference Δt of the input signals is half or less of the shift time tf. In these cases, the process proceeds to step S62 described later, and the time based on the number of shifts of the adjacent pulse 30 is detected as the second error.

When the absolute value of the time difference Δt obtained from the output code D _tdc is larger than half of tf, the arithmetic control unit 54 increases the delay time of the variable delay circuit 44a of the first delay circuit unit 32a by the shift time tf. (S58).

  By this step 58, each pulse (first pulse 16 and first to third delay pulses 28a to 28c) generated by the first pulse train generator 32a is shifted by tf. Therefore, as shown in FIG. 24, the adjacent pulse 30 is also shifted by the shift time tf toward the second pulse 26 in the first shift period 80a. The shift time tf is a time (> 0) that is equal to or less than the width of the measurement range 76 of the STDC 50. The shift time tf of the present embodiment is the measurement range 76 of the STDC 50.

Next, the calculation control unit 54, the delay time of the variable delay circuit 44a is returned to the original delay time t _c, fewer or generation of the next adjacent pulse 30b to maintain the original delay time t _c until the end. (S60). By this step 60, as shown in FIG. 24, during the first memory period 82a following the first shift period 80a, the adjacent pulses 30b and 30c maintain the tf-shifted state. The time difference between the adjacent pulse 30 and the second pulse 26 in the memory period 82a is shorter by tf than the time difference before the shift (second residual time t _over2 ).

The arithmetic control unit 54 returns to step S54 and again reads the output code D _tdc of the STDC 50 in the first memory period 82a. The arithmetic control unit 54 determines again whether the absolute value of the time difference Δt corresponding to the read output code D _tdc is less than or equal to half of the shift time tf (S56), and the absolute value of the time difference Δt is not less than or equal to half of the shift time tf. In this case, the delay time of the variable delay circuit 44a is increased again by tf (S58).

  The arithmetic control unit 54 repeats the above steps. Therefore, as shown in FIG. 24, the shift period 80 and the memory period 82 are alternately repeated, and finally the absolute value of the time difference between the adjacent pulse 30 and the second pulse 26 becomes equal to or less than half of tf.

Then, the arithmetic control unit 54 determines that the absolute value of the time difference Δt corresponding to the output D _tdc of the _STDC has become half or less of the shift time tf (for example, 1 ps), and shifts the adjacent pulse 30 N3 (for example, 7 time corresponding to the times) (= tf × N3, for example 7 ps) is calculated as the second error _{t 2} (S62). Further, the arithmetic control unit 54 records the output code D _tdc of the _STDC 50 at this time in, for example, the memory of the arithmetic control unit 54 (S62).

As described with reference to FIG. 11, the second error t ₂ is the time difference between the adjacent pulse 30 and the second pulse 26 before the shift start (second residual time t _over2 ) and the third residual time t. _It differs by _over3 minutes.

  In the above example, the delay time of the variable delay circuit 44 a is lengthened, and the adjacent pulse 30 rising first among the pair of adjacent pulses is shifted toward the second pulse 26. However, the delay time of the variable delay circuit 44a may be shortened to shift the adjacent pulse that rises later among the pair of adjacent pulses. In that case, the delay time of the first and second delay circuits 38a, 38b is made longer by the capacitor, and the switch 58 (FIG. 15) of the variable delay circuit 44a is opened, so that the variable delay circuit 44a The delay time can be shorter than that of the first and second delay circuits 38a and 38b.

-Third error measurement (S8 in Fig. 2)-
Next, the error detection unit 10 detects the third remaining time t _over3 as the third error t ₃ using the _{STDC 50} . FIG. 25 is a flowchart for explaining the third error detection procedure.

The arithmetic control unit 54 first reads out the output code D _tdc of the _STD 50 recorded in step 62 from the memory (S72). The arithmetic control unit 54 calculates the time difference Δt corresponding to the read output code D _tdc as the third error t ₃ (S74). Third error t _3, for example is calculated based on the following equation.

Here, D _x is an output code D _tdc that the arithmetic control unit 54 reads from the _{STD 50} . This output code D _tdc is an output code when the absolute value of the time difference Δt of the input signals of the STDC ₅₀ is less than half of the shift time tf. D ₀ is an output code when the time difference Δt is 0 seconds. _DL is an output code corresponding to the upper limit value or the lower limit value of the measurement range 76. MR is the width of the measurement range of the STDC 50.

In the example shown in FIG. 19, D ₀ is 133. _{D L} corresponding to the upper limit of the measurement range 76 is 212. _{D L} corresponding to the lower limit of the measurement range 76 is 59. The width MR of the measurement range is 200 fs. When D _x is not less than _{D 0} is the upper limit of the measurement range 76 is used as _{D L.} On the other hand, when _{D x} is _{D 0} or less, the lower limit of the measurement range 76 is used as _{D L.}

Assuming that D _x is 75, the third error is −78f [= (75-133) / (59-133)] according to the equation (1).

-Calculation of wide range time difference (S10 in Fig. 2)-
Finally, the arithmetic control unit 54 determines the first time based on the time t ₀ , the first error t ₁ , the second error t ₂ , and the third error t ₃ corresponding to the count number of the counter circuit 8. A time difference (= t ₀ + t ₁ + t ₂ + t ₃ ) between the signal 12 and the second signal 14 is calculated.

For example, when t ₀ , t ₁ , t ₂ , and t ₃ are 1200 ps, 200 ps, 7 ps, and −78 fs, respectively, the arithmetic control unit 54 calculates 14006.992 fs. The dynamic range of this value is 8 digits. The count corresponding to t ₀ = 1200 ps is about one digit. Since the count number of the counter circuit 8 easily reaches several digits, the dynamic range is further widened.

The dynamic range of each time t _{0 to} t ₃ measured in the present embodiment is about three digits at most. However, in this embodiment, as described above, a wide dynamic range of 8 digits or more is realized by performing error detection in a plurality of stages while increasing measurement accuracy.

  Further, the TDC 2a of the present embodiment delays an input signal by connecting delay circuits in a ring shape. Therefore, according to the TDC 2a of the present embodiment, the input signal can be delayed for a long time with a small number of delay circuits. Therefore, according to the present embodiment, the TDC device can be easily downsized.

  By the way, even if the pulse generation periods T of the first pulse train generation unit 32a and the second pulse train generation unit 32b are slightly shifted, if the count number of the counter circuit 8 is large, the measured value of the time difference is shifted from the actual time difference. Becomes larger. Therefore, it is preferable to adjust the delay times of the first and second delay circuits 38a and 38b before starting the measurement of the time difference so that such a deviation does not occur. In order to adjust the delay time of the delay circuit, for example, a minute capacitor may be connected to the delay circuit. In order to detect a shift in the generation period T of the first and second pulses, for example, the first signal and the second signal are simultaneously input to the TDC 2 and a considerable number of first and second pulses are generated. Then, the time difference between the two pulses may be measured with the STDC 50 or the like.

(Embodiment 3)
FIG. 26 is a configuration diagram of the TDC 2b according to the present embodiment. The structure and operation of TDC 2b in the present embodiment are substantially the same as TDC 2a in the second embodiment. That is, as shown in FIG. 26, the TDC 2b includes a first pulse generator 4A, a second pulse generator 6A, a counter circuit 8A, and an error detector 10A (hereinafter referred to as the first pulse generator 4A, etc.). Called). In FIG. 13 and FIG. 26 showing the TDC 2a, the positions of the first pulse generation unit 4A and the second pulse generation unit 6A are switched.

  However, as shown in FIG. 26, the TDC 2b has a first inverting input terminal / 20A to which an inverted signal of the first signal is input in addition to the first input terminal 20A to which the first signal is input. Yes. The TDC 2b has a second inverting input terminal / 20B to which an inverted signal of the second signal is input in addition to the second input terminal 20B to which the second signal is input. Then, the first pulse generation unit 4A and the like receive the normal input signal and the inverted input signal, and output the normal output signal and the inverted output signal. These normal input signal and inverted input signal are inputted substantially simultaneously. Further, the delay times of the normal output signal and the inverted output signal are substantially equal. The same applies to the circuits and the like included in the first pulse generator 4A and the like.

(1) First Pulse Generation Unit The first pulse generation unit 4A is similar to the first pulse generation unit 4a of the second embodiment in that the first delay circuit unit 32A, the first inversion delay circuit 34A, And a first gate circuit 36A (hereinafter referred to as a first delay circuit unit 32A or the like). However, the first delay circuit unit 32A and the like receive a normal input signal and an inverted input signal, and output a normal output signal and an inverted output signal.

  The first delay circuit unit 32A and the like delay the normal rotation input signal in the same manner as the first delay circuit unit 32a and the like of the second embodiment, and output it as a normal rotation output signal. Further, the first delay circuit unit 32A and the like delay the inverted input signal (inverted signal of the normal input signal) and output it as an inverted output signal (inverted signal of the normal output signal).

-First delay circuit unit-
As shown in FIG. 26, the first delay circuit unit 32A includes first delay circuits 38A connected in cascade. FIG. 27 is a circuit diagram illustrating an example of the first delay circuit 38A (excluding the variable delay circuit 44A). As illustrated in FIG. 27, the delay circuit 38A includes a normal rotation delay unit 84 and an inversion delay unit 86. The structures of the forward delay section 84 and the inversion delay section 86 are substantially the same as those of the first delay circuit 38a of the second embodiment (see FIG. 14).

  The input unit of the normal rotation delay unit 84 is connected to the normal rotation input unit 88. The output unit of the normal rotation delay unit 84 is connected to the normal rotation output unit 90. Similarly, the input unit and the output unit of the inverting delay unit 86 are connected to the inverting input unit 92 and the inverting output unit 94, respectively.

  Similarly to the first delay circuit 38a of the second embodiment, the first delay circuit 38A delays the normal rotation input signal input to the normal rotation input unit 88 by a predetermined time and outputs the normal rotation from the normal rotation delay unit 90. Output as a force signal. Similarly, the first delay circuit 38A delays the inverting input signal input to the inverting input unit 92 for a predetermined time, and outputs the inverted output signal from the inverting delay unit 94 as an inverted output signal. The delay times of the forward rotation delay unit 84 and the inversion delay unit 86 are substantially equal.

  The variable delay circuit 44A in the first stage of the first pulse train generation unit 6A has a normal rotation delay unit and an inversion delay unit, like the other delay circuits 38A. The normal delay section and the inversion delay section of the variable delay circuit 44A have substantially the same structure as the variable delay circuit 44a of the second embodiment described with reference to FIG. Therefore, the variable delay circuit 44A delays the normal input signal and the inverted input signal for a predetermined time and outputs them. In addition, the variable delay circuit 44A delays and outputs the normal input signal and the inverted input signal for a time longer than the predetermined time in accordance with the control signal of the first timing control circuit 4A.

-First inversion delay circuit-
The first inversion delay circuit 34A has substantially the same structure as the first delay circuit 38A in FIG. However, the output 84 of the normal delay part of the first inverting delay circuit 34A is connected to the inverting output part 94. On the other hand, the output of the inversion delay unit 86 is connected to the normal output unit 90. Accordingly, the first inversion delay circuit 34A functions as an inversion delay circuit that inverts and outputs the input signal. Furthermore, the normal rotation delay unit and the inversion delay unit of the first inversion delay circuit 34A have a switch between the power supply and the ground.

FIG. 28 is a circuit diagram for explaining an example of the normal rotation delay unit 84a of the first inversion delay circuit 34A. As shown in FIG. 28, the normal rotation delay unit 84a has a main body portion 96 having substantially the same structure as the normal rotation delay unit 84 of the first delay circuit 38A. Further, the normal rotation delay unit 84a includes a pair of switches 98a and 98b that disconnect the normal rotation delay unit 96 from the power source V _DD and the ground G. By opening and closing the pair of switches 98a and 98b, the input unit 88a and the output unit 90a are connected or disconnected. The switches 98a and 98b open and close according to the control signal of the first timing control circuit 42A. The inversion delay unit of the first inversion delay circuit 34A also has substantially the same structure and function as the normal rotation delay unit. Therefore, the first inversion delay circuit 34A also functions as a switch circuit that turns ON / OFF the output of the first inversion delay circuit 34A.

-First gate circuit-
The first gate circuit 36A includes a first switch circuit 40A and a first timing control circuit 42A. The structure and function of the first timing control circuit 42A are substantially the same as those of the first timing control circuit 42a of the second embodiment.

  The first switch circuit 40A has substantially the same structure as the first inversion delay circuit 38A described with reference to FIG. However, the output of the normal delay part is connected to the normal output part, and the output of the reverse delay part is connected to the reverse output part. Therefore, the first switch circuit 40A functions as a switch circuit that connects or disconnects the input units 20B and / 20B of the TDC 2b and the first pulse train generation unit 6A.

(2) Second Pulse Generation Unit The second pulse generation unit 6A has substantially the same structure and function as the first pulse generation unit 4A. However, the first-stage delay circuit 44B of the second delay circuit unit 32B is not a variable delay circuit, and has substantially the same structure and delay time as the other delay circuits 38B.

(3) Switch circuit 48A, etc. The structures and functions of the switch circuit 48A, the counter circuit 8A, and the STDC 50A are substantially the same as those of the second embodiment. However, these devices process a normal signal and an inverted signal supplied from the first pulse train generator 4A and the second pulse train generator 6A.

  With the above structure, the TDC 2b, like the TDC 2a of the second embodiment, calculates the time difference between the first signal input to the first input terminal 20A and the second signal input to the second input terminal 20B. taking measurement. According to the present embodiment, the first and second pulse train generation units 4A and 6A (excluding the first and second timing control units) can be formed only by a substantially CMOS inverter circuit. Variation in delay time is reduced.

(Embodiment 4)
FIG. 29 is a configuration diagram of the TDC 2c according to the present embodiment. As shown in FIG. 29, the TDC 2c includes a first pulse train generator 4a, a second pulse train generator 6a, a counter circuit 8, and an error detector 10c.

  The structure and operation of the first pulse train generator 4a are substantially the same as those of the first pulse train generator 4a of the second embodiment. The structures and operations of the second pulse train generation unit 6a and the counter circuit 8 are also substantially the same as those of the second pulse train generation unit 6a and the counter circuit 8 of the second embodiment.

  The error detection unit 10c includes an STDC 50 and a calculation control unit 54c as in the second embodiment (see FIG. 13). However, the error detection unit 10 c does not have the switch circuit 48. The structure and operation of STDC 50 are substantially the same as STDC 50 of the second embodiment. The structure of the arithmetic control unit 54c is substantially the same as the arithmetic control unit 54 of the second embodiment. The operation of the arithmetic control unit 54c is as described below.

  FIG. 30 is a flowchart for explaining the operation of the TDC 2c. As shown in FIG. 4, the first pulse train generator 4 a starts generating the first pulse 16 that is repeated at a predetermined period T in response to the first signal 12. The counter circuit 8 starts counting the first pulse in response to the first signal 12.

Similar to the calculation control unit 54 of the second embodiment, the calculation control unit 54c sets the time t ₀ based on the count number of the counter circuit 8 when the second signal 14 is input to the first signal 12 and the second signal The time difference of the signal 14 is calculated (S82).

The time t ₀ based on the count number of the counter circuit 8 is different from the time difference Δ between the first signal 12 and the second signal 14 by the first remaining time t _over1 (see FIG. 4). The error detection unit 10c detects a time substantially equal to the first remaining time t _over1 as a fourth error. FIG. 31 is a time chart for explaining the fourth error detection procedure (S84).

As described with reference to FIG. 6, the first remaining time t _over1 is equal to the time difference t ′ _over1 between the first pulse 16 and the second pulse 26.

The arithmetic control unit 54c shifts the first pulse 16 by a predetermined shift time tf by increasing the delay time of the first stage variable delay circuit 44a of the first pulse train generation unit 4a (see FIG. 31). The arithmetic control unit 54c reads the output code D _tdc of the _STD 50 corresponding to the time difference 100 between the rising edge RE16 of the first pulse and the rising edge RE26 of the second pulse 26 every time the first pulse 16 is shifted. . The arithmetic control unit 54c determines whether the absolute value of the time difference 100 is equal to or less than half of the shift time tf based on the read output code D _tdc .

When the arithmetic control unit 54c determines that the absolute value of the time difference 100 has become half or less of the shift time tf, the arithmetic control unit 54c records the number of shifts N4 of the first pulse 16 and the output code D _tdc of the _{STDC 50 at} that time. Arithmetic control unit 54c, the time corresponding to the number N4 of the shift of the first pulse 16 (= tf × N4), is calculated as a fourth error _{t 4} (S84). The above procedure (S84) is substantially the same as the procedure of the second embodiment that detects the second error by shifting the adjacent pulse 30 described with reference to FIGS.

Furthermore, the calculation control unit 54c, similar to the third error detection procedure of the second embodiment (FIG. 25), the time difference 100 reads the output code D _tdc recorded in the memory, calculating a fifth error t ₅ (S86).

Finally, the arithmetic control unit 54c, based on the time t ₀ based on the count number, the fourth error t ₄ , and the fifth error t ₅ , calculates the time difference Δ () between the first signal 12 and the second signal 14. = T ₀ + t ₄ + t ₅ ) is calculated (S88).

  As shown in FIG. 29, the TDC 2c of the present embodiment does not have the switch circuit 48 (see FIG. 13). Therefore, according to the present embodiment, the time digital conversion device can be reduced in size.

  In the example shown in FIG. 29, the first pulse train generator 4a has only one inversion delay circuit 34a. However, the first pulse train generation unit 4a may include a plurality of inversion delay circuits (including the variable delay circuit 44a). For example, the first pulse train generation unit 4a may have only an inversion delay circuit. In such a case, the number of inversion delay circuits included in the first pulse train generation unit 4a is set to an odd number so that the pulses are repeatedly generated. The same applies to the second pulse train generator 26.

In this embodiment, in the first variable delay circuit 44a shifts the time tf longer by, and calculates the fourth error t _4. However, the variable delay circuit 44a delays time by the t _c shift time tf minute short of, may calculate the fourth error t _4. In this case, when the period of the first pulse is T, the time difference Δ between the first signal 12 and the second signal 14 is t ₀ + T−t ₄ + t ₅ .

(Embodiment 5)
FIG. 32 is a configuration diagram of the TDC 2d according to the present embodiment. As shown in FIG. 32, the structure of the TDC 2d is substantially the same as the TDC 2c of the embodiment. However, the first-stage delay circuit 44c of the third delay circuit unit 32c included in the first pulse train generation unit 4d is not a variable delay circuit, but one delay time t _c substantially equal to the other first delay circuits 38a. have. Further, the first stage delay circuit 44d of the fourth delay circuit unit 32d having a second pulse train generating unit 6d includes a shift time tf min shorter delay time than the delay time t _c of the other of the second delay circuit 38b ing.

  The operation of the TDC 2d is substantially the same as the TDC 2c of the fourth embodiment described with reference to FIG. However, the fourth error detection procedure (step 84) based on the pulse shift is different from the operation of the TDC 2c of the fourth embodiment.

FIG. 33 is a time chart for explaining a fourth error detection procedure in the present embodiment. As described above, the delay time of the first delay circuit 44d of the second pulse train generation unit 6d is shorter than the delay time of the other delay circuits of the first and second delay circuit units 4d and 6d by the shift time tf. Accordingly, the second pulse 26 is shifted by the shift time tf toward the first pulse 16. The arithmetic control unit 54c corresponds to the number of shifts N5 when the absolute value of the time difference between the rising edge RE16 of the first pulse 16 and the rising edge RE26 of the second pulse 26 is equal to or less than half of the predetermined shift time tf. calculates time (= tf × N5) as a fourth error _{t 4.} In the present embodiment, the time difference Δ between the first pulse 12 and the second pulse 14 is detected using the fourth error t ₄ .

  As shown in FIG. 32, the TDC 2d of the present embodiment does not have the switch circuit 48 (see FIG. 13). Therefore, according to the present embodiment, the time digital conversion device can be reduced in size.

  In the example of FIG. 32, the first and second pulse train generation units 4d and 6d have one inversion delay circuit. However, as in the fourth embodiment, the first and second pulse train generation units 4d and 6d may have an odd number of inversion delay circuits.

By the way, in the first to fourth embodiments, the delay time of the first variable delay circuit of the delay circuit unit included in the first pulse generation unit is increased to increase the delay time toward the adjacent pulse (or the first pulse). 2 pulses are shifted. However, as in this embodiment, the delay time of the first delay circuit of the delay circuit unit included in the second pulse generation unit is shortened, so that the second pulse is added to the adjacent pulse (or the first pulse). May be shifted toward. The second error t ₂ (or the fourth error t ₄ ) can also be detected by such a procedure.

In the above embodiment, either the adjacent pulse (or the first pulse) or the second pulse is shifted toward the other to detect the second error (or the fourth error). Yes. However, both the adjacent pulse (or the first pulse) and the second pulse may be shifted toward the other to detect the two errors (or the fourth error). In this case, the second error t ₂ (or the fourth error t ₄ ) can be detected based on the total number of shifts of both pulses.

  Regarding the above embodiment, the following additional notes are disclosed.

(Appendix 1)
In response to the first signal, a first pulse train generator that starts generating the first pulse repeated at a predetermined period;
A counter circuit that starts counting the first pulse in response to the first signal;
A stochastic time-to-digital converter having a plurality of delay flip-flops whose input terminals are connected to each other and whose clock terminals are connected to each other, the first based on the count number of the counter circuit when the second signal is input A time-to-digital conversion device that detects the time of time as a time difference between the first signal and the second signal.

(Appendix 2)
In the time digital conversion device according to attachment 1,
The first pulse train generation unit repeatedly generates a plurality of delay pulses each rising after a predetermined delay time from the first pulse,
Further, in response to a second signal, a second pulse train generation unit that starts generating a second pulse that is repeated at the predetermined period;
Of the edges of the first pulse and the delayed pulse, the time difference between one of a pair of adjacent edges adjacent to the rising edge of the second pulse and the rising edge of the first pulse is defined as a first error. Having an error detection unit to detect,
A time-to-digital conversion apparatus, wherein a second time based on the first time and the first error is detected as a time difference between the first signal and the second signal.

(Appendix 3)
In the time digital conversion device according to attachment 2,
The error detection unit shifts one or both of the adjacent pulse having one of the adjacent edges and the second pulse toward the other by a predetermined shift time, and the rising edge of the second pulse and the second pulse Detecting a second time based on the number of shifts of the adjacent pulse and the second pulse as a second error when the absolute value of the time difference from one of the adjacent edges is less than half of the predetermined shift time;
A time-to-digital conversion device, wherein a third time based on the second time and the second error is detected as a time difference between the first signal and the second signal.

(Appendix 4)
In the time digital conversion device according to attachment 3,
The error detection unit further detects a time difference between one of the adjacent edges and the rising edge of the second pulse when the absolute value is equal to or less than half of the shift time as a third error,
A time-to-digital conversion apparatus, wherein a time based on the third time and the third error is detected as a time difference between the first signal and the second signal.

(Appendix 5)
In the time digital conversion device according to any one of appendices 1 to 4,
The first pulse train generator is
A first delay circuit unit having a predetermined number of first delay circuits for outputting an input signal delayed by the predetermined time, wherein the first delay circuits are connected in cascade;
An input section is connected to the output section of the first delay circuit at the final stage of the first delay circuit unit, and inverts the input signal and outputs the input signal after delaying the predetermined delay time. A delay circuit;
The first signal is supplied to the input portion of the first delay circuit in the first stage of the first delay circuit unit, and then to the input portion of the first delay circuit in the first stage of the first delay circuit unit. And a first gate circuit for connecting the output section of the first inversion delay circuit.

(Appendix 6)
In the time digital conversion device according to any one of appendices 2 to 5,
The second pulse train generator is
A second delay circuit unit having the predetermined number of second delay circuits for outputting the input signal with a delay for the predetermined time, wherein the predetermined number of second delay circuits are connected in cascade;
An input section is connected to the output section of the second delay circuit at the final stage of the second delay circuit unit, and inverts the input signal and outputs the input signal with a delay of the predetermined delay time. A delay circuit;
The second signal is supplied to the input portion of the second delay circuit in the first stage of the second delay circuit unit, and then to the input portion of the second delay circuit in the first stage of the second delay circuit unit. And a second gate circuit connecting the output section of the second inversion delay circuit.

(Appendix 7)
In the time digital conversion device according to attachment 4,
The stochastic time digital apparatus measures a time difference between one of the adjacent edges whose absolute value is equal to or less than the shift time and a rising edge of the second pulse.

(Appendix 8)
In the time digital conversion device according to attachment 1,
Furthermore, in response to the second signal, a second pulse train generation unit that starts generating a second pulse repeated at the predetermined period;
Either or both of the first pulse and the second pulse are shifted by a predetermined shift time, and the absolute value of the time difference between the rising edge of the first pulse and the rising edge of the second pulse is An error detection unit for detecting, as a fourth error, a time based on the number of shifts of the first pulse and the second pulse when the predetermined shift time is half or less,
A time-to-digital conversion apparatus, wherein a time based on the count number and the fourth error is detected as a time difference between the first signal and the second signal.

(Appendix 9)
In the time digital conversion device according to attachment 8,
The error detection unit further detects, as a fifth error, a time difference between the rising edge of the first pulse and the rising edge of the second pulse when the absolute value becomes half or less of the shift time. ,
A time-to-digital converter characterized by detecting a time based on the count number, the fourth error, and the fifth error as a time difference between the first signal and the second signal.

2 ... TDC
4 ... 1st pulse train generation part 6 ... 2nd pulse train generation part 8 ... Counter circuit 10 ... Error detection part

Claims (6)

In response to the first signal, a first pulse train generator that starts generating the first pulse repeated at a predetermined period;
A counter circuit that starts counting the first pulse in response to the first signal;
A stochastic time digital conversion device having a plurality of delay flip-flops having input terminals connected to each other and clock terminals connected to each other, and a first signal based on a count number of the counter circuit when a second signal is input A time digital conversion device that detects time as a time difference between the first signal and the second signal. The time digital conversion apparatus according to claim 1,
The first pulse train generation unit repeatedly generates a plurality of delay pulses each rising after a predetermined delay time from the first pulse,
Further, in response to a second signal, a second pulse train generation unit that starts generating a second pulse that is repeated at the predetermined period;
Of the edges of the first pulse and the delayed pulse, the time difference between one of a pair of adjacent edges adjacent to the rising edge of the second pulse and the rising edge of the first pulse is defined as a first error. Having an error detection unit to detect,
A time-to-digital conversion apparatus, wherein a second time based on the first time and the first error is detected as a time difference between the first signal and the second signal. In the time digital conversion device according to claim 2,
The error detection unit shifts one or both of the adjacent pulse having one of the adjacent edges and the second pulse toward the other by a predetermined shift time, and the rising edge of the second pulse and the second pulse Detecting a second time based on the number of shifts of the adjacent pulse and the second pulse as a second error when the absolute value of the time difference from one of the adjacent edges is less than half of the predetermined shift time;
A time-to-digital conversion device, wherein a third time based on the second time and the second error is detected as a time difference between the first signal and the second signal. In the time digital conversion device according to claim 3,
The error detection unit further detects a time difference between one of the adjacent edges and the rising edge of the second pulse when the absolute value is equal to or less than half of the shift time as a third error,
A time-to-digital converter characterized by detecting a time based on the third time and the third error as a time difference between the first signal and the second signal. The time digital conversion apparatus according to claim 1,
Furthermore, in response to the second signal, a second pulse train generation unit that starts generating a second pulse repeated at the predetermined period;
Either or both of the first pulse and the second pulse are shifted by a predetermined shift time, and the absolute value of the time difference between the rising edge of the first pulse and the rising edge of the second pulse is An error detection unit for detecting, as a fourth error, a time based on the number of shifts of the first pulse and the second pulse when the predetermined shift time is half or less,
A time-to-digital conversion apparatus, wherein a time based on the count number and the fourth error is detected as a time difference between the first signal and the second signal. In the time digital conversion device according to claim 5,
The error detection unit further detects, as a fifth error, a time difference between the rising edge of the first pulse and the rising edge of the second pulse when the absolute value becomes half or less of the shift time. ,
A time-to-digital converter characterized by detecting a time based on the count number, the fourth error, and the fifth error as a time difference between the first signal and the second signal.

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