JP2012170327A - Multilevel inverter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilevel inverter configured to reduce at least one of the number of switching elements, the number of diodes, and the number of floating power supplies compared to a conventional multilevel inverter.SOLUTION: A multilevel inverter 1 includes inverter arms 6000 and 6001. The inverter arm 6000 is disposed between a maximum potential point and a minimum potential point, and includes a second switching element group in which switching elements 611a-614a with diodes 611b-614b connected thereto in reverse parallel are connected in series. The inverter arm 6000 includes a diode 621 for each of power supply connection points and a diode 622 for each of the power supply connection points. A connection point of connection points between the switching elements included in the second switching element group, at which the number of the switching elements disposed between them and the maximum potential point and the number of the switching elements disposed between them and the minimum potential point are equal to each other, and a U-phase output terminal 606 are connected to each other.

Description

  The present invention relates to a multilevel inverter.

  Conventionally, various types of multi-level inverters such as those disclosed in Patent Document 1 have been proposed. FIG. 25 is a circuit diagram showing a configuration of one phase (referred to as U phase) of a conventional single-phase three-level inverter.

  A component indicated by reference numerals 101 and 102 is a DC power source. The DC power source 101 has a positive pole connected to the DC voltage terminal 101a and a negative pole connected to the DC voltage terminal 102a. A voltage of 1/2 V volts is applied between the DC voltage terminal 101a and the DC voltage terminal 102a. Apply. The DC power source 102 has a positive pole connected to the DC voltage terminal 102a and a negative pole connected to the DC voltage terminal 103a. A voltage of 1/2 V volts is applied between the DC voltage terminal 102a and the DC voltage terminal 103a. Apply. As a result, DC voltages having different voltage levels are generated at the DC voltage terminals 101a to 103a, respectively.

  An inverter arm 131 is provided between the DC voltage terminals 101 a to 103 a and the U-phase output terminal 106. The inverter arm 131 has an anode connected to switching elements 111a to 114a connected in series, diodes 111b to 114b connected in antiparallel to the respective switching elements, and a DC voltage terminal 102a that is a DC voltage dividing point. And a diode 122 having a cathode connected to the DC voltage dividing point. The U-phase voltage is output from the U-phase output terminal 106 by selectively controlling the switching elements 111 a to 114 a by PWM (Pulse Width Modulation).

The diodes 111b to 114b connected in reverse parallel are turned on when the phase of the line voltage v _uw is different from the phase of the output current io.

  FIG. 26 is a circuit diagram showing a configuration of the other phase (referred to as W phase) of a conventional single-phase three-level inverter. The DC power supplies 101 and 102 are used in common with the U phase, and an inverter arm 132 is provided between the DC voltage terminals 101 a to 103 a and the W phase output terminal 107. Similarly to the U-phase inverter arm 131 described above, the inverter arm 132 includes switching elements 115a to 118a connected in series, diodes 115b to 118b connected in antiparallel to the respective switching elements, and a DC voltage division. This is composed of a diode 123 having an anode connected to the DC voltage terminal 102a, which is a point, and a diode 124 having a cathode connected to the DC voltage dividing point. Then, the W-phase voltage is output from the W-phase output terminal 107 by selectively PWM controlling the switching elements 115a to 118a.

  FIG. 27 is a circuit diagram of a conventional single-phase three-level inverter. The conventional single-phase three-level inverter of FIG. 27 is configured by combining the U-phase circuit of FIG. 25 and the W-phase circuit of FIG.

In the single-phase three-level inverter of FIG. 27, the line voltage v _uw that is a difference voltage between the U-phase voltage output from the U-phase output terminal 106 and the W-phase voltage output from the W-phase output terminal 107 is It is supplied to a load connected between the U-phase output terminal 106 and the W-phase output terminal 107.

In FIG. 27, _io is an output current. In the waveform diagram of FIG. 28, a waveform corresponding to one cycle of the line voltage v _uw is shown, and the state of the switching element is shown in the circuit diagrams of FIGS.

  29 to 32 will be specifically described. FIG. 29 shows the state of the switching element in the period from time t1 to time t2 in FIG. 28 and in the period from time t3 to time t4 in FIG. 28 when the output current io is positive in the circuit of FIG. FIG. FIG. 30 is a circuit diagram showing the state of the switching element in the period from time t2 to time t3 in FIG. 28 when the output current io is positive in the circuit in FIG. Further, FIG. 31 shows the switching element in the period from time t4 to time t5 in FIG. 28 and in the period from time t6 to time t7 in FIG. 28 when the output current io is negative in the circuit of FIG. It is a circuit diagram which shows a state. FIG. 32 is a circuit diagram showing the state of the switching element in the period from time t5 to time t6 in FIG. 28 when the output current io is negative in the circuit in FIG.

29 to 32 show states of the switching elements in the grid-connected inverter to which a load in which the line voltage v _uw and the output current i _o have the same phase is connected.

  The operation of the conventional single-phase three-level inverter of FIG. 27 will be described below.

  First, in the period from time t1 to time t4 in FIG. 28, in the U-phase inverter arm 131, the switching element 112a is turned on and the switching element 114a is turned off. Further, the switching element 111a and the switching element 113a are PWM-controlled with opposite polarities.

  On the other hand, in W-phase inverter arm 132, switching element 115a is turned off and switching element 117a is turned on. Further, the switching element 116a and the switching element 118a are PWM-controlled with opposite polarities.

By performing such switching control, the state as shown in FIG. 29 is repeated in the period from time t1 to time t2 and in the period from time t3 to time t4. Further, in the period from time t2 to time t3, the state as shown in FIG. 30 is repeated. Therefore, the line voltage v _uw has a waveform shown in the period from time t1 to time t4 in FIG.

  Next, in the period from time t4 to time t7 in FIG. 28, in the U-phase inverter arm 131, the switching element 111a is turned off and the switching element 113a is turned on. Further, the switching element 112a and the switching element 114a are PWM-controlled with opposite polarities.

  On the other hand, in W-phase inverter arm 132, switching element 116a is turned on and switching element 118a is turned off. Further, the switching element 115a and the switching element 117a are PWM-controlled with opposite polarities.

By performing such switching control, the state shown in FIG. 31 is repeated in the period from time t4 to time t5 and in the period from time t6 to time t7. Further, in the period from time t5 to time t6, the state as shown in FIG. 32 is repeated. Therefore, the line voltage v _uw has a waveform shown in the period from time t4 to time t7 in FIG.

  In this way, in the conventional single-phase three-level inverter of FIG. 27, one cycle control is performed from time t1 to time t7. When one cycle of control is completed, the process returns to time t1.

  As a conventional example related to the multilevel inverter, in addition to the multilevel inverter disclosed in Patent Document 1 and the conventional single-phase three-level inverter illustrated in FIG. A power converter is disclosed. Patent Document 3 discloses a bidirectional switch used in an inverter in which a neutral point is clamped.

Japanese Patent Laid-Open No. 5-308778 (published on November 19, 1993) JP-A-11-220886 (released on August 10, 1999) JP-T 63-502953 (announced on October 27, 1988)

  In the conventional single-phase three-level inverter of FIG. 27 (conventional multi-level inverter), the U-phase voltage output from the U-phase output terminal 106 and the W-phase voltage output from the W-phase output terminal 107 are Need to switch to level. For this reason, there exists a problem that the number of switching elements and the number of diodes increase.

  In addition, there is a problem that floating power supplies for driving the switching elements corresponding to the number between the gate and the source of the switching elements are required.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to reduce at least one of the number of switching elements, the number of diodes, and the number of floating power supplies as compared with the conventional multilevel inverter. Is to provide a multi-level inverter.

  In order to solve the above problems, a multilevel inverter according to the present invention includes a plurality of DC power supplies connected in series, a first output terminal and a second output terminal for outputting an AC voltage, A first voltage that outputs either a DC voltage applied to the highest potential point in the plurality of DC power supplies or a DC voltage applied to the lowest potential point in the plurality of DC power supplies to the first output terminal. Any of an inverter arm, a DC voltage applied to the highest potential point, a DC voltage applied to the lowest potential point, and a DC voltage applied to a power supply connection point that is a connection point between the adjacent DC power supplies Or a second inverter arm that outputs to the second output terminal, wherein the first inverter arm includes the highest potential point and the lowest electric potential. And a switching element included in the first switching element group. The switching element group includes a first switching element group in which two switching elements each having a diode connected in antiparallel are connected in series. And the first output terminal, the second inverter arm is provided between the highest potential point and the lowest potential point, and a diode is connected in antiparallel. A second switching element group including an even number of switching elements connected in series, an anode connected to the power supply connection point, and a cathode included in the second switching element group; A diode connected to the highest potential point through the same number of switching elements as the DC power source provided between the potential point and the power source connection point. For each power connection point, the cathode is connected to the power connection point, and the anode is included in the second switching element group, between the lowest potential point and the power connection point. A diode connected to the lowest potential point via the same number of switching elements as the DC power supply provided is provided for each power connection point, and the switching elements included in the second switching element group are connected to each other. A connection point where the number of switching elements provided between the highest potential point and the number of switching elements provided between the lowest potential point is the same, and the second output The terminal is connected.

  According to the above invention, the DC voltage applied to the highest potential point and the DC voltage applied to the lowest potential point by appropriately controlling on / off of the switching element of the second inverter arm. , And any one of the DC voltages applied to the power connection point can be output to the second output terminal. Further, by appropriately controlling on / off of the switching element included in the first inverter arm, any one of a DC voltage applied to the highest potential point and a DC voltage applied to the lowest potential point is selected. Can be output to the first output terminal. Thereby, it is possible to output the AC voltage.

  As an example, when the positive output current is output from the second output terminal and the voltage of the second output terminal viewed from the first output terminal is the highest potential, the highest potential is used. All the switching elements between a point and the second output terminal may be turned on, and the switching elements between the lowest potential point and the first output terminal may be turned on.

  As another example, when a negative output current is output from the second output terminal, and the voltage of the second output terminal viewed from the first output terminal is the highest potential voltage. All the switching elements included in the first switching element group may be turned off, and all the switching elements included in the second switching element group may be turned off. In this case, the diode is provided between the lowest potential point and the first output terminal and is connected between the highest potential point and the second output terminal. A negative output current can be output from the second output terminal by flowing a current through the diode connected in reverse parallel.

  Further, the first inverter arm is the same as the conventional single-phase three-level inverter described in the background section, and the inverter arm having four switching elements and six diodes is simplified. Thus, two switching elements and four diodes can be reduced. In addition, since two switching elements can be reduced, two floating power sources can be reduced accordingly.

  Therefore, it is possible to provide a multilevel inverter in which at least one of the number of switching elements, the number of diodes, and the number of floating power supplies is reduced as compared with the conventional multilevel inverter.

  For reference, in the multi-level inverter, a switching element included in the first switching element group and a signal for controlling on or off of the switching element included in the second switching element group are supplied to the switching elements. And the control means controls so that the switching elements included in the first switching element group are not simultaneously turned on, and all the switching elements included in the second switching element group are simultaneously controlled. Control is performed so as not to be turned on, and pulse width modulation control is performed on an arbitrary number of switching elements included in the second switching element group so as to maintain other switching elements on or off. And the first switching element It may be controlled to be turned on or off depending on the polarity of the output current outputted either from the second output terminal of the switching element included in.

  As a result, a pulse-width modulated voltage can be output as the AC voltage.

  In addition, the multilevel inverter can be applied to both a load that requires a positive output current and a load that requires a negative output current.

  For reference, in the multilevel inverter, the switching element included in the first switching element group and the switching element included in the second switching element group may be semiconductor switches.

  Thereby, the multilevel inverter can be configured without using a mechanical switch.

  In order to solve the above problems, a multilevel inverter according to the present invention includes a plurality of DC power supplies connected in series, a first output terminal and a second output terminal for outputting an AC voltage, and the plurality of DC power supplies. DC voltage applied to the highest potential point in the DC power supply, DC voltage applied to the lowest potential point in the plurality of DC power supplies, and a power supply connection point that is a connection point between the adjacent DC power supplies. A first inverter arm that outputs any one of the DC voltages to the first output terminal; a DC voltage applied to the highest potential point; a DC voltage applied to the lowest potential point; and the power supply connection A second inverter arm that outputs any one of the DC voltages applied to the point to the second output terminal, wherein the first inverter arm A first switching element group that is provided between the highest potential point and the lowest potential point and in which an odd number of switching elements connected in reverse parallel to each other is connected in series; Via the same number of switching elements as the DC power supply provided between the highest potential point and the power supply connection point, which is connected to the power supply connection point and the other end is included in the first switching element group. The first switching element connected to the highest potential point is provided for each power connection point, the cathode is connected to the power connection point, and the anode is included in the first switching element group. A diode connected to the lowest potential point through the same number of switching elements as the DC power supply provided between the lowest potential point and the power supply connection point, Among the connection points of the switching elements included in the first switching element group, the number of switching elements provided between the highest potential points is provided between the lowest potential points. A connection point that is one less than the number of switching elements provided on the first output terminal is connected to the first output terminal, and the second inverter arm is connected between the highest potential point and the lowest potential point. Provided with a second switching element group in which an odd number of switching elements having diodes connected in anti-parallel are connected in series, one end is connected to the power supply connection point, and the other end is Through the same number of switching elements as the DC power supply provided between the highest potential point and the power supply connection point included in the second switching element group, the highest potential point A second switching element connected to each power supply connection point; a cathode connected to the power supply connection point; and an anode included in the second switching element group; A diode connected to the lowest potential point through the same number of switching elements as the DC power supply provided between the power supply connection points is provided for each power supply connection point, and the second switching element group The number of switching elements provided between the switching elements included in the first potential point is one less than the number of switching elements provided between the lowest potential points. The point is connected to the second output terminal.

  According to the above invention, the DC voltage applied to the highest potential point and the DC voltage applied to the lowest potential point by appropriately controlling on / off of the switching element of the second inverter arm. , And any one of the DC voltages applied to the power connection point can be output to the second output terminal. Further, by appropriately controlling on / off of the switching element included in the first inverter arm, a DC voltage applied to the highest potential point, a DC voltage applied to the lowest potential point, and Any DC voltage applied to the power connection point can be output to the first output terminal. Thereby, it is possible to output the AC voltage.

  As an example, when the negative output current is output from the second output terminal and the voltage of the second output terminal viewed from the first output terminal is set to the lowest potential voltage, the highest potential is used. All the switching elements between a point and the first output terminal may be turned on, and all the switching elements between the lowest potential point and the second output terminal may be turned on.

  As another example, when a positive output current is output from the second output terminal, and the voltage of the second output terminal viewed from the first output terminal is set to the lowest potential voltage. All the switching elements included in the second inverter arm may be turned off, and all the switching elements included in the first inverter arm may be turned off. In this case, an anti-parallel connected diode provided between the lowest potential point and the second output terminal, and provided between the highest potential point and the first output terminal. A positive output current can be output from the second output terminal by flowing a current through the diode connected in reverse parallel.

  Further, in the multi-level inverter, particularly the 3-level inverter, four diodes can be reduced as compared with the conventional single-phase 3-level inverter. Although the number of switching elements is not reduced, the third switching element is included in the first switching element, the second switching element, and the first switching element group, and one end is connected to the highest potential point. When the fourth switching element included in the second switching element group and the second switching element group, one end of which is connected to the highest potential point, is constituted by a MOSFET, the source can be made common. For this reason, two systems of floating power supplies can be reduced.

  Therefore, it is possible to provide a multilevel inverter in which at least one of the number of switching elements, the number of diodes, and the number of floating power supplies is reduced as compared with the conventional multilevel inverter.

  In order to solve the above problems, the multilevel inverter of the present invention includes a plurality of DC power supplies connected in series, and a first output terminal and a second output terminal for outputting an AC voltage, DC voltage applied to the highest potential point in the plurality of DC power supplies, DC voltage applied to the lowest potential point in the plurality of DC power supplies, and a power supply connection point that is a connection point between the adjacent DC power supplies A first inverter arm that outputs any of the DC voltages to be output to the first output terminal; a DC voltage applied to the highest potential point; a DC voltage applied to the lowest potential point; and A multi-level inverter comprising: a second inverter arm that outputs any one of DC voltages applied to a power connection point to the second output terminal, wherein the first inverter And a first switching element group which is provided between the highest potential point and the lowest potential point and in which an odd number of switching elements connected in reverse parallel are connected in series, and the anode Are connected to the power supply connection point and the cathode is included in the first switching element group, and the same number of switchings as the DC power supply provided between the highest potential point and the power supply connection point. A diode connected to the highest potential point via an element is provided for each power connection point, one end is connected to the power connection point, and the other end is included in the first switching element group. The first switching element connected to the lowest potential point through the same number of switching elements as the DC power supply provided between the lowest potential point and the power supply connection point The number of switching elements provided between the switching elements included in the first switching element group and provided between the switching terminals included in the first switching element group and the highest potential point is the lowest potential point. A connection point that is one more than the number of switching elements provided between the first output terminal and the first output terminal is connected, and the second inverter arm includes the highest potential point and the lowest potential point. And a second switching element group in which an odd number of switching elements having diodes connected in antiparallel are connected in series, an anode is connected to the power supply connection point, and a cathode is The number of switching elements included in the second switching element group is the same as that of the DC power supplies provided between the highest potential point and the power supply connection point, A diode connected to the highest potential point is provided for each power supply connection point, one end is connected to the power supply connection point, and the other end is included in the second switching element group. A second switching element connected to the lowest potential point via the same number of switching elements as the DC power supply provided between the point and the power supply connection point, for each of the power supply connection points, Of the connection points of the switching elements included in the second switching element group, the number of switching elements provided between the highest potential points is equal to the number of switching elements provided between the lowest potential points. One more connection point and the second output terminal are connected.

  According to the above invention, the DC voltage applied to the highest potential point and the DC voltage applied to the lowest potential point by appropriately controlling on / off of the switching element of the second inverter arm. , And any one of the DC voltages applied to the power connection point can be output to the second output terminal. Further, by appropriately controlling on / off of the switching element included in the first inverter arm, a DC voltage applied to the highest potential point, a DC voltage applied to the lowest potential point, and Any DC voltage applied to the power connection point can be output to the first output terminal. Thereby, it is possible to output the AC voltage.

  As an example, when the negative output current is output from the second output terminal and the voltage of the second output terminal viewed from the first output terminal is set to the lowest potential voltage, the highest potential is used. All the switching elements between a point and the first output terminal may be turned on, and all the switching elements between the lowest potential point and the second output terminal may be turned on.

  As another example, when a negative output current is output from the second output terminal, and the voltage of the second output terminal viewed from the first output terminal is the highest potential voltage. All the switching elements included in the first inverter arm may be turned off, and all the switching elements included in the second inverter arm may be turned off. In this case, the diode is provided between the lowest potential point and the first output terminal and is connected between the highest potential point and the second output terminal. A negative output current can be output from the second output terminal by flowing a current through the diode connected in reverse parallel.

  Further, in the multi-level inverter, particularly the 3-level inverter, four diodes can be reduced as compared with the conventional single-phase 3-level inverter.

  Therefore, it is possible to provide a multilevel inverter in which at least one of the number of switching elements, the number of diodes, and the number of floating power supplies is reduced as compared with the conventional multilevel inverter.

  In any one of the multilevel inverters, a switching element included in the first switching element group, a switching element included in the second switching element group, the first switching element, and the first switching element Control means for outputting a signal for controlling on or off of the two switching elements to each of the switching elements, wherein the control means prevents all of the switching elements included in the first switching element group from being simultaneously turned on. And the switching elements included in the second switching element group are controlled not to be simultaneously turned on, and the switching element between the lowest potential point or the highest potential point and the first output terminal. Of any number of switching elements, up to the lowest potential point. Is a pulse width modulation control of any number of switching elements between the highest potential point and the second output terminal, and the lowest potential point among the other switching elements. Alternatively, the switching element between the highest potential point and the first and second output terminals is controlled to remain on or off, and the highest potential point or the lowest potential point and the first potential point A switching element between the output terminal, a switching element between the highest potential point or the lowest potential point and the second output terminal, the first switching element, and a second switching element, You may control to turn on or off according to the polarity of the output current output from the 2nd output terminal.

  As a result, a pulse-width modulated voltage can be output as the AC voltage.

  Furthermore, the multi-level inverter can be applied to both a load that needs to have a positive output current and a load that needs to have a negative output current.

  In any one of the multilevel inverters, a switching element included in the first switching element group, a switching element included in the second switching element group, the first switching element, and the second switching element May be a semiconductor switch.

  Thereby, the multilevel inverter can be configured without using a mechanical switch.

  In the multilevel inverter of the present invention, as described above, the first inverter arm is provided between the highest potential point and the lowest potential point, and two switching elements having diodes connected in antiparallel are connected in series. A first switching element group connected to each other, a connection point between the switching elements included in the first switching element group, and a first output terminal are connected to each other, and a second inverter arm Is provided between the highest potential point and the lowest potential point, and includes a second switching element group in which an even number of switching elements connected in reverse parallel to each other are connected in series, and an anode, A cathode is provided between the highest potential point and the power source connection point, which is connected to the power source connection point and the cathode is included in the second switching element group. A diode connected to the highest potential point via the same number of switching elements as the DC power source is provided for each power supply connection point, a cathode is connected to the power supply connection point, and an anode is connected to the second power supply point. A diode connected to the lowest potential point via the same number of switching elements as the DC power supply provided between the lowest potential point and the power supply connection point included in the switching element group Provided for each connection point, among the connection points of the switching elements included in the second switching element group, between the number of switching elements provided between the highest potential point and the lowest potential point A connection point where the number of provided switching elements is the same and a second output terminal are connected.

  In the multilevel inverter of the present invention, as described above, the first inverter arm is provided between the highest potential point and the lowest potential point, and an odd number of switching elements connected in reverse parallel are connected in series. The highest switching point and the power supply connection point, one end of which is connected to a power supply connection point and the other end is included in the first switching element group. A first switching element connected to the highest potential point via the same number of switching elements as the DC power supply provided between the power supply connection point and the cathode, The same number of switching power sources as the DC power sources provided between the lowest potential point and the power source connection point, which are connected and whose anodes are included in the first switching element group. A diode connected to the lowest potential point via an element is provided for each power supply connection point, and the connection point between the switching elements included in the first switching element group is between the highest potential point. A first output terminal is connected to a connection point in which the number of switching elements provided in the first output terminal is one less than the number of switching elements provided between the lowest potential point and the second inverter The arm is provided between the highest potential point and the lowest potential point, and includes a second switching element group in which an odd number of switching elements connected in reverse parallel to each other are connected in series, and one end of the arm The direct current connected to the power source connection point and having the other end included between the highest potential point and the power source connection point included in the second switching element group. A second switching element connected to the highest potential point via the same number of switching elements as the source is provided for each power supply connection point, a cathode is connected to the power supply connection point, and an anode is connected to the power supply connection point. A diode connected to the lowest potential point through the same number of switching elements as the DC power supply provided between the lowest potential point and the power supply connection point, included in the second switching element group, The number of switching elements provided between the switching points included in the second switching element group and provided between the switching points included in the second switching element group and the highest potential point is different from the lowest potential point. A connection point that is one less than the number of switching elements provided therebetween is connected to the second output terminal.

  Furthermore, in the multilevel inverter of the present invention, as described above, the first inverter arm is provided between the highest potential point and the lowest potential point, and an odd number of switching elements having diodes connected in antiparallel are connected in series. A first switching element group connected to the power supply connection point, an anode connected to a power supply connection point, and a cathode included in the first switching element group. And a diode connected to the highest potential point through the same number of switching elements as the DC power supply provided between each of the power supply connection points, one end is connected to the power supply connection point, and The other end includes the same number of switching elements as the DC power source provided between the lowest potential point and the power source connection point, which are included in the first switching element group. The first switching element connected to the lowest potential point is provided for each power connection point, and the highest potential point among the connection points of the switching elements included in the first switching element group A connection point where the number of switching elements provided between the first output terminal and the connection point where the number of switching elements provided between the first output terminal and the lowest potential point is one more than the number of switching elements provided between The inverter arm includes a second switching element group that is provided between the highest potential point and the lowest potential point, and in which an odd number of switching elements connected in reverse parallel are connected in series. An anode is connected to the power supply connection point, and a cathode is provided between the highest potential point and the power supply connection point included in the second switching element group. A diode connected to the highest potential point through the same number of switching elements as the DC power supply is provided for each power supply connection point, one end is connected to the power supply connection point, and the other end is connected to the first power supply point. The second switching connected to the lowest potential point through the same number of switching elements as the DC power supply provided between the lowest potential point and the power supply connection point included in the two switching element groups An element is provided for each power supply connection point, and the number of switching elements provided between the switching element included in the second switching element group and the highest potential point is the lowest potential. A connection point that is one more than the number of switching elements provided between the point and the second output terminal is connected.

  Therefore, it is possible to provide a multilevel inverter in which at least one of the number of switching elements, the number of diodes, and the number of floating power supplies is reduced as compared with the conventional multilevel inverter.

1 is a circuit diagram of a multilevel inverter according to an embodiment of the present invention. FIG. 29 is a circuit diagram showing states of switching elements in a period from time t1 to time t2 in FIG. 28 and a period from time t3 to time t4 in FIG. 28 when the output current io is positive in the circuit of FIG. is there. FIG. 29 is a circuit diagram showing a state of a switching element in a period from time t2 to time t3 in FIG. 28 when the output current io is positive in the circuit of FIG. FIG. 29 is a circuit diagram showing the state of the switching element in the period from time t4 to time t5 in FIG. 28 and in the period from time t6 to time t7 in FIG. 28 when the output current io is negative in the circuit of FIG. is there. FIG. 29 is a circuit diagram showing a state of a switching element in a period from time t5 to time t6 in FIG. 28 when the output current io is negative in the circuit of FIG. FIG. 29 is a circuit diagram showing states of switching elements in a period from time t1 to time t2 in FIG. 28 and a period from time t3 to time t4 in FIG. 28 when the output current io is negative in the circuit of FIG. is there. FIG. 29 is a circuit diagram showing a state of a switching element in a period from time t2 to time t3 in FIG. 28 when the output current io is negative in the circuit of FIG. FIG. 29 is a circuit diagram showing states of switching elements in a period from time t4 to time t5 in FIG. 28 and a period from time t6 to time t7 in FIG. 28 when the output current io is positive in the circuit of FIG. is there. FIG. 29 is a circuit diagram showing a state of a switching element in a period from time t5 to time t6 in FIG. 28 when the output current io is positive in the circuit of FIG. It is a circuit diagram of the multilevel inverter which concerns on the other Example of this invention. When the output current io is positive in the circuit of FIG. 10, it is a circuit diagram showing the state of the switching element in the period from time t1 to time t2 in FIG. 28 and in the period from time t3 to time t4 in FIG. . When the output current io is negative in the circuit of FIG. 10, it is a circuit diagram showing the state of the switching element in the period from time t1 to time t2 in FIG. 28 and in the period from time t3 to time t4 in FIG. . FIG. 29 is a circuit diagram showing a state of a switching element in a period from time t2 to time t3 in FIG. 28 when the output current io is positive in the circuit of FIG. FIG. 29 is a circuit diagram showing a state of a switching element in a period from time t2 to time t3 in FIG. 28 when the output current io is negative in the circuit of FIG. When the output current io is negative in the circuit of FIG. 10, it is a circuit diagram showing the state of the switching element in the period from time t4 to time t5 in FIG. 28 and in the period from time t6 to time t7 in FIG. . When the output current io is positive in the circuit of FIG. 10, it is a circuit diagram showing the state of the switching element in the period from time t4 to time t5 in FIG. 28 and in the period from time t6 to time t7 in FIG. . FIG. 29 is a circuit diagram illustrating a state of a switching element in a period from time t5 to time t6 in FIG. 28 when the output current io is negative in the circuit of FIG. FIG. 29 is a circuit diagram showing a state of a switching element in a period from time t5 to time t6 in FIG. 28 when the output current io is positive in the circuit of FIG. FIG. 11 is a circuit diagram of a multi-level inverter in which a high side and a low side of U-phase and W-phase inverter arms in the multi-level inverter of FIG. FIG. 11 is a circuit diagram of a three-phase three-level inverter in which a V-phase inverter arm having the same configuration as the U-phase and W-phase inverter arms is added in the multi-level inverter 2 of FIG. 10. It is a figure which shows the case where MOSFET is used as a switching element in the Example of this invention and the other Example of this invention. It is a figure which shows the case where IGBT is used as a switching element in the Example of this invention and the other Example of this invention. It is a circuit diagram which shows the inverter arm of patent document 2 applied instead of the inverter arm of FIG. It is a circuit diagram of the 4 level inverter which concerns on embodiment of this invention. It is a circuit diagram which shows the structure of one phase (U phase) of the conventional single phase 3 level inverter. It is a circuit diagram which shows the structure of the other phase (W phase) of the conventional single phase 3 level inverter. It is a circuit diagram of the conventional single phase 3 level inverter. It is a wave form diagram which shows the waveform for line voltage 1 period. 27 is a circuit diagram showing the state of the switching element in the period from time t1 to time t2 in FIG. 28 and in the period from time t3 to time t4 in FIG. 28 when the output current io is positive in the circuit of FIG. is there. FIG. 29 is a circuit diagram showing a state of a switching element in a period from time t2 to time t3 in FIG. 28 when the output current io is positive in the circuit of FIG. 27 is a circuit diagram showing the state of the switching element in the period from time t4 to time t5 in FIG. 28 and in the period from time t6 to time t7 in FIG. 28 when the output current io is negative in the circuit of FIG. is there. FIG. 29 is a circuit diagram showing a state of a switching element in a period from time t5 to time t6 in FIG. 28 when the output current io is negative in the circuit of FIG.

  An embodiment of the present invention will be described below with reference to FIGS. First, an embodiment of the present invention will be described with reference to FIGS. 1 to 9 and FIG.

[Example 1]
FIG. 1 is a circuit diagram of a multilevel inverter 1 according to the first embodiment.

In the multilevel inverter 1 of FIG. 1, a line voltage v _uw (AC voltage) that is a difference voltage between the U-phase voltage output from the U-phase output terminal 606 and the W-phase voltage output from the W-phase output terminal 607. ) Is supplied to a load connected between the U-phase output terminal 606 and the W-phase output terminal 607. In FIG. 1, i _o is an output current.

  The multi-level inverter 1 generally includes DC power supplies 601, 602 (plural DC power supplies), an inverter arm 6000 (second inverter arm), and an inverter arm 6001 (first inverter arm). Yes.

  The DC power supply 601 has a positive pole connected to the DC voltage terminal 601a and a negative pole connected to the DC voltage terminal 602a. A voltage of 1/2 V volts is applied between the DC voltage terminal 601a and the DC voltage terminal 602a. Apply. The DC power source 602 has a positive pole connected to the DC voltage terminal 602a and a negative pole connected to the DC voltage terminal 603a, and between the DC voltage terminal 602a and the DC voltage terminal 603a. Apply a voltage of 1 / 2V volts. As a result, DC voltages having different voltage levels are generated at the DC voltage terminals 601a to 603a, respectively.

  An inverter arm 6000 is provided between the DC voltage terminals 601a to 603a and the U-phase output terminal 606 (second output terminal). The inverter arm 6000 includes switching elements 611a to 614a (even number of switching elements) connected in series, diodes 611b to 614b connected in antiparallel to the respective switching elements, and a DC voltage that is a DC voltage dividing point. It has a diode 621 whose anode is connected to the terminal 602a and a diode 622 whose cathode is connected to the DC voltage dividing point. Then, two switching elements 611a to 614a are selected and controlled by PWM (Pulse Width Modulation), and the other two switching elements are turned on / off, so that the U-phase output terminal 606 Phase voltage is output.

  An inverter arm 6001 is provided between the DC voltage terminals 601a and 603a and the W-phase output terminal 607 (first output terminal). The inverter arm 6001 includes switching elements 615a and 616a connected in series, and diodes 615b and 616b connected in antiparallel to the respective switching elements. The W-phase output terminal 607 is controlled by controlling on / off of the switching elements 615a and 616a according to the direction of the output current io output from the inverter (whether the output current io is positive or negative). Outputs a W-phase voltage.

  In the multilevel inverter 1 of FIG. 1, the DC voltage terminal 601a is connected to one end of the switching element 611a, the cathode of the diode 611b, one end of the switching element 615a, and the cathode of the diode 615b.

  The other end of the switching element 611a, the anode of the diode 611b, the one end of the switching element 612a, the cathode of the diode 612b, and the cathode of the diode 621 are connected to each other.

  The other end of the switching element 612a, the anode of the diode 612b, one end of the switching element 613a, the cathode of the diode 613b, and the U-phase output terminal 606 are connected to each other.

  The other end of the switching element 615a, the anode of the diode 615b, one end of the switching element 616a, the cathode of the diode 616b, and the W-phase output terminal 607 are connected to each other.

  The other end of the switching element 613a, the anode of the diode 613b, the one end of the switching element 614a, the cathode of the diode 614b, and the anode of the diode 622 are connected to each other.

  The anode of the diode 621, the cathode of the diode 622, and the DC voltage terminal 602a are connected to each other.

  The other end of the switching element 614a, the anode of the diode 614b, the other end of the switching element 616a, the anode of the diode 616b, and the DC voltage terminal 603a are connected to each other.

  The state in which the switching element and the diode are connected in antiparallel indicates the following state. That is, one end of the switch and the cathode of the diode are connected, and the other end of the switch and the anode of the diode are connected, and when the switch is turned on, current flows from one end of the switch to the other end of the switch. However, the diode does not conduct.

  In the multilevel inverter 1 according to the first embodiment shown in FIG. 1, the inverter arm 6001 has the conventional single-phase three-level inverter described in the background section, and includes four switching elements and six diodes. This is a simplified inverter arm 132 having two. Therefore, in the multilevel inverter 1 of the first embodiment shown in FIG. 1, two switching elements and four diodes can be reduced compared to the conventional single-phase three-level inverter shown in FIG. In addition, since two switching elements can be reduced, two floating power sources can be reduced accordingly.

  Accordingly, a multi-level (single-phase three-level) inverter is provided in which at least one of the number of switching elements, the number of diodes, and the number of floating power supplies is reduced as compared with the conventional single-phase three-level inverter (FIG. 27). Can do.

(Load where line voltage v _uw and output current i _o are in phase)
2 to 5 are circuit diagrams showing states of switching elements in the multilevel inverter 1 of FIG. More specifically, FIGS. 2 to 5 show a case where the line voltage v _uw and the output current i _o have the same phase (for example, the present invention is applied to a grid-connected inverter and this is connected to the grid-connected inverter. It is a circuit diagram which shows the state of the switching element in the case of making it drive | operate. The waveform for one cycle of the line voltage v _uw is shown in the waveform diagram of FIG. 28 as in the conventional example.

  The grid interconnection inverter is an inverter that is connected to a commercial system and supplies AC power, and the commercial system is a load.

  2 to 5 will be specifically described. FIG. 2 shows the state of the switching element in the period from time t1 to time t2 in FIG. 28 and in the period from time t3 to time t4 in FIG. 28 when the output current io is positive in the circuit of FIG. FIG. FIG. 3 is a circuit diagram showing the state of the switching element in the period from time t2 to time t3 in FIG. 28 when the output current io is positive in the circuit of FIG. Further, FIG. 4 shows the switching element in the period from time t4 to time t5 in FIG. 28 and in the period from time t6 to time t7 in FIG. 28 when the output current io is negative in the circuit of FIG. It is a circuit diagram which shows a state. FIG. 5 is a circuit diagram showing the state of the switching element in the period from time t5 to time t6 in FIG. 28 when the output current io is negative in the circuit of FIG.

  First, in the period from time t1 to time t2 in FIG. 28 and in the period from time t3 to time t4 in FIG. 28, switching element 611a is turned off and switching element 614a is turned off in U-phase inverter arm 6000. . In addition, the switching element 612a and the switching element 613a are PWM-controlled with the same polarity. When PWM control is performed with the same polarity, when one switching element is turned on, the other switching element is also turned on. The same applies to the off state.

  On the other hand, in W-phase inverter arm 6001, switching element 615a is turned off and switching element 616a is turned on.

By performing such switching control, the state as shown in FIG. 2 is repeated. Therefore, the line voltage v _uw has a waveform shown in the period from time t1 to time t2 in FIG. 28 and in the period from time t3 to time t4 in FIG. When the line voltage v _uw is 0, the diodes 613b and 614b connected in antiparallel are turned on.

  Next, in the period from time t2 to time t3 in FIG. 28, in the U-phase inverter arm 6000, the switching element 612a is turned on and the switching element 614a is turned off. Further, the switching element 611a and the switching element 613a are subjected to PWM control with opposite polarities. When PWM control is performed with opposite polarities, when one switching element is turned on, the other switching element is turned off.

  On the other hand, in W-phase inverter arm 6001, switching element 615a is turned off and switching element 616a is turned on.

By performing such switching control, the state as shown in FIG. 3 is repeated. Therefore, the line voltage v _uw has a waveform shown in the period from time t2 to time t3 in FIG.

  Further, in the period from time t4 to time t5 in FIG. 28 and in the period from time t6 to time t7 in FIG. 28, switching element 611a is turned off and switching element 614a is turned off in U-phase inverter arm 6000. . In addition, the switching element 612a and the switching element 613a are PWM-controlled with the same polarity.

  On the other hand, in W-phase inverter arm 6001, switching element 615a is turned on and switching element 616a is turned off.

By performing such switching control, the state as shown in FIG. 4 is repeated. Therefore, the line voltage v _uw has a waveform shown in the period from time t4 to time t5 in FIG. 28 and in the period from time t6 to time t7 in FIG. When the line voltage v _uw is 0, the diodes 611b and 612b connected in antiparallel are turned on.

  In the period from time t5 to time t6 in FIG. 28, in the U-phase inverter arm 6000, the switching element 611a is turned off and the switching element 613a is turned on. Further, the switching element 612a and the switching element 614a are PWM-controlled with opposite polarities.

  On the other hand, in W-phase inverter arm 6001, switching element 615a is turned on and switching element 616a is turned off.

By performing such switching control, the state as shown in FIG. 5 is repeated. Therefore, the line voltage v _uw has a waveform shown in the period from time t5 to time t6 in FIG.

  In this manner, in the multilevel inverter 1 of FIG. 1, one cycle of control is performed from time t1 to time t7. When one cycle of control is completed, the process returns to time t1.

(Loads in which the phase of the line voltage v _{uw and} the phase of the output current i _o are different)
6 to 9 show a case where the phase of the line voltage v _{uw and} the phase of the output current i _o are different (for example, the present invention is applied to a grid-connected inverter, which is operated independently, and the load is reduced to L It is a circuit diagram which shows the state of the switching element when it is set as a load (system interconnection inverter self-sustained operation L load, mentioned later).

  Here, the operation state of the grid interconnection inverter will be described. There are basically two operation states in the grid interconnection inverter, that is, interconnection operation and independent operation. The interconnection operation is an operation of “connecting to a commercial system and supplying AC power”. On the other hand, the self-sustained operation is an operation in which AC power is supplied to various loads that are not connected to a commercial system and are not a commercial system. A state in which the load connected during the self-sustained operation is an L load such as a motor is referred to as a “system-connected inverter self-sustained operation L load” as described above.

  In the following description, FIGS. 6 to 9 will be described in detail. FIG. 6 shows the state of the switching element in the period from time t1 to time t2 in FIG. 28 and in the period from time t3 to time t4 in FIG. 28 when the output current io is negative in the circuit of FIG. FIG. FIG. 7 is a circuit diagram showing the state of the switching element in the period from time t2 to time t3 in FIG. 28 when the output current io is negative in the circuit of FIG. Further, FIG. 8 shows the switching element in the period from time t4 to time t5 in FIG. 28 and in the period from time t6 to time t7 in FIG. 28 when the output current io is positive in the circuit of FIG. It is a circuit diagram which shows a state. FIG. 9 is a circuit diagram showing the state of the switching element in the period from time t5 to time t6 in FIG. 28 when the output current io is positive in the circuit of FIG.

  First, in the period from time t1 to time t2 in FIG. 28 and the period from time t3 to time t4 in FIG. 28, the output current io is positive. In this case, in the multilevel inverter 1, FIG. Each switch may be turned on and off as shown in FIG.

  On the other hand, in the period from time t1 to time t2 in FIG. 28 and in the period from time t3 to time t4 in FIG. 28, in the U-phase inverter arm 6000, the switching element 611a is turned on when the output current io is negative. The switching element 613a is turned on. Further, the switching element 612a and the switching element 614a are PWM-controlled with opposite polarities. On the other hand, in W-phase inverter arm 6001, switching element 615a is turned off and switching element 616a is turned off.

By performing such switching control, the state as shown in FIG. 6 is repeated. Therefore, the line voltage v _uw has a waveform shown in the period from time t1 to time t2 in FIG. 28 and in the period from time t3 to time t4 in FIG. 28 in a state where the output current io is negative. In the state shown in FIG. 6, the diode 616b connected in anti-parallel is conductive.

  Next, in the period from time t2 to time t3 in FIG. 28, the output current io is positive. In this case, in the multilevel inverter 1, each switch may be turned on / off as shown in FIG. .

  On the other hand, in the period from time t2 to time t3 in FIG. 28, when the output current io is negative, the U-phase inverter arm 6000 turns off the switching element 611a and turns off the switching element 614a. In addition, the switching element 612a and the switching element 613a are PWM-controlled with the same polarity. On the other hand, in W-phase inverter arm 6001, switching element 615a is turned off and switching element 616a is turned off.

By performing such switching control, the state as shown in FIG. 7 is repeated. Therefore, the line voltage v _uw has a waveform shown in the period from time t2 to time t3 in FIG. 28 when the output current io is negative. In the state shown in FIG. 7, the diode 616b connected in anti-parallel is conductive. Further, when the line voltage v _uw is V, the diodes 611b and 612b connected in antiparallel are turned on.

  Next, in the period from time t4 to time t5 in FIG. 28 and in the period from time t6 to time t7 in FIG. 28, the output current io is negative. Each switch may be turned on and off as shown in FIG.

  On the other hand, in the period from time t4 to time t5 in FIG. 28 and in the period from time t6 to time t7 in FIG. 28, in the U-phase inverter arm 6000, the switching element 612a is turned on when the output current io is positive. Turns on and turns off the switching element 614a. Further, the switching element 611a and the switching element 613a are subjected to PWM control with opposite polarities. On the other hand, in W-phase inverter arm 6001, switching element 615a is turned off and switching element 616a is turned off.

By performing such switching control, the state as shown in FIG. 8 is repeated. Therefore, the line voltage v _uw has a waveform shown in the period from time t4 to time t5 in FIG. 28 and in the period from time t6 to time t7 in FIG. 28 when the output current io is positive. In the state shown in FIG. 8, the diode 615b connected in anti-parallel is conducted.

  Next, in the period from time t5 to time t6 in FIG. 28, the output current io is negative. In this case, in the multilevel inverter 1, each switch may be turned on / off as shown in FIG. .

  On the other hand, when the output current io is positive in the period from time t5 to time t6 in FIG. 28, in the U-phase inverter arm 6000, the switching element 611a is turned off and the switching element 614a is turned off. In addition, the switching element 612a and the switching element 613a are PWM-controlled with the same polarity. On the other hand, in W-phase inverter arm 6001, switching element 615a is turned off and switching element 616a is turned off.

By performing such switching control, the state as shown in FIG. 9 is repeated. Therefore, the line voltage v _uw has a waveform shown in the period from time t5 to time t6 in FIG. 28 when the output current io is positive. In the state shown in FIG. 9, the diode 615b connected in antiparallel is conductive. Further, when the line voltage v _uw is −V, the diodes 613b and 614b connected in antiparallel are turned on.

  In this manner, in the multilevel inverter 1 of FIG. 1, one cycle of control is performed from time t1 to time t7. When one cycle of control is completed, the process returns to time t1.

As described above, according to the multilevel inverter 1 according to the first embodiment, the DC voltage applied to the highest potential point by appropriately controlling on / off of the switching element included in the inverter arm 6000, Either a DC voltage applied to the lowest potential point or a DC voltage applied to the power supply connection point can be output to the U-phase output terminal 606. In addition, by appropriately controlling on / off of the switching element included in the inverter arm 6001, either the DC voltage applied to the highest potential point or the DC voltage applied to the lowest potential point, It can be output to the W-phase output terminal 607. As a result, the line voltage v _uw can be output.

  In the multilevel inverter 1, the switching elements 615a and 616a included in the first switching element group and the signals for controlling the on / off of the switching elements 611a to 614a included in the second switching element group are respectively switched. A control circuit 50 (control means) for outputting to the elements is further provided. The control circuit 50 controls the switching elements 615a and 616a included in the first switching element group so as not to be turned on at the same time. While controlling so that all the switching elements 611a-614a contained may not be turned on simultaneously, you may perform switching control shown in FIGS. That is, the control circuit 50 performs pulse width modulation control on an arbitrary number of switching elements included in the second switching element group, and maintains other switching elements on or off. And any one of the switching elements included in the first switching element group may be controlled to be turned on or off according to the polarity of the output current output from the second output terminal. .

As a result, a pulse width modulated voltage can be output as the line voltage v _uw .

  Further, the multilevel inverter 1 can be applied to both a load where the output current io needs to be positive and a load where the output current io needs to be negative.

  As a modification of the first embodiment, instead of the inverter arm 6000 shown in FIG. 1, the inverter arm 6000 'shown in FIG. 23 shown in FIG. 23 can be applied. Due to the effect of the invention according to Patent Document 2, the number of diodes and floating power supplies is further reduced.

[Example 2]
The following will describe another embodiment of the present invention with reference to FIGS. The configuration other than that described in the second embodiment is the same as that of the first embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of the first embodiment are given the same reference numerals, and explanation thereof is omitted.

  FIG. 10 is a circuit diagram of the multilevel inverter 2 according to the second embodiment.

In the multilevel inverter 2 of FIG. 10, the line voltage v _uw , which is the difference between the U-phase voltage output from the U-phase output terminal 906 and the W-phase voltage output from the W-phase output terminal 907, is It is supplied to a load connected between the phase output terminal 906 and the W-phase output terminal 907. In FIG. 10, i _o is an output current. Further, the waveform for one cycle of the line voltage v _uw is shown in the waveform diagram of FIG. 28 as in the conventional example.
The multi-level inverter 2 generally includes DC power sources 901 and 902 (a plurality of DC power sources), an inverter arm 9000 (second inverter arm), and an inverter arm 9001 (first inverter arm). Yes.

  The DC power supply 901 has a positive pole connected to the DC voltage terminal 901a and a negative pole connected to the DC voltage terminal 902a. A voltage of 1/2 V volts is applied between the DC voltage terminal 901a and the DC voltage terminal 902a. Apply. The DC power source 902 has a positive pole connected to the DC voltage terminal 902a, a negative pole connected to the DC voltage terminal 903a, and between the DC voltage terminal 902a and the DC voltage terminal 903a. Apply a voltage of 1 / 2V volts. As a result, DC voltages having different voltage levels are generated at the DC voltage terminals 901a to 903a, respectively.

An inverter arm 9000 is provided between the DC voltage terminals 901a to 903a and the U-phase output terminal 906 (second output terminal). The inverter arm 9000 includes switching elements 911a to 913a (second switching element group) connected in series, diodes 911b to 913b connected in antiparallel to the respective switching elements, and a DC that is a DC voltage dividing point. A switching element 931 (second switching element) having one end connected to the voltage terminal 902a and a diode 921 having a cathode connected to the DC voltage dividing point are provided. Then, the on-off switching element 911a, 931, and controlled in accordance with the direction of the output current _{i o} of the multilevel inverter 2 (or the output current io is positive or negative), the switching element 912a, the 913a A U-phase voltage is output from the U-phase output terminal 906 by selectively performing PWM control.

An inverter arm 9001 is provided between the DC voltage terminals 901a to 903a and the W-phase output terminal 907 (first output terminal). The inverter arm 9001 includes switching elements 914a to 916a (first switching element group) connected in series, diodes 914b to 916b connected in antiparallel to the respective switching elements, and direct current that is a direct current dividing point. A switching element 932 (first switching element) having one end connected to the voltage terminal 902a and a diode 922 having a cathode connected to the DC voltage dividing point are included. Then, the on-off switching element 914a, 932, and controlled in accordance with the direction of the output current _{i o} of the multilevel inverter 2, a switching element 915a, by selectively PWM control 916a, W-phase output terminal 907 Outputs a W-phase voltage.

  In the multilevel inverter 2 of FIG. 10, the DC voltage terminal 901a is connected to one end of the switching element 911a, the cathode of the diode 911b, one end of the switching element 914a, and the cathode of the diode 914b.

  The other end of the switching element 911a, the anode of the diode 911b, one end of the switching element 912a, the cathode of the diode 912b, the other end of the switching element 931, and the U-phase output terminal 906 are connected to each other.

  The other end of the switching element 912a, the anode of the diode 912b, the one end of the switching element 913a, the cathode of the diode 913b, and the anode of the diode 921 are connected to each other.

  The other end of the switching element 914a, the anode of the diode 914b, one end of the switching element 915a, the cathode of the diode 915b, the other end of the switching element 932, and the W-phase output terminal 907 are connected to each other.

  The other end of the switching element 915a, the anode of the diode 915b, the one end of the switching element 916a, the cathode of the diode 916b, and the anode of the diode 922 are connected to each other.

  One end of the switching element 931, the cathode of the diode 921, the one end of the switching element 932, the cathode of the diode 922, and the DC voltage terminal 902a are connected to each other.

  The other end of the switching element 913a, the anode of the diode 913b, the other end of the switching element 916a, the anode of the diode 916b, and the DC voltage terminal 903a are connected to each other.

  In the multilevel inverter 2 of the second embodiment shown in FIG. 10, four diodes can be reduced compared to the conventional single-phase three-level inverter shown in FIG. Although the number of switching elements is not reduced, the sources of switching elements 911a and 931 and switching elements 914a and 932 in FIG. For this reason, two systems of floating power supplies can be reduced.

  Accordingly, a multi-level (single-phase three-level) inverter is provided in which at least one of the number of switching elements, the number of diodes, and the number of floating power supplies is reduced as compared with the conventional single-phase three-level inverter (FIG. 27). Can do.

  11 to 18 are circuit diagrams showing states of switching elements in the multilevel inverter 2 of FIG.

  11 to 18 will be specifically described. FIG. 11 shows the state of the switching element in the period from time t1 to time t2 in FIG. 28 and in the period from time t3 to time t4 in FIG. 28 when the output current io is positive in the circuit of FIG. It is a circuit diagram. 12 shows the state of the switching element in the period from time t1 to time t2 in FIG. 28 and in the period from time t3 to time t4 in FIG. 28 when the output current io is negative in the circuit of FIG. FIG. Further, FIG. 13 is a circuit diagram showing the state of the switching element in the period from time t2 to time t3 in FIG. 28 when the output current io is positive in the circuit of FIG. Further, FIG. 14 is a circuit diagram showing the state of the switching element in the period from time t2 to time t3 in FIG. 28 when the output current io is negative in the circuit of FIG. Further, FIG. 15 shows the state of the switching element in the period from time t4 to time t5 in FIG. 28 and in the period from time t6 to time t7 in FIG. 28 when the output current io is negative in the circuit of FIG. FIG. Further, FIG. 16 shows the state of the switching element in the period from time t4 to time t5 in FIG. 28 and in the period from time t6 to time t7 in FIG. 28 when the output current io is positive in the circuit of FIG. FIG. Further, FIG. 17 is a circuit diagram showing the state of the switching element in the period from time t5 to time t6 in FIG. 28 when the output current io is negative in the circuit of FIG. FIG. 18 is a circuit diagram showing the state of the switching element during the period from time t5 to time t6 in FIG. 28 when the output current io is positive in the circuit of FIG.

  First, in the period from time t1 to time t2 in FIG. 28 and in the period from time t3 to time t4 in FIG. 28, in the U-phase inverter arm 9000, the switching element 911a Turns on, turns off the switching element 912a, turns off the switching element 913a, and turns off the switching element 931. On the other hand, in the W-phase inverter arm 9001, the switching element 914a is turned off, the switching element 916a is turned off, and the switching element 932 is turned off. Further, the switching element 915a is PWM-controlled.

By performing such switching control, the state as shown in FIG. 11 is repeated. Therefore, the line voltage v _uw has a waveform shown in the period from time t1 to time t2 in FIG. 28 and in the period from time t3 to time t4 in FIG. 28 with the output current io being positive. When the line voltage v _uw is 0, the diode 914b connected in antiparallel is conducted.

  On the other hand, in the period from time t1 to time t2 in FIG. 28 and in the period from time t3 to time t4 in FIG. 28, in the U-phase inverter arm 9000, the switching element 911a is turned on when the output current io is negative. It is turned off, the switching element 913a is turned off, and the switching element 931 is turned off. Further, the switching element 912a is PWM-controlled. On the other hand, in the W-phase inverter arm 9001, the switching element 914a is turned off, the switching element 915a is turned off, the switching element 916a is turned off, and the switching element 932 is turned on.

By performing such switching control, the state as shown in FIG. 12 is repeated. Therefore, the line voltage v _uw has a waveform shown in the period from time t1 to time t2 in FIG. 28 and in the period from time t3 to time t4 in FIG. 28 in a state where the output current io is negative. When the line voltage v _uw is 1 / 2V, the diode 911b connected in antiparallel is turned on.

  Next, in the period from time t2 to time t3 in FIG. 28, when the output current io is positive, in the U-phase inverter arm 9000, the switching element 911a is turned on, the switching element 912a is turned off, and the switching element 913a is turned on. Is turned off, and the switching element 931 is turned off. On the other hand, in the W-phase inverter arm 9001, the switching element 914a is turned off, the switching element 915a is turned on, and the switching element 932 is turned off. Further, the switching element 916a is PWM-controlled.

By performing such switching control, the state as shown in FIG. 13 is repeated. Therefore, the line voltage v _uw has a waveform shown in the period from time t2 to time t3 in FIG. 28 when the output current io is positive.

  On the other hand, when the output current io is negative during the period from time t2 to time t3 in FIG. 28, in the U-phase inverter arm 9000, the switching element 911a is turned off, the switching element 913a is turned off, and the switching element 931 is turned off. Turn off. Further, the switching element 912a is PWM-controlled. On the other hand, in the W-phase inverter arm 9001, the switching element 914a is turned off, the switching element 915a is turned off, the switching element 916a is turned off, and the switching element 932 is turned off.

By performing such switching control, the state as shown in FIG. 14 is repeated. Therefore, the line voltage v _uw has a waveform shown in the period from time t2 to time t3 in FIG. 28 when the output current io is negative. In the state shown in FIG. 14, the diodes 915b and 916b connected in anti-parallel are conducted. When the line voltage v _uw is V, the diode 911b connected in antiparallel is conducted.

  Next, when the output current io is negative in the period from time t4 to time t5 in FIG. 28 and in the period from time t6 to time t7 in FIG. 28, the switching element 911a is used in the U-phase inverter arm 9000. Is turned off, the switching element 913a is turned off, and the switching element 931 is turned off. Further, the switching element 912a is PWM-controlled. On the other hand, in the W-phase inverter arm 9001, the switching element 914a is turned on, the switching element 915a is turned off, the switching element 916a is turned off, and the switching element 932 is turned off.

By performing such switching control, the state as shown in FIG. 15 is repeated. Therefore, the line voltage v _uw has a waveform shown in the period from time t4 to time t5 in FIG. 28 and in the period from time t6 to time t7 in FIG. 28 in a state where the output current io is negative. When the line voltage v _uw is 0, the diode 911b connected in antiparallel is conducted.

  On the other hand, when the output current io is positive in the period from time t4 to time t5 in FIG. 28 and in the period from time t6 to time t7 in FIG. 28, in the U-phase inverter arm 9000, the switching element 911a is It is turned off, the switching element 912a is turned off, the switching element 913a is turned off, and the switching element 931 is turned on. On the other hand, in the W-phase inverter arm 9001, the switching element 914a is turned off, the switching element 916a is turned off, and the switching element 932 is turned off. Further, the switching element 915a is PWM-controlled.

By performing such switching control, the state as shown in FIG. 16 is repeated. Therefore, the line voltage v _uw has a waveform shown in the period from time t4 to time t5 in FIG. 28 and in the period from time t6 to time t7 in FIG. 28 when the output current io is positive. When the line voltage v _uw is _−1/2 V, the diode 914 b connected in antiparallel is turned on.

  Next, in the period from time t5 to time t6 in FIG. 28, when the output current io is negative, in the U-phase inverter arm 9000, the switching element 911a is turned off, the switching element 912a is turned on, and the switching element 931 is turned on. Turn off. Further, the switching element 913a is PWM-controlled. On the other hand, in the W-phase inverter arm 9001, the switching element 914a is turned on, the switching element 915a is turned off, the switching element 916a is turned off, and the switching element 932 is turned off.

By performing such switching control, the state as shown in FIG. 17 is repeated. Therefore, the line voltage v _uw has a waveform shown in the period from time t5 to time t6 in FIG. 28 when the output current io is negative.

  On the other hand, in the period from time t5 to time t6 in FIG. 28, when the output current io is positive, in the U-phase inverter arm 9000, the switching element 911a is turned off, the switching element 912a is turned off, and the switching element 913a is turned on. The switching element 931 is turned off. On the other hand, in the W-phase inverter arm 9001, the switching element 914a is turned off, the switching element 916a is turned off, and the switching element 932 is turned off. Further, the switching element 915a is PWM-controlled.

By performing such switching control, the state as shown in FIG. 18 is repeated. Therefore, the line voltage v _uw has a waveform shown in the period from time t5 to time t6 in FIG. 28 when the output current io is positive. In the state shown in FIG. 18, the diodes 912b and 913b connected in antiparallel are turned on. When the line voltage v _uw is −V, the diode 914b connected in antiparallel is turned on.

  In this way, in the multilevel inverter 2 of FIG. 10, one cycle of control is performed from time t1 to time t7. When one cycle of control is completed, the process returns to time t1.

As described above, according to the multilevel inverter 2 according to the second embodiment, the DC voltage applied to the highest potential point by appropriately controlling on / off of the switching element of the inverter arm 9000, Either a DC voltage applied to the lowest potential point or a DC voltage applied to the power supply connection point can be output to the U-phase output terminal 906. In addition, the DC voltage applied to the highest potential point, the DC voltage applied to the lowest potential point, and the power supply connection point can be controlled by appropriately controlling on / off of the switching element included in the inverter arm 9001. Any of the DC voltages applied to can be output to the W-phase output terminal 907. As a result, the line voltage v _uw can be output.

  In the multilevel inverter 2, a signal for controlling on or off of the switching elements 914a, 915a, 916a included in the first switching element group and the switching elements 911a, 912a, 913a included in the second switching element group is provided. The control circuit 50 further includes a control circuit 50 (control means) that outputs to each switching element, and the control circuit 50 controls the switching elements 914a, 915a, and 916a included in the first switching element group not to be turned on at the same time, The switching elements 911a, 912a, and 913a included in the second switching element group may be controlled not to be turned on at the same time, and the switching control illustrated in FIGS. That is, the control circuit 50 includes any number of switching elements between the lowest potential point 903a and the W-phase output terminal 907, and between the lowest potential point 903a and the U-phase output terminal 906. Any of a number of switching elements is subjected to pulse width modulation control, and among the other switching elements, the lowest potential point 901a, the W-phase output terminal 907, and the U-phase output terminal 906 A switching element between the highest potential point 901a and the W-phase output terminal 907, and the switching element between the highest potential point 901a and the U-phase output terminal 906. Output from the U-phase output terminal 906, the first switching element 932 and the second switching element 931. Depending on the polarity of the output current io that may be controlled so as to turn on or off.

As a result, a pulse width modulated voltage can be output as the line voltage v _uw .

  Furthermore, the multilevel inverter 2 can be applied to both a load that requires the output current io to be positive and a load that requires the output current io to be negative.

(Modification of Example 2)
As a modification of the second embodiment, the U-phase and W-phase inverter arms 9000 and 9001 in the multi-level inverter 2 in FIG. 10 are interchanged to obtain the multi-level inverter 2 ′ in FIG. Is possible. FIG. 19 is a circuit diagram of the multilevel inverter 2 ′.

  In the multilevel inverter 2 ′ in FIG. 19, the U-phase inverter arm 9000 ′ has a configuration in which the high side and the low side of the U-phase inverter arm 9000 in the multilevel inverter 2 in FIG. 10 are interchanged. Similarly, in the multilevel inverter 2 ′ of FIG. 19, the W-phase inverter arm 9001 ′ has a configuration in which the high side and the low side of the W-phase inverter arm 9001 in the multilevel inverter 2 of FIG. 10 are interchanged.

The multilevel inverter 2 ′ according to the present modification includes DC power supplies 901 and 902 connected in series, and a U-phase output terminal 906 and a W-phase output terminal 907 for outputting the line voltage v _uw. The DC voltage applied to the highest potential point 901a in the DC power supplies 901 and 902, the DC voltage applied to the lowest potential point 903a in the DC power supplies 901 and 902, and the connection point between adjacent DC power supplies 901 and 902 Any one of the DC voltages applied to the power supply connection point 902a is applied to the inverter arm 9001 ′ for outputting to the W-phase output terminal 907, the DC voltage applied to the highest potential point 901a, and applied to the lowest potential point 903a. Output to the U-phase output terminal 906 is either a DC voltage to be applied or a DC voltage applied to the power supply connection point 902a. The inverter arm 9001 ′ is provided between the highest potential point 901a and the lowest potential point 903a, and diodes 914b ′, 915b ′, and 916b ′ are reversed. The switching element 914a ', 915a', 916a 'connected in parallel includes a first switching element group formed by connecting an odd number (three in this example) in series, and an anode is connected to the power supply connection point 902a. The same number of DC power sources 901 connected between the highest potential point 901a and the power source connection point 902a included in the first switching element group (in this example, one). The diode 922 ′ connected to the highest potential point 901a is connected to the power supply via the switching element 916a ′. The lowest potential point 903a is provided for each (however, in this example, the power supply connection point is only 902a), one end of which is connected to the power supply connection point 902a and the other end is included in the first switching element group. Switching element 932 ′ (first element) connected to the lowest potential point 903a via the same number (in this example, one) of switching elements 914a ′ as the DC power sources 902 provided between the power source connection point 902a and the power source connection point 902a. 1 switching element) for each power supply connection point (in this example, the power supply connection point is only 902a), and among the connection points of the switching elements included in the first switching element group, the highest potential point The number of switching elements provided between 901a and the switch 901a is one more than the number of switching elements provided between the lowest potential point 903a. A connection point (in this example, a connection point between the switching element 914a ′ and the switching element 915a ′) and a W-phase output terminal 907 are connected, and the inverter arm 9000 ′ has the highest potential point 901a and the lowest potential point. The switching elements 911a ′, 912a ′, and 913a ′ are connected in series with the diodes 911b ′, 912b ′, and 913b ′ connected in reverse parallel to each other. A second switching element group, an anode connected to the power supply connection point 902a, and a cathode included in the second switching element group; the highest potential point 901a and the power supply connection point 902a; Through the same number (one in this example) of switching devices 913a ′ as the DC power sources 901 provided between the A diode 921 ′ connected to the power point 901a is provided for each power connection point (in this example, the power connection point is only 902a), one end is connected to the power connection point 902a, and the other end is Via the same number (one in this example) of switching elements 911a ′ as the number of DC power supplies 902 provided between the lowest potential point 903a and the power supply connection point 902a included in the second switching element group. A switching element 931 ′ (second switching element) connected to the lowest potential point 903a is provided for each power connection point (in this example, the power supply connection point is only 902a), and the second switching element group Among the connection points of the switching elements included in each other, the number of switching elements provided between the highest potential point 901a is the lowest potential point 903. One lot comprising connection points than the number of switching elements provided between (the connection point of this example 'a switching element 912a' switching elements 911a and), and a U-phase output terminal 906 is connected between the.

According to the above configuration, the DC voltage applied to the highest potential point 901a and the DC voltage applied to the lowest potential point 903a by appropriately controlling on / off of the switching element of the inverter arm 9000 ′. , And any DC voltage applied to the power supply connection point 902a can be output to the U-phase output terminal 906. Further, by appropriately controlling on / off of the switching element included in the inverter arm 9001 ′, a DC voltage applied to the highest potential point 901a, a DC voltage applied to the lowest potential point 903a, and Any DC voltage applied to the power supply connection point 902a can be output to the W-phase output terminal 907. As a result, the line voltage v _uw can be output.

As an example, when a negative output current io is output from the U-phase output terminal 906 and the voltage (line voltage v _uw ) of the U-phase output terminal 906 viewed from the W-phase output terminal 907 is −V, All the switching elements 915a ′ and 916a ′ between the highest potential point 901a and the W-phase output terminal 907 are turned on, and all the switching elements 911a ′ between the lowest potential point 903a and the U-phase output terminal 906 are turned on. You can turn on.

  As another example, when the negative output current io is output from the U-phase output terminal 906 and the voltage of the U-phase output terminal 906 viewed from the W-phase output terminal 907 is V, the lowest potential point The switching element 914a ′ between 903a and the W-phase output terminal 907 may be turned off, and all the switching elements 912a ′ and 913a ′ between the highest potential point 901a and the U-phase output terminal 906 may be turned off. In this case, an anti-parallel diode 914b ′ provided between the lowest potential point 903a and the W-phase output terminal 907, and between the highest potential point 901a and the U-phase output terminal 906 are provided. The negative output current io can be output from the U-phase output terminal 906 by flowing a current through the diodes 912b ′ and 913b ′ connected in reverse parallel.

  Further, in the multilevel inverter 2 ', four diodes can be reduced compared to the conventional single-phase three-level inverter (FIG. 27).

  Accordingly, it is possible to provide a multi-level (single-phase three-level) inverter in which at least one of the number of switching elements, the number of diodes, and the number of floating power supplies is reduced as compared with the conventional single-phase three-level inverter.

(Extended modification of Example 2)
Further, as an extended variation of the second embodiment, by adding a V-phase inverter arm 9002 having the same configuration as the U-phase and W-phase inverter arms 9000 and 9001 in the multilevel inverter 2 of FIG. It is also possible to constitute a three-phase three-level inverter 2 ″. FIG. 20 is a circuit diagram of the three-phase three-level inverter 2 ″.

In the multilevel inverter 2, the inverter arm 9000 and the inverter arm 9001 have the same configuration, and in the multilevel inverter 2 ′, the inverter arm 9000 ′ and the inverter arm 9001 ′ have the same configuration. Here, for example, a multi-level inverter cannot be configured by combining the inverter arm 9000 and the inverter arm 9001 ′. The reason is that when the output voltage v _uw is either positive or negative, a multi-level output is obtained, but the other can only output two levels.

[Switching element]
A semiconductor switch can be used as the switching element in the first and second embodiments. By using the semiconductor switch, the multilevel inverters 1, 2, 2 ′ can be configured without using a mechanical switch.

  However, as the switching elements 931 and 932 in FIG. 10, a semiconductor switch having a parasitic antiparallel diode such as a MOSFET (metal-oxide-semiconductor field-effect transistor) cannot be used.

  In contrast, the switching elements 611a, 612a, 613a, 614a, 615a, 616a in FIG. 1 and the switching elements 911a, 912a, 913a, 914a, 915a, 916a in FIG. A semiconductor switch with an antiparallel diode may be used. Accordingly, the diodes 611b, 612b, 613b, 614b, 615b, and 616b in FIG. 1 and the diodes 911b, 912b, 913b, 914b, 915b, and 916b in FIG. 10 can be omitted.

  When a MOSFET is used as the switching element, the switching elements 611a, 612a, 613a, 614a, 615a, 616a in FIG. 1 and the switching elements 911a, 912a, 913a, 914a, 915a, 916a in FIG. What is necessary is just to insert with the polarity shown in FIG.

  When an IGBT (Insulated Gate Bipolar Transistor) is used as the switching element, the switching elements 611a, 612a, 613a, 614a, 615a, and 616a in FIG. 1 and the switching elements 911a and 912a in FIG. , 913a, 914a, 915a, 916a, 931, and 932 with the polarity shown in FIG.

[Number of multi-level inverter levels]
Although the three-level inverter has been described in the above embodiment, the present invention is not limited to the three-level inverter, but can be applied to multi-level inverters having any number of levels such as four levels, five levels,. As an example, FIG. 24 shows a circuit diagram of a four-level inverter according to an embodiment of the present invention.

  In addition, in this embodiment, although the grid connection inverter was mainly described, the object of this invention is not restricted to a grid connection inverter. The present invention can be applied to a motor drive inverter in addition to a grid interconnection inverter.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  Since the multilevel inverter of the present invention can reduce at least one of the number of switching elements, the number of diodes, and the number of floating power supplies as compared with the conventional multilevel inverter, reduction in circuit scale and cost is required. It can be suitably used for a multi-level inverter.

1,2,2 'multi-level inverter 2''three-phase three-level inverter 6000 inverter arm (second inverter arm)
6001 Inverter arm (first inverter arm)
6000 'inverter arm 601 and 602 DC power supply (plural DC power supplies)
601a to 603a DC voltage terminal 606 U-phase output terminal (second output terminal)
607 W-phase output terminal (first output terminal)
611a, 612a, 613a, 614a Switching element (second switching element group)
615a, 616a switching element (first switching element group)
611b, 612b, 613b, 614b Diode 615b, 616b Diode 621 Diode 622 Diode 9000, 9000 'Inverter arm (second inverter arm)
9001, 9001 ′ inverter arm (first inverter arm)
9002 Inverter arm 901, 902 DC power supply (plural DC power supplies)
901a to 903a DC voltage terminal 906 U-phase output terminal (second output terminal)
907 W-phase output terminal (first output terminal)
911a, 912a, 913a switching element (second switching element group)
911a ′, 912a′913a ′ switching element (second switching element group)
914a, 915a, 916a Switching element (first switching element group)
914a ′, 915a ′, 916a ′ switching element (first switching element group)
931, 931 ′ switching element (second switching element)
932, 932 ′ switching element (first switching element)
911b, 912b, 913b Diode 911b ', 912b', 913b 'Diode 914b, 915b, 916b Diode 914b', 915b ', 916b' Diode 921, 921 'Diode 922, 922' Diode 50 Control circuit (control means)
io Output current v _uw line voltage (AC voltage)

Claims (4)

A plurality of DC power supplies connected in series;
A first output terminal and a second output terminal for outputting an alternating voltage;
DC voltage applied to the highest potential point in the plurality of DC power supplies, DC voltage applied to the lowest potential point in the plurality of DC power supplies, and a power supply connection point that is a connection point between the adjacent DC power supplies A first inverter arm that outputs any of the DC voltages to be output to the first output terminal;
A second voltage that outputs any one of a DC voltage applied to the highest potential point, a DC voltage applied to the lowest potential point, and a DC voltage applied to the power supply connection point to the second output terminal. A multi-level inverter equipped with an inverter arm of
The first inverter arm is
A first switching element group that is provided between the highest potential point and the lowest potential point, and in which an odd number of switching elements connected in reverse parallel are connected in series;
One end is connected to the power source connection point, and the other end is included in the first switching element group, and the same number as the DC power sources provided between the highest potential point and the power source connection point. A first switching element connected to the highest potential point via a switching element is provided for each power connection point,
A cathode is connected to the power supply connection point, and an anode is included in the first switching element group, and the same number of the DC power supplies provided between the lowest potential point and the power supply connection point. A diode connected to the lowest potential point via a switching element is provided for each power supply connection point,
Of the connection points of the switching elements included in the first switching element group, the number of switching elements provided between the highest potential points is equal to the number of switching elements provided between the lowest potential points. A connection point that is one less than the number is connected to the first output terminal,
The second inverter arm is
A second switching element group provided between the highest potential point and the lowest potential point and having an odd number of switching elements connected in antiparallel with a diode connected in series;
One end is connected to the power supply connection point, and the other end is included in the second switching element group, and the same number as the DC power supply provided between the highest potential point and the power supply connection point. A second switching element connected to the highest potential point via the switching element of each of the power supply connection points,
A cathode is connected to the power source connection point, and an anode is included in the second switching element group, and the same number as the DC power sources provided between the lowest potential point and the power source connection point. A diode connected to the lowest potential point via a switching element is provided for each power supply connection point,
Of the connection points of the switching elements included in the second switching element group, the number of switching elements provided between the highest potential points is equal to the number of switching elements provided between the lowest potential points. A multi-level inverter, characterized in that a connection point that is one less than the number is connected to the second output terminal. A plurality of DC power supplies connected in series;
A first output terminal and a second output terminal for outputting an alternating voltage;
DC voltage applied to the highest potential point in the plurality of DC power supplies, DC voltage applied to the lowest potential point in the plurality of DC power supplies, and a power supply connection point that is a connection point between the adjacent DC power supplies A first inverter arm that outputs any of the DC voltages to be output to the first output terminal;
A second voltage that outputs any one of a DC voltage applied to the highest potential point, a DC voltage applied to the lowest potential point, and a DC voltage applied to the power supply connection point to the second output terminal. A multi-level inverter equipped with an inverter arm of
The first inverter arm is
A first switching element group that is provided between the highest potential point and the lowest potential point, and in which an odd number of switching elements connected in reverse parallel are connected in series;
The anode is connected to the power supply connection point, and the cathode is included in the first switching element group, and the same number as the DC power supplies provided between the highest potential point and the power supply connection point. A diode connected to the highest potential point via a switching element is provided for each power supply connection point,
One end is connected to the power supply connection point, and the other end is included in the first switching element group, and the same number as the DC power supply provided between the lowest potential point and the power supply connection point. A first switching element connected to the lowest potential point via the switching element, for each power supply connection point;
Of the connection points of the switching elements included in the first switching element group, the number of switching elements provided between the highest potential points is equal to the number of switching elements provided between the lowest potential points. The connection point that is one more than the number is connected to the first output terminal,
The second inverter arm is
A second switching element group provided between the highest potential point and the lowest potential point and having an odd number of switching elements connected in antiparallel with a diode connected in series;
The anode is connected to the power supply connection point, and the cathode is included in the second switching element group, and the same number of the DC power supplies provided between the highest potential point and the power supply connection point. A diode connected to the highest potential point via a switching element is provided for each power supply connection point,
One end is connected to the power source connection point, and the other end is included in the second switching element group, and the same number as the DC power source provided between the lowest potential point and the power source connection point. A second switching element connected to the lowest potential point via the switching element, for each power connection point,
Of the connection points of the switching elements included in the second switching element group, the number of switching elements provided between the highest potential points is equal to the number of switching elements provided between the lowest potential points. A multi-level inverter, characterized in that a connection point that is one more than the number is connected to the second output terminal. ON / OFF of switching elements included in the first switching element group, switching elements included in the second switching element group, and the first switching element and the second switching element. A control means for outputting a control signal to each switching element;
The control means includes
Control so that all the switching elements included in the first switching element group are not simultaneously turned on,
Control is performed so that all the switching elements included in the second switching element group are not simultaneously turned on, and
Any number of switching elements among the switching elements between the lowest potential point or the highest potential point and the first output terminal, the lowest potential point or the highest potential point, and the second output terminal Any of a number of switching elements between the first and second switching elements is subjected to pulse width modulation control, and among the other switching elements, the lowest potential point or the highest potential point, and the first and second potential elements. A switching element between the output terminal and the output terminal is controlled to remain on or off, and
A switching element between the highest potential point or the lowest potential point and the first output terminal; a switching element between the highest potential point or the lowest potential point and the second output terminal; The multi-switch according to claim 1 or 2, wherein the switching element and the second switching element are controlled to be turned on or off in accordance with a polarity of an output current output from the second output terminal. Level inverter.   The switching element included in the first switching element group, the switching element included in the second switching element group, the first switching element, and the second switching element are semiconductor switches. The multi-level inverter according to claim 1 or 2.

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