JP2012169406A - Field-effect transistor - Google Patents

Abstract

In a field effect transistor using a nitride semiconductor, a high-density drain current can be realized without deteriorating transistor characteristics.
A channel layer 101 made of a first nitride semiconductor whose main surface is a (0001) plane, and a nitride semiconductor having a larger bandgap energy than the first nitride semiconductor formed on the channel layer 101. A band larger than the second nitride semiconductor is formed on the first barrier layer 102 and the first barrier layer 102 in the source formation region 122 and the drain formation region 123 across the gate formation region 121 where the gate electrode 104 is formed. Second barrier layer 105 and third barrier layer 106 made of a third nitride semiconductor having a gap energy, and a fourth barrier made of a second nitride semiconductor formed on second barrier layer 105 and third barrier layer 106 A layer 107 and a fifth barrier layer 108.
[Selection] Figure 1

Description

  The present invention relates to a field effect transistor using a nitride semiconductor.

  An example of a field effect transistor (FET) using a nitride semiconductor is a heterostructure field effect transistor (HFET). This nitride semiconductor FET is very promising as a next-generation high-temperature / high-output / high-voltage high-frequency transistor, and is actively researched for practical use. Nitride semiconductor FETs are usually formed in the + c plane ((0001) plane) direction, which is the polar plane direction, and since there is a large polarization charge at the hetero interface, doping processing for supplying carriers is generally performed. Even if not, carriers contributing to conduction are induced in the channel as channel electrons (two-dimensional electrons).

  The nitride semiconductor FET having such a feature has an advantageous aspect that a large current is easily obtained. On the other hand, as a device operation, in general, a so-called depletion type (or normally on) having a negative threshold is used. Type) device operation. That is, even when no voltage is applied to the gate electrode (that is, when the gate voltage is zero), the drain current flows by applying the drain voltage, and by applying a negative voltage to the gate electrode, the drain current becomes zero. This is suitable for the transistor operation of becoming (that is, pinching off).

  Therefore, a so-called enhancement-type (normally-off type) device operation with a positive threshold, which is a device operation contrary to this, can be realized in a GaN-based heterostructure field effect transistor (HFET) (non-patent document). As a general nitride semiconductor FET, it is not easy to realize. In a state where no voltage is applied to the gate electrode (when the gate voltage is zero), the drain current does not flow even when the drain voltage is applied, and the drain current flows when a positive voltage is applied to the gate electrode. This device operation is disadvantageous for a general nitride semiconductor FET.

  Furthermore, in so-called enhancement type device operation, the magnitude of the drain current and the magnitude of the positive threshold are generally negatively correlated, and if a device for obtaining a high positive threshold is applied, the drain current There is a problem in that it decreases. On the other hand, in the enhancement type device operation, if some device is used to obtain a high drain current, there is generally a problem that the ease of realizing the designed threshold value is impaired in the device manufacturing process.

  However, particularly in power applications, it is essential to realize a high-density drain current simultaneously with a depletion type device operation and an enhancement type device operation. Further, in the enhancement type device, it is essential that the ease of realizing the designed threshold value is not impaired in the device manufacturing process. For this reason, in the enhancement type nitride semiconductor FET formed on the normal polar plane (that is, in the c-axis direction), a high-density drain current can be realized, and the designed threshold value can be easily realized in the device manufacturing process. It is strongly desired to develop an FET that does not impair the performance.

M. Asif Khan et al., "Enhancement and depletion mode GaN / AlGaN heterostructure field effect transistors", Appl. Phys. Lett., Vol.68, no.4, pp.514-516, 1996.

  However, as described above, it is difficult to increase the drain current in the conventional enhancement type nitride semiconductor FET. This point will be described with reference to FIGS. FIG. 5 is a cross-sectional view schematically showing a partial configuration of a general enhancement type nitride semiconductor FET.

  In this nitride semiconductor FET, a heterostructure of a channel layer 501 and a barrier layer 502 is formed on the + c plane, ie, the (0001) plane, which is a polar plane of a semiconductor substrate (not shown). A source electrode 503 and a drain electrode 504 are formed, and a gate electrode 506 is provided between the source electrode 503 and the drain electrode 504 with an insulating layer 505 interposed therebetween, thereby forming a field effect transistor.

  Here, the enhancement-type nitride semiconductor FET is generally characterized in that the thickness of the barrier layer 502 existing below the gate electrode 506 is thin in order to obtain channel electron depletion. .

  Such a nitride semiconductor FET has a so-called insulated gate structure or MIS (Metal-Insulator-Semiconductor) structure in which an insulating layer 505 is disposed between the gate electrode 506 and the barrier layer 502 in order to obtain a high gate breakdown voltage. It is used. In this insulated gate structure, the thickness of the barrier layer 502 existing in the region below the gate electrode 506 may be zero in order to obtain a higher threshold value. However, in this case, since the quality of the channel interface generally deteriorates, the speed of channel electrons flowing through the channel layer 501 as carriers may decrease, and a problem may occur in that the drain current decreases.

  Further, in the nitride semiconductor FET described above, the layer thickness of the barrier layer 502 between the source electrode 503 and the gate electrode 506 and between the gate electrode 506 and the drain electrode 504 is in the region below the gate electrode 506. A so-called recess gate structure that is thicker than the thickness of the existing barrier layer 502 is used. This is because the access resistance (source resistance) from the source electrode 503 to the channel electrons existing in the region below the gate electrode 506 is lowered. Employing this recess gate structure is also a characteristic of a typical enhancement type nitride semiconductor FET.

  FIG. 6 is a cross-sectional view schematically showing the presence or absence of channel electrons in the enhancement-type nitride semiconductor FET described above. As shown in FIG. 6, the thickness d1 of the barrier layer 502 below the gate electrode 506 is small, and the thickness d2 of the barrier layer 502 in other regions is large. As a result, in a region below the gate electrode 506 of the channel layer 501, there is an electron depletion region 602 in which electrons serving as carriers are depleted, and in other regions, two-dimensional electrons 601 are present as carriers. It has become.

  FIG. 7 schematically shows the presence or absence of channel electrons in the enhancement type nitride semiconductor FET described above, in the form of electron distribution, along with the potential shape (channel potential shape) of the layer structure of the nitride semiconductor layer. It is explanatory drawing. FIG. 7A shows the presence or absence of channel electrons in the region below the gate electrode 506, together with the potential shape of the layer structure of the nitride semiconductor layer. FIG. 7B shows the presence or absence of channel electrons in a region other than the region below the gate electrode 506, together with the potential shape of the layer structure of the nitride semiconductor layer.

  In any of the region below the gate electrode 506 shown in FIG. 7A and the other region shown in FIG. 7B, the heterointerface between the barrier layer 502 and the channel layer 501 is formed. As a result of the presence of positive polarization charge, the potential shape of the barrier layer 502 generally has a high slope.

  However, as shown in FIG. 7A, in the region below the gate electrode 506, the barrier layer 502 is thin, so that the potential position of the channel layer 501 is sufficiently below the Fermi level. Will not be pushed down. Therefore, with the above-described configuration, channel electrons are depleted and an electron depletion region 602 exists.

  On the other hand, as shown in FIG. 7B, since the thickness of the barrier layer 502 is sufficiently large in a region other than the region below the gate electrode 506, the potential position of the channel layer 501 is Fermi level. Is fully pushed down. Therefore, the two-dimensional electron 601 is induced as the two-dimensional electron gas.

  In general, in order to increase the drain current of the enhancement type nitride semiconductor FET, it is effective to increase the electron concentration of the two-dimensional electrons 601 existing in the region other than the region below the gate electrode 506 and reduce the source resistance. is there. However, if any ordinary contrivance is applied to the barrier layer 502 for this purpose, in general, the ease of realizing the designed threshold value is impaired in the device manufacturing process. Hereinafter, this problem will be described.

  For example, in an AlGaN / GaN heterostructure in which the barrier layer 502 is composed of AlGaN and the channel layer 501 is composed of GaN, in order to reduce the source resistance, the Al composition is increased or the AlGaN layer thickness is increased. Consider increasing the two-dimensional electron concentration at the heterointerface.

  First, consider the situation when the Al composition is increased. When the Al composition is increased, it is possible to increase the electron concentration of the two-dimensional electron 601 existing in a region other than the region below the gate electrode 506. However, at the same time, two-dimensional electrons are also induced in the region below the gate electrode 506, and the enhancement type device operation cannot be realized.

  Therefore, when the Al composition is increased, in order to realize an enhancement type device operation using the region below the gate electrode 506 as an electron depletion region, the layer thickness d1 of the barrier layer 502 below the gate electrode 506 is further reduced. In addition, it is necessary to control this layer thickness.

  In the device manufacturing process, the layer thickness d1 is controlled by removing the barrier layer 502 having a layer thickness d2 in a region other than the region below the gate electrode 506 by a technique such as dry etching. For this reason, in the current normal process technology, when the layer thickness d1 is reduced, it is difficult to control the layer thickness with high accuracy. Here, since the threshold value is very sensitively dependent on the value of the layer thickness d1, if it is difficult to control the layer thickness d1 with high accuracy, it becomes difficult to realize the designed threshold value. As described above, when the Al composition of the barrier layer 502 is increased, there arises a problem that the ease of realizing the designed threshold value is impaired in the device manufacturing process.

  Next, consider the situation when the layer thickness of the barrier layer 502 made of AlGaN is increased. When the thickness d2 of the barrier layer 502 in the region other than the region below the gate electrode 506 is increased, the electron concentration of the two-dimensional electrons 601 can be increased to some extent. At this time, if the layer thickness d1 of the barrier layer 502 below the gate electrode 506 is not changed, an enhancement type device operation is realized. However, in the device manufacturing process, the layer thickness d1 is controlled by removing the barrier layer 502 having a layer thickness d2 in a region other than the region below the gate electrode 506 by a technique such as dry etching. For this reason, in the current normal process technology, when the ratio of the layer thickness d1 to the layer thickness d2 becomes small, it is difficult to control the layer thickness d1 with high accuracy.

  Here, since the threshold value is very sensitively dependent on the value of the layer thickness d1, if it is difficult to control the layer thickness d1 with high accuracy, it becomes difficult to realize the designed threshold value. That is, when the AlGaN layer thickness is increased, there arises a problem that the ease of realizing the designed threshold value is impaired in the device manufacturing process.

  As described above, in general, in order to increase the drain current of the enhancement type nitride semiconductor field effect transistor (nitride semiconductor FET), the electron concentration of the two-dimensional electrons 601 existing in the region other than the lower portion of the gate electrode 506 It is effective to increase the source resistance and reduce the source resistance. However, if any ordinary device is applied to the barrier layer 502 in order to increase the electron concentration, there is a problem that the ease of realizing the designed threshold value is generally impaired in the device manufacturing process.

  In the depletion type nitride semiconductor FET, it is important to increase the drain current. Even in this case, it is effective to increase the electron concentration by increasing the thickness of the barrier layer. However, even in the depletion type, there is a problem in increasing the thickness of the barrier layer. In the depletion type, there is a problem that the gain decreases when the barrier layer is thickened. As described above, the nitride semiconductor FET has a problem that a high-density drain current cannot be obtained without deteriorating the characteristics of the transistor.

  The present invention has been made to solve the above problems, and is a field effect transistor using a nitride semiconductor so that a high-density drain current can be realized without deteriorating the characteristics of the transistor. The purpose is to do.

  The field effect transistor according to the present invention includes a channel layer made of a first nitride semiconductor having a main surface of (0001) plane and a second nitride semiconductor having a band gap energy larger than that of the first nitride semiconductor, and has a layer thickness. A first barrier layer having a thickness of 1 to 10 nm formed on the channel layer, a gate electrode formed on the first barrier layer via an insulating layer, and a gate formation region in which the gate electrode is formed A second barrier layer formed on the first barrier layer in the source formation region and the drain formation region, made of a third nitride semiconductor having a larger band gap energy than the second nitride semiconductor, and having a layer thickness of 1 to 4 nm A fourth barrier layer made of a second nitride semiconductor and having a thickness of 4 to 50 nm and formed on the second barrier layer and the third barrier layer; 4 barriers And a source electrode and a drain electrode formed on the fifth barrier layer, and the thickness of the first barrier layer in the gate formation region is equal to or less than the thickness of the first barrier layer in the source formation region and the drain formation region. Has been.

  In addition, the field effect transistor according to the present invention includes a channel layer made of a first nitride semiconductor having a (0001) plane as a main surface and a channel made of a second nitride semiconductor having a larger band gap energy than the first nitride semiconductor. A first barrier layer formed on the first layer, and a third nitride semiconductor formed on the first barrier layer and having a band gap energy larger than that of the second nitride semiconductor, and has a thickness of 1 to 4 nm. A second barrier layer, a third barrier layer formed on the second barrier layer made of the second nitride semiconductor, a gate electrode formed on the third barrier layer via an insulating layer, and a gate electrode And a source electrode and a drain electrode formed on the third barrier layer, and the total thickness of the first barrier layer and the third barrier layer is in the range of 5 to 50 nm.

  In the field effect transistor, the insulating layer may have a thickness of 1 to 100 nm.

In the field effect transistor, the combination of the second nitride semiconductor and the first nitride semiconductor is Al _x Ga _1-X N and GaN (0 <X ≦ 1), Al _x 1Ga _1-X 1N and In _x. 2Ga _1-X 2N (0 <X1 ≦ 1, 0 ≦ X2 ≦ 1), Al _X1 Ga _1-X1 N and Al _X2 Ga _1-X2 N (0 <X1 ≦ 1, 0 ≦ X2 <1, X1> X2 ), GaN and _{InXGa 1-X N (0 <} X ≦ 1), In X1 Ga 1-X1 N and _{In X2 Ga 1-X2 N (} 0 ≦ X1 <1,0 <X2 ≦ 1, X1 <X2), In _X Al _1-X N and GaN (0 ≦ X <0.5), In _X1 Al _1-X1 N and Al _X2 Ga _1-X2 N (0 ≦ X1 <0.5, 0 ≦ X2 <1, X1 + X2 <1), a combination selected from In _X1 Al _{1 -X1} N and In _X2 Ga _{1 -X2} N (0 ≦ X1 <1, 0 ≦ X2 ≦ 1), and the third nitride semiconductor and the second nitride With semiconductors Combined is, Al _X Ga _1-X N and GaN (0 <X ≦ 1) , Al X 1Ga 1-X 1N and _{In X 2Ga 1-X 2N (} 0 <X1 ≦ 1,0 ≦ X2 ≦ 1), Al _X1 Ga _1-X1 N and _{Al X2 Ga 1-X2 N (} 0 <X1 ≦ 1,0 ≦ X2 <1, X1> X2), GaN and _{InXGa 1-X N (0 <} X ≦ 1), In X1 Ga _1-X1 N and In _X2 Ga _1-X2 N (0 ≦ X1 <1, 0 <X2 ≦ 1, X1 <X2), In _X Al _1-X N and GaN (0 ≦ X <0.5), In _X1 Al _1-X1 N and _{Al X2 Ga 1-X2 N (} 0 ≦ X1 <0.5,0 ≦ X2 <1, X1 + X2 <1), In X1 Al 1-X1 N and In _X2 Ga _1-X2 N ( Any combination selected from 0 ≦ X1 <1, 0 ≦ X2 ≦ 1) may be used. For example, the first nitride semiconductor may be GaN, the second nitride semiconductor may be Al _0.3 Ga _0.7 N, and the third nitride semiconductor may be Al _0.45 Ga _0.55 N.

  In the field effect transistor, a doping process may be performed on a part of the first barrier layer, the second barrier layer, and the third barrier layer. Moreover, you may make it provide the buffer layer arrange | positioned under the channel layer.

  As described above, according to the present invention, the first barrier layer, the second barrier layer having a larger bandgap energy, and the third barrier layer that is the same as the first barrier layer are used. A field effect transistor using a physical semiconductor has an excellent effect that a high-density drain current can be realized without degrading the characteristics of the transistor.

FIG. 1 is a cross-sectional view showing a configuration of a field effect transistor according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view showing the configuration of the field effect transistor according to Embodiment 1 of the present invention. FIG. 3 shows the state of the electron concentration of the two-dimensional electrons 201 together with the potential shape of the layer structure of the channel layer 101, the first barrier layer 102, the second barrier layer 105, and the fourth barrier layer 107 in the source formation region 122. It is explanatory drawing. FIG. 4 is a cross-sectional view showing the configuration of the field effect transistor according to Embodiment 2 of the present invention. FIG. 5 is a cross-sectional view schematically showing a partial configuration of a general enhancement type nitride semiconductor FET. FIG. 6 is a cross-sectional view schematically showing the presence or absence of channel electrons in the enhancement type nitride semiconductor FET. FIG. 7 is an explanatory diagram schematically showing the presence or absence of channel electrons in the enhancement type nitride semiconductor FET, in the form of electron distribution, along with the potential shape of the layer structure of the nitride semiconductor layer.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[Embodiment 1]
First, Embodiment 1 of the present invention will be described. FIG. 1 is a cross-sectional view showing a configuration of a field effect transistor according to Embodiment 1 of the present invention. In this field effect transistor, first, a channel layer 101 made of a first nitride semiconductor having a main surface of (0001) plane, and nitriding with a larger band gap energy than the first nitride semiconductor formed on the channel layer 101. A first barrier layer 102 made of a physical semiconductor and a gate electrode 104 formed on the first barrier layer 102 with an insulating layer 103 interposed therebetween are provided.

  The field effect transistor is formed on the first barrier layer 102 in the source formation region 122 and the drain formation region 123 across the gate formation region 121 where the gate electrode 104 is formed, and is larger than the second nitride semiconductor. A second barrier layer 105 and a third barrier layer 106 made of a third nitride semiconductor having a band gap energy, and a fourth nitride semiconductor made on the second barrier layer 105 and the third barrier layer 106. The barrier layer 107 and the fifth barrier layer 108, and the source electrode 109 and the drain electrode 110 formed on the fourth barrier layer 107 and the fifth barrier layer 108 are provided.

  The first barrier layer 102 has a layer thickness of 1 to 10 nm, the second barrier layer 105 and the third barrier layer 106 have a layer thickness of 1 to 4 nm, and the fourth barrier layer 107 and the fifth barrier layer 108 are layers. The thickness is 4 to 50 nm, and the thickness of the first barrier layer 102 in the gate formation region 121 is equal to or less than the thickness of the first barrier layer 102 in the source formation region 122 and the drain formation region 123. The layer thickness of the first barrier layer 102 in the gate formation region 121 may be zero. Moreover, the layer thickness of the insulating layer 103 should just be 1-100 nm.

  In this field effect transistor, as shown in FIG. 2, two-dimensional electrons 201 exist in the source formation region 122 and drain formation region 123 of the channel layer 101, and electrons are depleted in the gate formation region 121 of the channel layer 101. An electron depletion region 202 exists. According to the first embodiment, the concentration of the two-dimensional electron 201 is increased by providing the second barrier layer 105 and the third barrier layer 106. This state is shown in the band diagram of FIG. FIG. 3 shows the state of the electron concentration of the two-dimensional electrons 201 together with the potential shape of the layer structure of the channel layer 101, the first barrier layer 102, the second barrier layer 105, and the fourth barrier layer 107 in the source formation region 122. ing. As shown in FIG. 3, compared with the state shown in FIG. 7B, the electron concentration of the two-dimensional electron 201 is increased. This state is also the same in the drain formation region 123.

  As shown in FIG. 3, in the source formation region 122, a high-thin and thin second barrier layer 105 having a larger band gap energy than the first barrier layer 102 and the fourth barrier layer 107 exists. Similarly, in the drain region 123, the third barrier layer 106 having a high barrier and a thin layer having a larger band gap energy than the first barrier layer 102 and the fifth barrier layer 108 exists.

  As a result, polarization charges are induced at the hetero interfaces on the upper and lower sides of the second barrier layer 105 and the third barrier layer 106. Positive polarization charges are induced at the lower (channel side) heterointerface of the second barrier layer 105 and the third barrier layer 106, and negative polarization charges are induced at the upper (surface side) heterointerface. Due to this induced polarization charge, an internal electric field in the second barrier layer 105 and the third barrier layer 106 is formed.

  Due to the internal electric fields in the second barrier layer 105 and the third barrier layer 106 thus formed, the barrier effect of the entire barrier layer is greatly increased, and the potential position of the channel is lowered. Thereby, the electron concentration of the two-dimensional electrons 201 in the source formation region 122 and the drain formation region 123 is increased, and the electric resistance in the source formation region 122 and the drain formation region 123 is significantly reduced. As a result, according to the field effect transistor of the first embodiment, a high-density drain current can be obtained.

  Further, according to the first embodiment, since the second barrier layer 105 and the third barrier layer 106 are thin layers of 1 to 4 nm, the increase in the thickness of the entire barrier layer due to the addition of this layer. Is small. Therefore, in the device manufacturing process, the ease of realizing the designed threshold value realized by controlling the thickness of the barrier layer semiconductor in the designed gate formation region 121 is not impaired.

  Here, in the gate formation region 121, when the thickness of the first barrier layer 102 exceeds 10 nm, the channel layer is not applied to the gate electrode 104 (that is, when the gate voltage is zero). Two-dimensional electrons are generated in the channel 101, and the enhancement operation cannot be obtained. Therefore, the layer thickness of the first barrier layer 102 in the gate formation region 121 needs to be 10 nm or less.

  In the case where the thickness of the first barrier layer 102 present in the gate formation region 121 is zero, that is, the insulating layer 103 is formed immediately above the channel layer 101 without the first barrier layer 102 being present. Even when the voltage is not applied to the gate electrode 104 (that is, when the gate voltage is zero), two-dimensional electrons are not generated in the channel of the channel layer 101, so that the device can be used as an enhancement operation device.

  Therefore, in the gate formation region 121, the thickness of the first barrier layer 102 formed on the channel layer 101 on which the carrier of the transistor travels needs to be any thickness in the range of 0 nm to 10 nm. It is.

  On the other hand, in the source formation region 122 and the drain formation region 123 other than the gate formation region 121 where depletion of channel electrons necessary for obtaining the enhancement operation is realized as the electron depletion region 202, the first barrier layer 102 is The gate forming region 121 is formed thicker than the first barrier layer 102. Further, on the first barrier layer 102 existing in the source formation region 122 and the drain formation region 123, a thin-layer first layer made of a nitride semiconductor having a bandgap (that is, a high barrier) larger than that of the first barrier layer 102. The second barrier layer 105 and the third barrier layer 106 are formed, and an accelerated barrier layer structure is configured. The source electrode 109 and the drain electrode 110 are formed on the fourth barrier layer 107 and the fifth barrier layer 108 on the second barrier layer 105 and the third barrier layer 106.

  In the above-described configuration, in the source formation region 122 and the drain formation region 123, that is, the region where the enhanced barrier layer structure is formed, the layer thickness of the first barrier layer 102 is 1 nm or more and 10 nm in the polar plane direction (+ c plane direction). The thickness of the second barrier layer 105 and the third barrier layer 106 is 1 nm or more and 4 nm or less, and the thickness of the fourth barrier layer 107 and the fifth barrier layer 108 is 4 nm or more and 50 nm or less. Has been.

  That is, in the source formation region 122 and the drain formation region 123, the first barrier on the channel layer 101 is used in order for the semiconductor layer having the first barrier layer 102 in the gate formation region 121 to have a thickness of 1 nm to 10 nm. The layer 102 needs to have a thickness in the range of 1 nm or more and 10 nm or less, but does not need to exceed 10 nm.

  Further, the layer thickness of the second barrier layer 105 and the third barrier layer 106 is required to be 1 nm or more in order to effectively obtain the effect of the existence. On the other hand, if the layer thickness exceeds 4 nm, two-dimensional electrons are generated at the lower hetero interface of the second barrier layer 105 and the third barrier layer 106, which undesirably affects device characteristics. For this reason, the layer thickness of the second barrier layer 105 and the third barrier layer 106 should not exceed 4 nm. The fourth barrier layer 107 and the fifth barrier layer 108 have a thickness of 4 nm or more in order to embed the second barrier layer 105 and the third barrier layer 106 at a sufficient depth from the element surface. Although necessary, layer thicknesses above 50 nm are not required.

From the examination results as described above, each layer of the field effect transistor according to the first embodiment can be configured as follows. First, the channel layer 101 may be made of GaN having a layer thickness of 3 μm. Next, the first barrier layer 102 is made of Al _0.3 Ga _0.7 N, the gate formation region 121 may have a layer thickness of 3 nm, and the source formation region 122 and the drain formation region 123 may have a layer thickness of 6 nm. .

Next, the second barrier layer 105 and the third barrier layer 106 may be made of Al _0.45 Ga _0.55 N having a layer thickness of 2 nm. Next, the fourth barrier layer 107 and the fifth barrier layer 108 may be made of Al _0.3 Ga _0.7 N having a layer thickness of 12 nm.

Each of these layers includes a channel layer 101 made of GaN having a thickness of 3 μm and a first barrier layer made of Al _0.3 Ga _0.7 N having a thickness of 6 nm on a semiconductor substrate such as a c-plane sapphire substrate, SiC substrate, or Si substrate. 102, a second barrier layer 105 and a third barrier layer 106 made of Al _0.45 Ga _0.55 N with a layer thickness of 2 nm, a fourth barrier layer 107 and a fifth barrier layer 108 made of Al _0.3 Ga _0.7 N with a layer thickness of 12 nm, After growing by a crystal growth method such as metal vapor phase epitaxy (MOVPE), it can be formed by a conventional patterning technique such as a dry etching method. The Al _0.3 Ga _0.7 N constituting the first barrier layer 102 is doped with Si at a concentration of about 1 × 10 ¹⁹ cm ⁻³ .

In addition, an Al _0.3 Ga _0.7 N layer (12 nm) to be the first barrier layer 102, an Al _0.45 Ga _0.55 N layer (2 nm) to be the second barrier layer 105 and the third barrier layer 106, the fourth barrier layer 107 and the fifth barrier layer After the Al _0.3 Ga _0.7 N layer (12 nm) to be the barrier layer 108 is sequentially stacked, the gate formation region 121 is selectively removed by a dry etching method or the like, whereby the structure below the gate electrode 104 can be formed. . In this patterning, etching is performed halfway through the first barrier layer 102. However, it is relatively easy to perform this with high controllability according to the dry etching method of the state of the art. However, when the thickness of the layer to be etched is larger than the above-described conditions, it becomes difficult to form the first barrier layer 102 in the gate formation region 121 with a controllability of about 3 nm.

As described above, after forming each nitride semiconductor layer, an electrode metal is deposited on the fourth barrier layer 107 and the fifth barrier layer 108 in the source formation region 122 and the drain formation region 123 to form the source electrode 109. And the drain electrode 110 is formed. Next, Al ₂ O ₃ is deposited on the first barrier layer 102 in the gate formation region 121 to a thickness of about 30 nm by a deposition method such as atomic layer deposition (ALD), thereby forming the insulating layer 103. Thereafter, by depositing an electrode metal on the insulating layer 103 to form the gate electrode 104, the field effect transistor (nitride semiconductor FET) in the first embodiment can be manufactured. The gate electrode 104 can be formed with a gate length of 2 μm, for example.

  When an enhancement type device operation having a threshold of +3 V was performed on the fabricated nitride semiconductor FET (gate length: 2 μm), a high drain current density of 1.6 A / mm could be obtained.

  Here, for comparison, a nitride semiconductor FET to be compared that does not use the second barrier layer 105 and the third barrier layer 106 of the nitride semiconductor FET of the first embodiment described above is manufactured. An enhancement type device operation having a threshold of +3 V was performed. As a device operation result in the manufactured comparative nitride semiconductor FET, the drain current density can be obtained only at 1.2 A / mm even when Si doping is performed in the same manner, and 0 when no doping is performed. 0.7 A / mm. Thus, according to the first embodiment, it was found that a significant increase in drain current was obtained.

Next, materials constituting each layer will be described. First, a combination of the first nitride semiconductor and the second nitride semiconductor will be described. This combination (second nitride semiconductor / first nitride semiconductor) includes Al _X Ga _1-X N / GaN (0 <X ≦ 1), Al _X 1Ga _1-X 1N / In _X 2Ga _1-X 2N ( 0 <X1 ≦ 1, 0 ≦ X2 ≦ 1), Al _X1 Ga ₁ -X1 N / Al _X2 Ga ₁ -X2 N (0 <X1 ≦ 1, 0 ≦ X2 <1, X1> X2), GaN / InXGa _{1 -X N (0 <X ≦ 1} ), In X1 Ga 1-X1 N / In X2 Ga 1-X2 N (0 ≦ X1 <1,0 <X2 ≦ 1, X1 <X2), In X Al 1-X N / GaN (0 ≦ X <0.5), In _X1 Al _1-X1 N / Al _X2 Ga _1-X2 N (0 ≦ X1 <0.5, 0 ≦ X2 <1, X1 + X2 <1), In _X1 A combination of semiconductor materials selected from Al _{1 -X 1} N / In _{X 2} Ga ₁ -X ₂ N (0 ≦ X1 <1, 0 ≦ X2 ≦ 1) may be used.

Further, although Al _0.45 Ga _0.55 N and Al _0.3 Ga _0.7 N are used as the semiconductor materials of the third nitride semiconductor / second nitride semiconductor, respectively, the present invention is not limited to this, but the second barrier layer 105, Other semiconductor materials may be used as long as the barrier layer 106 can be formed between the first barrier layer 102 and the fourth barrier layer 107 and the fifth barrier layer 108. As a combination of the third nitride semiconductor / second nitride semiconductor, any nitride semiconductor may be used as long as a nitride semiconductor having a band gap larger than that of the second nitride semiconductor is used as the third nitride semiconductor. .

For example, as a combination of the semiconductor materials of the third nitride semiconductor / second nitride semiconductor, Al _X1 Ga _{1 -X1} N / Al _X2 Ga _{1 -X2} N (0 <X1 ≦ 1, 0 ≦ X2 <1, _{X1> X2), In X1 Al} 1-X1 N / Al X2 Ga 1-X2 N (0 ≦ X1 <0.5,0 ≦ X2 <1, X1 + X2 <1), AlXGa 1-X N / GaN (0 < _{X ≦ 1), InXAl 1-} X N / GaN (0 ≦ X <0.5), Al X1 Ga 1-X1 N / In X2 Ga 1-X2 N (0 <X1 ≦ 1,0 ≦ X2 ≦ 1) _{, GaN / InXGa 1-X N} (0 <X ≦ 1), In X1 Ga 1-X1 N / In X2 Ga 1-X2 N (0 ≦ X1 <1,0 <X2 ≦ 1, X1 <X2), In _{X1 Al 1-X1 N / In} X2 Ga 1-X2 N (0 ≦ X1 <1,0 ≦ X2 ≦ 1), In X1 Al 1-X1 N / In X2 Al 1-X2 N (0 ≦ X1 <X2 ≦ Of the semiconductor material selected from 1) It may be formed by using the combined viewing.

  In the first embodiment, in order to obtain a higher drain current density, impurities (the main half of the first barrier layer 102 in the source forming region 122 and the drain forming region 123) Although the doping process of Si) is performed in the first embodiment, the drain current can be increased even when the doping process is not performed at all. Even when the second barrier layer 105, the third barrier layer 106, and a part of the upper and lower layers are doped in a region different from the first embodiment, the drain current Can be increased.

  By the way, there is no limitation on the structure below the channel layer 101. For example, the channel layer 101 may be thinned to 40 nm, and a buffer layer made of AlGaN having a layer thickness of 1.5 μm may be provided in the lower layer to form a double heterostructure consisting of buffer layer / channel layer / barrier layer. Even in such a configuration, the above-described effects obtained by providing the second barrier layer 105 and the third barrier layer 106 are the same.

[Embodiment 2]
Next, a second embodiment of the present invention will be described. FIG. 4 is a cross-sectional view showing a configuration of a field effect transistor (nitride semiconductor FET) in the second embodiment of the present invention. The nitride semiconductor FET includes a channel layer 401 made of a first nitride semiconductor having a main surface of (0001) plane, and a channel layer 401 made of a second nitride semiconductor having a larger band gap energy than the first nitride semiconductor. And a first barrier layer 402 formed thereon.

  The nitride semiconductor FET is formed on the first barrier layer 402, is made of a third nitride semiconductor having a larger band gap energy than the second nitride semiconductor, and has a thickness of 1 to 4 nm. A layer 403, a third barrier layer 404 formed on the second barrier layer 403 made of the second nitride semiconductor, and a gate electrode 406 formed on the third barrier layer 404 with an insulating layer 405 interposed therebetween. And a source electrode 407 and a drain electrode 408 formed on the third barrier layer 404 with the gate electrode 406 interposed therebetween. The total thickness of the first barrier layer 402 and the third barrier layer 404 is in the range of 5 to 50 nm.

  In this field effect transistor, two-dimensional electrons 421 exist in the channel layer 401. According to the second embodiment, by providing the second barrier layer 403, the concentration of the two-dimensional electrons 421 increases. This will be described in more detail. By providing the second barrier layer 403 having a larger band gap with respect to the upper and lower first barrier layers 402 and the third barrier layer, polarization charges are induced at the upper and lower hetero interfaces of the second barrier layer 403. Positive polarization charge is induced at the lower (channel side) heterointerface of the second barrier layer 403 and negative polarization charge is induced at the upper (surface side) heterointerface. Due to this induced polarization charge, an internal electric field in the second barrier layer 403 is formed.

  Due to the internal electric field in the second barrier layer 403 thus formed, the barrier effect of the entire barrier layer is greatly increased, and the potential position of the channel is lowered. As a result, the electron concentration of the two-dimensional electrons 421 in the channel layer 401 is increased, and the electrical resistance in each region of the source electrode 407 and under the drain electrode 408 is significantly reduced. As a result, according to the field effect transistor of the second embodiment, a high-density drain current can be obtained.

  In addition, according to the second embodiment, the second barrier layer 403 is a thin layer of 1 to 4 nm, so that the increase in the thickness of the entire barrier layer due to the addition of this layer is small.

  Here, when a barrier layer material made of a normal nitride semiconductor that can be used is used, in order to obtain a depletion type operation by causing the two-dimensional electrons 421 to exist in the channel layer 401, the first barrier layer 402 and The total layer thickness of the third barrier layer 404 needs to be 5 nm or more. However, the total thickness of the first barrier layer 402 and the third barrier layer 404 need not exceed 50 nm.

  Further, the layer thickness of the second barrier layer 403 needs to be 1 nm or more in order to effectively obtain the effect of this existence. On the other hand, if the layer thickness exceeds 4 nm, two-dimensional electrons are generated at the lower hetero interface of the second barrier layer 403, which undesirably affects device characteristics. For this reason, the layer thickness of the second barrier layer 403 should not exceed 4 nm. In order to dispose the second barrier layer 403 at a sufficient depth from the element surface, it is important that the third barrier layer 404 has a thickness of 4 nm or more. Note that the insulating layer 405 may have a thickness of 1 to 100 nm.

From the above examination results, each layer of the field effect transistor according to the second embodiment can be configured as follows. First, the channel layer 401 may be made of GaN having a layer thickness of 3 μm. Next, the first barrier layer 402 may be made of Al _0.3 Ga _0.7 N having a layer thickness of 6 nm. Next, the second barrier layer 403 may be made of Al _0.45 Ga _0.55 N having a thickness of 2 nm. Next, the third barrier layer 404 may be made of Al _0.3 Ga _0.7 N having a layer thickness of 12 nm.

Each of these layers includes a channel layer 401 made of GaN having a thickness of 3 μm and a first barrier layer made of Al _0.3 Ga _0.7 N having a thickness of 6 nm on a semiconductor substrate such as a c-plane sapphire substrate, SiC substrate, or Si substrate. 402, a second barrier layer 403 made of Al _0.45 Ga _0.55 N with a thickness of 2 nm and a third barrier layer 404 made of Al _0.3 Ga _0.7 N with a thickness of 12 nm are grown by a crystal growth method such as metal organic chemical vapor deposition. Then, it can be formed by a conventional patterning technique such as a dry etching method. The Al _0.3 Ga _0.7 N constituting the first barrier layer 402 is doped with Si at a concentration of about 1 × 10 ¹⁹ cm ⁻³ .

As described above, after forming each nitride semiconductor layer, an electrode metal is vapor-deposited in a predetermined region on the third barrier layer 404 to form a source electrode 407 and a drain electrode 408. Next, Al ₂ O ₃ is deposited to a thickness of about 30 nm by a deposition method such as an atomic layer deposition method in the gate formation region of the third barrier layer 404 to form an insulating layer 405. Thereafter, an electrode metal is deposited on the insulating layer 405 to form the gate electrode 406, whereby the nitride semiconductor FET according to the second embodiment can be manufactured. The gate electrode 406 can be formed with a gate length of 2 μm, for example.

  When a depletion type device operation having a threshold of −6 V was performed on the manufactured nitride semiconductor FET (gate length: 2 μm), a high drain current density of 2.0 A / mm could be obtained.

  Here, for comparison, a comparative nitride semiconductor FET that does not use the second barrier layer 403 of the nitride semiconductor FET of the second embodiment described above is manufactured, and has a threshold value of −3 V as described above. Depletion type device operation was performed. As a device operation result in the manufactured comparative nitride semiconductor FET, a drain current density of only 1.5 A / mm can be obtained even when Si doping is performed in the same manner. 0.0 A / mm. As described above, according to the second embodiment, it was found that the drain current was significantly increased.

Next, materials constituting each layer will be described. In the above description, GaN is used as the first nitride semiconductor and Al _0.3 Ga _0.7 N is used as the second nitride semiconductor. However, the present invention is not limited to this. As a combination of the second nitride semiconductor / first nitride semiconductor, any combination may be used as long as the first nitride semiconductor has a nitride semiconductor having a smaller band gap than the second nitride semiconductor. .

For example, the combination of the second nitride semiconductor / first nitride semiconductor is Al _X Ga _1-X N / GaN (0 <X ≦ 1), Al _X 1Ga _1-X 1N / In _X 2Ga _1-X 2N ( 0 <X1 ≦ 1, 0 ≦ X2 ≦ 1), Al _X1 Ga ₁ -X1 N / Al _X2 Ga ₁ -X2 N (0 <X1 ≦ 1, 0 ≦ X2 <1, X1> X2), GaN / InXGa _{1 -X N (0 <X ≦ 1} ), In X1 Ga 1-X1 N / In X2 Ga 1-X2 N (0 ≦ X1 <1,0 <X2 ≦ 1, X1 <X2), In X Al 1-X N / GaN (0 ≦ X <0.5), In _X1 Al _1-X1 N / Al _X2 Ga _1-X2 N (0 ≦ X1 <0.5, 0 ≦ X2 <1, X1 + X2 <1), In _X1 Any combination of semiconductor materials selected from Al _{1 -X 1} N / In _{X 2} Ga ₁ -X ₂ N (0 ≦ X1 <1, 0 ≦ X2 ≦ 1) may be used.

Further, Al _0.45 Ga _0.55 N and Al _0.3 Ga _0.7 N are used as the semiconductor materials of the third nitride semiconductor / second nitride semiconductor, respectively, but the present invention is not limited to this, and the second barrier layer 403 is formed by Other semiconductor materials may be used as long as they can be formed between the first barrier layer 402 and the third barrier layer 404. As a combination of the third nitride semiconductor / second nitride semiconductor, any nitride semiconductor may be used as long as a nitride semiconductor having a band gap larger than that of the second nitride semiconductor is used as the third nitride semiconductor. .

For example, as a combination of the semiconductor materials of the third nitride semiconductor / second nitride semiconductor, Al _X1 Ga _{1 -X1} N / Al _X2 Ga _{1 -X2} N (0 <X1 ≦ 1, 0 ≦ X2 <1, _{X1> X2), In X1 Al} 1-X1 N / Al X2 Ga 1-X2 N (0 ≦ X1 <0.5,0 ≦ X2 <1, X1 + X2 <1), AlXGa 1-X N / GaN (0 < _{X ≦ 1), InXAl 1-} X N / GaN (0 ≦ X <0.5), Al X1 Ga 1-X1 N / In X2 Ga 1-X2 N (0 <X1 ≦ 1,0 ≦ X2 ≦ 1) _{, GaN / InXGa 1-X N} (0 <X ≦ 1), In X1 Ga 1-X1 N / In X2 Ga 1-X2 N (0 ≦ X1 <1,0 <X2 ≦ 1, X1 <X2), In _{X1 Al 1-X1 N / In} X2 Ga 1-X2 N (0 ≦ X1 <1,0 ≦ X2 ≦ 1), In X1 Al 1-X1 N / In X2 Al 1-X2 N (0 ≦ X1 <X2 ≦ Of the semiconductor material selected from 1) It may be formed by using the combined viewing.

  In the second embodiment, in order to obtain a higher drain current density, a part of the first barrier layer 402 (lower half portion) is doped with impurities (Si in the second embodiment). Although the treatment is performed, the drain current can be increased even when the doping treatment is not performed at all. In addition, even when the second barrier layer 403 and a part of the upper and lower layers are subjected to a doping process on a region different from the second embodiment, the drain current can be increased. it can.

  By the way, also in the second embodiment, there is no limitation on the configuration below the channel layer 401. For example, the channel layer 401 may be thinned to 40 nm, and a buffer layer made of AlGaN having a layer thickness of 1.5 μm may be provided below the channel layer 401 to form a double heterostructure consisting of buffer layer / channel layer / barrier layer. Even in such a configuration, the above-described effects obtained by providing the second barrier layer 105 and the third barrier layer 106 are the same.

  In the nitride semiconductor FET according to the second embodiment, an example of a structure in which the barrier layer in the region under the gate electrode 406 is not deleted is shown, but the present invention is not limited to this. A portion of the third barrier layer 404 and the second barrier layer 403 under the gate electrode 406 was deleted for threshold adjustment (decreasing the absolute value of the negative threshold) and gain (transconductance); A so-called recess gate structure may be used. Even in this configuration, a depletion-type operation can be obtained as long as the channel layer 401 under the gate electrode can have the presence of the two-dimensional electrons 421 necessary for obtaining a negative threshold. In other words, any configuration may be used as long as the two-dimensional electrons 421 can be obtained even in the region under the gate electrode.

  The present invention is not limited to the embodiments described above, and many combinations and modifications can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention. It is obvious.

  DESCRIPTION OF SYMBOLS 101 ... Channel layer, 102 ... 1st barrier layer, 103 ... Insulating layer, 104 ... Gate electrode, 105 ... 2nd barrier layer, 106 ... 3rd barrier layer, 107 ... 4th barrier layer, 108 ... 5th barrier layer, DESCRIPTION OF SYMBOLS 109 ... Source electrode, 110 ... Drain electrode, 121 ... Gate formation region, 122 ... Source formation region, 123 ... Drain formation region, 201 ... Two-dimensional electron, 202 ... Electron depletion region, 401 ... Channel layer, 402 ... First barrier 403 ... second barrier layer, 404 ... third barrier layer, 405 ... insulating layer, 406 ... gate electrode, 407 ... source electrode, 408 ... drain electrode, 421 ... two-dimensional electrons.

Claims (7)

A channel layer made of a first nitride semiconductor having a main surface of (0001) plane;
A first barrier layer made of a second nitride semiconductor having a larger band gap energy than the first nitride semiconductor and having a layer thickness of 1 to 10 nm and formed on the channel layer;
A gate electrode formed on the first barrier layer via an insulating layer;
The third nitride semiconductor is formed on the first barrier layer in the source formation region and the drain formation region sandwiching the gate formation region where the gate electrode is formed, and has a larger band gap energy than the second nitride semiconductor. A second barrier layer and a third barrier layer having a layer thickness of 1 to 4 nm,
A fourth barrier layer and a fifth barrier layer made of the second nitride semiconductor and having a layer thickness of 4 to 50 nm and formed on the second barrier layer and the third barrier layer;
A source electrode and a drain electrode formed on the fourth barrier layer and the fifth barrier layer,
The field effect transistor according to claim 1, wherein a thickness of the first barrier layer in the gate formation region is equal to or less than a thickness of the first barrier layer in the source formation region and the drain formation region. A channel layer made of a first nitride semiconductor having a main surface of (0001) plane;
A first barrier layer formed on the channel layer made of a second nitride semiconductor having a larger band gap energy than the first nitride semiconductor;
A second barrier layer formed on the first barrier layer, made of a third nitride semiconductor having a larger band gap energy than the second nitride semiconductor, and having a layer thickness of 1 to 4 nm;
A third barrier layer formed on the second barrier layer made of the second nitride semiconductor;
A gate electrode formed on the third barrier layer via an insulating layer;
A source electrode and a drain electrode formed on the third barrier layer with the gate electrode interposed therebetween,
The total thickness of the first barrier layer and the third barrier layer is in the range of 5 to 50 nm. The field effect transistor according to claim 1 or 2,
The field effect transistor according to claim 1, wherein the insulating layer has a thickness of 1 to 100 nm. The field effect transistor according to any one of claims 1 to 3,
The combination of the second nitride semiconductor and the first nitride semiconductor includes Al _x Ga _1-x N and GaN (0 <X ≦ 1), Al _x 1Ga _1-x 1N and In _x 2Ga _1-x 2N ( 0 <X1 ≦ 1, 0 ≦ X2 ≦ 1), Al _X1 Ga ₁ -X1 N and Al _X2 Ga ₁ -X2 N (0 <X1 ≦ 1, 0 ≦ X2 <1, X1> X2), GaN and InXGa _{1 -X N (0 <X ≦ 1} ), In X1 Ga 1-X1 N and _{In X2 Ga 1-X2 N (} 0 ≦ X1 <1,0 <X2 ≦ 1, X1 <X2), In X Al 1-X N and GaN (0 ≦ X <0.5), In _X1 Al _{1 -X1} N and Al _X2 Ga _{1 -X2} N (0 ≦ X1 <0.5, 0 ≦ X2 <1, X1 + X2 <1), In _X1 A combination selected from Al _1-X1 N and In _X2 Ga _1-X2 N (0 ≦ X1 <1, 0 ≦ X2 ≦ 1),
The combination of the third nitride semiconductor and the second nitride semiconductor includes Al _x Ga _1-X N and GaN (0 <X ≦ 1), Al _x 1Ga _1-X 1N and In _x 2Ga _1-X 2N. (0 <X1 ≦ 1, 0 ≦ X2 ≦ 1), Al _X1 Ga ₁ -X1 N and Al _X2 Ga ₁ -X2 N (0 <X1 ≦ 1, 0 ≦ X2 <1, X1> X2), GaN and InXGa _1-X N (0 <X ≦ 1), In _X1 Ga _1-X1 N and In _X2 Ga _1-X2 N (0 ≦ X1 <1, 0 <X2 ≦ 1, X1 <X2), In _X Al _{1- X} N and GaN (0 ≦ X <0.5) , In X1 Al 1-X1 N and _{Al X2 Ga 1-X2 N (} 0 ≦ X1 <0.5,0 ≦ X2 <1, X1 + X2 <1), In _X1 Al _1-X1 N and _{in X2 Ga 1-X2 N (} 0 ≦ X1 <1,0 ≦ X2 ≦ 1) field effect transistor, characterized in that a combination selected from among. The field effect transistor according to claim 4, wherein
The first nitride semiconductor is GaN;
The second nitride semiconductor is Al _0.3 Ga _0.7 N;
The third nitride semiconductor is Al _0.45 Ga _0.55 N. The field effect transistor according to claim 1, wherein: The field effect transistor according to any one of claims 1 to 5,
A field effect transistor, wherein a part of the first barrier layer, the second barrier layer, and the third barrier layer is doped. In the field effect transistor according to any one of claims 1 to 6,
A field effect transistor comprising a buffer layer disposed under the channel layer.