JP2012164951A - Device and method for peeling semiconductor chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device for peeling a semiconductor chip which prevents damage to semiconductor chips when the semiconductor chips are peeled from dicing tapes, and to provide a method for peeling the semiconductor chip.SOLUTION: A device for peeling a semiconductor chip has: a first push-up member 43 moving in a vertical direction and having a first push-up surface 43a pushing up a first portion of the semiconductor chip, which corresponds to at least a formation region of a through electrode, through a dicing tape; and a second push-up member 44 moving in the vertical direction and having a second push-up surface 44a pushing up a second portion of the semiconductor chip, which the through electrode is not formed, through the dicing tape.

Description

  The present invention relates to a semiconductor chip peeling apparatus and a semiconductor chip peeling method.

  Conventionally, a plurality of semiconductor chips are separated into individual pieces by pasting a dicing tape on the back surface of a semiconductor substrate (semiconductor wafer) on which a plurality of semiconductor chips are collectively formed, and then cutting the semiconductor substrate. The semiconductor chip is picked up by peeling the wafer from the dicing tape.

  In Patent Document 1, the semiconductor chip is pushed up together with the dicing tape by a surface having a substantially smaller shape than the adhesion area of the semiconductor chip on the dicing tape, and the semiconductor chip is partially peeled from the dicing tape. And a second push-up mechanism that pushes up the central part of the semiconductor chip partially peeled from the dicing tape by the first push-up mechanism together with the dicing tape, and peels off the central part of the semiconductor chip. A semiconductor chip peeling apparatus and a semiconductor chip peeling method are disclosed in which a semiconductor chip is gradually peeled from a dicing tape by a first push-up mechanism, and then a central portion of the semiconductor chip is peeled from the dicing tape by a second push-up mechanism. Yes.

  Further, Patent Documents 2 to 5 provide a plurality of push-up mechanisms from the center of the semiconductor chip to the outer periphery of the semiconductor chip, and sequentially push up from the push-up mechanism disposed on the outer periphery of the semiconductor chip. A semiconductor chip peeling apparatus and a semiconductor chip peeling method for peeling a dicing tape in the direction from the center to the center of the semiconductor chip are disclosed.

JP 2003-124290 A JP 2005-1117019 A JP 2006-5030 A JP 2007-42996 A JP 2009-4403 A

However, Patent Documents 1 to 5 do not consider the case of peeling a thin semiconductor chip having a through electrode.
In a thin semiconductor chip having a through electrode (for example, a thickness of about 50 μm), the through electrode is formed so as to penetrate the semiconductor substrate and the circuit element layer, and the through chip is not formed. It is weaker than
Therefore, a slight stress concentration at the time of peeling the semiconductor chip from the dicing tape causes a chip crack in the semiconductor substrate with the through electrode as a base point (in other words, the semiconductor chip is damaged).

  For example, in the case of Patent Document 1, when a part of the penetrating electrode is detached from the second push-up block, when the second push-up block is pushed up, a part of the penetrating part removed from the second push-up block Since stress concentrates on the electrode, there is a possibility that a chip crack may occur with a part of the through electrode as a base point. For this reason, it is difficult to pick up a semiconductor chip having a through electrode from a dicing tape.

  According to one aspect of the present invention, the semiconductor chip is peeled from the dicing tape by pushing up the suction collet that adsorbs the surface of the semiconductor chip and the semiconductor chip attached to the dicing tape and provided with the through electrode. A semiconductor chip peeling device having a chip push-up mechanism, wherein the chip push-up mechanism is configured to be movable in a vertical direction, and at least of the through electrode of the semiconductor chip via the dicing tape. A first push-up member having a first push-up surface that pushes up the first portion corresponding to the formation region, and a structure that is movable in the vertical direction; and, among the semiconductor chips, through the dicing tape, A second push-up member having a second push-up surface that pushes up the second portion where the through electrode is not formed; The semiconductor chip peeling apparatus characterized by comprising is provided.

  According to the semiconductor chip peeling apparatus of the present invention, it is configured to be movable in the vertical direction, and the first portion of the semiconductor chip corresponding to at least the through electrode forming region is pushed up through the dicing tape. A first push-up member having a push-up surface, and a second movable member that is movable in the vertical direction, and pushes up a second portion of the semiconductor chip on which no through electrode is formed through a dicing tape. By providing a chip push-up mechanism having a second push-up member having a push-up surface, substantially the entire semiconductor chip can be pushed up by the first and second push-out surfaces, and the semiconductor chip After pushing up substantially the whole, the entire first portion corresponding to the through-electrode formation region (the region where a plurality of through-electrodes are formed) by the first push-up surface It can be pushed up to become.

  This prevents the semiconductor chip from being pushed up with some of the plurality of through-electrodes provided on the semiconductor chip being detached from the first push-up member, thereby avoiding stress concentration on the through-electrodes. It becomes.

  Therefore, it can suppress that the chip crack which makes a penetration electrode a starting point in a semiconductor substrate occurs. That is, when the semiconductor chip is pushed up through the dicing tape, the semiconductor chip can be prevented from being damaged.

It is a figure which shows typically schematic structure of the die-bonding apparatus provided with the peeling apparatus of the semiconductor chip concerning the 1st Embodiment of this invention. It is a top view which shows schematic structure of the semiconductor chip which has the penetration electrode. It is sectional drawing of the AA line direction of the semiconductor chip shown in FIG. It is the perspective view which expanded the peeling apparatus of the semiconductor chip which concerns on 1st Embodiment shown in FIG. It is a top view of the chip | tip pushing-up mechanism shown in FIG. It is sectional drawing of the CC pushing direction of the chip | tip pushing-up mechanism shown in FIG. It is sectional drawing which shows schematic structure of the adsorption | suction collet which adsorb | sucked the semiconductor chip. It is sectional drawing (the 1) which shows the manufacturing process of the semiconductor device using the peeling method of the semiconductor chip which concerns on the 1st Embodiment of this invention. It is sectional drawing (the 2) which shows the manufacturing process of the semiconductor device using the peeling method of the semiconductor chip which concerns on the 1st Embodiment of this invention. It is sectional drawing (the 3) which shows the manufacturing process of the semiconductor device using the peeling method of the semiconductor chip which concerns on the 1st Embodiment of this invention. It is sectional drawing (the 4) which shows the manufacturing process of the semiconductor device using the peeling method of the semiconductor chip which concerns on the 1st Embodiment of this invention. It is sectional drawing (the 5) which shows the manufacturing process of the semiconductor device using the peeling method of the semiconductor chip which concerns on the 1st Embodiment of this invention. It is sectional drawing (the 6) which shows the manufacturing process of the semiconductor device using the peeling method of the semiconductor chip which concerns on the 1st Embodiment of this invention. It is sectional drawing (the 7) which shows the manufacturing process of the semiconductor device using the peeling method of the semiconductor chip which concerns on the 1st Embodiment of this invention. It is sectional drawing (the 8) which shows the manufacturing process of the semiconductor device using the peeling method of the semiconductor chip which concerns on the 1st Embodiment of this invention. It is sectional drawing (the 9) which shows the manufacturing process of the semiconductor device using the peeling method of the semiconductor chip which concerns on the 1st Embodiment of this invention. It is sectional drawing (the 10) which shows the manufacturing process of the semiconductor device using the peeling method of the semiconductor chip which concerns on the 1st Embodiment of this invention. It is sectional drawing (the 11) which shows the manufacturing process of the semiconductor device using the peeling method of the semiconductor chip which concerns on the 1st Embodiment of this invention. It is sectional drawing (the 12) which shows the manufacturing process of the semiconductor device using the peeling method of the semiconductor chip which concerns on the 1st Embodiment of this invention. It is sectional drawing (the 13) which shows the manufacturing process of the semiconductor device using the peeling method of the semiconductor chip which concerns on the 1st Embodiment of this invention. It is sectional drawing (the 14) which shows the manufacturing process of the semiconductor device using the peeling method of the semiconductor chip which concerns on the 1st Embodiment of this invention. It is a top view which shows schematic structure of the chip | tip pushing-up mechanism which concerns on the 2nd Embodiment of this invention. It is a top view which shows schematic structure of the chip | tip pushing-up mechanism which concerns on the 3rd Embodiment of this invention. It is sectional drawing (the 1) for demonstrating the peeling method of the semiconductor chip using the peeling apparatus which concerns on the 4th Embodiment of this invention. It is sectional drawing (the 2) for demonstrating the peeling method of the semiconductor chip using the peeling apparatus which concerns on the 4th Embodiment of this invention. It is sectional drawing (the 3) for demonstrating the peeling method of the semiconductor chip using the peeling apparatus which concerns on the 4th Embodiment of this invention. It is sectional drawing (the 4) for demonstrating the peeling method of the semiconductor chip using the peeling apparatus which concerns on the 4th Embodiment of this invention. It is a side view which shows the 1st modification of the 1st pushing-up member which concerns on 4th Embodiment. It is a side view which shows the 2nd modification of the 1st pushing-up member which concerns on 4th Embodiment.

  Embodiments to which the present invention is applied will be described below in detail with reference to the drawings. The drawings used in the following description are for explaining the configuration of the embodiment of the present invention. The size, thickness, dimensions, and the like of each part shown in the drawings are the actual die bonding apparatus (semiconductor chip peeling). The size relationship of the semiconductor chip and the semiconductor device may be different.

(First embodiment)
FIG. 1 is a diagram schematically showing a schematic configuration of a die bonding apparatus provided with a semiconductor chip peeling apparatus according to a first embodiment of the present invention.

  Referring to FIG. 1, a die bonding apparatus 10 includes a substrate supply unit 11, a substrate transport path 12, a jig supply unit 13, a pickup unit 14, a bonding unit 16, and a semiconductor chip peeling device 17 (hereinafter referred to as “chip peeling device 17”). , Simply referred to as “peeling device 17”) and an unloader 19.

  The substrate supply unit 11 is provided at one end of the substrate transport path 12. The substrate supply unit 11 includes a wiring mother board (FIG. 1 illustrates a semiconductor device (a semiconductor device 95 (chip stacked semiconductor device) illustrated in FIG. 21 described later, which is not illustrated in FIG. 1)). A wiring mother board 71) shown in FIG. The substrate supply unit 11 supplies the wiring mother substrate to the bonding unit 16 through the substrate conveyance path 12.

The jig supply unit 13 is a structure in which a plurality of semiconductor chips (semiconductor chips 26 including through electrodes 34 shown in FIGS. 2 and 3 described later, which are not shown in FIG. 1) are formed on the pickup unit 14. (A structure shown in FIG. 10 which will be described later which is not shown in FIG. 1) is supplied, and a dicing tape (dicing tape 27 which is shown in FIG. 11 which is not shown in FIG. 1) after the pickup process is completed. Accommodate.
The jig supply unit 13 includes a frame-shaped ring jig 21. A dicing tape (not shown) is affixed to the ring jig 21, and a plurality of individual semiconductor chips (not shown) are fixed on the dicing tape.

  The pickup unit 14 includes an expander (not shown) connected to the transport mechanism, a chip push-up mechanism 23, and a chip push-up mechanism moving unit (not shown in FIG. 1 to be described later) that drives the chip push-up mechanism 23. 6 and a chip push-up mechanism moving means 45) shown in FIG. The expander holds a structure (a structure shown in FIG. 10 described later) supplied from the jig supply unit 13.

  The chip push-up mechanism 23 is disposed below a semiconductor substrate (semiconductor substrate 68 shown in FIG. 8 described later) held by an expander (not shown). The chip push-up mechanism 23 is moved in the vertical direction by a chip push-up mechanism moving means (not shown), thereby being bonded to a wiring mother board (wiring mother board 71 shown in FIG. 15 described later). 3 is peeled from the dicing tape (dicing tape 27 shown in FIG. 11).

The bonding unit 16 includes an adsorption collet 24 and an adsorption collet moving unit (the adsorption collet moving unit 38 shown in FIG. 4 which will be described later, which is not illustrated in FIG. 1) for driving the adsorption collet 24.
The bonding unit 16 is peeled from the dicing tape (the dicing tape 27 shown in FIG. 11) by the pickup unit 14 by moving the suction collet 24 in the vertical direction by the suction collet moving unit (the suction collet moving unit 38 shown in FIG. 4). The surface of the semiconductor chip to be formed (the surface 26a of the semiconductor chip 26 shown in FIGS. 2 and 3) is sucked and held, then the semiconductor chip is picked up, and then the wiring mother board (wiring mother board 71 shown in FIG. 15 described later). The semiconductor chip is bonded to the substrate.

The peeling device 17 of the first embodiment includes a chip push-up mechanism 23 provided in the pickup unit 14, an adsorption collet 24 and an adsorption collet moving unit 38 (not shown in FIG. 1) provided in the bonding unit 16. 4) to be described later.
A specific description of the configuration of the peeling device 17 will be described later with reference to FIGS.

  The unloader unit 19 is provided at the other end of the substrate transport path 12. The unloader unit 19 accommodates a wiring board (not shown) on which a semiconductor chip (not shown) is mounted.

FIG. 2 is a plan view showing a schematic configuration of a semiconductor chip having through electrodes, and FIG. 3 is a cross-sectional view of the semiconductor chip shown in FIG.
Here, the configuration of the semiconductor chip 26 that is peeled from the dicing tape (the dicing tape 27 shown in FIG. 11) by the peeling device 17 will be described.
With reference to FIGS. 2 and 3, the semiconductor chip 26 includes a semiconductor substrate 31, a circuit element layer 32, a through electrode 34, a front electrode 35, and a back electrode 36.

  2 and 3, the semiconductor substrate 31 has a rectangular shape and is thinned (for example, 50 μm or less). The back surface 31 b of the semiconductor substrate 31 is a surface corresponding to the back surface 26 b of the semiconductor chip 26. As the semiconductor substrate 31, for example, a thinned silicon substrate (silicon wafer) can be used.

  Referring to FIG. 3, the circuit element layer 32 is formed on the surface 31 a of the semiconductor substrate 31. The circuit element layer 32 includes a transistor (not shown) formed on the surface 31a of the semiconductor substrate 31, a plurality of insulating layers (not shown) covering the transistor, and a plurality of wirings formed on the plurality of insulating layers. And a multilayer wiring structure (not shown) constituted by vias (not shown). The surface 32 a of the circuit element layer 32 is a surface corresponding to the surface 26 a of the semiconductor chip 26.

  When the semiconductor chip 26 is an IF (Interface) semiconductor chip, an IF circuit for controlling the memory semiconductor chip is formed in the circuit element layer 32. When the semiconductor chip 26 is a memory semiconductor chip (for example, DRAM (Dynamic Random Access Memory)), a DRAM element is formed in the circuit element layer 32.

Referring to FIGS. 2 and 3, a plurality of through electrodes 34 are formed so as to penetrate the semiconductor substrate 31 and the circuit element layer 32. The plurality of through-electrodes 34 are through-vias, and are arranged on the inner side (specifically, the central portion of the semiconductor chip 26) than the outer periphery of the semiconductor chip 26. In other words, the semiconductor chip 26 has a through electrode group (a region in which the plurality of through electrodes 34 are formed) at the center thereof.
One end 34 a of the through electrode 34 is exposed from the front surface 26 a of the semiconductor chip 26, and the other end 34 b of the through electrode 34 is exposed from the back surface 26 b of the semiconductor chip 26.

  Referring to FIG. 3, the surface electrode 35 is provided at one end 34 a of the through electrode 34 and protrudes from the surface 26 a of the semiconductor chip 26. The front surface electrode 35 is an electrode that is electrically connected to the back surface electrode 36 provided on the semiconductor chip 26 disposed above when the semiconductor chips 26 are stacked. As the surface electrode 35, for example, a bump (for example, a height of 15 μm) can be used.

  Referring to FIG. 3, the back electrode 36 is provided at the other end 34 b of the through electrode 34 and protrudes from the back surface 26 b of the semiconductor chip 26. When the semiconductor chip 26 is stacked, the back surface electrode 36 is a back surface electrode 36 provided on the semiconductor chip 26 disposed below or a pad (not shown) shown in FIG. The electrodes are electrically connected to the connection pads 77) of the mother board 51. As the back electrode 36, for example, a bump (for example, a height of 10 μm) can be used.

2 and 3, the semiconductor chip 26 configured as described above includes a first portion 26-1 corresponding to the formation region B of the through electrode 34 and a second portion in which the through electrode 34 is not formed. Part 26-2.
In addition, the semiconductor chip 26 having the above-described configuration is a chip that is thin (for example, 50 μm or less in thickness) and has a through electrode 34 and is easily damaged when an external force is applied.

When a plurality of the semiconductor chips 26 are stacked to form a semiconductor device 95 (chip stacked semiconductor device) shown in FIG. 21 to be described later, for example, an IF (Interface) semiconductor as the semiconductor chip 26 disposed in the lowermost layer. While using a chip, a semiconductor chip for memory (for example, DRAM) can be used as the other semiconductor chip 26.
In this way, by using an IF semiconductor chip as the semiconductor chip 26 arranged in the first stage, signals between a plurality of memory semiconductor chips and a wiring board (wiring board 74 shown in FIG. 21 described later) are transmitted. Can communicate.

  FIG. 4 is an enlarged perspective view of the semiconductor chip peeling apparatus according to the first embodiment shown in FIG. FIG. 5 is a plan view of the chip push-up mechanism shown in FIG. 4, and FIG. 6 is a cross-sectional view of the chip push-up mechanism shown in FIG.

In FIG. 4, the illustration of the tip push-up mechanism moving means 45 shown in FIG. Further, in FIG. 5, for convenience of explanation, the semiconductor chip 26 shown in FIGS. 2 and 3 that is not a component of the chip push-up mechanism 23 is illustrated by an imaginary line. Further, in FIG. 5, illustration of the chip push-up mechanism moving unit 45 shown in FIG. 6 which is a component of the chip push-up mechanism 23 is omitted.
Further, in FIG. 6, for convenience of explanation, the semiconductor chip 26 shown in FIGS. 2 and 3, which is not a component of the chip push-up mechanism 23, and the dicing tape 27 attached to the back surface 26 b of the semiconductor chip 26 are illustrated by imaginary lines. To do. Moreover, the Y direction in FIG. 6 has shown the moving direction (up-down direction) of the 1st and 2nd pushing-up member 43,44.

Next, with reference to FIGS. 4-6, the specific structure of the peeling apparatus 17 is demonstrated.
4 to 6, the peeling device 17 includes a tip push-up mechanism 23, a suction collet 24, and a suction collet moving means 38.
4 to 6, the tip push-up mechanism 23 includes a suction stage 41, a first push-up member 43, a second push-up member 44, a tip push-up mechanism moving unit 45, and a first suction unit. 46 and a second suction portion 47.

Referring to FIG. 4, the suction stage 41 is disposed below the suction collet 24. Referring to FIGS. 4 and 5, the outer shape of the suction stage 41 is circular. The suction stage 41 is provided outside the second push-up member 44.
The suction stage 41 includes an opening 51, a suction surface 41a, and a third suction portion 53. The opening 51 is provided at substantially the center of the suction stage 41. The opening 51 is a space for accommodating the first and second push-up members 43 and 44. Referring to FIG. 5, the opening 51 has a rectangular shape and is slightly smaller than the outer shape of the semiconductor chip 26.

  Referring to FIG. 6, the suction surface 41a (the upper surface of the suction stage 41) is a flat surface. The suction surface 41 a is a surface that comes into contact with the back surface 27 b of the dicing tape 27 attached to the back surface 26 b of the semiconductor chip 26.

  Referring to FIGS. 4 to 6, a plurality of third suction portions 53 are provided in a portion of the suction stage 41 that constitutes the suction surface 41 a. The third suction portion 53 is a suction hole that is circular in plan view. The 3rd adsorption | suction part 53 is connected with the vacuum device which is not shown in figure. Accordingly, the third suction unit 53 sucks and holds the dicing tape 27 on the suction surface 41 a of the suction stage 41.

  4 to 6, the first push-up member 43 is disposed in an opening 55 described later provided in the center of the second push-up member 44. That is, the first push-up member 43 is provided inside the second push-up member 44.

Referring to FIG. 6, the first push-up member 43 is independent of the second push-up member 44 by the first moving means 45-1 (see FIG. 6) constituting the tip push-up mechanism moving means 45. It is configured to be movable in the Y direction (vertical direction).
The first push-up member 43 has a first push-up surface 43a that comes into contact with the back surface 27b of the dicing tape 27 to which the semiconductor chip 26 is attached. The first push-up surface 43a is a flat surface.

Referring to FIG. 5, the first push-up surface 43 a is disposed on the entire first portion 26-1 of the semiconductor chip 26 (the portion corresponding to the formation region B of the through electrode 34 shown in FIG. 3) via the dicing tape 27. It is the size that can push up the whole).
As a result, the first push-up member 43 is brought into the state shown in FIG. 6 (the suction face 41a, the first push-out face 43a, and the second push-out face 44a are substantially on the same plane by the first moving means 45-1. The first portion 26-1 of the semiconductor chip 26 is pushed up through the dicing tape 27. The shape of the first push-up member 43 can be a rectangular parallelepiped, for example.

Referring to FIGS. 4 to 6, the second push-up member 44 is disposed in the opening 51 located outside the first push-up member 43. That is, the second push-up member 44 is disposed between the first push-up member 43 and the suction stage 41. The outer shape of the second push-up member 44 is a rectangle in a plan view.
The second push-up member 44 has an opening 55 and a notch 56. The opening 55 is provided at the center of the second push-up member 44. The opening 55 is a space for accommodating the first push-up member 43.
The notches 56 are respectively formed on the four outer walls of the second push-up member 44 corresponding to the formation region of the second suction part 47.

Referring to FIG. 6, the second push-up member 44 is moved in the Y direction independently of the first push-up member 43 by a second moving means 45-2, which will be described later, provided in the chip push-up mechanism moving means 45. It is configured to be movable in the (vertical direction).
The second push-up member 44 has a second push-up surface 44a that comes into contact with the back surface 27b of the dicing tape 27 to which the semiconductor chip 26 is attached. The second push-up surface 44a is a flat surface.
Referring to FIGS. 5 and 6, the outer shape of the portion of the second push-up member 44 that contacts the dicing tape 27 is configured to be smaller than the outer shape of the semiconductor chip 26.

Referring to FIG. 5, the second push-up surface 44a is formed on the second portion 26-2 where the through electrode 34 of the semiconductor chip 26 is not formed via the dicing tape 27 (in the case of the first embodiment). The portion surrounding the first portion 26-1 and the portion disposed slightly inside the outer peripheral edge of the semiconductor chip 26) can be pushed up.
Thereby, when the second push-up member 44 is moved upward from the state shown in FIG. 6 by the second moving means 45-2, the second portion of the semiconductor chip 26 is interposed via the dicing tape 27. Push up 26-1.

Referring to FIG. 6, the tip push-up mechanism moving unit 45 includes a first moving unit 45-1 and a second moving unit 45-2.
The first moving unit 45-1 is a drive unit that moves the first push-up member 43 in the Y direction (vertical direction) independently of the second push-up member 44. The second moving unit 45-2 is a drive unit that moves the second push-up member 44 in the Y direction (vertical direction) independently of the first push-up member 43.

4 to 6, the first suction portion 46 is provided on the outer peripheral edge of the first push-up member 43. The first suction portion 46 is formed by a gap formed between the outer wall of the first push-up member 43 and the surface of the second push-up member 44 constituting the opening 55, and has a frame shape. It is a groove.
The 1st adsorption | suction part 46 is connected with the vacuum device which is not shown in figure. Thereby, the 1st adsorption | suction part 46 adsorb | sucks the dicing tape 27 in the state shown in FIG.

4 to 6, the second suction portion 47 is provided on the outer peripheral edge of the second push-up member 44. The second suction portion 47 is a groove-like space formed between the notch portion 56 and the surface of the second push-up member 44 facing the notch portion 56.
The second suction unit 47 is connected to a vacuum device (not shown). Thereby, the 2nd adsorption | suction part 47 adsorb | sucks the dicing tape 27 in the state shown in FIG.

FIG. 7 is a cross-sectional view showing a schematic configuration of an adsorption collet that adsorbs a semiconductor chip. 7, the same components as those of the semiconductor chip 26 shown in FIG.
Referring to FIG. 7, the suction collet 24 has a suction surface 24 a, suction holes 61 and 63, and a recess 62.
The suction surface 24a is a flat surface, and when the suction collet 24 sucks the semiconductor chip 26, the surface that contacts the surface 26a-2 of the second portion 26-2 of the surface 26a of the semiconductor chip 26. It is.

  A plurality of suction holes 61 are provided in a portion of the suction collet 24 that constitutes the suction surface 24a. The suction hole 61 is connected to a vacuum device (not shown). Thereby, the suction hole 61 sucks the surface 26a-2 of the second portion 26-2 of the semiconductor chip 26.

  The recess 62 is a recess that is recessed with respect to the suction surface 24 a and is provided in the center of the suction collet 24. The recess 62 exposes the first portion 26-1 (in other words, the portion corresponding to the through electrode group) located on the surface 26 a side of the semiconductor chip 26 when the suction collet 24 sucks the semiconductor chip 26. Is formed. In addition, the recess 62 has a plurality of surface electrodes 35 provided on the semiconductor chip 26 without contacting the surface electrode 35 (electrode protruding from the surface 26 a of the semiconductor chip 26) with the surface of the suction collet 24 constituting the recess 62. Can be accommodated.

As described above, the suction collet 24 and the surface electrode 35 come into contact with each other by providing the suction collet 24 with the recesses 62 that accommodate the plurality of surface electrodes 35 provided in the first portion 26-1 of the semiconductor chip 26. Nothing will happen.
Thereby, it is possible to avoid stress concentration on the through electrode 34 via the surface electrode 35. Therefore, when the semiconductor chip 26 is adsorbed by the adsorption collet 24, it is possible to suppress the occurrence of chip cracks starting from the through electrode 24 in the semiconductor substrate 31. In other words, the suction collet 24 can prevent the semiconductor chip 26 from being damaged when the semiconductor chip 26 is sucked.

  The width of the recess 62 is preferably slightly larger than the outer shape of the first portion 26-1 of the semiconductor chip 26 in consideration of the clearance when the suction collet 24 sucks the semiconductor chip 26. Specifically, the width of the recess 62 is preferably formed to be about 100 μm larger than the outer shape of the first portion 26-1 of the semiconductor chip 26.

The suction hole 63 is provided on the bottom surface 62 a of the recess 62. The suction hole 63 is connected to a vacuum device (not shown). Thereby, the suction hole 61 sucks and holds the first portion 26-1 of the semiconductor chip 26 exposed in the recess 62.
Therefore, the distance D ₁ of the and the bottom surface 62a of the front electrode 35 and the recess 62 is large (in other words, the deeper the recess 62) and, since the warpage occurs in the semiconductor chip 26, the specific location of the semiconductor chip 26 Stress is concentrated.
Therefore, the distance D ₁ of the and the bottom surface 62a of the front electrode 35 and the recess 62 when the suction collet 24 is adsorbed to the semiconductor chip 26 is preferably smaller. Distance _{D 1} of the and the bottom surface 62a of the front electrode 35 and the recess 62 may be, for example, to 100 [mu] m.

  Referring to FIG. 4, the suction collet moving means 38 is a drive unit that moves the suction collet 24 in the vertical direction (the direction shown in FIG. 6) and the plane direction orthogonal to the vertical direction.

  According to the semiconductor chip peeling apparatus of the first embodiment, it is configured to be movable in the vertical direction, and the first corresponding to the formation region B of the through electrode 34 in the semiconductor chip 26 via the dicing tape 27. A first push-up member 43 having a first push-up surface 43 a that pushes up the first portion 26-1, and a structure that is movable in the vertical direction, and the through-electrode of the semiconductor chip 26 through the dicing tape 27. By providing the tip push-up mechanism 23 including the second push-up member 44 having the second push-up surface 44a that pushes up the second portion 26-2 in which the 34 is not formed, the first push-up member 43 The first and second projecting surfaces 43A and 44a can push up substantially the entire semiconductor chip 26 and project almost the entire semiconductor chip 26. After raising, the first pushing-up surface 43a, it is possible to push up the entire first part 26-1 corresponding to the formation region B of the through electrode 34.

  Accordingly, the semiconductor chip 26 is not pushed up in a state where a part of the plurality of through electrodes 34 provided on the semiconductor chip 26 is detached from the first push-up surface 43a, so that stress is concentrated on the through-electrode 34. Can be avoided.

  Therefore, it is possible to suppress the occurrence of chip cracks having the through electrode 34 as a base point in the semiconductor substrate 31. That is, when the semiconductor chip 26 is pushed up via the dicing tape 27, the semiconductor chip 26 can be prevented from being damaged.

  8 to 21 are cross-sectional views showing a manufacturing process of a semiconductor device using the semiconductor chip peeling method according to the first embodiment of the present invention. 8 to 21, the same components as those of the semiconductor chip 26 (see FIG. 3) and the peeling device 17 (see FIGS. 4 to 6) described above are denoted by the same reference numerals.

  Next, with reference to FIG. 8 to FIG. 21, in the description of the method for manufacturing the semiconductor device 95 (chip stacked semiconductor device) shown in FIG. 21, the method for peeling the semiconductor chip 26 of the first embodiment. explain. In addition, the process shown in FIGS. 11-14 is a figure corresponding to the peeling method of the semiconductor chip 26 which concerns on 1st Embodiment.

  First, in the step shown in FIG. 8, a dicing tape 27 is prepared that is attached to the frame-shaped ring jig 21 (see FIG. 1). Next, on the surface 27a of the dicing tape 27 exposed from the ring jig 21, a plurality of semiconductor chips 26 (through electrodes 34, surface electrodes 35 (for example, 15 μm in height), and back electrodes 36 (for example, 10 μm in height)). The back surface 68a of the semiconductor substrate 68 on which the semiconductor chip having the) is formed is attached.

The dicing tape 27 has a tape body 66 and an adhesive layer 67. The adhesive layer 67 is formed on the tape body 66. The upper surface of the adhesive layer 67 is a surface corresponding to the surface 27 a of the dicing tape 27. The lower surface of the tape body 66 is a surface corresponding to the back surface 27 b of the dicing tape 27.
In the step shown in FIG. 8, the semiconductor substrate 68 is attached to the dicing tape 27 so that the back electrode 36 is embedded in the adhesive layer 67.

  Further, as the adhesive layer 67, for example, a UV tape having a characteristic that a chemical reaction is caused in the component of the adhesive material by ultraviolet (UV) irradiation and the adhesive force of the adhesive layer 67 is reduced can be used. In the present embodiment, the following description will be given by taking the case of using the UV tape as the dicing tape 27 as an example.

  Referring to FIG. 8, the semiconductor substrate 68 has a plurality of chip formation regions E, and the semiconductor chip 26 (for example, a thickness of 50 μm or less) shown in FIG. ing. At this stage, the plurality of semiconductor chips 26 formed on the semiconductor substrate 68 are connected (in other words, not separated into individual pieces).

The semiconductor substrate 68 has a dicing line 69 that partitions the chip formation region E. The semiconductor substrate 68 is a substrate that becomes a plurality of semiconductor substrates 31 (see FIG. 3) by cutting the dicing lines 69 by a dicer.
The back surface 68a of the semiconductor substrate 68 is a surface corresponding to the back surface 31b (the back surface 26b of the semiconductor chip 26) of the semiconductor substrate 31 shown in FIG. As the semiconductor substrate 68, for example, a thinned silicon wafer can be used.

Next, in the process shown in FIG. 9, the circuit element layer 32 and the semiconductor substrate 68 corresponding to the dicing line 69 shown in FIG. 8 are cut to singulate a plurality of semiconductor chips 26. At this time, the circuit element layer 32 and the semiconductor substrate 68 are cut (full cut) so that a part of the adhesive layer 67 located below the dicing line 69 is cut.
Specifically, for example, after the structure shown in FIG. 8 is fixed to a dicing table (not shown) of a dicing apparatus (not shown), a dicing blade 69 (not shown) that rotates at high speed is used. The circuit element layer 32 and the semiconductor substrate 68 corresponding to the above are cut by rotating and grinding.

Next, in the process shown in FIG. 10, the adhesive layer 67 is applied to the adhesive layer 67 from the back surface 27 b side of the dicing tape 27 to which a plurality of separated semiconductor chips 26 are attached by an ultraviolet (UV) irradiation device (not shown). Irradiate with UV light (ultraviolet light).
As described above, in this embodiment, a UV tape that causes a chemical reaction in the component of the adhesive material by ultraviolet (UV) irradiation and reduces the adhesive strength of the adhesive layer 67 is used. Therefore, by irradiating the adhesive layer 67 with UV light, the semiconductor chip 26 adhered and fixed on the dicing tape 27 can be easily peeled off.

  Next, in the step shown in FIG. 11, the suction surface 41 a of the suction stage 41, the first protrusion surface 43 a of the first protrusion member 43, and the second of the second protrusion member 44 disposed inside the suction stage 41. The rear surface of the dicing tape 27 in which a plurality of semiconductor chips 26 are bonded to the suction surface 41a, the first protrusion surface 43a, and the second protrusion surface 44a. Adsorb 27b.

Specifically, a plurality of semiconductor chips 26 attached to a dicing tape 27 are supplied to an expander (not shown) of the pickup unit 14 of the die bonding apparatus 10 shown in FIG. Next, a semiconductor chip 26 to be picked up is placed on the chip push-up mechanism 23 by a moving mechanism provided in an expander (not shown).
At this time, the semiconductor chip 26 is disposed so that the first portion 26-1 of the semiconductor chip 26 faces the recess 62 of the suction collet 24.
Next, the back surface 27b of the dicing tape 27 is brought into close contact with the chip push-up mechanism 23 by vacuum suction of the first suction portion 46, the second suction portion 47, and the third suction portion 53 by a vacuum device (not shown). Let

Next, in the step shown in FIG. 12, from the state shown in FIG. 11 (the state where the first and second protruding surfaces 43a and 44a are substantially flush with the suction surface 41a), the first and second protruding surfaces are formed. By moving the first and second push-up members 43 and 44 upward by the same amount by the tip push-up mechanism moving means 45 so that 43a and 44a are arranged above the suction surface 41a, they are substantially on the same plane. The substantially entire semiconductor chip 26 is pushed up by the first and second push-up surfaces 43a and 44a arranged.
Thereby, the back surface 26b located in the vicinity of the outer peripheral edge of the second portion 26-2 of the semiconductor chip 26 is peeled off from the dicing tape 27.

  Next, in the step shown in FIG. 13, from the state shown in FIG. 12, the first moving means 45- is arranged so that the position of the first push-up surface 43a is arranged above the position of the second push-up face 44a. 1, the entire first portion 26-1 of the semiconductor chip 26 is pushed up by moving the first push-up surface 43 a upward.

Thereby, the dicing tape 27 is peeled from the vicinity of the outer peripheral edge of the second portion 26-2 (the portion where the dicing tape 27 is peeled) toward the center of the semiconductor chip 26, and the semiconductor chip 26 and the dicing tape 27 are bonded to each other. The area is reduced, and only the first portion 26-1 of the semiconductor chip 26 is attached to the dicing tape 27.
Next, the surface 26 a of the semiconductor chip 26 is adsorbed by the adsorption collet 24 so that the surface electrode 35 formed in the first portion 26-1 of the semiconductor chip 26 is accommodated in the recess 62.

  Next, in the step shown in FIG. 14, the first push-up member 43 is moved downward from the state shown in FIG. Thereby, the semiconductor chip 26 is separated from the dicing tape 27, and the dicing tape 27 is peeled off from the entire back surface 26 b of the semiconductor chip 26. Thereafter, the positions of the first and second push-up surfaces 43a and 44a are adjusted so that the first and second push-up surfaces 43a and 44a are substantially flush with the suction surface 41a.

  In this way, after the substantially entire semiconductor chip 26 is pushed up with the first and second push-up surfaces being substantially flush with each other, the plurality of through electrodes 34 are formed by the first push-up member 43. The entire first portion 26-1 of the semiconductor chip 26 is further pushed up, and then the first push-up member 43 is moved downward to peel the semiconductor chip 26 from the dicing tape 27, thereby providing the semiconductor chip 26. In addition, since the semiconductor chip 26 is not pushed up in a state in which a part of the plurality of through electrodes 34 is detached from the first push-up member 43, it is possible to avoid stress concentration on the through-electrode 34.

  As a result, even when the thinned semiconductor chip 26 (in other words, a semiconductor chip that is easily damaged) having the through electrodes 34 is peeled off from the dicing tape 27, stress is concentrated on some of the through electrodes 34. This can be avoided.

  Therefore, it is possible to suppress the occurrence of chip cracks with the through electrode 34 as a base point in the semiconductor substrate 31. That is, when the semiconductor chip 26 is pushed up via the dicing tape 27, the semiconductor chip 26 can be prevented from being damaged.

  Further, by adsorbing the semiconductor chip 26 so that the surface electrode 35 formed in the first portion 26-1 of the semiconductor chip 26 is accommodated in the recess 62 provided in the adsorption collet 24, the surface electrode 35 and the adsorption collet 24 do not come into contact with each other. Thereby, when the semiconductor chip 26 is adsorbed by the adsorbing collet 24, it is possible to suppress the occurrence of chip cracks with the through electrode 34 as a starting point in the semiconductor substrate 31. That is, when the semiconductor chip 26 is pushed up via the dicing tape 27, the semiconductor chip 26 can be prevented from being damaged.

Next, in a process shown in FIG. 15, a wiring mother board 71 used for manufacturing the semiconductor device 95 (chip stacked semiconductor device) shown in FIG. 21 is prepared.
The wiring mother board 71 is arranged in a matrix, and includes a plurality of semiconductor device formation regions F in which the semiconductor devices 95 are formed, a dicing line 73 surrounding each semiconductor device formation region F, and the outside of the plurality of semiconductor device formation regions F. And a positioning hole (not shown) that is arranged in the frame at a predetermined interval and is used when the wiring mother board 71 is transported and positioned.

  The wiring mother board 71 is a board processed by a MAP (Mold Array Process) method. The wiring mother board 71 is cut along the dicing line 73 to become a wiring board 74 (see FIG. 21 described later) which is one of the components of the semiconductor device 95 shown in FIG. That is, the wiring mother board 71 has a configuration in which a plurality of wiring boards 74 are connected.

Here, the configuration of the wiring board 74 will be described.
Referring to FIG. 15, the wiring substrate 74 includes a substrate body 76, connection pads 77, lands 79, a wiring pattern 81, and solder resists 83 and 84. The thickness of the wiring board 74 can be set to 0.2 mm, for example.
The substrate body 76 is substantially rectangular and has a flat front surface 76a and a back surface 76b. As the substrate body 76, for example, a glass epoxy substrate can be used.

The connection pad 77 is provided on the surface 76 a of the substrate body 76. A chip stack 86 shown in FIG. 16 described later is mounted on the connection pad 77. The land 79 is provided on the back surface 76 b of the substrate body 76.
The wiring pattern 81 is provided in the board body 76. One end of the wiring pattern 81 is connected to the connection pad 77, and the other end of the wiring pattern 81 is connected to the land 79.

The solder resist 83 is provided on the surface 76a of the substrate body 76 so as to expose the upper surface 77a of the connection pad 77 (the surface on which a chip stack 86 shown in FIG. 16 described later is mounted).
The solder resist 84 is provided on the back surface 76b of the substrate body 76 so as to expose the lower surface of the land 79 (the surface on which an external connection terminal 93 shown in FIG. 19 described later is mounted).

  In the step shown in FIG. 15, after preparing the wiring mother board 71, bumps (not shown) are formed on the upper surface 77 a of the connection pad 77. The bumps are formed, for example, by bonding an Au wire to the upper surface 77a of the connection pad 77 by ultrasonic thermocompression bonding using a bonding apparatus (not shown), and then cutting the rear end of the Au wire (wire stud bump method). .

Next, in the step shown in FIG. 16, a bump (not shown) formed on the upper surface 77a of the connection pad 77 is brought into contact with the back electrode 36 of the semiconductor chip 26 disposed in the lowermost layer of the chip stack 86, and thereafter By melting the bump (not shown) and the back electrode 36 (for example, a bump having a height of 10 μm) at a low temperature (for example, 150 ° C.), the semiconductor chip 26 (one step) is connected to the connection pad 77 of the wiring mother board 71. The semiconductor chip of the eye) is temporarily fixed.
At this time, for example, an IF semiconductor chip can be used as the semiconductor chip 26 disposed in the lowermost layer of the chip stacked body 86.

  Next, the back surface electrode 36 of the semiconductor chip 26 disposed in the second stage from the bottom of the chip stacked body 86 and the surface electrode 35 of the semiconductor chip 26 disposed in the lowermost layer of the chip stacked body 86 (for example, having a height of 15 μm). The semiconductor chip 26 arranged in the second stage is arranged on the semiconductor chip 26 arranged in the lowermost layer so that the bumps are in contact with each other.

  Thereafter, the front surface electrode 35 and the back surface electrode 36 are melted at a low temperature (for example, 150 ° C.), so that the semiconductor chip 26 disposed in the second stage is temporarily fixed onto the semiconductor chip 26 disposed in the lowermost layer. . As the semiconductor chip 26 arranged in the second stage, a semiconductor chip for memory (for example, DRAM) can be used.

Next, two semiconductor chips 26 (in other words, the third and fourth stages) are formed on the semiconductor chip 26 arranged in the second stage by a method similar to the method of mounting the semiconductor chip 26 arranged in the second stage. The semiconductor chips 26) arranged at the stage are temporarily fixed sequentially.
As the semiconductor chips 26 arranged in the second and fourth stages, memory semiconductor chips (for example, DRAMs) can be used.

  Thereafter, the plurality of stacked semiconductor chips 26 (four chip semiconductors 26 in the case of the present embodiment) are heated to a high temperature (for example, 300 ° C.) and a load is applied, whereby the back electrode of the semiconductor chip 26 is obtained. 36 and bumps (not shown) of the wiring mother board 71, and the front electrode 35 and the back electrode 36 are completely crimped.

As a result, a plurality of semiconductor chips 26 are electrically connected, and the chip stack 86 (the plurality of semiconductor chips 26 is stacked) is electrically connected to the wiring mother board 71 (the base material of the wiring board 74). Structure) is formed.
At this time, gaps are formed between the semiconductor chips 26 and between the semiconductor chip 26 and the wiring motherboard 71.

  In the above description, the case where the plurality of semiconductor chips 26 and the wiring motherboard 71 are electrically connected by applying a load after temporary fixing has been described as an example. However, for example, an ultrasonic wave is applied. Thus, the front electrode 35 and the back electrode 36, and the back electrode 36 of the semiconductor chip 26 and the connection pads 77 of the wiring mother board 71 (wiring board 74) may be electrically connected. Further, every time one semiconductor chip among the plurality of semiconductor chips 26 is stacked, the main pressure bonding may be performed by pressurizing at a high temperature without temporarily fixing.

  Next, in the step shown in FIG. 17, the gap formed between the semiconductor chips 26 and the gap formed between the semiconductor chip 26 and the wiring board 74 are filled, and the outer peripheral side face 86a and the upper face 86b of the chip stack 86 are filled. And a first sealing body 89 that seals the chip stack 86 is formed.

Specifically, for example, an underfill resin 88 (a base material of the first sealing body 89) having a smaller elastic force (Young's modulus) than a second sealing body 91 shown in FIG. By dropping and supplying to the upper surface 86b of 86, the gap formed between the semiconductor chips 26 and the gap formed between the semiconductor chip 26 and the wiring motherboard 71 are filled by capillary action.
At this time, the upper surface 86b of the chip stacked body 86 is covered with the underfill resin 88 supplied dropwise. Further, the outer peripheral side surface 86a of the chip stacked body 86 is covered with an underfill resin 88 that moves below the chip stacked body 86 due to gravity.

  As a result, the gap formed between the semiconductor chips 26 and the gap formed between the semiconductor chip 26 and the wiring mother board 71 are filled, and the underfill covering the outer peripheral side surface 86a and the upper surface 86b of the chip stack 86 is provided. Resin 88 is formed. At this stage, the underfill resin 88 has not yet been cured.

  Next, by curing the underfill resin 88, the first sealing body has a smaller elastic force (Young's modulus) than the second sealing body 91 shown in FIG. 18 and seals the chip stack 86. A plurality of 89 are formed.

  Specifically, when a thermosetting resin is used as the underfill resin 88, the unfilled underfill resin 88 is thermoset at a temperature of 150 ° C. As the underfill resin 88 serving as a base material of the first sealing body 89, for example, silicone rubber can be used.

  Next, in the step shown in FIG. 18, a plurality of first sealing bodies 89 are sealed on the upper surface of the wiring mother board 71 (the surface formed by the upper surface 77a of the connection pad 77 and the upper surface 83a of the solder resist 83); A second sealing body 91 having a larger elastic force (Young's modulus) than the first sealing body 89 and having a flat upper surface 91a is formed.

  The second sealing body 91 is formed by, for example, a transfer mold method. When the transfer molding method is used, the structure shown in FIG. 17 is placed in a cavity (not shown) formed in upper and lower molds (not shown), and then, for example, an epoxy resin or the like is placed in the cavity. The second sealing body 91 is formed by filling the thermosetting resin, and then thermally curing the epoxy resin in the cavity by heating. Thereafter, the structure shown in FIG. 18 is taken out from upper and lower molds (not shown).

  In FIG. 18, the case where the second sealing body 91 is formed by the transfer molding method has been described as an example, but a compression molding apparatus that is less influenced by the flow of the mold resin is used (in other words, compression). The second sealing body 91 may be formed by a molding method.

  Thus, using a material having a smaller elastic force than the second sealing body 91, the gap formed between the semiconductor chips 26 and the chip stack 86 and the upper surface of the wiring mother board 71 are formed. The first sealing body 89 that fills the gaps and covers the upper surface 86b and the outer peripheral side surface 86a of the chip stack 86 is formed, and then the second sealing body 91 that covers the first sealing body 89 is formed. By forming it, it is possible to make it difficult for internal stress generated inside the semiconductor device 95 to be transmitted to the plurality of semiconductor chips 26.

As a result, it is possible to prevent damage to the plurality of semiconductor chips 26 and to make it difficult for internal stress to be transmitted to the connection portion between the semiconductor chips 26 and the connection portion between the semiconductor chip 26 and the wiring board 74. It becomes.
Therefore, the reliability of electrical connection between the plurality of semiconductor chips 26 and between the chip stack 86 and the wiring board 74 can be improved. That is, the yield of the semiconductor device 95 can be improved.

Next, in the step shown in FIG. 19, the structure shown in FIG. 18 is turned upside down. Next, external connection terminals 93 are mounted on lands 79 provided on the wiring motherboard 71.
Specifically, the external connection terminal 93 is adsorbed to a plurality of adsorption holes (not shown) provided in a ball mount tool (not shown), and then a flux (not shown) is applied to the adsorbed external connection terminal 93. ).

  Next, the external connection terminals 93 on which flux (not shown) is formed are collectively mounted on the plurality of lands 79 arranged in the semiconductor device formation region F. Next, external connection terminals 93 are mounted on all lands 79 provided on the wiring mother board 71, and then the wiring mother board 71 is heated to fix the external connection terminals 93 to the lands 79.

  As a result, the semiconductor devices 95 are formed in the plurality of semiconductor device formation regions F of the wiring motherboard 71, respectively. At this stage, the plurality of semiconductor devices 95 are connected to the adjacent semiconductor devices 95 and are not separated.

  Next, in the step shown in FIG. 20, the wiring mother board 71 on which the structure shown in FIG. 19 (specifically, the chip stacked body 86, the first sealing body 89, and the second sealing body 91 is formed). The dicing tape 93 is affixed to the upper surface 91a of the second sealing body 91 provided in FIG. Accordingly, the structure shown in FIG. 19 is supported by the dicing tape 93.

  Next, the wiring mother board 71 and the second sealing body 91 are cut along the dicing line 73 by a dicing blade (not shown) provided in a dicing apparatus (not shown), thereby a plurality of semiconductor devices. 95 is divided into pieces.

  Next, in the step shown in FIG. 21, a plurality of semiconductor devices 95 attached to the dicing tape 96 shown in FIG. 20 are picked up. Thereafter, the plurality of picked up semiconductor devices 95 are turned upside down to produce the plurality of semiconductor devices 95 shown in FIG.

  According to the semiconductor chip peeling method of the first embodiment, the first and second push-up members 43 and 44 make the first and second push-ups 43a and 44a substantially flush with each other. After pushing up substantially the entire chip 26, the first push-up surface 43a pushes up the entire first portion 26-1 of the semiconductor chip 26 in which the plurality of through electrodes 34 are formed, and then the suction collet 24 By adsorbing the surface 26 a of the semiconductor chip 26, and then moving the first push-up surface 43 a downward and peeling the semiconductor chip 26 from the dicing tape 27, a plurality of through electrodes 34 provided on the semiconductor chip 26. Since the semiconductor chip 26 is not pushed up in a state where a part of the chip is removed from the first push-up member 43, stress is concentrated on the through electrode 34. It is possible to avoid the Rukoto.

  As a result, even when the thinned semiconductor chip 26 (in other words, a semiconductor chip that is easily damaged) having the through electrodes 34 is peeled off from the dicing tape 27, stress is concentrated on some of the through electrodes 34. This can be avoided.

  Therefore, it is possible to suppress the occurrence of chip cracks with the through electrode 34 as a base point in the semiconductor substrate 31. That is, when the semiconductor chip 26 is pushed up via the dicing tape 27, the semiconductor chip 26 can be prevented from being damaged.

In the first embodiment, a case where a semiconductor chip having only one through electrode group at the center is peeled off from the dicing tape 27 as an example of the semiconductor chip 26 has been described. The present invention is also applicable to a semiconductor chip having a plurality of through electrode groups.
In this case, by providing the second push-up member corresponding to each of the plurality of through electrode groups, the same effect as the peeling device 17 of the semiconductor chip 26 and the peeling method of the semiconductor chip 26 of the first embodiment can be obtained. Obtainable.

(Second Embodiment)
FIG. 22 is a plan view showing a schematic configuration of a tip push-up mechanism according to the second embodiment of the present invention. In FIG. 22, the same components as those of the tip push-up mechanism 23 of the first embodiment shown in FIG.

  Referring to FIG. 22, the tip push-up mechanism 100 of the second embodiment is replaced with the first and second push-out members 43 and 44 provided in the tip push-up mechanism 23 described in the first embodiment. In addition, the structure is the same as that of the chip push-up mechanism 23 except that the first and second push-out members 101 and 102 are provided.

The first protruding portion 101 is the same as the first protruding member 43 described in the first embodiment except that the first protruding portion 101 has the wide portion 104 at one end and the wide portion 105 at the other end (see FIG. 5)). That is, the first protruding surface 101a of the first protruding portion 101 is a flat surface.
The wide portions 104 and 105 are disposed on the short side of the second protruding member 102. The width W ₁ of the wide portion 104 and the width W ₂ of the wide portion 105 are set to be narrower than the width W _{3 of} the first protruding portion 101 located between the wide portion 104 and the wide portion 105. Yes.

  The 2nd protrusion part 102 respond | corresponded to the shape of the 1st protrusion part 101 instead of the opening part 55 provided in the 2nd protrusion part 44 (refer FIG. 5) demonstrated in 1st Embodiment. The structure is the same as that of the second protrusion 44 except that the opening 107 is provided. That is, the second protruding surface 102a of the second protruding portion 102 is a flat surface.

According to the chip push-up mechanism of the second embodiment, the dicing tape 27 shown in FIGS. 11 to 14 is provided by having the first push-up member 101 having wide portions 104 and 105 that are wide at both ends. The semiconductor chip 26 can be easily peeled off.
Further, instead of the chip push-up mechanism 23 provided in the peeler 17 shown in FIG. 4, the peeler to which the chip push-up mechanism 100 of the second embodiment is applied is the same as the peeler 17 of the first embodiment. Similar effects can be obtained.

  Further, when the semiconductor chip 26 is peeled from the dicing tape 27 using a peeling device to which the chip push-up mechanism 100 is applied, it is possible to use a technique similar to the method for peeling the semiconductor chip 26 of the first embodiment. The same effects as those of the semiconductor chip 26 peeling method of the first embodiment can be obtained.

(Third embodiment)
FIG. 23 is a plan view showing a schematic configuration of a tip push-up mechanism according to the third embodiment of the present invention. In FIG. 23, the same components as those of the tip push-up mechanism 23 of the first embodiment shown in FIG.

  Referring to FIG. 23, the tip push-up mechanism 110 according to the third embodiment includes a second push-out member 44 and a first suction portion 46 provided in the tip push-up mechanism 23 described in the first embodiment. Instead of providing the second push-out member 111 and the first suction portion 112, and further providing a pair (two) of third push-out members 113, the tip push-up mechanism 23 has the same configuration. ing.

  The second protruding member 111 includes a first protruding portion 43 and a pair of third third members instead of the opening 55 provided in the second protruding portion 44 (see FIG. 5) described in the first embodiment. The configuration is the same as that of the second protruding portion 44 except that the opening 115 has a shape capable of accommodating the protruding member 113. That is, the second protruding surface 111a of the second protruding portion 111 is a flat surface.

The first suction portion 112 is disposed so as to surround the first protrusion portion 43 and the two third protrusion members 113.
The pair of third protrusion members 113 are arranged on the long side of the first protrusion member 43 so as to sandwich the first protrusion member 43. The third protruding surface 113a of the third protruding member 113 is a flat surface.

  According to the chip push-up mechanism of the second embodiment, the pair of third push-out members 113 that sandwich the first push-up member 43 is provided between the first push-out member 43 and the second push-up member 111. Thus, the semiconductor chip 26 can be peeled off stepwise from the dicing tape 27 shown in FIGS.

  Further, when the semiconductor chip 26 is peeled from the dicing tape 27 by using a peeling device to which the chip push-up mechanism 110 is applied, it is possible to use a method similar to the method for peeling the semiconductor chip 26 of the first embodiment. The semiconductor chip 26 can be peeled off from the dicing tape 27 step by step.

(Fourth embodiment)
24 to 27 are cross-sectional views for explaining a semiconductor chip peeling method using the peeling apparatus according to the fourth embodiment of the present invention.

Here, before explaining the peeling method of the semiconductor chip 26 using the peeling apparatus 120 which concerns on 4th Embodiment, the structure of the peeling apparatus 120 which concerns on 4th Embodiment is demonstrated.
Referring to FIG. 24, a peeling device 120 according to the fourth embodiment is replaced with a chip pushing mechanism instead of the chip pushing mechanism 23 provided in the peeling device 17 (see FIG. 11) according to the first embodiment. Except for providing 121, it is configured in the same manner as the peeling device 17.

  The chip push-up mechanism 121 is the same as the chip push-up mechanism 23 except that a first push-up member 122 is provided instead of the first push-up member 43 provided in the chip push-up mechanism 23 described in the first embodiment. It is set as the same structure.

The first push-up member 122 is disposed inside the second push-up member 44. The first push-up member 122 is a single curved surface, and has a first push-up surface 122 a that pushes up the semiconductor chip 26 via the dicing tape 27.
Of the first push-up member 122, the portion constituting the first push-up surface 122a is high in the direction from the outer peripheral edge 122A of the first push-up member 122 toward the center G1 of the _first push-up member 122. It is configured to be high. Moreover, the 1st pushing-up surface 122a is comprised by one curved surface.
That is, the part which comprises the 1st pushing-up surface 122a is made into the round shape which protruded upwards.

  Next, with reference to FIGS. 24 to 27, a method for peeling the semiconductor chip 26 using the peeling apparatus 120 according to the fourth embodiment will be described.

  First, in the step shown in FIG. 24, the suction surface 41a of the suction stage 41 and the center of the first protrusion surface 122a of the first protrusion member 122 (in other words, the highest portion of the first protrusion surface 122a). And the second projecting surface 44a of the second projecting member 44 are arranged on substantially the same plane, and then a plurality of suction surfaces 41a, the center of the first projecting surface 122a, and the second projecting surface 44a The back surface 27b of the dicing tape 27 to which the semiconductor chip 26 is attached is adsorbed.

Next, in the step shown in FIG. 25, from the state shown in FIG. 24 (the state where the center of the first protrusion surface 122a and the second protrusion surface 44a are substantially flush with the suction surface 41a), the first protrusion is performed. The tip push-up mechanism moving means 45 moves the first push-up member 122 and the second push-up member 44 upward by the same amount so that the center of the surface 122a and the second push-out surface 44a are arranged above the suction surface 41a. By moving, substantially the entire semiconductor chip 26 is pushed up by the center of the first protruding surface 122a and the second protruding surface 44a arranged on substantially the same plane.
Thereby, the back surface 26b located in the vicinity of the outer peripheral edge of the second portion 26-2 of the semiconductor chip 26 is peeled off from the dicing tape 27.

  Next, in the step shown in FIG. 26, from the state shown in FIG. 25, the first moving means 45- is arranged so that the position of the first push-up surface 122a is positioned higher than the position of the second push-up surface 44a. 1, the first push-up surface 122 a is moved upward to push up the entire first portion 26-1 of the semiconductor chip 26, and only the first portion 26-1 of the semiconductor chip 26 is dicing tape 27. Make it affixed to.

At this time, as described above, the portion constituting the first push-up surface 122a (curved surface) is in the direction from the outer peripheral edge 122A of the first push-up member 122 toward the center G1 of the _first push-up member 122. On the other hand, since the height is a round shape, the center of the semiconductor chip 26 extends from the vicinity of the outer peripheral edge of the second portion 26-2 (the portion where the dicing tape 27 is peeled off) so as to follow the round shape. The dicing tape 27 is gradually peeled off.

  Therefore, the through electrode 34 is formed when the dicing tape 27 is peeled off as compared with the case where the first push-up member 43 having the flat first push-up surface 43a described in the first embodiment is used. Since stress can be suppressed from concentrating on the first portion 26-1 of the semiconductor chip 26, damage to the semiconductor chip 26 can be suppressed.

  Next, the surface 26 a of the semiconductor chip 26 is adsorbed by the adsorption collet 24 so that the surface electrode 35 formed in the first portion 26-1 of the semiconductor chip 26 is accommodated in the recess 62.

Next, in the step shown in FIG. 27, the first push-up member 122 is moved downward from the state shown in FIG. Thereby, the semiconductor chip 26 is separated from the dicing tape 27, and the dicing tape 27 is peeled off from the entire back surface 26 b of the semiconductor chip 26.
Thereafter, the positions of the first push-up surface 122a and the second push-up surface 44a are adjusted so that the center of the first push-out surface 122a and the second push-out surface 44a are substantially flush with the suction surface 41a. .

According to the fourth embodiment, the portion constituting the first push-up surface 122a (curved surface) is in the direction from the outer peripheral edge 122A of the first push-up member 122 toward the center G1 of the _first push-up member 122. By using the tip push-up mechanism 121 having a round shape with a higher height, the vicinity of the outer peripheral edge of the second portion 26-2 (the portion from which the dicing tape 27 has been peeled off) so as to follow the round shape. Thus, the dicing tape 27 can be gradually peeled from the semiconductor chip 26 toward the center.

  Therefore, the through electrode 34 is formed when the dicing tape 27 is peeled off as compared with the case where the first push-up member 43 having the flat first push-up surface 43a described in the first embodiment is used. Since stress can be suppressed from concentrating on the first portion 26-1 of the semiconductor chip 26, damage to the semiconductor chip 26 can be suppressed.

28 and 29 are side views showing modifications of the first push-up member according to the fourth embodiment.
Referring to FIG. 28, the first push-up member 125 protrudes in a step-like manner from the portion constituting the first push-up surface 127 and has upper surfaces 126A and 126B (a plurality of upper surfaces) having different heights. A portion 126 is provided. The first push-up surface 127 is composed of upper surfaces 126A and 126B having different heights. The upper surfaces 126A and 126B are flat surfaces.

  Referring to FIG. 29, the first push-up member 130 has upper surfaces 131A, 131B, and 131C (a plurality of upper surfaces) that protrude in a stepped manner and have different heights at the portions constituting the first push-up surface 132. The protrusion 131 which has is provided. The first push-up surface 132 is composed of upper surfaces 131A, 131B, and 131C having different heights. The upper surfaces 131A, 131B, and 131C are flat surfaces.

  When the semiconductor chip 26 is peeled off from the dicing tape 27 using the first push-up members 125 and 130 having such a configuration, the case where the first push-up member 122 of the fourth embodiment is used and Similar effects can be obtained.

The number of the upper surfaces (first push-up surfaces 127 and 132) having different heights is not limited to FIGS. 28 and 29. The number of the upper surfaces having different heights may be two or more.
Further, the upper surfaces 126B and 131C arranged at the top may be curved surfaces like the first push-up surface 122a shown in FIG. 24 described above.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and within the scope of the present invention described in the claims, Various modifications and changes are possible.

  Specifically, in the first to fourth embodiments, the semiconductor chip 26 having a plurality of through electrodes 34 formed in the center of the semiconductor chip 26 (in other words, the semiconductor chip 26 having a through electrode group in the center). In the above description, the dicing tape 27 is peeled off as an example. However, the first protruding members 43, 101, 122, 125, and 130 push up all the through-electrode forming regions of the semiconductor chip, and the dicing tape 27. The present invention can be applied to any semiconductor chip as long as it can be separated from the semiconductor chip.

  The present invention is applicable to a semiconductor chip peeling apparatus and a semiconductor chip peeling method.

DESCRIPTION OF SYMBOLS 10 ... Die bonding apparatus, 11 ... Substrate supply part, 12 ... Substrate conveyance path, 13 ... Jig supply part, 14 ... Pick-up part, 16 ... Bonding part, 17, 120 ... Stripping apparatus, 19 ... Unloader, 21 ... Ring treatment 23, 100, 110, 121 ... chip push-up mechanism, 24 ... suction collet, 24a, 41a ... suction surface, 26 ... semiconductor chip, 26a, 26a-2, 27a, 31a, 32a, 76a ... surface, 26b, 27b , 31b, 68a, 76b ... back surface, 26-1 ... first part, 26-2 ... second part, 26, 96 ... dicing tape, 31, 68 ... semiconductor substrate, 32 ... circuit element layer, 34 ... penetration 34a ... the other end, 35 ... the front electrode, 36 ... the back electrode, 38 ... the suction collet moving means, 41 ... the suction stage, 43, 101, 22, 125, 130 ... first push-up member, 43a, 101a, 122a, 127, 132 ... first push-up surface, 44, 102, 111 ... second push-up member, 44a, 102a, 111a ... second push-up 45, tip pushing mechanism moving means, 45-1 ... first moving means, 45-2 ... second moving means, 46, 112 ... first suction part, 47 ... second suction part, 51, 55, 107, 115 ... opening, 53 ... third suction portion, 56 ... notch, 61, 63 ... suction hole, 62 ... recess, 62a ... bottom surface, 66 ... tape body, 67 ... adhesive layer, 69, 73 ... Dicing line, 71 ... Wiring mother board, 74 ... Wiring board, 76 ... Board body, 77 ... Connection pad, 77a, 83a, 86b, 91a, 126A, 126B, 131A, 131B, 131C ... Upper surface, 79 ... La 81, wiring pattern, 83, 84 ... solder resist, 86 ... chip laminated body, 86a ... outer peripheral side, 88 ... underfill resin, 89 ... first sealing body, 91 ... second sealing body, 93 ... External connection terminal, 95 ... semiconductor device, 96 ... dicing tape, 104,105 ... wide portion, 113 ... third protruding member, 113a ... third protruding surface, 122A ... outer peripheral edge, 126,131 ... projecting portion, B ... formation region, D ₁ ... distance, E ... chip formation region, F ... semiconductor device formation region, G ₁ ... center, W ₁ , W ₂ , W ₃ ... width

Claims (14)

Adsorption collet that adsorbs the surface of the semiconductor chip;
A chip push-up mechanism that peels off the semiconductor chip from the dicing tape by sticking up the semiconductor chip attached to the dicing tape and provided with a through electrode;
A semiconductor chip peeling apparatus comprising:
The chip push-up mechanism is configured to be movable in the vertical direction, and the first push-up surface pushes up at least a first portion of the semiconductor chip corresponding to the through electrode formation region via the dicing tape. A first push-up member having
A second push-up member that is configured to be movable in the vertical direction and has a second push-up surface that pushes up a second portion of the semiconductor chip where the through electrode is not formed through the dicing tape. When,
A semiconductor chip peeling apparatus comprising: The through electrode is disposed on the inner side of the outer periphery of the semiconductor chip,
2. The semiconductor chip peeling apparatus according to claim 1, wherein the first push-up member is disposed inside the second push-up member.   3. The semiconductor chip peeling apparatus according to claim 1, wherein the first push-up surface is a flat surface.   Of the first push-up member, the portion constituting the first push-up surface is higher in the direction from the outer peripheral edge of the first push-up member toward the center of the first push-up member. 3. A semiconductor chip peeling apparatus according to claim 1, wherein the semiconductor chip peeling apparatus is a semiconductor chip peeling apparatus.   5. The semiconductor chip peeling apparatus according to claim 4, wherein the first push-up surface is a single curved surface. Of the first push-up member, a portion constituting the first push-up surface is provided with a protrusion having a plurality of upper surfaces protruding in a step shape and having different heights.
5. The semiconductor chip peeling apparatus according to claim 4, wherein the plurality of upper surfaces having different heights are the first push-up surfaces.   7. The semiconductor chip peeling apparatus according to claim 1, wherein the second push-up surface is a flat surface.   8. The semiconductor chip according to claim 2, wherein an outer shape of a portion of the second push-up member that contacts the dicing tape is smaller than an outer shape of the semiconductor chip. 9. Peeling device. A first suction part for sucking the dicing tape is provided on the outer peripheral edge of the first push-up member,
9. The semiconductor chip peeling apparatus according to claim 1, wherein a second suction portion that sucks the dicing tape is provided on an outer peripheral edge of the second push-up member. 10.   Outside the second push-up member, there are an opening that accommodates the first and second push-up members, a flat suction surface that contacts the dicing tape, and a third suction portion that sucks the dicing tape. 10. The semiconductor chip peeling apparatus according to claim 2, further comprising a suction stage.   11. The semiconductor chip peeling apparatus according to claim 2, wherein a wide portion having a wide shape is provided at both ends of the first push-up member.   The pair of third push-up members that sandwich the first push-up member is provided between the first push-up member and the second push-up member. A semiconductor chip peeling apparatus according to claim 1. A surface electrode protruding from the surface of the semiconductor chip is provided at one end of the through via, and a back electrode protruding from the back surface of the semiconductor chip is provided at the other end of the through via. And
13. The semiconductor chip peeling apparatus according to claim 1, wherein the suction collet has a concave portion that accommodates the surface electrode at a position facing the first portion. A semiconductor chip peeling method for peeling a semiconductor chip having a through electrode from a dicing tape,
The suction surface of the suction stage, the first protrusion surface of the first protrusion member disposed inside the suction stage, and the second protrusion surface of the second protrusion member disposed inside the suction stage are substantially the same. A tape adsorbing step that is arranged on the same plane and adsorbs the back surface of the dicing tape to which the semiconductor chip is adhered to the adsorbing surface, the first protruding surface, and the second protruding surface;
A first push-up step in which the first and second push-out members are moved by the same amount above the suction surface, and the first and second push-out surfaces push up substantially the entire semiconductor chip;
After the first push-up step, the first protruding surface is moved above the second protruding surface, and at least a first portion of the semiconductor chip corresponding to the through electrode formation region is formed. A second pushing-up step to push up;
A chip adsorbing step for adsorbing the surface of the semiconductor chip by an adsorbing collet after the second pushing-up step;
A step of moving the first protruding surface downward after the chip suction step;
A method for peeling a semiconductor chip, comprising:

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