JP2012161222A - Parallel multiplex chopper device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a parallel multiplex chopper device capable of achieving little adverse effect of current ripple, high current response speed and suppressed LC resonance.SOLUTION: The parallel multiplex chopper device includes a plurality of chopper sections connected in parallel and operates with a value obtained by dividing 360 degrees by the number of the chopper sections as a phase difference. A travelling average width Tis taken as the time obtained by dividing a cycle Tof a PWM carrier signal by the number of the chopper sections and is synchronized with a peak value of the PWM carrier signal. In addition, a sampling interval Tis set at one half or less as many as the traveling average width Tand is synchronized with the PWM carrier signal.

Description

  The present invention relates to a parallel multiple chopper device in which a plurality of chopper units are connected in parallel.

  A chopper device is known as a circuit that boosts or lowers the voltage of a DC power supply to a predetermined voltage by a switching operation of a semiconductor switching element such as a power transistor. FIG. 5 shows a general main circuit configuration of the chopper device. As shown in FIG. 5, the chopper unit 1 of the chopper device includes a switching module 6 and a reactor DCL, and boosts or steps down the voltage of the DC power supply 4 and supplies it to the load 5.

  There is also known a parallel multiple chopper device in which a plurality of chopper units 1 are connected in parallel and the switching elements in each chopper unit are shifted in on / off timing. As a control circuit of a parallel multiple chopper device, for example, Patent Documents 1 and 2 are disclosed.

JP 09-215322 A JP 2008-289317 A

  As shown in FIG. 5, the load 5 of the chopper device is often capacitive. In this case, LC resonance occurs between the inductance of the reactor DCL of the chopper device and the capacity of the load 5, and control is impossible in the worst case.

  When the capacity of the load 5 is not changed and is generally known, the resonance frequency can be changed and resonance can be suppressed by changing the inductance value of the reactor DCL. However, when the capacity of the load 5 changes, it is difficult to suppress resonance in all the capacitors only by changing the inductance value of the reactor DCL.

  As a solution, resonance suppression control is generally performed. However, when a current detection delay occurs, the current response speed decreases. When the current response speed is equal to or lower than the resonance frequency, there is a problem that the resonance suppression control becomes impossible.

  Here, calculation of current detection and current control in the conventional chopper device will be described. The output voltage of the switching module 1 has a pulse waveform, and the current detection waveform includes a current ripple.

  For this reason, in general, a method of detecting the output current by sampling at a timing synchronized with the PWM carrier signal and applying the method of synchronizing the current control period with the timing of the PWM carrier signal is applied to reduce the influence of the current ripple. Yes. For example, as shown in FIG. 6, the output current is detected by sampling with the upper limit value and the lower limit value of the PWM carrier signal, and the moving average of the current detection values of the two times (upper limit value and lower limit value) is taken, This is used to calculate the next current control cycle.

  However, if a current is detected at a timing synchronized with the PWM carrier signal, a current detection delay corresponding to at least one cycle of the PWM carrier signal occurs. When the current response speed decreases due to this current detection delay and the current response speed becomes equal to or lower than the resonance frequency, the resonance suppression control becomes impossible.

  Therefore, in the chopper device, it is necessary to increase the current response speed. However, in the control circuit of the parallel multiple chopper device disclosed in Patent Document 1 and Patent Document 2, a method for increasing the current detection and current response speed. Is not disclosed, and LC resonance due to a delay in current detection could not be suppressed.

  As described above, it is an object to provide a parallel multiple chopper device that reduces the influence of current ripple, increases the current response speed, and suppresses LC resonance.

  The present invention has been devised in view of the above-described conventional problems, and one aspect thereof is a detected current value obtained by moving average calculation of a plurality of chopper units connected in parallel and a sampling value in an output current of each chopper unit. The voltage command value calculated by the current control is compared with the PWM carrier signal of each chopper part using a value obtained by dividing 360 degrees by the number of chopper parts as a phase difference. A parallel multiple chopper device including a control unit that outputs a gate command to the unit, wherein the control unit sets the moving average width as a time obtained by dividing the period of the PWM carrier signal by the number of chopper units, and PWM In synchronization with the peak of the carrier signal, the sampling interval is set to be less than or equal to half of the moving average width, and is synchronized with the PWM carrier signal.

  The period of the current control may be the sampling interval.

  According to the present invention, it is possible to provide a parallel multiple chopper device that reduces the influence of current ripple, increases the current response speed, and suppresses LC resonance.

It is a block diagram which shows the main circuit of the parallel multiple chopper apparatus in embodiment. It is a block diagram which shows the control part of the parallel multiple chopper apparatus in embodiment. It is a current waveform figure of the parallel multiple chopper device in an embodiment. It is a time chart which shows the electric current detection timing of the parallel multiple chopper apparatus in embodiment. It is a block diagram which shows the main circuit of the conventional common chopper apparatus. It is a time chart which shows the electric current detection timing in the conventional common chopper apparatus.

  Hereinafter, a parallel multiple chopper device according to an embodiment of the present invention will be described in detail with reference to the drawings.

[Embodiment]
FIG. 1 shows a main circuit configuration of a parallel multiple chopper device according to this embodiment. About the same location as the chopper apparatus shown in FIG. 5, the same code | symbol is attached | subjected and the detailed description is abbreviate | omitted.

  The parallel multiple chopper device according to the present embodiment is configured to connect a plurality (n) of chopper units 1 to 3 in parallel and operate with a value obtained by dividing 360 degrees by the number n of chopper units 1 to 3 as a phase difference. . That is, the parallel multiple chopper device is operated by equally shifting the phases of the chopper units 1 to 3 and equally distributing the current supplied to the load 5 to the chopper units 1 to 3.

  Here, the number n of chopper parts is a natural number of 2 or more. In this embodiment, the case where n = 3 is described as an example, but the same operation is performed when n ≠ 3.

  The chopper unit 1 includes a switching module 6 and a reactor DCL1. The switching module 6 includes switching elements S1 and S2 and diodes D1 and D2 connected in antiparallel to the switching elements S1 and S2. In the present embodiment, the load 5 is capacitive.

  The chopper unit 1 includes a switching element S1 and a switching element S2 and a diode D1 and a diode D2 connected in series to connect both ends and each intermediate connection point in common, and to the intermediate connection point, one end of the reactor DCL1. Are connected.

  Although the switching elements S1 and S2 shown in FIG. 1 are IGBTs, this is not limited to IGBTs, and any self-extinguishing switching device such as IGBTs or GTOs may be used.

  Similarly to the chopper unit 1, the chopper units 2 and 3 also include switching modules 7 and 8 and reactors DCL 2 and DCL 3. The switching modules 7 and 8 include switching elements S3, S4, S5 and S6 and diodes D3, D4, D5 and D6 connected in reverse parallel to the switching elements S3, S4, S5 and S6 ( (Not shown).

  In the chopper unit 1 configured as described above, the switching element S1 is on / off controlled to step down the DC voltage of the DC power supply 4 at the switching element S1 and charge the load 5 via the reactor DCL1.

Here, when the switching element S1 is turned on, the chopper part current I ₁ flows through the path of the switching element S1 → reactor DCL1 → load 5, and charges the load 5.

Next, when the switching element S1 is turned off, the chopper section current I ₁ that has flown as the stored energy of the reactor DCL1 flows as a circulating current through the path of load 5 → diode D2 → reactor DCL1, and the residual energy of the reactor DCL1 is loaded into the load 5 To charge.

  Further, the switching element S <b> 2 is on / off controlled to discharge the power of the load 5 and regenerate the DC power supply 4.

  First, when the switching element S2 is turned on, the current of the load 5 is discharged through the reactor DCL1 and the switching element S2, and the energy at this time is accumulated in the DCL1.

  Next, when the switching element S2 is turned off, a voltage due to the counter electromotive force is generated in the reactor DCL1, and the voltage of the load 5 and the voltage due to the electromotive force of the reactor DCL1 are added and regenerated to the DC power source 4 via the diode D1. Then, the boost chopper is operated.

  Although the chopper unit 1 has been described in detail, the chopper units 2 and 3 operate in the same manner as the chopper unit 1.

  Here, based on FIG. 2, the control part 10 of the chopper apparatus in this embodiment is demonstrated. The signal processing in the control unit 10 is performed by digital processing using a computer. FIG. 2 shows a control unit in one chopper unit (for example, the chopper unit 1), but the control units of the other chopper units (for example, the chopper units 2 and 3) are similarly configured.

  As shown in FIG. 2, the control unit 10 includes a current controller (ACR) 11, a PWM (Pulse Width Modulation) signal generation unit 12, a carrier generation unit 13, a moving average unit 15, and an ADC. A trigger generation unit 16.

The current controller 11 performs current control using a deviation between the current command value I _ref ^* and the detected current value I _det output from the moving average unit 15. The output of the current controller 11 becomes the voltage command value V _ref ^* of the parallel multiple chopper device 4.

The PWM signal generation unit 12 compares the PWM carrier signal having the period T _carry generated by the carrier generation unit 13 with the voltage command value V _ref ^*, and outputs the first gate to the switching module 6 (switching elements S1, S2). A command G1 is generated.

The moving average unit 15 performs a moving average calculation of the output current I ₁ of the chopper unit 1, improves current detection accuracy against disturbance, and feeds it back to the current controller 11 as a current detection value I _det . Specifically, first, a detected value of the output current I ₁ is sampled and digitally converted by an AD converter (ADC), and then a moving average calculation is performed by an integrated circuit (for example, FPGA) to obtain a current detected value I Output as _det .

  FIG. 3 shows a current waveform diagram of the parallel multiple chopper device in the present embodiment. As shown in FIG. 3, since the phase of the carrier signal in each chopper unit is shifted, the parallel multiple chopper device is a single chopper device in which the carrier frequency is n times the number of chopper units (3 in this embodiment). And almost the same ripple waveform.

FIG. 4 is a time chart showing the current detection timing of the chopper unit output current I ₁ in the moving average unit 15. The moving average width T _c shown in FIG. 4 is T _carry / n (in this embodiment, n = 3) and is synchronized with the peak of the PWM carrier signal. Thereby, the current detection delay due to the moving average is minimized, and a wasteful time of the current control response can be shortened.

The sampling interval T _smp of the moving average unit 15 is generated by the ADC trigger generating unit 16 and is output to the moving average unit 15 and the current controller 11. As a result, the sample trigger in the AD converter (moving average unit 15) and the calculation interval in the current controller 11 are synchronized. The sampling interval T _smp is not more than half of the moving average width T _c and is synchronized with the PWM carrier signal. In the present embodiment, as shown in FIG. 4, two points on the moving average width T _C (PWM carrier signal one cycle 6 points) shall be sampled.

Furthermore, the calculation cycle (update cycle) of the current controller 11 is also set to the sampling interval T _smp and is synchronized with the moving average width T _c .

  In addition, in this embodiment, although the control part 10 of the chopper part 1 was demonstrated in detail, electric current is detected by the same method also about the control part of the chopper parts 2 and 3, and current control is performed.

As described above, the parallel multiple chopper device according to the present embodiment sets the current detection moving average width T _c to T _carry / n and synchronizes with the peak of the PWM carrier signal, and the current detection sampling interval T _smp is the moving average. By synchronizing with the carrier signal so that it is equal to or less than half of the width _Tc , it is possible to reduce the influence of the current ripple and shorten the current detection delay. As a result, the current response speed can be increased and LC resonance can be suppressed.

Moreover, the current response speed can be further increased by setting the control period of the current control unit 11 to the sampling interval T _smp . As a result, LC resonance can be suppressed.

  Although the present invention has been described in detail only for the specific examples described above, it is obvious to those skilled in the art that various changes and modifications are possible within the scope of the technical idea of the present invention. Such variations and modifications are naturally within the scope of the claims.

  For example, in the embodiment, the two-quadrant reversible chopper is applied to the chopper parts 1, 2 and 3. However, the chopper parts 1, 2 and 3 are not limited thereto, and may have other configurations.

DESCRIPTION OF SYMBOLS 1, 2, 3 ... Chopper part 4 ... DC power supply 5 ... Load 6, 7, 8 ... Switching module 10 ... Control part 11 ... Current control part (ACR)
12 ... PWM signal generator 13 ... carrier generator 15 ... moving average unit 16 ... ADC trigger generation unit G ₁ ... gate command T _Smp ... sampling period T _c ... moving average interval T _carry ... carrier period I _ref ^* ... current command value I _det … Current detection value V _ref ^* … Voltage command value

Claims (2)

A plurality of chopper units connected in parallel;
The current control is performed with the detected current value obtained by moving average calculation of the sampling value in the output current of each chopper unit, and the voltage command value calculated by the current control and the value obtained by dividing 360 degrees by the number of chopper units are the phase difference. The PWM carrier signal of each chopper unit, and a control unit that outputs a gate command to each chopper unit,
A parallel multiple chopper device comprising:
The controller is
The moving average width is a time obtained by dividing the period of the PWM carrier signal by the number of chopper parts, and is synchronized with the peak of the PWM carrier signal,
The parallel multiple chopper device characterized in that the sampling interval is set to half or less of the moving average width and is synchronized with a PWM carrier signal.    The parallel multiple chopper device according to claim 1, wherein the cycle of the current control is the sampling interval.

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