JP2012154856A - Frequency measurement device and frequency phase difference comparison device - Google Patents

Abstract

A high-resolution frequency measurement device and a frequency phase difference comparison device capable of obtaining a necessary resolution for period measurement without increasing the frequency of a base clock supplied to a digital circuit.
A multi-stage delay 201 including a plurality of delay means 202 for subdividing a base clock cycle at equal intervals is used to delay an input rectangular wave signal, and at a timing obtained from each delay element 202, a counter 203 is provided. Is obtained by the register, and the values of the respective registers are compared to determine at which timing of the base clock the up edge of the rectangular wave signal is located. Then, by giving the value of the deviation on the time axis according to the determination result to the value of the period obtained by the period counter 105, the resolution of the period measurement can be improved.
[Selection] Figure 2

Description

The present invention relates to a frequency measurement device and a frequency phase difference comparison device.
More specifically, the present invention relates to a frequency measurement device and a frequency phase difference comparison device that can obtain an arbitrary high resolution necessary for cycle measurement without increasing the frequency of a base clock that measures the cycle of a signal under measurement.

In various industrial fields such as factories and experimental facilities, there is always a demand for continuously measuring the frequency and / or period, displaying the value, and controlling the system based on the information. The applicant manufactures and sells period / frequency measuring devices to meet such demands.
A prior art document considered to be related to the present invention is shown as Patent Document 1.

JP 2000-180482 A

Usually, in order to improve measurement response for the purpose of measuring a frequency, a technique for measuring from a cycle which is the reciprocal thereof is known. For this purpose, prepare a base clock and counter with a frequency sufficiently higher than the signal to be measured, capture the edge of the signal to be measured, and how many base clocks are included between the edges The period is measured by counting with the counter. Therefore, the measurement resolution of the period and / or frequency depends on the frequency of the base clock.
Generally, in order to improve the resolution, it is necessary to increase the frequency of the base clock. However, when the frequency of the base clock is increased, a semiconductor device capable of handling the high frequency becomes expensive, the board design becomes difficult, and there is a technical limit in handling the frequency.

  The present invention solves such a problem, and provides a high-resolution frequency measurement device and a frequency phase difference comparison device capable of obtaining a resolution for necessary period measurement without increasing the frequency of a base clock supplied to a digital circuit. The purpose is to provide.

  In order to solve the above-mentioned problem, the frequency measuring device of the present invention is characterized by including one or more delay means for subdividing into base clock periods.

  Next to the delay means having a delay substantially equal to the resolution required from the trigger time of the base clock, a multi-stage delay having N delay means that are N times the integer is used to determine the arrival time of the input signal from each delay means. The counter value is obtained by the register at the obtained timing, and the value of each register is compared, whereby it is possible to determine at which timing the edge of the input signal is located during one base clock. The resolution of the period measurement can be improved by giving the value of the deviation on the time axis according to the determination result to the period value obtained by the period counter.

  According to the present invention, it is possible to provide a high-resolution frequency measurement device and a frequency phase difference comparison device that can obtain a necessary resolution for period measurement without increasing the frequency of a base clock supplied to a digital circuit.

It is a block diagram of the period and frequency measuring device concerning this embodiment. It is a block diagram of a time width measuring unit. It is a block diagram of a determination part. It is a circuit diagram of the 1st judgment unit, the 2nd judgment unit, the 3rd judgment unit, and the 4th judgment unit. It is a circuit diagram of a coincidence determination circuit and a mismatch determination circuit. It is a time chart explaining operation | movement of a time width measurement part. It is a time chart explaining operation | movement of a time width measurement part. It is a block diagram of an extended arithmetic unit, which is an application example of the period / frequency measuring device of the present embodiment. It is a block diagram of the frequency phase difference measuring device which is an application example of the period / frequency measuring device of the present embodiment.

FIG. 1 is a block diagram of a period / frequency measuring apparatus according to this embodiment.
The period / frequency measuring apparatus 101 is a digital device composed of a microcomputer or an ASIC. When the period / frequency measuring apparatus 101 receives a rectangular wave signal output from the external rectangular wave signal source 102 to be measured, the period / frequency measuring apparatus 101 measures the period of the rectangular wave signal and calculates the frequency from the period. In addition to displaying the period and / or frequency on the display unit 103, the period information and / or frequency information as measurement results are output to various external devices through the external output terminal 104.

The rectangular wave signals generated by the external rectangular wave signal source 102 are input to the period counter 105 and the time width measuring unit 106, respectively.
The period counter 105 measures the period of the input rectangular wave signal using the base clock output from the base clock oscillator 107, and outputs a count value. The period counter 105 can count the number of digits necessary to measure the period of the rectangular wave signal. For example, when the base clock is 20 nsec (50 MHz), in order to measure the period of a rectangular wave signal having a frequency of 100 kHz or more, the period counter 105 needs to be able to count at least 500 from the following equation (1). is there.

  50 MHz / (100 KHz) = 500 (1)

  In the case of the period / frequency measuring apparatus 101 of the present embodiment, the period counter 105 is a 32-bit wide counter as a specified state. Therefore, when the base clock is 50 MHz, it is possible to measure up to about 0.01 Hz.

The time width measurement unit 106 outputs time information corresponding to a shift of the rectangular wave signal with respect to the base clock with a resolution equal to or higher than the period of the base clock.
The calculating unit 108 calculates the relative value of the rising edge of the rectangular wave signal by calculating the count value output by the cycle counter 105 and the time information output by the time width measuring unit 106, calculates the cycle, and calculates the numerical value. Divide “1” by the period to calculate the frequency.
Period information and frequency information, which are calculation results of the calculation unit 108, are displayed on the display unit 103 such as an LCD and supplied to an external device through the external output terminal 104.
Although not shown in FIG. 1, a control unit that controls the calculation unit 108 and an operation unit such as a keyboard are separately provided to select information output to the display unit 103 and the external output terminal 104. Can do.

The period / frequency measuring apparatus 101 of the present embodiment is newly provided with a time width measuring unit 106 in order to obtain a resolution equal to or higher than the period of the base clock. The details of the time width measurement unit 106 will be described step by step.
FIG. 2 is a block diagram of the time width measuring unit 106.
The rectangular wave signal is supplied to the multistage delay 201. In the multistage delay 201, a plurality of delay elements 202 are connected in series. Each delay element 202 realizes an equal delay time. The delay time of the delay elements 202 in the multi-stage delay 201 is designed to match the period of the base clock when multiplied by the number of delay elements 202 plus one. In FIG. 2, a first delay element 202a, a second delay element 202b, a third delay element 202c, and three delay elements are housed in a multistage delay 201, and each delay element 202 has a base clock cycle. It is the structure which delays only 1/4 time.

  On the other hand, the base clock is supplied to the counter 203. The counter 203 counts the base clock and outputs a numerical value with a predetermined number of bits. The output data of the counter 203 is supplied to the first register 204, the second register 205, the third register 206, and the fourth register 207, respectively. The first register 204, the second register 205, the third register 206, and the fourth register 207 are provided with data storage command terminals (hereinafter abbreviated as “Cp terminal”), and these registers are signals input to the Cp terminal. Data is stored at the up-edge.

A rectangular wave signal is directly supplied to the Cp terminal of the first register 204. Next, the output signal of the first delay element 202 a of the multistage delay 201 is supplied to the Cp terminal of the second register 205. Similarly, the output signal of the second delay element 202b of the multistage delay 201 is supplied to the Cp terminal of the third register 206. Similarly, the output signal of the third delay element 202 c of the multistage delay 201 is supplied to the Cp terminal of the fourth register 207.
The first register 204, the second register 205, the third register 206, and the fourth register 207 hold the value of the counter 203 at the timing of the signal input to each Cp terminal.

  The first register 204, the second register 205, the third register 206, and the fourth register 207 are each connected to the determination unit 208. The determination unit 208 compares the values of the first register 204, the second register 205, the third register 206, and the fourth register 207, and outputs time information corresponding to the result.

FIG. 3 is a block diagram of the determination unit 208.
The output data of the first register 204, the second register 205, the third register 206, and the fourth register 207 are supplied to the first determination unit 301, the second determination unit 302, the third determination unit 303, and the fourth determination unit 304, respectively. Is done.

The first determination unit 301 outputs a signal indicating logic “true” when the output data of the first register 204, the second register 205, the third register 206, and the fourth register 207 are all the same value.
When the output data of the first register 204, the second register 205, and the third register 206 are the same, and the output data of the fourth register 207 is different from the values of the other registers, the second determination unit 302 A signal indicating “true” is output.

The third determination unit 303 has the same output data from the first register 204 and the second register 205, the same output data from the third register 206 and the fourth register 207, and the values of the second register 205 and the third register 206. When is different, a signal indicating logic “true” is output.
The fourth determination unit 304 outputs a logical value when the output data of the second register 205, the third register 206, and the fourth register 207 are the same and the value of the first register 204 is different from the values of the other registers. A signal indicating “true” is output.

  Output signals of the first determination unit 301, the second determination unit 302, the third determination unit 303, and the fourth determination unit 304 are supplied to the time width data output unit 305. The time width data output unit 305 has a well-known ROM and outputs data corresponding to the input signal.

4A, 4 </ b> B, 4 </ b> C, and 4 </ b> D are circuit diagrams of the first determination unit 301, the second determination unit 302, the third determination unit 303, and the fourth determination unit 304.
FIG. 4A is a circuit diagram of the first determination unit 301.
The first determination unit 301 includes three match determination circuits 401a, 401b and 401c, and an AND gate 402a.

The coincidence determination circuit outputs a logical true when the two input data coincide.
The coincidence determination circuit 401a is supplied with the output data of the first register 204 and the second register 205.
The coincidence determination circuit 401b is supplied with the output data of the second register 205 and the third register 206.
The coincidence determination circuit 401c is supplied with the output data of the third register 206 and the fourth register 207.
Therefore, the output data of the first register 204 and the second register 205 match, the output data of the second register 205 and the third register 206 match, and the output data of the third register 206 and the fourth register 207 match. When doing so, AND gate 402a outputs a logical true.

FIG. 4B is a circuit diagram of the second determination unit 302.
The second determination unit 302 includes two match determination circuits 401d and 401e, one mismatch determination circuit 403a, and an AND gate 402b.
The coincidence determination circuit 401d is supplied with the output data of the first register 204 and the second register 205.
The coincidence determination circuit 401e is supplied with output data of the second register 205 and the third register 206.

The mismatch determination circuit outputs a logic true when the two input data do not match.
Output data of the third register 206 and the fourth register 207 is supplied to the mismatch determination circuit 403a.
Therefore, the output data of the first register 204 and the second register 205 match, the output data of the second register 205 and the third register 206 match, and the output data of the third register 206 and the fourth register 207 match. When not done, the AND gate 402b outputs a logic true.

FIG. 4C is a circuit diagram of the third determination unit 303.
The third determination unit 303 includes two match determination circuits 401f and 401g, one mismatch determination circuit 403b, and an AND gate 402c.
The coincidence determination circuit 401f is supplied with output data from the first register 204 and the second register 205.
Output data of the second register 205 and the third register 206 is supplied to the mismatch determination circuit 403b.
The coincidence determination circuit 401g is supplied with the output data of the third register 206 and the fourth register 207.
Therefore, the output data of the first register 204 and the second register 205 match, the output data of the second register 205 and the third register 206 do not match, and the output of the third register 206 and the fourth register 207. When the data matches, the AND gate 402c outputs logic true.

FIG. 4D is a circuit diagram of the fourth determination unit 304.
The second determination unit 302 includes two match determination circuits 401h and 401i, one mismatch determination circuit 403c, and an AND gate 402d.
Output data of the first register 204 and the second register 205 is supplied to the mismatch determination circuit 403c.
The coincidence determination circuit 401h is supplied with output data of the second register 205 and the third register 206.
The coincidence determination circuit 401i is supplied with the output data of the third register 206 and the fourth register 207.

  Therefore, the output data of the first register 204 and the second register 205 do not match, the output data of the second register 205 and the third register 206 match, and the output of the third register 206 and the fourth register 207. When the data matches, the AND gate 402d outputs logic true.

  FIGS. 5A and 5B are circuit diagrams of the coincidence determination circuit 401 and the mismatch determination circuit 403. The coincidence determination circuits 401a, 401b, 401c, 401d, 401e, 401f, 401g, 401h, and 401i in FIGS. 4A, 4B, 4C, and 4D are collectively referred to as the coincidence determination circuit 401. Define. Similarly, the mismatch determination circuits 403a, 403b, and 403c are collectively defined as the mismatch determination circuit 403.

FIG. 5A is a circuit diagram of the coincidence determination circuit 401. The coincidence determination circuit 401 shown in FIGS. 4A, 4B, 4C, and 4D determines the coincidence of two data strings having the same number of bits. The coincidence determination circuit 401 shown in FIG. 5A discloses how the coincidence determination circuit 401 determines the coincidence of two data strings in a specific configuration of a logic circuit for each bit.
The coincidence determination circuit 401 has a configuration in which an exclusive NOR gate 501 is connected for each bit of two input data, and the output of each exclusive NOR gate 501 is received by the AND gate 502.
The exclusive NOR gate 501 outputs logic true when the two input signals have the same logic. Therefore, if all the bits of the two data match, the AND gate 502 outputs logic true.

FIG. 5B is a circuit diagram of the mismatch determination circuit 403. A mismatch determination circuit 403 shown in FIGS. 4A, 4B, 4C, and 4D determines a mismatch between two data strings having the same number of bits. The mismatch determination circuit 403 shown in FIG. 5B specifically discloses how the mismatch determination circuit 403 determines a mismatch between two data strings in the configuration of a logic circuit for each bit.
The mismatch determination circuit 403 has a configuration in which an exclusive OR gate 503 is connected to each bit of two input data, and the output of each exclusive OR gate 503 is received by the OR gate 504.
The exclusive OR gate 503 outputs a logic true when the logics of the two input signals are different. Therefore, if one or more bits of the two data do not match, the OR gate 504 outputs a logical true.

FIGS. 6A and 6B, and FIGS. 7C and 7D are time charts for explaining the operation of the time width measuring unit 106.
6 and 7, it is assumed that the base clock period is 20 nsec (50 MHz) and the delay time of the delay element 202 is 5 nsec (200 MHz).

  FIG. 6A shows the value of the counter 203, the first register 204, the second register 205, the third register 206, and the like when the up edge of the rectangular wave signal is within a range of 5 nsec from the up edge of the base clock. 10 is a time chart showing a waveform of a pulse input to a Cp terminal of a fourth register 207.

Now, the counter 203 counts the base clock, and the value of the counter 203 is n at the time t621, and the value of the counter 203 is n + 1 at the time t622 (P601).
In the state as described above, an up edge of the rectangular wave signal occurs at time t623. This up edge is input to the Cp terminal of the first register 204 as it is (P602). The value of the counter 203 at time t623 is n.

Next, the up-edge of the rectangular wave signal delayed by 5 nsec by the delay element 202 is input to the Cp terminal of the second register 205 at time t624 (P603). The value of the counter 203 at time t624 is n.
Similarly, the up edge of the rectangular wave signal further delayed by 5 nsec by the delay element 202 is input to the Cp terminal of the third register 206 at time t625 (P604). The value of the counter 203 at time t625 is n.
Similarly, the up edge of the rectangular wave signal further delayed by 5 nsec by the delay element 202 is input to the Cp terminal of the fourth register 207 at time t626 (P605). The value of the counter 203 at time t626 is n.

That is, since the value of the counter 203 is n at all time points t623, t624, t625, and t626, all the n values are stored in the first register 204, the second register 205, the third register 206, and the fourth register 207. Remembered. As described above, when the determination unit 208 determines that all the registers indicate the same value, it becomes clear that the up edge of the rectangular wave signal exists within a range of 5 nsec from the time of the up edge of the base clock. .
In order to determine the state in which all the registers indicate the same value, the first determination unit 301 implements this using three match determination circuits 401a, 401b and 401c and an AND gate 402a.

  FIG. 6B shows the values of the counter 203, the first register 204, the second register 205, and the third register when the up edge of the rectangular wave signal is within the range of 5 nsec to 10 nsec from the up edge of the base clock. 10 is a time chart showing waveforms of pulses input to Cp terminals of a register 206 and a fourth register 207.

Now, the counter 203 counts the base clock, and the value of the counter 203 is n at the time t621, and the value of the counter 203 is n + 1 at the time t622 (P606).
In the state as described above, an up-edge of the rectangular wave signal occurs at time t633. This up edge is input to the Cp terminal of the first register 204 as it is (P607). The value of the counter 203 at time t633 is n.

Next, the up-edge of the rectangular wave signal delayed by 5 nsec by the delay element 202 is input to the Cp terminal of the second register 205 at time t634 (P608). The value of the counter 203 at time t634 is n.
Similarly, the up edge of the rectangular wave signal further delayed by 5 nsec by the delay element 202 is input to the Cp terminal of the third register 206 at time t635 (P609). The value of the counter 203 at time t635 is n.
Similarly, the up edge of the rectangular wave signal further delayed by 5 nsec by the delay element 202 is input to the Cp terminal of the fourth register 207 at time t636 (P610). The value of the counter 203 at time t636 is n + 1.

That is, at all time points t633, t634, and t635, the value of the counter 203 is n, while the value of the counter 203 at time point t636 is n + 1. Therefore, n is stored in the first register 204, the second register 205, and the third register 206, and n + 1 is stored in the fourth register 207.
As described above, when the determination unit 208 determines that only the fourth register 207 shows a value different from the other registers, the up edge of the rectangular wave signal is within a range of 5 to 10 nsec from the time of the up edge of the base clock. It becomes clear that it exists.
In order to determine a state in which only the fourth register 207 shows a different value, the second determination unit 302 realizes this by using two match determination circuits 401d and 401e, one mismatch determination circuit 403a, and an AND gate 402b. ing.

  FIG. 7C shows the value of the counter 203, the first register 204, the second register 205, and the third register when the up edge of the rectangular wave signal is within the range of 10 nsec to 15 nsec from the up edge of the base clock. 10 is a time chart showing waveforms of pulses input to Cp terminals of a register 206 and a fourth register 207.

Now, the counter 203 counts the base clock, and the value of the counter 203 is n at the time t621, and the value of the counter 203 is n + 1 at the time t622 (P701).
In the state as described above, an up-edge of the rectangular wave signal occurs at time t723. This up edge is input to the Cp terminal of the first register 204 as it is (P702). The value of the counter 203 at time t723 is n.

Next, the up-edge of the rectangular wave signal delayed by 5 nsec by the delay element 202 is input to the Cp terminal of the second register 205 at time t724 (P703). The value of the counter 203 at time t724 is n.
Similarly, the up edge of the rectangular wave signal further delayed by 5 nsec by the delay element 202 is input to the Cp terminal of the third register 206 at time t725 (P704). The value of the counter 203 at time t725 is n + 1.
Similarly, the up edge of the rectangular wave signal further delayed by 5 nsec by the delay element 202 is input to the Cp terminal of the fourth register 207 at time t726 (P705). The value of the counter 203 at time t726 is n + 1.

That is, at the time points t723 and t724, the value of the counter 203 is n, while the value of the counter 203 at time points t725 and t726 is n + 1. Therefore, n is stored in the first register 204 and the second register 205, and n + 1 is stored in the third register 206 and the fourth register 207.
As described above, the determination unit 208 determines a state in which the first register 204 and the second register 205 are equal, the third register 206 and the fourth register 207 are equal, and the second register 205 and the third register 206 indicate different values. Then, it becomes clear that the up edge of the rectangular wave signal exists within a range of 10 to 15 nsec from the time of the up edge of the base clock.
In order to determine a state in which the first register 204 and the second register 205 are equal, the third register 206 and the fourth register 207 are equal, and the second register 205 and the third register 206 indicate different values, The determination unit 302 achieves this by using two match determination circuits 401f and 401g, one mismatch determination circuit 403b, and an AND gate 402c.

  FIG. 7D shows the value of the counter 203, the first register 204, the second register 205, and the third register when the up edge of the rectangular wave signal is within the range of 15 nsec to 20 nsec from the up edge of the base clock. 10 is a time chart showing waveforms of pulses input to Cp terminals of a register 206 and a fourth register 207.

Now, the counter 203 counts the base clock, and the value of the counter 203 is n at the time t731, and the value of the counter 203 is n + 1 at the time t732 (P706).
In the state as described above, an up-edge of the rectangular wave signal occurs at time t733. This up edge is inputted as it is to the Cp terminal of the first register 204 (P707). The value of the counter 203 at time t733 is n.

Next, the up edge of the rectangular wave signal delayed by 5 nsec by the delay element 202 is input to the Cp terminal of the second register 205 at time t734 (P708). The value of the counter 203 at time t734 is n.
Similarly, the up edge of the rectangular wave signal further delayed by 5 nsec by the delay element 202 is input to the Cp terminal of the third register 206 at time t735 (P709). The value of the counter 203 at time t735 is n + 1.
Similarly, the up edge of the rectangular wave signal further delayed by 5 nsec by the delay element 202 is input to the Cp terminal of the fourth register 207 at time t736 (P710). The value of the counter 203 at time t736 is n + 1.

That is, the value of the counter 203 is n at the time point t733, while the value of the counter 203 at the time points t734, t725, and t726 is n + 1. For this reason, n is stored in the first register 204, and n + 1 is stored in the second register 205, the third register 206, and the fourth register 207.
As described above, when the determination unit 208 determines that only the first register 204 shows a value different from the other registers, the up-edge of the rectangular wave signal is within a range of 10 to 15 nsec from the time of the up-edge of the base clock. It becomes clear that it exists.
In order to determine the state in which only the first register 204 shows a value different from the other registers, the second determination unit 302 uses two match determination circuits 401h and 401i, one mismatch determination circuit 403c, and an AND gate 402d. This is realized.

The time width data output unit 305 outputs a value “0” when the first determination unit 301 indicates logic true. This means that the up edge of the rectangular wave signal has an offset of 0 nsec with respect to the up edge of the base clock.
On the other hand, the time width data output unit 305 outputs a value “5” when the second determination unit 302 indicates logic true. This means that the up edge of the rectangular wave signal has an offset of 5 nsec with respect to the up edge of the base clock.
Similarly, the time width data output unit 305 outputs a value “10” when the third determination unit 303 indicates logic true. This means that the up edge of the rectangular wave signal has an offset of 10 nsec with respect to the up edge of the base clock.
Similarly, the time width data output unit 305 outputs the value “15” when the fourth determination unit 304 indicates logic true. This means that the up edge of the square wave signal has an offset of 15 nsec with respect to the up edge of the base clock.

In this manner, the multi-stage delay 201 including a plurality of delay elements 202 that subdivide the base clock cycle at equal intervals is used to delay the input rectangular wave signal, and the counter 203 at a timing obtained from each delay element 202. Is obtained by the register, and the values of the respective registers are compared to determine at which timing of the base clock the up edge of the rectangular wave signal is located. Then, by giving the value of the deviation on the time axis according to the determination result to the value of the period obtained by the period counter 105, the resolution of the period measurement and the frequency measurement can be improved.
For example, when the base clock is 50 MHz (the cycle is 20 nsec) and the delay time of the delay element 202 is 5 nsec (corresponding to a frequency of 200 MHz), the maximum measurable frequency is 50 MHz, but the resolution is 5 nsec, that is, 200 MHz. Resolution can be provided.

  Here, when the first determination unit 301, the second determination unit 302, the third determination unit 303, and the fourth determination unit 304 shown in FIGS. 4A, 4B, 4C, and 4D are viewed again. You will understand what these decision units are detecting.

The first determination unit 301 detects a state in which the values of all the registers of the first register 204, the second register 205, the third register 206, and the fourth register 207 are equal. For this purpose, the coincidence determination circuits 401a, 401b, and 401c determine the coincidence between adjacent registers.
The second determination unit 302 detects a state in which the values of the first register 204, the second register 205, and the third register 206 match and the values of the third register 206 and the fourth register 207 are not equal. For this reason, the mismatch determination circuit 403 a determines a mismatch between the third register 206 and the fourth register 207.

In the third determination unit 303, the values of the first register 204 and the second register 205 match, the values of the third register 206 and the fourth register 207 match, and the second register 205 and the third register 206 Detects unequal values. Therefore, the mismatch determination circuit 403b determines a mismatch between the second register 205 and the third register 206.
The fourth determination unit 304 detects a state in which the values of the second register 205, the third register 206, and the fourth register 207 match and the values of the first register 204 and the second register 205 are not equal. For this reason, the mismatch determination circuit 403 c determines a mismatch between the second register 205 and the third register 206.

Looking at the second determination unit 302, the third determination unit 303, and the fourth determination unit 304 from a bird's-eye view, the mismatch determination circuit 403a determines a mismatch between the third register 206 and the fourth register 207, and the mismatch determination circuit 403b The mismatch between the second register 205 and the third register 206 is determined, and the mismatch determination circuit 403c determines the mismatch between the first register 204 and the second register 205. That is, the mismatch determination circuits 403a, 403b, and 403c capture which register the value of the counter 203 has changed.
Therefore, the coincidence determination circuits 401d, 401e, 401f, 401g, 401h, and 401i of the second determination unit 302, the third determination unit 303, and the fourth determination unit 304 and the AND gates 402b, 402c, and 402d If the trouble caused by the overflow can be prevented, it is not necessary.

In addition to the embodiment described above, the following application examples are conceivable.
(1) In the period / frequency measuring apparatus 101 of the above-described embodiment, the up edge of the rectangular wave signal is used as a reference for the operation of the apparatus, but the down edge may be used as a reference. It is a design matter whether an edge is acquired by an up edge or a down edge.

(2) In the case of the period / frequency measuring apparatus 101 of the present embodiment, the determination unit 208 includes four determination units: a first determination unit 301, a second determination unit 302, a third determination unit 303, and a fourth determination unit 304. Is provided. The number of determination units varies depending on the delay time and the number of delay elements 202 that subdivide the base clock.
In the period / frequency measuring apparatus 101 of this embodiment, the delay element 202 has a delay time that divides the base clock period into four. In that case, the determination unit provided in the determination unit 208 requires a total number of determination units including one determination unit that determines whether all the registers match and one determination unit including one mismatch determination circuit 403 as many as the number of registers. Become.
Since the mismatch determination circuit 403 determines a mismatch between adjacent registers, only one mismatch is required.
Note that the determination unit disclosed in FIGS. 4 and 5 is an example, and any means may be used as long as it is a configuration that realizes determination of matching of all registers and determination of mismatch of adjacent registers. In particular, when the program is configured, it is determined whether the values stored in the variables match or not, instead of the configuration shown in FIG.

(3) FIG. 8 is a block diagram of an extended arithmetic unit, which is an application example of the period / frequency measuring apparatus 101 of the present embodiment.
The extended calculation unit 801 has a configuration in which a differentiator 802 is added to the calculation unit 108 in FIG. 1, and replaces the calculation unit 108 in FIG.
The count value output from the period counter 105 is converted into time information by the adder 803 and then added to the time information output from the time width measuring unit 106. Data output from the adder 803 is period information of a rectangular wave signal.

The divider 804 divides the numerical data 805 of “1” by the time information output from the adder 803. Data output from the divider 804 is frequency information of a rectangular wave signal.
When this frequency information is differentiated by the differentiator 802, the degree of frequency increase / decrease, that is, acceleration can be obtained.
As described above, in the case of the period / frequency measuring apparatus 101 of the present embodiment, when the differentiator 802 for differentiating the measured period information and / or frequency information is provided, it also functions as an acceleration measuring apparatus that measures the acceleration of an arbitrary tacho pulse. Can be made.
The differentiator 802 may differentiate the period. In this case, the divider 804 and the numerical data 805 are unnecessary.

(4) By providing two period / frequency measuring devices 101 of this embodiment in parallel and comparing the respective frequency measurement values, the frequency and phase difference can be detected. At that time, by driving the two period / frequency measuring devices 101 with the same base clock, a highly accurate frequency and phase difference can be detected.
FIG. 9 is a block diagram of the frequency phase difference measuring apparatus. FIG. 9 shows a specific example in which two rectangular wave signal sources are provided from a motor as an example of a measurement target input to the frequency phase difference measuring apparatus 901.

  The motor 902 is provided with two shielding disks 903 and 904 and photo interrupters 905 and 906. The shielding disks 903 and 904 rotate in conjunction with driving objects (not shown). Due to factors such as torsion and slip that occur between the shaft 907 of the motor 902 and the object to be driven, a rotational deviation occurs between the shielding disks 903 and 904. The frequency phase difference measuring device 901 receives a first rectangular wave signal obtained from the photo interrupter 905 and a second rectangular wave signal obtained from the photo interrupter 906, detects the frequency and phase difference, and displays the display unit. 103.

The first frequency measurement unit 908 includes a first period counter 909, a first time width measurement unit 910, and a first calculation unit 911.
The second frequency measurement unit 912 includes a second period counter 913, a second time width measurement unit 914, and a second calculation unit 915.
The first cycle counter 909 and the second cycle counter 913 have the same configuration as the cycle counter 105 of FIG.
The first time width measurement unit 910 and the second time width measurement unit 914 have the same configuration as the time width measurement unit 106 in FIG.
The first calculation unit 911 and the second calculation unit 915 have the same configuration as the calculation unit 108 in FIG.
The base clock oscillator 107 supplies a base clock to the first period counter 909 and the first time width measuring unit 910, and the second period counter 913 and the second time width measuring unit 914.
The comparison calculation unit 916 calculates the difference between the frequency measurement value of the first rectangular wave signal output from the first calculation unit 911 and the frequency measurement value of the second rectangular wave signal output from the second calculation unit 915. Calculate and output to the display unit 103 as the value of the frequency difference and the phase difference.

(5) Moreover, the period measuring device, the acceleration measuring device, and the frequency phase difference measuring device according to the present embodiment can take the following configurations.
<< 1 >>
The period measuring device of this embodiment is
A base clock oscillator that oscillates the base clock; and
A period counter that measures the period of the input signal using the base clock;
A multi-stage delay comprising a plurality of delay elements that subdivide the period of the base clock into equal intervals;
A counter for counting the base clock;
A plurality of registers for obtaining the count value of the counter at the timing of the input signal and the output signals of the delay elements of the multi-stage delay;
A determination unit that compares values of the plurality of registers and determines a time difference between an edge of the input signal and an edge of the base clock;
An arithmetic unit that calculates a period of the input signal using time information output from the determination unit and a value of the period counter;
<< 2 >>
The acceleration measuring device of the present embodiment is
A base clock oscillator that oscillates the base clock; and
A period counter that measures the period of the input signal using the base clock;
A multi-stage delay comprising a plurality of delay elements that subdivide the period of the base clock into equal intervals;
A counter for counting the base clock;
A plurality of registers for obtaining the count value of the counter at the timing of the input signal and the output signals of the delay elements of the multi-stage delay;
A determination unit that compares values of the plurality of registers and determines a time difference between an edge of the input signal and an edge of the base clock;
And calculating a period of the input signal using time information output by the determination unit and a value of the period counter, and then differentiating the period or a frequency calculated from the period.
<< 3 >>
The frequency phase difference measuring apparatus of the present embodiment is
A base clock oscillator that oscillates the base clock; and
A period counter that measures the period of the input signal using the base clock; a multi-stage delay that includes a plurality of delay elements that subdivide the period of the base clock at equal intervals; a counter that counts the base clock; and the input signal And a plurality of registers for obtaining the count value of the counter at the timing of each output signal of the delay element of the multi-stage delay, and comparing the values of the plurality of registers to determine the edges of the input signal and the base clock edge A first frequency measurement unit comprising: a determination unit that determines a time difference between; and a calculation unit that calculates the frequency of the input signal using time information output from the determination unit and a value of the period counter;
A second frequency measurement unit having the same configuration as the first frequency measurement unit;
A comparison operation unit that calculates a difference between the first frequency measurement value output from the first frequency measurement unit and the second frequency measurement value output from the second frequency measurement unit;

In the present embodiment, the period / frequency measurement device 101, the acceleration measurement device, and the frequency phase difference measurement device have been disclosed.
A multi-stage delay 201 including a plurality of delay elements 202 that subdivide the base clock cycle at equal intervals is used to delay an input rectangular wave signal and register the value of the counter 203 at a timing obtained from each delay element 202. And by comparing the values of the respective registers, it is possible to determine at which timing of the base clock the up edge of the rectangular wave signal is located. Then, by giving the value of the deviation on the time axis according to the determination result to the value of the period obtained by the period counter 105, the resolution of the period measurement can be improved.

  The embodiment of the present invention has been described above. However, the present invention is not limited to the above-described embodiment, and other modifications may be made without departing from the gist of the present invention described in the claims. Includes application examples.

  DESCRIPTION OF SYMBOLS 101 ... Period / frequency measuring device, 102 ... Rectangular wave signal source, 103 ... Display part, 104 ... External output terminal, 105 ... Period counter, 106 ... Time width measuring part, 107 ... Base clock oscillator, 108 ... Calculation part, 201 ... multi-stage delay, 202, 202a, 202b, 202c ... delay element, 203 ... counter, 204 ... first register, 205 ... second register, 206 ... third register, 207 ... fourth register, 208 ... determination unit, 301 ... First determination unit, 302 ... second determination unit, 303 ... third determination unit, 304 ... fourth determination unit, 305 ... time width data output unit, 401, 401a, 401b, 401c, 401d, 401e, 401f, 401g, 401h, 401i ... coincidence determination circuit, 402a, 402b, 402c, 402d ... AND 403, 403a, 403b, 403c ... mismatch judgment circuit, 501 ... exclusive NOR gate, 502 ... AND gate, 503 ... exclusive OR gate, 504 ... OR gate, 801 ... extended arithmetic unit, 802 ... differentiator, 803 ... Adder, 804 ... divider, 805 ... numerical data, 901 ... frequency phase difference measuring device, 902 ... motor, 903 ... shielding disk, 905 ... photo interrupter, 906 ... photo interrupter, 907 ... axis, 908 ... first frequency measurement , 909 ... first period counter, 910 ... first time width measurement part, 911 ... first calculation part, 912 ... second frequency measurement part, 913 ... second period counter, 914 ... second time width measurement part, 915 ... second calculation unit, 916 ... comparison calculation unit

Claims (2)

  A frequency measuring device using a period measuring method, comprising at least one delay means for subdividing in a base clock period. A frequency phase difference comparison apparatus characterized in that the means of claim 1 is employed in two frequency measurement apparatuses driven by a single base clock generation means.

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