JP2012151359A - Capacitor built-in wiring board, method of manufacturing capacitor built-in wiring board, and capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a capacitor built-in wiring board, along with a manufacturing method thereof and a capacitor thereof, capable of incorporating a capacitor which has a dielectric body of high specific dielectric constant and has a good characteristic by a simple process.SOLUTION: The capacitor built-in wiring board includes: a ceramic dielectric single layer; first and second metal conductor layers which have the same surface shape as that of the dielectric single layer and are provided to tightly contact to each surface of the dielectric single layer; first and second conductive member layers provided on the first and second metal conductor layers respectively; a plate-like organic material member in which a laminate is arranged not to generate a gap at the edge of an opening, with the laminate having first and second surfaces and an opening connecting them, containing the dielectric single layer, the first and second metal conductor layers, and the first and second conductive member layers in such a manner as the first and second conductive member layers are positioned on the first and second surface sides, at the opening; and first and second wiring patterns provided on the first and second surfaces of the organic material member respectively.

Description

  BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor built-in wiring board with a built-in capacitor element, a method for manufacturing the same, and a capacitor used therefor, and in particular, a capacitor built-in wiring board considering compatibility between general wiring board materials and capacitor performance , A manufacturing method thereof, and a capacitor.

  Examples of the structure in which the capacitor element is built in and provided in the wiring board include those disclosed in the following patent documents. In a general wiring board using an organic material (resin material) for an insulating layer, a resin-based material must be used as a capacitor dielectric material from the viewpoint of heat resistance of the organic material. The temperature (for example, 600 ° C. to 1200 ° C.) when the ceramic dielectric is fired in the course of manufacturing greatly exceeds the heat resistance temperature (for example, two hundred and several tens of degrees C.) of the organic material of the wiring board.

  However, with resin-based dielectric materials, the content of filler, which is a dielectric substance, is limited in terms of consistency with the resin material of the wiring board and mechanical strength, making it difficult to make capacitors with large capacitance. There is. Ceramic dielectrics have a relative dielectric constant of 1000 or more, but resin-based dielectric materials have a relative dielectric constant of about 50, which is very different.

  In addition, since the resin-based dielectric material has the property of being cured and shrunk, the area may not be set with good controllability depending on the manufacturing method. In this case, the accuracy of setting the capacitance as an element becomes difficult. In addition, after it is made, it also has a property of causing characteristic change due to size change due to hygroscopicity and thermal expansion.

  In addition, the capacitor built-in wiring board is different from simply making a capacitor element. In order to obtain a structure in which this is included in the wiring board, the process tends to be complicated, resulting in productivity and cost problems. Cheap.

Japanese Patent Laid-Open No. 10-56251 US Pat. No. 5,079,069 US Pat. No. 6,349,456 JP 2006-245588 A

  The present invention has been made in consideration of the above-described circumstances, and has a capacitor-embedded wiring board with a built-in capacitor element, a method for manufacturing the same, and a capacitor used therefor having a dielectric having a high relative dielectric constant and characteristics. An object of the present invention is to provide a capacitor built-in wiring board capable of incorporating a good capacitor by a simple process, a method for manufacturing the same, and a capacitor used therefor.

  In order to solve the above-described problems, a capacitor-embedded wiring board according to one aspect of the present invention has a ceramic dielectric single layer having a constant surface shape, and a surface shape identical to the surface shape of the dielectric single layer. A first metal conductor layer provided in close contact with one surface of the dielectric single layer; a first conductive member layer provided on the first metal conductor layer; A second metal conductor layer having the same surface shape as that of the dielectric single layer and provided in close contact with the other surface of the dielectric single layer; and the second metal A second conductive member layer provided on the conductor layer; a first surface; a second surface; and an opening penetrating from the first surface to the second surface. And in the opening, the first conductive member layer is positioned on the first surface side, and the second conductive member layer is positioned on the second surface. A laminated body having a dielectric single layer, the first metal conductor layer, the first conductive member layer, the second metal conductor layer, and the second conductive member layer is connected to an edge of the opening. A plate-shaped organic material member disposed so as not to generate a gap therebetween, and a first surface provided on the first surface of the organic material member so as to cover at least the first conductive member layer And a second wiring pattern provided on the second surface of the organic material member so as to cover at least the second conductive member layer.

  This wiring board has a structure in which a built-in capacitor portion is suitable for being formed as a process different from a process such as a lamination process for manufacturing a wiring board. The capacitor portion has a ceramic dielectric and has a simple structure, and can itself be formed by a simple process. Therefore, this wiring board is a wiring board with a built-in capacitor that can incorporate a capacitor having a dielectric having a high relative dielectric constant and good characteristics by a simple process.

  In addition, a method for manufacturing a capacitor built-in wiring board according to another aspect of the present invention includes a ceramic dielectric single layer having a constant surface shape, and a surface shape identical to the surface shape of the dielectric single layer. A first metal conductor layer provided in close contact with one surface of the dielectric single layer, and a surface shape identical to the surface shape of the dielectric single layer. A step of forming a laminate having a second metal conductor layer provided in close contact with the other surface of the first layer, and a first conductive member on the first metal foil. The step of arranging the first metal conductor layer side of the laminate opposite to each other through the composition, and on the first metal foil, from the laminate corresponding to the position of the laminate A step of laminating a prepreg provided with a large through-opening, and the second of the laminated body placed on the first metal foil Applying the second composition to be the second conductive member on the metal conductor layer, placing the second metal foil on the prepreg on the first metal foil, pressurizing and heating The prepreg is provided with fluidity so that the prepreg adheres to the laminate with fluidity, and the second conductive member and the second metal conductor layer are formed by the second conductive member. Stacking and integrating the first metal foil, the prepreg, the laminate, and the second metal foil by changing the prepreg and the second composition so as to connect, After the prepreg is cured, patterning the first metal foil so that a pattern covering at least the first conductive member is formed; and after the prepreg is cured, the second Pattern covering at least the conductive member As emissions is formed, characterized by comprising the step of patterning the second metal foil.

  This manufacturing method is one method for manufacturing the capacitor built-in wiring board. The wiring board manufactured in this way is a so-called double-sided wiring board, but has a metal foil (= wiring pattern) pre-patterned on the surface instead of the first metal foil in order to make a multilayer wiring board. An insulating plate can also be used. For the same purpose, instead of the second metal foil, an insulating plate having a metal foil (= wiring pattern) patterned in advance on the surface can be used. In these cases, the patterning is performed in advance without patterning the metal foil after the entire lamination and integration.

  A capacitor according to still another aspect of the present invention includes a ceramic dielectric single layer having a constant surface shape, and a surface shape identical to the surface shape of the dielectric single layer. A first metal conductor layer disposed in close contact with one surface of the single layer and positioned as an outermost layer having no laminated structure on the side opposite to the side of the dielectric single layer; A laminated structure on the side opposite to the side of the dielectric single layer, which has the same surface shape as that of the single layer of the body and is in close contact with the other side of the dielectric single layer. And a second metal conductor layer positioned as the outermost layer.

  This capacitor is a capacitor used for the capacitor built-in wiring board.

  According to the present invention, a capacitor built-in wiring board with a built-in capacitor element, a method for manufacturing the same, and a capacitor used therefor, a capacitor having a dielectric with a high relative dielectric constant and good characteristics is built in a simple process. It is possible to provide a capacitor built-in wiring board, a manufacturing method thereof, and a capacitor used therefor.

Sectional drawing which shows typically the structure of the wiring board with a built-in capacitor which is one Embodiment of this invention. Process drawing which shows the manufacturing process of the capacitor built-in wiring board shown in FIG. FIG. 3 is a continuation diagram of FIG. 2, and a process diagram schematically showing a cross-sectional view of a manufacturing process of the capacitor built-in wiring board shown in FIG. 1. Process drawing which shows typically the process in which the capacitor element used for the capacitor built-in wiring board shown in FIG. Sectional drawing which shows typically the structure of the wiring board with a built-in capacitor which is another embodiment of this invention. Process drawing which shows a part of manufacturing process of the capacitor built-in wiring board shown in FIG.

  As an embodiment of the present invention, the first conductive member layer is a layer obtained by curing an anisotropic conductive paste, an anisotropic conductive film, or a conductive paste having no anisotropy, It can be. These are examples for forming the first conductive member layer. In general, a film is easier to use than a paste because the shape controllability after curing is better. In addition, in the case of an anisotropic material, the portion that protrudes from the gap does not exhibit conductivity, so it is less likely to adversely affect other areas of the wiring board and is used more than a non-anisotropic material. Cheap.

  As an embodiment, the first conductive member layer may be a solder layer, and the first wiring pattern may cover the entire region of the first conductive member layer. . The first conductive member layer can be a solder layer in addition to the paste or film as described above. When solder is used, the first wiring pattern is formed in a pattern that covers the entire area of the solder so that the solder is not exposed on the first surface of the organic material member. If the solder is exposed, it is melted when the component is mounted on the wiring board (secondary mounting), and the solder flows out to prevent this.

  As an embodiment, the second conductive member layer can be a layer obtained by curing an anisotropic conductive paste or a conductive paste having no anisotropy. These are examples for forming the second conductive member layer. In the case of an anisotropic material, the portion protruding from the gap does not exhibit conductivity, so that it is less likely to adversely affect other areas of the wiring board and is easier to use than a material without anisotropy. Further, by using the paste, the amount can be controlled to appropriately correspond to the volume to be filled between the second metal conductor layer and the second wiring pattern.

  As an embodiment, the second conductive member layer may be a solder layer, and the second wiring pattern may cover the entire region of the second conductive member layer. . The second conductive member layer can also be a solder layer in addition to being derived from the paste. When solder is used, the second wiring pattern is formed in a pattern that covers the entire area of the solder so that the solder is not exposed on the second surface of the organic material member. If the solder is exposed, it is melted when the component is mounted on the wiring board (secondary mounting), and the solder flows out to prevent this.

  Based on the above, embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing a configuration of a capacitor built-in wiring board according to an embodiment of the present invention. As shown in the figure, this capacitor built-in wiring board includes an insulating layer 11, wiring patterns (wiring layers) 21 and 22, an interlayer connector 31, a capacitor element 40, and conductive adhesive layers (conductive member layers) 51 and 52. Have Here, the capacitor element 40 includes a dielectric single layer 41 and metal conductor layers 42 and 43.

  This wiring board is a so-called double-sided wiring board, and has a structure in which a capacitor element 40 is provided inside the board thickness. Here, the capacitor element 40 is disposed inside so as to replace a partial region of the insulating layer 11 which is a plate member as a wiring board, and there is no gap between the capacitor element 40 and the insulating layer 11. Although it is structurally simple and the manufacturing process will be described later, manufacturing with less burden on the process is possible.

  About the capacitor element 40 of this wiring board and each part except the circumference | surroundings, the thing similar to the structure of a well-known double-sided wiring board may be sufficient. For example:

  The insulating layer 11 is an organic material member (plate material) such as glass epoxy resin. The thickness is a little thicker than that according to the thickness of the capacitor element 40, and can be, for example, about 50 μm to 100 μm. The wiring patterns 11 and 12 can be obtained by patterning a metal foil (copper foil) having a thickness of 18 μm, for example, laminated on both surfaces of the insulating layer 11. As the interlayer connector 31, here, a conductor derived from bumps of a conductive paste formed on a metal foil by screen printing is used. The interlayer connection body 31 is not limited to this, but may be another known one, for example, a conductor formed by plating on the inner wall of a through hole, a conductor derived from a conductive paste filled in a through hole, or plating on a metal foil. It can be replaced with a grown metal bump or a bump obtained by etching a metal plate.

  The capacitor element 40 is electrically connected to the wiring patterns 22 and 21 by electrically conductive adhesive layers 51 and 52, respectively. For this reason, the insulating layer 11 has an opening penetrating between both surfaces, and a laminated body including the capacitor element 40 and the conductive adhesive layers 51 and 52 is disposed in the opening. Here, there is no gap between the laminated body and the edge of the opening, and no other member is interposed, and the structure is simple.

  The dielectric single layer 41 of the capacitor element 40 is a ceramic single layer, and has a certain surface shape (for example, a rectangle). The metal conductor layers 42 and 43 each have the same surface shape as that of the dielectric single layer 41 and are provided in close contact with both surfaces of the dielectric single layer 41. The metal conductor layers 42 and 43 are conductor layers functioning as both electrodes of the capacitor element 40, whereby the capacitor element 40 is electrically connected via the conductive adhesive layers 51 and 52 as described above. The wiring patterns 22 and 21 are connected. The wiring patterns 22 and 21 are formed on each surface of the insulating layer 11 so as to cover at least the conductive adhesive layers 51 and 52.

  The thickness of the dielectric single layer 41 of the capacitor element 40 can be, for example, 40 μm to 60 μm. As will be described later, the sintering is obtained by firing a green sheet (for example, containing barium titanate powder) before firing. It is a layer of the body. The metal conductor layers 42 and 43 are, for example, conductor layers obtained by forming a conductor paste layer on both surfaces of the dielectric single layer 41 and baking the layers, and have a thickness of, for example, several μm. The planar size of the capacitor element 40 having the dielectric single layer 41 and the metal conductor layers 42 and 43 can be considered to be about several hundred μm square to 2 mm square, for example, depending on the capacitance to be set. .

  The conductive adhesive layer 51 is an anisotropic conductive paste, anisotropic conductive film, or conductive material having no anisotropy provided between the metal conductor layer 42 of the capacitor element 40 and the wiring pattern 22. It is a layer obtained by curing the conductive paste (here, an anisotropic conductive film is used). In general, this layer is easier to use in the case of a film than a paste because the shape controllability after curing is better. In addition, in the case of an anisotropic material, the portion that protrudes from the gap does not exhibit conductivity, so it is less likely to adversely affect other areas of the wiring board and is used more than a non-anisotropic material. Cheap.

  The conductive adhesive layer 52 is obtained by curing an anisotropic conductive paste or an anisotropic conductive paste provided between the metal conductor layer 43 of the capacitor element 40 and the wiring pattern 21. (Here, an anisotropic conductive paste is used). In the case of an anisotropic material, this layer has no anisotropy because it is unlikely to adversely affect other areas of the wiring board because the portion protruding from the gap does not exhibit conductivity. Easy to use. Further, by using the paste, the amount can be controlled to appropriately correspond to the volume to be filled between the metal conductor layer 43 and the wiring pattern 21.

  As will be described later, this wiring board has a structure that is suitable for forming a part of the built-in capacitor element 40 as a process different from a process such as a lamination process for manufacturing the wiring board. The capacitor element 40 includes a ceramic dielectric single layer 41 and has a simple structure, which can be formed by a simple process. Therefore, this wiring board is a wiring board with a built-in capacitor that has a dielectric having a high relative dielectric constant and can incorporate a capacitor having a good characteristic by a simple process.

  Next, a method for manufacturing the capacitor built-in wiring board shown in FIG. 1 will be described with reference to FIGS. 2 to 3 are a series of process diagrams, each of which is a process diagram schematically showing a manufacturing process of the capacitor built-in wiring board shown in FIG. 2 and 3, the same or equivalent components as those shown in FIG. 1 are denoted by the same reference numerals.

  First, as shown in FIG. 2 (a), a paste-like conductive composition to be an interlayer connection 31 is formed on a metal foil (electrolytic copper foil) 22A having a thickness of 18 μm, for example, by screen printing. Form bumps. This conductive composition is obtained by dispersing fine metal particles such as silver, gold and copper or fine carbon particles in a paste-like resin. After the interlayer connector 31 is printed, it is dried and cured.

  Next, as shown in FIG. 2B, the FR-4 prepreg 11A is laminated on the metal foil 22A to penetrate the interlayer connector 31, so that the head is exposed. The tip may be crushed by plastic deformation during or after exposure. In the prepreg 11A, an opening 11o is provided in advance in a region corresponding to a capacitor element to be built in and included.

  Subsequently, as shown in FIG. 2 (c), a conductive adhesive 51A (here, different adhesive) which is a composition for fixing a built-in capacitor element on the metal foil 22A in the opening 11o. An isotropic conductive film is placed using, for example, a mounter. As already described, an anisotropic conductive paste or a conductive paste having no anisotropy can be used instead of the anisotropic conductive film. In these cases, for example, a dispenser can be used on the metal foil 22A.

  Next, as shown in FIG. 3A, the capacitor element 40 is disposed on the conductive adhesive 51A using, for example, a mounter. The structure of the capacitor element 40 has already been described, but at the time of this arrangement, the capacitor element 40 that has been made in advance through another process is used. An example of a process for forming the capacitor element 40 will be described later (FIG. 4). For convenience of the subsequent steps, the capacitor element 40 may be temporarily fixed by thermally curing the conductive adhesive 51A to some extent at the time of this arrangement. For temporary fixing, the capacitor element 40 is disposed on the conductive adhesive 51 </ b> A by a flip chip bonder that can be heated instead of the mounter.

  Next, as shown in FIG. 3B, a conductive adhesive 52A (an anisotropic conductive paste in this case) as a composition is applied onto the capacitor element 40 using, for example, a dispenser. As already described, a conductive paste having no anisotropy can be used instead of the anisotropic conductive paste. The amount of the conductive adhesive 52A is set corresponding to the volume to be filled between the capacitor element 40 and the metal foil 21A. This is because the tolerance between the thickness of the capacitor element 40 and the thickness of the prepreg 11 </ b> A depends on the setting, and the volume varies depending on the planar size of the capacitor element 40.

  Next, as shown in FIG. 3C, a metal foil (electrolytic copper foil) 21A is laminated on the prepreg 11A, and is pressed and heated to integrate the whole (FIG. 3D). The heating temperature can be set to 175 ° C., for example. At this time, due to the fluidity of the prepreg 11A obtained by heating, the prepreg 11A flows toward the space around the capacitor element 40 and the edge of the opening 11o moves. Thus, the prepreg 11A is in close contact with the capacitor element 40 and the like, and no gap is generated. The prepreg 11 </ b> A is completely cured to become the insulating layer 11.

  Further, the metal foil 22A and the capacitor element 40 (the metal conductor layer 42) are bonded by thermosetting of the conductive adhesive 51A, and the metal foil 21A and the capacitor element 40 (by the thermosetting of the conductive adhesive 52A). To the metal conductor layer 43). Furthermore, the metal foil 21 </ b> A is also in close contact with the interlayer connector 31, and an electrical continuity is established between them.

  After the structure shown in FIG. 3 (d) is obtained, the wiring patterns 21 and 22 are formed by patterning the metal foils 21A and 22A on both the upper and lower surfaces using a well-known photolithography to obtain the structure shown in FIG. A capacitor built-in wiring board as shown can be obtained. Normally, when used as a double-sided wiring board as it is, a layer of a solder resist (not shown) is formed on both the upper and lower surfaces, except for the land regions by the wiring layers 21 and 22 where solder is to be mounted by component mounting or the like. can do. The solder resist layer holds the molten solder at the time of solder connection to the land portion, and thereafter functions as a protective layer. An Ni / Au plating layer (not shown) with high corrosion resistance may be formed on the surface layer of the land portion.

  Next, with reference to FIG. 4, an example of a process for forming the capacitor element 40 mentioned above will be described. FIG. 4 is a process diagram schematically showing a process of manufacturing the capacitor element 40 used in the capacitor built-in wiring board shown in FIG. In the figure, the same or equivalent parts as those shown in the already described figures are denoted by the same reference numerals.

  First, as shown in FIG. 4A, a very thin green sheet 41A corresponding to the thickness of the dielectric single layer 41 of the capacitor element 40 to be produced is formed and prepared. The green sheet 41A mainly includes, for example, a dielectric powder (for example, barium titanate powder), and in addition, a metal additive (for adjusting characteristics such as a relative dielectric constant) and a sintering aid (enhance sinterability). For example), a composition having a binder resin, an organic solvent, and the like. In order to form the thin film, a known method such as a doctor blade method can be used. After the formation, it is punched into an appropriate size (a size of about a semiconductor wafer) that can be applied to a dicer.

  Next, as shown in FIG. 4B, a layer of the conductor paste 42A to be the metal conductor layer 42 is formed on one side of the green sheet 41A to a predetermined thickness by printing using the squeegee 101, for example. . The conductor paste 42A is, for example, a composition in which fine particles such as Ag and Cu, which are mainly conductors, are used as fillers and dispersed in a low-melting glass as a binder. After the layer of the conductor paste 42A is formed on one surface of the green sheet 41A, the conductor paste 42A is temporarily dried at a temperature of 100 ° C. to 300 ° C., for example.

  After temporary drying of the conductor paste 42A, as shown in FIG. 4C, a layer of the conductor paste 43A to be the metal conductor layer 43 is formed on the other surface of the green sheet 41A in the same manner as the conductor paste 42A. It is formed to a predetermined thickness by printing using the composition of Then, similarly to the case of the conductive paste 42A, for example, the conductor paste 43A is temporarily dried at a temperature of 100 ° C. to 300 ° C.

  Next, the sheet having the three-layer structure obtained above is fired. In this case, the firing temperature can be set to, for example, 850 ° C. to 900 ° C., which is a preferable firing temperature at which the metal fine particles of the conductive pastes 42A and 43A are connected to form a metal layer. The firing atmosphere is preferably a non-oxidizing atmosphere in order to suppress oxidation of the metal conductor layers 42 and 43 to be formed.

  Subsequently, the sintered body having the three-layer structure obtained by the above firing is cut and separated into pieces by using, for example, a dicer along the cut line CL corresponding to the required area as the capacitor element 40 to be obtained (see FIG. 4 (d)). Thus, the capacitor element 40 for use in the capacitor built-in wiring board shown in FIG. 1 can be obtained. In addition, as the metal conductor layers 42 and 43, as a part of these, after firing the conductive pastes 42A and 43A, an Sn (tin) layer may be additionally provided as a surface layer thereof. Good. In this way, good solderability can be ensured even when solder is used instead of the conductive adhesives 51A and 52A (described later), which is convenient.

  Since the capacitor element 40 is obtained as a single piece as described above, it is very easy to set the shape and area to be finally obtained. In addition, the capacitor element 40 is provided on both surfaces of the dielectric single layer 41 with the metal conductor layers 42 and 43 having the same surface shape as that of the dielectric single layer 41. Therefore, the capacitance is determined by these alone, and when used for a wiring board, it is not affected by the area where the conductive adhesive layers 51 and 52 are spread and the pattern shape of the wiring patterns 21 and 22. This is also a great advantage.

  In the method described above, the green sheet 41A and the conductive pastes 42A and 43A are fired at the same time to obtain a sheet before singulation, but the green sheet 41A is fired and the conductive pastes 42A and 43A. May be provided as separate steps. In this case, for example, the green sheet 41A is first fired at a temperature more appropriate as the firing temperature, for example, 1100 ° C. to 1300 ° C. In general, firing at a higher temperature results in a ceramic with a higher dielectric constant.

  After the green sheet 41A is fired, a layer of the conductor paste 42A is formed and temporarily dried, and further a layer of the conductor paste 43A is formed. Then, the formed conductor pastes 42A and 43A are baked at a temperature of 500 ° C. to 900 ° C., for example. Thereby, the metal conductor layers 42 and 43 are formed so as to be in close contact with the dielectric single layer 41.

  Capacitor element 40 can be formed in a separate step apart from the step of forming a wiring board by any of the above methods. Therefore, a capacitor having a high dielectric constant having a high dielectric constant utilizing a high firing temperature is not limited to the heat-resistant temperature of the organic material of the wiring board (for example, 2 to several tens of degrees Celsius). In this respect, if a ceramic dielectric layer corresponding to the capacitor element 40 is directly printed and formed as a layer directly on, for example, the metal foil 22A, it is not limited to the heat resistant temperature of the organic material of the wiring board. However, in this case, the printed dielectric layer loses its shape due to gravity, the dielectric layer warps after firing due to the difference in thermal expansion coefficient between the metal foil 22A and the dielectric layer, or the dielectric layer is cured and contracted. This makes it difficult to control the shape.

  The capacitor element 40 has an advantage that it has a dielectric single layer 41 and metal conductor layers 42 and 43 which are the outermost layers provided in close contact with the both surfaces, and is very useful as a film element mode. The point which can be formed with a thin structure is mentioned. As a result, since the wiring board has this built-in tool, it is not particularly necessary to take measures to make the insulating material layer thicker than usual. Therefore, it can be used for a very thin wiring board and, of course, can be applied to a wiring board having a thicker insulating material layer.

  As an application example to a wiring board having a thicker insulating material layer, for example, the electrical connection between the metal conductor layer 43 of the capacitor element 40 and the wiring pattern 21 opposed thereto is replaced with the conductive adhesive 52A. A configuration in which conductor bumps (for example, formed by plating) formed on the metal foil 21A are considered. In this case, the conductor bump functions as a contact between the capacitor element 40 and the wiring pattern 21 through the thicker insulating layer 11 in the vertical direction.

  As another application example of the capacitor element 40 in the wiring board having a thicker insulating material layer, a structure in which both the metal conductor layers 42 and 43 are electrically connected to the wiring pattern 22 side is conceivable. In this case, the metal conductor layer 42 is electrically connected to the wiring pattern 22 by the conductive adhesive layer 51, while the metal conductor layer 43 covers from the metal conductor layer 43 to the metal foil 22A. The conductive paste thus formed is electrically connected to the metal foil 22. The insulating layer 11 is positioned above the conductive paste.

  Next, a capacitor built-in wiring board according to another embodiment will be described with reference to FIG. FIG. 5 is a cross-sectional view schematically showing a configuration of a capacitor built-in wiring board according to another embodiment. In the figure, the same or equivalent parts as those shown in the already described figures are denoted by the same reference numerals.

  This capacitor built-in wiring board is a multilayer (8 layers) wiring board in which the semiconductor element component 61 and the chip resistor (electrical component) 62 are embedded and mounted, and in addition, the capacitor element 40 (401, 401 having the structure already described). 402, 403). In order to include the capacitor element 40 and the like inside, conductive adhesive layers 51 and 52 are interposed on the upper and lower surfaces thereof (the same applies to the other capacitor elements 401 and the like). In addition to these, insulating layers (insulating plates) 11 to 17, wiring layers (wiring patterns) 21 to 28, interlayer connectors 31 to 37, solders 71 and 72, and solder resists 81 and 82 are included.

  The semiconductor element component 61 is, for example, an LGA semiconductor element based on a wafer level chip scale package, and includes at least a semiconductor chip and a grid-arranged surface mounting terminal 61a formed on the semiconductor chip. The surface mounting terminals 61 a of the semiconductor element component 61 and the lands included in the wiring layer 22 are electrically and mechanically connected by solder 71.

  The chip resistor 62 is a surface mount type component, and its planar size is, for example, 0.6 mm × 0.3 mm. Terminals are provided at both ends, and a lower side thereof is opposed to a land included in the wiring layer 22. The terminal of the chip resistor 62 and the land are electrically and mechanically connected by solder 72. Alternatively, the chip resistor 42 may be embedded or embedded even if it is a chip capacitor or a chip inductor.

  Each of the wiring layers 21 and 28 is a wiring layer on the main surface, and various components (not shown) can be mounted thereon. Solder resist 81 that retains the solder melted at the time of solder connection on the land portion on the main surface except for the land portions of the wiring layers 21 and 28 on which solder (not shown) is to be placed in this mounting, and then functions as a protective layer. , 82 are formed. An Ni / Au plating layer (not shown) with high corrosion resistance may be formed on the surface layer of the land portion.

  Each of the wiring layers 21 to 28 is obtained by processing a metal (copper) foil into a predetermined pattern. The insulating layers 11 to 17 separating the wiring layers 21 to 28 are each a rigid material made of, for example, a glass epoxy resin. The insulating layers 13 to 15 have openings corresponding to the embedded semiconductor element component 61 and chip resistor 62, and provide a space for accommodating the components 61 and 62. The insulating layers 12 and 16 are deformed so as to fill the space of the opening of the insulating layers 13 to 15 for the embedded parts 61 and 62 so that a space serving as a void does not occur inside.

  The wiring layer 21 and the wiring layer 22 can be conducted by an interlayer connector 31 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 11. Similarly, the wiring layer 22 and the wiring layer 23 can be conducted by an interlayer connector 32 provided through the insulating layer 12. The wiring layer 23 and the wiring layer 24 can be conducted through an interlayer connector 33 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 13.

  Further, similarly, the wiring layer 24 and the wiring layer 25 can be conducted through an interlayer connector 34 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 14. The wiring layer 25 and the wiring layer 26 can be conducted through an interlayer connector 35 that is sandwiched between the surfaces of these patterns and penetrates the insulating layer 15. The wiring layer 26 and the wiring layer 27 can be conducted through an interlayer connector 36 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 16. The wiring layer 27 and the wiring layer 28 can be conducted through an interlayer connector 37 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 17.

  Each of the interlayer connectors 31 to 37 has a columnar structure derived from a conductive bump formed by screen printing of a conductive composition, and depends on the manufacturing process in the axial direction (shown in FIG. 5). The diameter changes in the upper and lower stacking directions and the penetration direction. These interlayer connection bodies 31 to 37 can be provided at a high density in a small region, which can contribute to finer substrate design.

  In the multilayer wiring board having the above-described structure, the capacitor element 40 (401, 402, 403) is replaced with a partial region of each of the insulating layers 11 (14, 16, 17) which are plate members as wiring boards. Arranged inside. Therefore, the degree of freedom of their arrangement is relatively high and does not significantly affect the ease of design as a wiring board. In addition, the process for arranging in this way is easy as described above, which is a great advantage.

  6 is a cross-sectional process diagram illustrating a part of the manufacturing process of the capacitor built-in wiring board illustrated in FIG. The reference numerals in the figure are the same as those in FIG. This process shows the final lamination process for obtaining this capacitor built-in wiring board.

  The laminated member 1 shown in FIG. 6 uses a wiring board that is almost the same as the wiring board with a built-in capacitor shown in FIG. 1 (the reference numerals are also common), and a semiconductor element component 61 and a chip resistor 62 are surface-mounted thereon. It is the member obtained by doing. Here, the state before patterning the metal foil 21A to obtain the wiring layer 21 is used.

  In the laminated member 2, an opening 2 o is formed in a region corresponding to the semiconductor element component 61 and the chip resistor 62. The opening 2o can be formed, for example, immediately before the stacking process shown in FIG. If this point is excluded, it can obtain as follows with reference to the already demonstrated process. That is, the part having the wiring pattern 23, the insulating layer 13, the wiring pattern 24, and the interlayer connector 33 (= double-sided wiring board) is completely explained in the process shown in FIG. No action is required). The same applies to the part having the wiring pattern 25, the insulating layer 15, the wiring pattern 25, and the interlayer connector 35 (= double-sided wiring board).

  Next, on the latter double-sided wiring board, on the side where the wiring pattern 25 is located, an interlayer connector 34 is formed, a prepreg to be the insulating layer 14 is stacked, and the capacitor element 401 is mounted. This point can be described with reference to FIGS. 2 and 3 by using a double-sided wiring board instead of the metal foil 22A. Thereafter, this double-sided wiring board and the former double-sided wiring board are laminated and integrated. Further, the formation of the interlayer connector 32 and the lamination of the prepreg 12A to be the insulating layer 12 are performed on the side where the wiring pattern 23 of the integrated laminated body is located. The laminated member 2 is obtained by forming the opening 2o in the obtained laminate.

  The laminated member 3 is as follows. Of the laminated member 3, the part having the wiring pattern 27, the insulating layer 17, the metal foil 28 </ b> A, the interlayer connector 37, and the capacitor element 403 (= double-sided wiring board with a built-in capacitor) is shown in FIGS. 2 and 3. The explanation is exhausted. However, the metal foil 28A is not patterned at this stage. Next, on this double-sided wiring board, on the side where the wiring pattern 27 is located, the interlayer connection 36 is formed, the prepreg 16A to be the insulating layer 16 is stacked, and the capacitor element 402 is mounted. Corresponding to the position of the capacitor element 402, the prepreg 16A is provided with an opening 16o. This is the same as the opening 11o in FIG. Thus, the laminated member 3 is obtained.

  Each of the laminated members 1, 2, and 3 is arranged in the arrangement as shown in FIG. 6, and is pressed and heated by a press. Thereby, the prepregs 12A and 16A are completely cured, and the whole is laminated and integrated. At this time, due to the fluidity of the prepregs 12 </ b> A and 16 </ b> A obtained by heating, the prepregs 12 </ b> A and 16 </ b> A are deformed and enter the space around the semiconductor element component 61 and the chip resistor 62, and no gap is generated. In addition, the wiring layers 22 and 26 are electrically connected to the interlayer connectors 32 and 36, respectively, by this lamination process. Note that the relationship between the prepreg 16A and the wiring patterns 26 and 27 around the capacitor element 402 and the capacitor element 402 (the action that occurs between them) is described with reference to FIGS. 3C and 3D. be able to.

  After the lamination step shown in FIG. 6, the metal foils 28A and 21A on the upper and lower surfaces are patterned in a predetermined manner using well-known photolithography, and further, layers of solder resists 81 and 82 are formed, as shown in FIG. Such a capacitor built-in wiring board can be obtained.

  In this capacitor built-in wiring board, the capacitor element 40 and the like can function as a decoupling capacitance having excellent frequency characteristics for the built-in semiconductor element part 61 and the semiconductor element part mounted on the surface. . That is, the capacitor element 40 and the like can be arranged immediately next to the component 61 and the like, and a layout with less inductance generation due to the pattern length is possible. The capacitor element 40 and the like are much smaller in size in the thickness direction than the chip component such as the chip resistor 62 and can be disposed on any insulating layer of the multilayer wiring board as shown in FIG. .

  Although several embodiments have been described above, the above description is based on the assumption that the conductive members (layers) are the conductive adhesive layers 51 and 52. As the conductive member layer, one or both of the conductive member layers may be solder. The structure in that case is a structure in which a solder layer is present instead of one or both of the conductive adhesive layers 51 and 52 in FIG. Also when using solder, a special manufacturing apparatus or the like is not required, and low-cost manufacturing is possible.

  The process in the case of such an embodiment is as follows. When the conductive adhesive layer 51 is a solder layer, cream solder as a composition is provided on the metal foil 22A instead of the conductive adhesive 51A in FIG. Corresponding to the stage of FIG. 3A, the cream solder can be reflowed to fix the capacitor element 40 on the metal foil. However, the reflow temperature needs to be a temperature at which the prepreg 11A is not thermally cured. For this reason, the solder component of the cream solder has a low melting point.

  Alternatively, the cream solder is not reflowed in the stage of FIG. 3A, but the cream solder is reflowed by heating in the subsequent stage (lamination process) of FIG. You may make it fix on top. As described above, since the lamination process is performed by heating at 175 ° C., for example, cream solder having a low melting point solder component that melts at such a low temperature is used.

  Alternatively, the application of the cream solder is performed on the metal foil 22A in advance before the formation of the interlayer connection body 31 shown in FIG. 2A, and the capacitor element 40 is placed and the cream solder is reflowed. From the formation of the interlayer connector 31 as shown in FIG. 2A, the following steps may be performed. In this case, since the reflow temperature of the cream solder is not limited to the curing temperature of the prepreg 11A, a cream solder having a solder component having a normal melting point (for example, about 220 ° C.) can be used.

  When using cream solder instead of the conductive adhesive 51A, it is preferable to use as little cream solder as possible. If the amount is small, the protrusion from the capacitor element 40 can be avoided, and adverse effects on other parts of the wiring board due to its conductivity can be prevented. Further, if the amount is made small, the adverse effect caused by re-melting and expanding when a component is mounted on the wiring board can be minimized.

  When a solder layer is used instead of the conductive adhesive layer 51, the wiring pattern 22 is a pattern that covers the entire area of the solder so that the solder is not exposed on the surface of the insulating layer 11. Formed. If the solder is exposed, it is melted when the component is mounted on the wiring board (secondary mounting), and the solder flows out to prevent this.

  The case where the conductive adhesive layer 52 is a solder layer is as follows. In this case, cream solder, which is a composition, is provided on the capacitor element 40 in place of the conductive adhesive 52A in FIG. Then, the cream solder is reflowed by heating in the next stage of FIG. 3C (lamination process), and the metal foil 21A and the capacitor element 40 are electrically connected simultaneously with the lamination. As described above, since the lamination process is performed by heating at 175 ° C., for example, cream solder having a low melting point solder component that melts at such a low temperature is used.

  When cream solder is used instead of the conductive adhesive 52A, it is preferable to use as little cream solder as possible. If the amount is small, the protrusion from the capacitor element 40 can be avoided, and adverse effects on other parts of the wiring board due to its conductivity can be prevented. Further, if the amount is made small, the adverse effect caused by re-melting and expanding when a component is mounted on the wiring board can be minimized. In this case, the thickness of the prepreg 11A is set so that the volume to be filled between the capacitor element 40 and the metal foil 21A is as small as possible so that a small amount of cream solder is sufficient.

  DESCRIPTION OF SYMBOLS 1 ... Laminated member, 2 ... Laminated member, 2o ... Built-in component opening part, 3 ... Laminated member, 11, 12, 13, 14, 15, 16, 17 ... Insulating layer, 11A, 12A, 16A ... Prepreg, 11o ... Capacitor element opening, 16o ... Capacitor element opening, 21, 22, 23, 24, 25, 26, 27, 28 ... Wiring layer (wiring pattern), 21A, 22A, 28A ... Metal foil (copper foil), 31, 32, 33, 34, 35, 36, 37 ... interlayer connection body (conductive bump by conductive composition printing), 40 ... capacitor element, 41 ... dielectric single layer, 41 A ... green sheet, 42, 43 ... Metal conductor layer, 42A, 43A ... conductor paste, 51 ... conductive adhesive layer, 51A ... conductive adhesive (before curing), 52 ... conductive adhesive layer, 52A ... conductive adhesive (before curing) 61 ... Semiconductor element Parts (wafer level / electrical parts by chip scale package), 61a... Surface mounting terminals, 62... Chip resistors (electric parts), 71, 72... Solder, 81, 82 .. solder resist, 101. 402, 403: Capacitor element, CL: Cut line.

Claims (7)

A ceramic dielectric single layer having a constant surface shape;
A first metal conductor layer having a surface shape identical to the surface shape of the dielectric single layer and provided in close contact with one surface of the dielectric single layer;
A first conductive member layer provided on the first metal conductor layer;
A second metal conductor layer having the same surface shape as that of the dielectric single layer and provided in close contact with the other surface of the dielectric single layer;
A second conductive member layer provided on the second metal conductor layer;
A first surface and a second surface, and an opening penetrating from the first surface to the second surface; and in the opening, on the side of the first surface The dielectric single layer, the first metal conductor layer, and the first conductive member layer so that the first conductive member layer is positioned on the second surface. A plate-shaped organic material member in which a laminate having the second metal conductor layer and the second conductive member layer is disposed so as not to cause a gap between the edge of the opening;
A first wiring pattern provided on the first surface of the organic material member so as to cover at least the first conductive member layer;
A capacitor built-in wiring board, comprising: a second wiring pattern provided on the second surface of the organic material member so as to cover at least the second conductive member layer.   The first conductive member layer is a layer obtained by curing an anisotropic conductive paste, an anisotropic conductive film, or a conductive paste having no anisotropy. The capacitor built-in wiring board as described. The first conductive member layer is a layer of solder;
The capacitor built-in wiring board according to claim 1, wherein the first wiring pattern covers the entire region of the first conductive member layer.   2. The capacitor built-in wiring board according to claim 1, wherein the second conductive member layer is a layer obtained by curing an anisotropic conductive paste or a conductive paste having no anisotropy. The second conductive member layer is a layer of solder;
The capacitor built-in wiring board according to claim 1, wherein the second wiring pattern covers the entire region of the second conductive member layer. A ceramic dielectric single layer having a constant surface shape, and having the same surface shape as the surface shape of the dielectric single layer, provided in close contact with one surface of the dielectric single layer A first metal conductor layer and a second metal conductor having the same surface shape as that of the dielectric single layer and provided in close contact with the other surface of the dielectric single layer Forming a laminate having a layer; and
Placing the first metal conductor layer side of the laminate facing the first metal foil via the first composition to be the first conductive member;
On the first metal foil, a step of laminating a prepreg provided with a through opening larger than the laminate corresponding to the position of the laminate,
Applying a second composition to be a second conductive member on the second metal conductor layer of the laminate placed on the first metal foil;
Arrange the second metal foil on the prepreg on the first metal foil, pressurize and heat to give fluidity to the prepreg, so that the prepreg adheres to the laminate by fluidity, The first metal is changed by changing the prepreg and the second composition so that the second metal foil and the second metal conductor layer are connected by the second conductive member. Laminating and integrating the foil, the prepreg, the laminate, and the second metal foil;
Patterning the first metal foil so that a pattern covering at least the first conductive member is formed after the prepreg is cured;
Patterning the second metal foil so that a pattern covering at least the second conductive member is formed after the prepreg is cured. Production method. A ceramic dielectric single layer having a constant surface shape;
Laminated on the opposite side of the dielectric single layer, having the same surface shape as the surface of the dielectric single layer, and in close contact with one surface of the dielectric single layer A first metal conductor layer positioned as the outermost layer without structure;
Laminated on the side opposite to the side of the dielectric single layer, having the same surface shape as the surface of the dielectric single layer, and being in close contact with the other side of the dielectric single layer And a second metal conductor layer positioned as an outermost layer having no structure.

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