JP2012133207A - Image display device and driving method for the same - Google Patents

Abstract

An image display apparatus having a small pixel size and a driving method thereof, in which luminance variations of light emitting elements are suppressed.
A reset switch SWR makes a gate electrode and a drain electrode of a driving transistor TRD conductive during a precharge period and a data writing period. The lighting control switch SWI conducts the drain electrode of the drive transistor TRD and the light emitting element IL during the light emission period. The charge discharge switch SWD makes the drain electrode of the drive transistor TRD conductive to the reset control line RES for controlling the potential of the gate electrode during the precharge period. In the precharge period, a potential lower than the drain electrode of the drive transistor TRD is applied to the reset control line RES.
[Selection] Figure 2

Description

  The present invention relates to an image display device having a light emitting element and a driving method thereof.

  An image display apparatus including a plurality of pixel circuits each having a light emitting element (for example, an organic EL element) is known. Each of these pixel circuits is connected to a data line for supplying a data signal (video signal) indicating light emission luminance, and a storage capacitor that holds a potential difference corresponding to the data signal and a potential difference that the storage capacitor holds. And a drive transistor for supplying a current corresponding to the gate-source voltage generated by the light-emitting element to the light-emitting element. The light emitting element emits light with luminance according to the amount of current controlled by the driving transistor, that is, luminance according to the data signal supplied from the data line.

  However, since it is difficult to align the characteristics such as the threshold voltage of the drive transistor with the current manufacturing technology, the luminance of the light emitting element varies for each pixel circuit only with the above configuration.

  Therefore, conventionally, a pixel circuit that corrects the potential difference caused by the data signal by the threshold voltage of the driving transistor and then holds it in the storage capacitor to suppress variation in the amount of current controlled by the driving transistor (variation in luminance of the light emitting element) and The driving method has been developed.

  For example, Patent Document 1 is provided with a lighting control switch for controlling lighting of a light emitting element, a precharge / reset switch for releasing charge accumulated in a holding capacitor for holding a potential difference according to a data signal, and the like. A pixel circuit is disclosed.

  Patent Document 2 discloses a driving method in which a power supply pulse provided with a non-driving period in which no current flows is applied to a light emitting element in an image display device in which data writing and light emission are performed at different timings for each row. Has been.

JP 2004-157250 A JP 2008-122497 A

  However, in the technique described in Patent Document 1, since the pixel circuit is provided with a precharge / reset switch in addition to the lighting control switch, the configuration of the pixel circuit is complicated. In Patent Document 2, a negative power source is required and the configuration of the pixel circuit is complicated. When the configuration of the pixel circuit is complicated, it is necessary to increase the pixel size, and it is difficult to improve the resolution.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide an image display device having a small pixel size and a driving method thereof, in which luminance variations of light emitting elements are suppressed.

  (1) In order to solve the above-described problem, an image display device according to the present invention is provided with a light emitting element that emits light with luminance corresponding to the amount of current, and a data signal from a data line is supplied to one end during a data writing period. In the data writing period, a current is supplied to the gate electrode through the source electrode and the drain electrode to supply a correction potential, which is the potential of the gate electrode, to the other end of the storage capacitor. A driving transistor for controlling an amount of current flowing from the source electrode to the drain electrode in accordance with a potential difference between the gate electrode and the source electrode in accordance with a potential difference held by the storage capacitor during a light emission period after the insertion period; In the precharge period before the data writing period and the data writing period, a reset switch for conducting the gate electrode and the drain electrode of the driving transistor, and in the light emitting period, A lighting control switch for conducting the drain electrode of the driving transistor and the light emitting element, and conducting the drain electrode of the driving transistor to a gate control line for controlling the potential of the gate electrode of the driving transistor during the precharge period The gate control line is applied with a lower potential than the drain electrode of the driving transistor during the precharge period.

  (2) In (1), the power supply control switch which interrupts | blocks conduction | electrical_connection with a power supply potential and the source electrode of the said drive transistor may be further included in the said precharge period.

  (3) In (2), the lighting control switch may make the drain electrode of the driving transistor and the light emitting element conductive even in the precharge period.

  (4) In (3), the precharge period includes a first precharge period in which the lighting control switch cuts off conduction between the drain electrode of the drive transistor and the light emitting element, and after the first precharge period. The lighting control switch may include a second precharge period in which the drain electrode of the driving transistor and the light emitting element are conducted.

  (5) In (1), a selection switch for electrically connecting one end of the storage capacitor to the data line may be further included in the precharge period and the data writing period.

  (6) In (5), the reset switch and the selection switch are transistors having the same polarity, and the gate electrode of the reset switch and the gate electrode of the selection switch control the potential of the gate electrode in common. It may be connected to a reset control line.

  (7) In (6), further comprising a light emission control signal supply switch for electrically connecting one end of the storage capacitor to a light emission control signal line for supplying a light emission control signal during the light emission period, wherein the drive transistor is in the light emission period. The amount of the current may be controlled according to the potential difference held by the storage capacitor and the potential at one end of the storage capacitor controlled by the light emission control signal.

  (8) In (7), the reset switch and the light emission control signal supply switch may be transistors having opposite polarities, and a gate electrode of the light emission control signal supply switch may be connected to the reset control line. .

  (9) In (8), the drive transistor, the reset switch, and the selection switch may be P-channel transistors, and the gate control line may be the reset control line.

  (10) In (7), the gate control line may be the light emission control signal line.

  (11) In (2), the power control switch and the charge discharge switch are transistors having opposite polarities, and the gate electrode of the power control switch and the gate electrode of the charge discharge switch have the potential of the gate electrode You may connect to the power switch control line controlled in common.

  (12) In order to solve the above problems, an image display device according to the present invention includes a plurality of light-emitting elements, a plurality of P-channel transistors that respectively control the amount of current flowing through the plurality of light-emitting elements, and the plurality of the plurality of light-emitting elements. A gate control line for controlling the potential of the gate electrode of each of the P-channel transistors, wherein at least one drain electrode of the plurality of P-channel transistors is connected to the gate control line. .

  (13) In order to solve the above-described problem, a driving method of an image display device according to the present invention is based on a light emitting element that emits light with luminance corresponding to an amount of current, a storage capacitor, and a potential difference held by the storage capacitor. A driving transistor for controlling an amount of current flowing from the source electrode to the drain electrode in accordance with a potential difference between the gate electrode and the source electrode, wherein the data signal from the data line Data writing that is supplied to one end of the storage capacitor and supplies a current to the gate electrode through the source electrode and drain electrode of the driving transistor to supply a correction potential that is the potential of the gate electrode to the other end of the storage capacitor A light emitting step for conducting the drain electrode of the driving transistor and the light emitting element after the data writing step; and the data writing Before the step, the gate electrode and the drain electrode of the driving transistor are made conductive, and the drain electrode of the driving transistor is a gate control line to which a potential lower than the drain electrode is applied, and the gate electrode of the driving transistor is And a precharge step of conducting to a gate control line for controlling the potential.

  According to the present invention, it is possible to reduce the pixel size while suppressing the luminance variation of the light emitting element.

It is a figure which shows an example of a structure of the image display apparatus which concerns on Embodiment 1-3 of this invention. 2 is a circuit diagram of a pixel circuit according to Embodiment 1. FIG. FIG. 3 is a waveform diagram showing an example of a signal supplied to the pixel circuit shown in FIG. 2. It is a figure which shows the state of the switch in a precharge period. It is a figure which shows the state of the switch in a data writing period. It is a figure which shows the state of the switch in the light emission period. FIG. 3 is a waveform diagram showing another example of a signal supplied to the pixel circuit shown in FIG. 2. It is a figure which shows the state of the switch in a 1st precharge period. It is a figure which shows the state of the switch in a 2nd precharge period. It is a figure which shows the state of the switch in a data writing period. It is a figure which shows the state of the switch in the light emission period. 6 is a circuit diagram of a pixel circuit according to Embodiment 2. FIG. FIG. 8 is a waveform diagram illustrating an example of a signal supplied to the pixel circuit illustrated in FIG. 7. It is a figure which shows the state of the switch in a 1st precharge period. It is a figure which shows the state of the switch in a 2nd precharge period. It is a figure which shows the state of the switch in a data writing period. It is a figure which shows the state of the switch in the light emission period. 5 is a circuit diagram of a pixel circuit according to Embodiment 3. FIG. FIG. 11 is a waveform diagram showing an example of a signal supplied to the pixel circuit shown in FIG. 10. It is a figure which shows the state of the switch in a precharge period. It is a figure which shows the state of the switch in a data writing period. It is a figure which shows the state of the switch in the light emission period. It is a figure which shows the modification of a structure of the image display apparatus which concerns on Embodiment 1-3. It is a figure which shows an example of a structure of the gate output buffer for reset control lines. FIG. 15 is a diagram showing a structure of a P-channel MOS of the reset control line gate output buffer shown in FIG. 14. FIG. 15 is a diagram showing a structure of an N-channel MOS of the reset control line gate output buffer shown in FIG. 14.

  Hereinafter, Embodiment 1-3 of this invention is demonstrated in detail based on drawing. In these embodiments, a case where the present invention is applied to an image display apparatus using an organic EL element as a light emitting element will be described. In addition, the same code | symbol is attached | subjected to the component which has the same function, and the description is abbreviate | omitted.

  FIG. 1 is a diagram illustrating an example of a configuration of an image display apparatus according to Embodiment 1-3. The image display device includes a vertical scanning circuit YDV, a data line driving circuit XDV, a power supply circuit PWU, a plurality of pixel circuits PC, an array substrate, a flexible printed circuit board, and a driver integrated circuit enclosed in a package. Including.

  Of these, the circuit shown in FIG. 1 is mainly provided on the array substrate and the driver integrated circuit. For example, the data line driving circuit XDV, the vertical scanning circuit YDV, and the power supply circuit PWU are provided in an area on the array substrate and outside the display area DA. Some of these are also provided in the driver integrated circuit. The pixel circuits PC are arranged in a matrix in a display area DA provided on the array substrate. If the resolution of the image display device is N rows and M columns and three-color display, pixel circuits PC of (3 × M) columns × N rows are arranged in the display area DA. Hereinafter, each row of the pixel circuit PC is referred to as a pixel row PXL.

  In the display area DA, the data lines DAT extend in the vertical direction in the drawing corresponding to each column of the pixel circuits PC. One end of the data line DAT is connected to the data line driving circuit XDV, and a data signal is supplied to one end of the data line DAT from the data line driving circuit XDV. In the drawing, the data line DAT corresponding to the pixel circuit PC in the m-th column is denoted as DATm.

  In the display area DA, the reset control line RES, the lighting control line ILM, and the power switch control line CTP extend in the left-right direction in the drawing corresponding to each row of the pixel circuits PC. One end of the reset control line RES, the lighting control line ILM, and the power switch control line CTP is connected to the vertical scanning circuit YDV. In the drawing, the reset control line RES corresponding to the pixel circuit PC in the n-th row is expressed as RESn, and the lighting control line ILM is expressed as ILMn.

  Each pixel circuit PC in the display area DA is connected to a power supply line PWL, and a power supply potential is supplied from the power supply circuit PWU through the power supply line PWL.

[Embodiment 1]
FIG. 2 is a circuit diagram of the pixel circuit PC according to the first embodiment. The pixel circuit PC includes a light emitting element IL, a storage capacitor CP, a drive transistor TRD, a reset switch SWR, a charge discharge switch SWD, a lighting control switch SWI, a power control switch SWP, a selection switch SWS, and light emission control. Signal supply switch SWF.

  The light emitting element IL is an element whose luminance changes in accordance with the amount of current flowing therethrough, and is an organic EL element in the present embodiment. The organic EL element is generally called an OLED (Organic light-emitting diode) because it has characteristics of a rectifying element. A ground potential is supplied to the cathode of the light emitting element IL. This ground potential is not necessarily supplied from the grounded electrode.

  The holding capacitor CP holds a potential difference corresponding to the data signal supplied from the data line DAT. One end of the storage capacitor CP is connected to the data line DAT via the selection switch SWS, and the other end is connected to the gate electrode of the drive transistor TRD.

  The drive transistor TRD is a P-channel thin film transistor, and controls the amount of current flowing from the source electrode to the drain electrode in accordance with the potential difference between the potential applied to the gate electrode and the potential applied to the source electrode. The source electrode of the drive transistor TRD is connected to the power supply line PWL via the power supply control switch SWP, and the drain electrode of the drive transistor TRD is connected to the anode of the light emitting element IL via the lighting control switch SWI.

  One end of the reset switch SWR is connected to the gate electrode of the drive transistor TRD, and the other end is connected to the drain electrode of the drive transistor TRD. One end of the charge discharge switch SWD is connected to the reset control line RES, and the other end is connected to the drain electrode of the drive transistor TRD. One end of the light emission control signal supply switch SWF is connected to one end of the storage capacitor CP, and the other end is connected to the light emission control signal line REF.

  The reset switch SWR, the selection switch SWS, and the power control switch SWP are P-channel thin film transistors (here, only the reset switch SWR has a double gate structure). On the other hand, the lighting control switch SWI and the drain charge discharge switch SWD are N-channel thin film transistors. Among these, the gate electrode of the reset switch SWR, the gate electrode of the selection switch SWS, and the gate electrode of the light emission control signal supply switch SWF are connected to the reset control line RES. On the other hand, the gate electrode of the lighting control switch SWI is connected to the lighting control line ILM, and the gate electrode of the power control switch SWP and the gate electrode of the charge discharge switch SWD are connected to the power switch control line CTP.

  As described above, one end of each of the reset control line RES, the lighting control line ILM, and the power switch control line CTP is connected to the vertical scanning circuit YDV, and the power line PWL is connected to the power circuit PWU.

  Next, a method for driving the image display apparatus according to the first embodiment will be described.

FIG. 3 is a waveform diagram showing an example of a signal supplied to the pixel circuit PC shown in FIG. FIG. 3 shows, in order from the top, the waveform of the potential applied to the reset control line RES, the waveform of the potential applied to the lighting control line ILM, and the waveform of the potential applied to the power switch control line CTP. . Here, one field period _TF includes a precharge period T ₁ for resetting charges accumulated in the pixel circuit PC, a data writing period T ₂ for writing data to the pixel circuit PC, and light emission for causing the light emitting element IL to emit light. includes a period _{T 3,} the. The boundaries between these periods differ according to the scanning timing of each pixel row PXL.

Figure 4A is a diagram showing a state of the pixel circuit PC in a precharge period T ₁ switches. In a precharge period T _1, so that the drive transistor TRD at the beginning of the next data writing period T ₂ is capable of sinking the drain electrode from the source electrode, the charge of the storage capacitor CP is discharged to the reset control line RES. Further, in order to prevent the light emitting element IL from slightly emitting light regardless of the data signal due to the charge accumulated in the parasitic capacitance CPR of the light emitting element IL, the charge of the parasitic capacitance CPR is also discharged to the reset control line RES.

That is, in the precharge period T _1, the potential of the reset control line RES becomes low level, the potential of the lighting control line ILM and the power switch control line CTP becomes high level (see FIG. 3). Accordingly, the selection switch SWS, the reset switch SWR, the lighting control switch SWI, and the charge discharge switch SWD are turned on (conductive state), and the light emission control signal supply switch SWF and the power supply control switch SWP are turned off (cut off state). As a result, one end of the storage capacitor CP on the drive transistor TRD side is conducted to the reset control line RES to which a low level (potential lower than the drain electrode of the drive transistor TRD) is applied, and the charge accumulated in the storage capacitor CP is reset controlled. Discharge to line RES. Further, one end of the light emitting element IL on the drive transistor TRD side is conducted to the reset control line RES, and the charge accumulated in the parasitic capacitance CPR of the light emitting element IL is also discharged to the reset control line RES.

Figure 4B is a diagram showing the state of the switch of the pixel circuits PC in the subsequent data writing period T _2. In the data writing period _{T 2,} the reset control line RES, the potential of the lighting control line ILM and the power switch control line CTP goes low (see FIG. 3). Accordingly, the selection switch SWS, the reset switch SWR, and the power control switch SWP are turned on, and the light emission control signal supply switch SWF, the lighting control switch SWI, and the charge discharge switch SWD are turned off. As a result, the driving transistor TRD is diode-connected, and the current flows until the potential difference between the source electrode and the gate electrode of the driving transistor TRD becomes the threshold voltage toward the gate electrode via the source electrode and the drain electrode of the driving transistor TRD. Flows. At this timing, the potential of the data signal is applied to the data line DAT, and the storage capacitor CP holds the potential difference between the potential obtained by subtracting the threshold voltage from the power supply potential (correction potential) and the potential of the data signal. As a result, variation in characteristics of the drive transistor TRD is compensated.

It should be noted that, when the data writing period T ₂ of the first row of the pixel circuit PC is finished, starts the data writing period T ₂ of the second row of the pixel circuit PC, sequential data to the pixel circuit PC after the N-th row Writing is performed.

Figure 4C is a diagram showing a state of a subsequent light emission period of the pixel circuit PC of T ₃ switch. In the emission period T _3, the potential of the reset control line RES and the lighting control line ILM becomes high level, the potential of the power supply switch control line CTP goes low (see FIG. 3). Accordingly, the light emission control signal supply switch SWF, the lighting control switch SWI, and the power control switch SWP are turned on, and the selection switch SWS, the reset switch SWR, and the charge discharge switch SWD are turned off. As a result, the source electrode of the drive transistor TRD is connected to the power supply line PWL, and the power supply circuit PWU supplies the power supply potential to the source electrode of the drive transistor TRD. At this timing, the potential of the light emission control signal is applied to the light emission control signal line REF, and a potential obtained by adding the potential difference held by the storage capacitor CP to the potential of the light emission control signal is supplied to the gate electrode of the drive transistor TRD. The drive transistor TRD controls the amount of current flowing from the source electrode to the drain electrode by the potential difference between the potential of the gate electrode and the potential of the source electrode. Except for the case where the driving transistor TRD is turned off in order to obtain the minimum luminance, the current from the driving transistor TRD flows through the light emitting element IL, and the light emitting element IL emits light with luminance according to the amount of the current. When the light-emitting period T ₃ is completed, it starts the next precharge period T _1.

  As described above, in the pixel circuit PC shown in FIG. 2, the reset control line RES, which is one of the gate control lines for controlling the potential of the gate electrode of the drive transistor TRD, is used as the holding capacitor CP and the parasitic capacitance CPR of the light emitting element IL. Since it is also used as a discharge path for accumulated charges, there is no need to newly provide a dedicated path for discharge. Further, the selection switch SWS and the reset switch SWR are transistors having the same polarity, and the light emission control signal supply switch SWF is a transistor having a polarity opposite to that, so that these three switching operations can be shared by one reset control line RES. Controls the increase in the number of wires. Similarly, by switching the power control switch SWP and the charge discharge switch SWD to transistors having opposite polarities, switching of these two is commonly controlled by one power switch control line CTP. For this reason, it is possible to reduce the pixel size while suppressing the luminance variation of the light emitting element IL.

Further, the pixel circuit PC shown in FIG. 2 by driving a signal waveform shown in FIG. 3, since the charge accumulated in the parasitic capacitance CPR of the light emitting element IL is discharged by the precharge period T _1, the light emitting element IL Unnecessary light emission can be suppressed and contrast can be improved. Furthermore, by interrupting the current from the power supply circuit PWU Power off control switch SWP in the precharge period T _1, it is possible to reduce the current flowing through the reset control line RES.

  Note that the pixel circuit PC illustrated in FIG. 2 may be supplied with a signal having a waveform different from the waveform illustrated in FIG.

FIG. 5 is a waveform diagram showing another example of a signal supplied to the pixel circuit PC shown in FIG. FIG. 5 shows, in order from the top, the waveform of the potential applied to the reset control line RES, the waveform of the potential applied to the lighting control line ILM, and the waveform of the potential applied to the power switch control line CTP. . Here, one field period T _F is, a first precharge period T _1A for resetting charges accumulated in the storage capacitor CP, the second precharge period for resetting the parasitic capacitance CPR to the charges accumulated in the light-emitting element IL T _1B , a data writing period T ₂ for writing data to the pixel circuit PC, and a light emission period T ₃ for causing the light emitting element IL to emit light.

FIG. 6A is a diagram illustrating a switch state of the pixel circuit PC in the first precharge period _T1A . In the first pre-charge period T _1, so that the drive transistor TRD at the beginning of the next data writing period T ₂ is capable of sinking the drain electrode from the source electrode, the charge of the storage capacitor CP is discharged to the reset control line RES .

That is, in the first precharge period T _1A, the potential of the reset control line RES and the lighting control line ILM becomes low level, the potential of the power supply switch control line CTP becomes high level (see FIG. 5). Accordingly, the selection switch SWS, the reset switch SWR, and the charge discharge switch SWD are turned on, and the light emission control signal supply switch SWF, the lighting control switch SWI, and the power control switch SWP are turned off. As a result, one end of the storage capacitor CP on the drive transistor TRD side is conducted to the reset control line RES to which a low level (potential lower than the drain electrode of the drive transistor TRD) is applied, and the charge accumulated in the storage capacitor CP is reset controlled. Discharge to line RES. Here, since the lighting control switch SWI cuts off the conduction between the drain electrode of the drive transistor TRD and the light emitting element IL, the charge accumulated in the parasitic capacitance CPR of the light emitting element IL is not discharged.

FIG. 6B is a diagram illustrating a switch state of the pixel circuit PC in the subsequent second precharge period _T1B . In the second precharge period _T1B , in order to prevent the light emitting element IL from slightly emitting light regardless of the data signal due to the charge accumulated in the parasitic capacitance CPR of the light emitting element IL, the charge of the parasitic capacitance CPR is applied to the reset control line RES. Discharged.

That is, in the second precharge period T _1B, the potential of the reset control line RES becomes low level, the potential of the lighting control line ILM and the power switch control line CTP becomes high level (see FIG. 5). Accordingly, the selection switch SWS, the reset switch SWR, the lighting control switch SWI, and the charge discharge switch SWD are turned on, and the light emission control signal supply switch SWF and the power control switch SWP are turned off. As a result, one end of the light emitting element IL on the drive transistor TRD side is conducted to the reset control line RES, and the charge accumulated in the parasitic capacitance CPR of the light emitting element IL is discharged to the reset control line RES to which the low level is applied.

6C is a diagram showing the state of the switch of the pixel circuits PC in the subsequent data writing period T _2. In the data writing period _{T 2,} the reset control line RES, the potential of the lighting control line ILM and the power switch control line CTP goes low (see FIG. 5). Accordingly, the selection switch SWS, the reset switch SWR, and the power control switch SWP are turned on, and the light emission control signal supply switch SWF, the lighting control switch SWI, and the charge discharge switch SWD are turned off. As a result, the driving transistor TRD is diode-connected, and the current flows until the potential difference between the source electrode and the gate electrode of the driving transistor TRD becomes the threshold voltage toward the gate electrode via the source electrode and the drain electrode of the driving transistor TRD. Flows. At this timing, the potential of the data signal is applied to the data line DAT, and the storage capacitor CP holds the potential difference between the potential obtained by subtracting the threshold voltage from the power supply potential (correction potential) and the potential of the data signal.

6D is a diagram showing a state of a subsequent light emission period of the pixel circuit PC of T ₃ switch. In the emission period T _3, the potential of the reset control line RES and the lighting control line ILM becomes high level, the potential of the power supply switch control line CTP goes low (see FIG. 5). Accordingly, the light emission control signal supply switch SWF, the lighting control switch SWI, and the power control switch SWP are turned on, and the selection switch SWS, the reset switch SWR, and the charge discharge switch SWD are turned off. As a result, the source electrode of the drive transistor TRD is connected to the power supply line PWL, and the power supply circuit PWU supplies the power supply potential to the source electrode of the drive transistor TRD. At this timing, the potential of the light emission control signal is applied to the light emission control signal line REF, and a potential obtained by adding the potential difference held by the storage capacitor CP to the potential of the light emission control signal is supplied to the gate electrode of the drive transistor TRD. The drive transistor TRD controls the amount of current flowing from the source electrode to the drain electrode by the potential difference between the potential of the gate electrode and the potential of the source electrode. Except for the case where the driving transistor TRD is turned off in order to obtain the minimum luminance, the current from the driving transistor TRD flows through the light emitting element IL, and the light emitting element IL emits light with luminance according to the amount of the current. When the light-emitting period _{T 3} is completed, the first precharge period _{T 1A} of the next begins.

As described above, when the pixel circuit PC shown in FIG. 2 is driven by the signal having the waveform shown in FIG. 5, after the charge accumulated in the storage capacitor CP is discharged in the first precharge period T _1A , The charge accumulated in the parasitic capacitance CPR is discharged in the second precharge period _T1B . For this reason, it is possible to prevent the charge accumulated in the storage capacitor CP from flowing into the light emitting element IL.

[Embodiment 2]
FIG. 7 is a circuit diagram of the pixel circuit PC according to the second embodiment. The pixel circuit PC includes a light emitting element IL, a storage capacitor CP, a drive transistor TRD, a reset switch SWR, a charge discharge switch SWD, a lighting control switch SWI, a power control switch SWP, a selection switch SWS, and light emission control. Signal supply switch SWF.

  The pixel circuit PC according to the second embodiment is different from the pixel circuit PC according to the first embodiment in that one end of the charge discharge switch SWD is connected to the light emission control signal line REF, the storage capacitor CP, and the light emitting element IL. The difference is that the charge accumulated in the parasitic capacitance CPR is discharged to the light emission control signal line REF. Below, it demonstrates centering on difference with Embodiment 1. FIG.

FIG. 8 is a waveform diagram showing an example of a signal supplied to the pixel circuit shown in FIG. In FIG. 8, in order from the top, the waveform of the potential applied to the reset control line RES, the waveform of the potential applied to the lighting control line ILM, the waveform of the potential applied to the power switch control line CTP, the light emission control signal line The waveform of the potential applied to REF is shown. Here, one field period T _F is, a first precharge period T _1A for resetting charges accumulated in the storage capacitor CP, the second precharge period for resetting the parasitic capacitance CPR to the charges accumulated in the light-emitting element IL T _1B , a data writing period T ₂ for writing data to the pixel circuit PC, and a light emission period T ₃ for causing the light emitting element IL to emit light.

FIG. 9A is a diagram illustrating a switch state of the pixel circuit PC in the first precharge period _T1A . In the first precharge period T _1A, so that the drive transistor TRD at the beginning of the next data writing period T ₂ is capable of sinking the drain electrode from the source electrode, the charge of the storage capacitor CP is discharged to the emission control signal line REF The

That is, in the first precharge period T _1A, the reset control line RES, the potential of the lighting control line ILM and the emission control signal line REF goes low, the potential of the power supply switch control line CTP becomes high level (see FIG. 8) . Accordingly, the selection switch SWS, the reset switch SWR, and the charge discharge switch SWD are turned on, and the light emission control signal supply switch SWF, the lighting control switch SWI, and the power control switch SWP are turned off. As a result, one end of the storage capacitor CP on the drive transistor TRD side is conducted to the light emission control signal line REF to which a low level (a potential lower than the drain electrode of the drive transistor TRD, preferably 0 V) is applied, and is stored in the storage capacitor CP. The discharged charges are discharged to the light emission control signal line REF. Here, since the lighting control switch SWI cuts off the conduction between the drain electrode of the drive transistor TRD and the light emitting element IL, the charge accumulated in the parasitic capacitance CPR of the light emitting element IL is not discharged.

FIG. 9B is a diagram illustrating a switch state of the pixel circuit PC in the subsequent second precharge period _T1B . In the second precharge period _T1B , in order to prevent the light emitting element IL from slightly emitting light regardless of the data signal due to the charge accumulated in the parasitic capacitance CPR of the light emitting element IL, the charge of the parasitic capacitance CPR is transferred to the light emission control signal line REF. Discharged.

That is, in the second precharge period T _1B, the potential of the reset control line RES and the emission control signal line REF goes low, the potential of the lighting control line ILM and the power switch control line CTP becomes high level (see FIG. 8) . Accordingly, the selection switch SWS, the reset switch SWR, the lighting control switch SWI, and the charge discharge switch SWD are turned on, and the light emission control signal supply switch SWF and the power control switch SWP are turned off. As a result, one end of the light emitting element IL on the drive transistor TRD side is conducted to the light emission control signal line REF, and the charge accumulated in the parasitic capacitance CPR of the light emitting element IL is discharged to the light emission control signal line REF to which the low level is applied. The

9C is a diagram showing the state of the switch of the pixel circuits PC in the subsequent data writing period T _2. In the data writing period T _2, the reset control line RES, the potential of the lighting control line ILM and the power switch control line CTP becomes low level, the potential of the emission control signal line REF goes low (see FIG. 8). Accordingly, the selection switch SWS, the reset switch SWR, and the power control switch SWP are turned on, and the light emission control signal supply switch SWF, the lighting control switch SWI, and the charge discharge switch SWD are turned off. As a result, the driving transistor TRD is diode-connected, and the current flows until the potential difference between the source electrode and the gate electrode of the driving transistor TRD becomes the threshold voltage toward the gate electrode via the source electrode and the drain electrode of the driving transistor TRD. Flows. At this timing, the potential of the data signal is applied to the data line DAT, and the storage capacitor CP holds the potential difference between the potential obtained by subtracting the threshold voltage from the power supply potential (correction potential) and the potential of the data signal.

9D is a diagram showing a state of a subsequent light emission period of the pixel circuit PC of T ₃ switch. In the emission period T _3, a reset control line RES, the potential of the lighting control line ILM and the emission control signal line REF goes high, the potential of the power supply switch control line CTP goes low (see FIG. 8). Accordingly, the light emission control signal supply switch SWF, the lighting control switch SWI, and the power control switch SWP are turned on, and the selection switch SWS, the reset switch SWR, and the charge discharge switch SWD are turned off. As a result, the source electrode of the drive transistor TRD is connected to the power supply line PWL, and the power supply circuit PWU supplies the power supply potential to the source electrode of the drive transistor TRD. At this timing, the potential of the light emission control signal is applied to the light emission control signal line REF, and a potential obtained by adding the potential difference held by the storage capacitor CP to the potential of the light emission control signal is supplied to the gate electrode of the drive transistor TRD. The drive transistor TRD controls the amount of current flowing from the source electrode to the drain electrode by the potential difference between the potential of the gate electrode and the potential of the source electrode. Except for the case where the driving transistor TRD is turned off in order to obtain the minimum luminance, the current from the driving transistor TRD flows through the light emitting element IL, and the light emitting element IL emits light with luminance according to the amount of the current. When the light-emitting period _{T 3} is completed, the first precharge period _{T 1A} of the next begins.

  As described above, in the pixel circuit PC shown in FIG. 7, the light emission control signal line REF, which is one of the gate control lines for controlling the potential of the gate electrode of the drive transistor TRD, is connected to the storage capacitor CP and the parasitic capacitance CPR of the light emitting element IL. Therefore, it is not necessary to newly provide a dedicated path for discharging. Further, the selection switch SWS and the reset switch SWR are transistors having the same polarity, and the light emission control signal supply switch SWF is a transistor having a polarity opposite to that, so that these three switching operations can be shared by one reset control line RES. To suppress the increase in the number of gate control lines. Similarly, by switching the power control switch SWP and the charge discharge switch SWD to transistors having opposite polarities, switching of these two is commonly controlled by one power switch control line CTP. For this reason, it is possible to reduce the pixel size while suppressing the luminance variation of the light emitting element IL.

  Further, since the light emission control signal line REF that does not cause a malfunction of the switch due to a potential rise is used as a discharge path, it is not necessary to reduce the impedance of the light emission control signal line REF or the impedance of the output buffer.

Further, when the pixel circuit PC shown in FIG. 7 is driven by the signal having the waveform shown in FIG. 8, the charge accumulated in the storage capacitor CP is discharged in the first precharge period T _1A and then the parasitic capacitance of the light emitting element IL. The charge accumulated in CPR is discharged in the second precharge period _T1B . For this reason, it is possible to prevent the charge accumulated in the storage capacitor CP from flowing into the light emitting element IL. In addition, unnecessary light emission of the light emitting element IL can be suppressed and the contrast can be improved. Further, by the first precharge period T _1A and the second precharge period T _1B turns off the power control switch SWP interrupting the current from the power supply circuit PWU, reducing the current flowing through the emission control signal line REF Can do.

  In the present embodiment, the charge accumulated in the parasitic capacitance CPR of the light emitting element IL is discharged after the charge accumulated in the storage capacitor CP is discharged. However, these discharges may be performed simultaneously (in the first embodiment). (See FIG. 4A).

[Embodiment 3]
FIG. 10 is a circuit diagram of a pixel circuit PC according to the third embodiment. The pixel circuit PC includes a light emitting element IL, a storage capacitor CP, a drive transistor TRD, a reset switch SWR, a charge discharge switch SWD, a lighting control switch SWI, a selection switch SWS, and a light emission control signal supply switch SWF. including.

The pixel circuit PC according to the third embodiment is different from the pixel circuit PC according to the second embodiment in that the power source control switch SWP is not provided and the source electrode of the drive transistor TRD is directly connected to the power source line PWL. point T ₁ is not divided into a first precharge period _{T 1A} and the second precharge period _{T 1B,} are different. Below, it demonstrates centering on difference with Embodiment 2. FIG.

FIG. 11 is a waveform diagram showing an example of a signal supplied to the pixel circuit shown in FIG. In FIG. 11, in order from the top, the waveform of the potential applied to the reset control line RES, the waveform of the potential applied to the lighting control line ILM, the waveform of the potential applied to the power switch control line CTP, the light emission control signal line The waveform of the potential applied to REF is shown. Here, one field period T _F is a precharge period T ₁ for resetting the electric charges accumulated in the storage capacitor CP, a data writing period T ₂ for writing data into the pixel circuit PC, causing the light emitting element IL emission includes a period _{T 3,} the.

Figure 12A is a diagram showing a state of the pixel circuit PC in a precharge period T ₁ switches. In a precharge period T _1, so that the drive transistor TRD at the beginning of the next data writing period T ₂ is capable of sinking the drain electrode from the source electrode, the charge of the storage capacitor CP is discharged to the emission control signal line REF.

That is, in the precharge period T _1, the reset control line RES, the potential of the lighting control line ILM and the emission control signal line REF goes low, the potential of the power supply switch control line CTP (see FIG. 10) becomes a high level (FIG. 11). Accordingly, the selection switch SWS, the reset switch SWR, and the charge discharge switch SWD are turned on, and the light emission control signal supply switch SWF and the lighting control switch SWI are turned off. As a result, one end of the storage capacitor CP on the drive transistor TRD side is conducted to the light emission control signal line REF to which a low level (a potential lower than the drain electrode of the drive transistor TRD, preferably 0 V) is applied, and is stored in the storage capacitor CP. The discharged charges are discharged to the light emission control signal line REF. In the present embodiment, since the source electrode of the drive transistor TRD is always connected to the power supply line PWL, a current flows from the power supply circuit PWU to the light emission control signal line REF. Further, since the lighting control switch SWI cuts off the conduction between the drain electrode of the drive transistor TRD and the light emitting element IL, the charge accumulated in the parasitic capacitance CPR of the light emitting element IL is not discharged.

Figure 12B is a diagram showing the state of the switch of the pixel circuits PC in the subsequent data writing period T _2. In the data writing period _{T 2,} the potential of the reset control line RES, the lighting control line ILM and the power switch control line CTP (see FIG. 10) goes low, the potential of the emission control signal line REF goes high (FIG. 11 reference). Accordingly, the selection switch SWS and the reset switch SWR are turned on, and the light emission control signal supply switch SWF, the lighting control switch SWI, and the charge discharge switch SWD are turned off. As a result, the driving transistor TRD is diode-connected, and the current flows until the potential difference between the source electrode and the gate electrode of the driving transistor TRD becomes the threshold voltage toward the gate electrode via the source electrode and the drain electrode of the driving transistor TRD. Flows. At this timing, the potential of the data signal is applied to the data line DAT, and the storage capacitor CP holds the potential difference between the potential obtained by subtracting the threshold voltage from the power supply potential (correction potential) and the potential of the data signal.

Figure 12C is a diagram showing a state of a subsequent light emission period of the pixel circuit PC of T ₃ switch. In the emission period _{T 3,} a reset control line RES, the lighting control line ILM becomes high level, the potential of the power supply switch control line CTP (see FIG. 10) becomes the low level (see FIG. 11). Accordingly, the light emission control signal supply switch SWF and the lighting control switch SWI are turned on, and the selection switch SWS, the reset switch SWR, and the charge discharge switch SWD are turned off. At this timing, the potential of the light emission control signal is applied to the light emission control signal line REF, and a potential obtained by adding the potential difference held by the storage capacitor CP to the potential of the light emission control signal is supplied to the gate electrode of the drive transistor TRD. The drive transistor TRD controls the amount of current flowing from the source electrode to the drain electrode by the potential difference between the potential of the gate electrode and the potential of the source electrode. Except for the case where the driving transistor TRD is turned off in order to obtain the minimum luminance, the current from the driving transistor TRD flows through the light emitting element IL, and the light emitting element IL emits light with luminance according to the amount of the current. When the light-emitting period T ₃ is completed, it starts the next precharge period T _1.

  As described above, in the pixel circuit PC shown in FIG. 10, since the charge accumulated in the description capacitor CPR of the light emitting element IL is not discharged, the contrast is worse than the first and second embodiments, but the power control switch SWP can be omitted. Therefore, the pixel circuit PC can be simplified.

  In this embodiment, the charge accumulated in the storage capacitor CP is discharged to the light emission control signal line REF. However, as in the first embodiment, one end of the charge discharge switch SWD is connected to the reset control line RES, and the storage capacitor The charge accumulated in the CP may be discharged to the reset control line RES.

[Modification]
In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible. In addition, the configuration described in the above embodiment can be replaced with a configuration that is substantially the same, a configuration that exhibits the same operational effects, or a configuration that can achieve the same purpose.

  For example, the power control switch SWP may be provided not for each pixel circuit PC but for each of a plurality of pixel circuits PC in the same pixel row PXL, or may be provided for each pixel row PXL as shown in FIG.

  Further, if the low level and the high level of the potential waveform (see FIGS. 3, 5, 8, and 11) applied to the power switch control line CTP are inverted, the power control switch SWP is turned into an N-channel type. A thin film transistor may be used, and the charge discharge switch SWD may be a P-channel thin film transistor. Similarly, if the low level and the high level of the waveform of the potential applied to the lighting control line ILM (see FIGS. 3, 5, 8, and 11) are inverted, the lighting control switch SWI is changed to a P-channel type. It may be a thin film transistor.

  By the way, as described above, the plurality of light emitting elements IL, the plurality of driving transistors TRD (P-channel transistors) for controlling the amount of current flowing through the plurality of light emitting elements IL, and the gate electrodes of the plurality of driving transistors TRD, respectively. In an image display device including a gate control line (for example, a reset control line RES) for controlling a potential, at least one (all in Embodiment 1-3) drain electrodes of the plurality of drive transistors TRD are provided in a precharge period. If the gate control line is connected to a gate control line for controlling the potential of the driving transistor electrode and a potential lower than that of the drain electrode of the driving transistor is applied to the gate control line, the gate control line also serves as a discharge path. The increase of is suppressed.

  However, when the gate control line is used as a discharge path, the potential of the gate control line rises due to the discharge, and the switch may malfunction. For example, when the reset control line RES is used as a discharge path as in the first embodiment, the potential of the reset control line RES rises due to discharge, and the selection switch SWS, the reset switch SWR, and the light emission control signal supply switch SWF may malfunction. There is.

  For this reason, it is desirable to reduce the impedance of the gate control line used as the discharge path and the impedance of the output buffer. For example, when the reset control line RES is used as a discharge path as in the first embodiment, a material having a resistance lower than that of other pixel circuit wiring (for example, Cu, Ag, etc.) is used for the reset control line RES, and the reset control line RES is used. It is made thicker than the pixel circuit wiring (for example, the width and height are doubled or more), and the NMOS gate length in the CMOS of the output buffer of the reset control line RES illustrated in FIG. 14 is made shorter than the PMOS (FIG. 15A, FIG. 15B) is effective. FIG. 14 is a diagram showing an example of the configuration of the gate output buffer for the reset control line. FIG. 15A shows the structure of the P channel MOS of the gate output buffer for the reset control line shown in FIG. FIG. 15B shows a structure of an N channel MOS of the gate output buffer for the reset control line shown in FIG.

DA display area, DAT data line, ILM lighting control line, RES reset control line, REF light emission control signal line, PC pixel circuit, PWL power supply line, PWU power supply circuit, PXL pixel row, XDV data line drive circuit, YDV vertical scanning circuit , CTP power switch control line, SWP power control switch, CP holding capacitor, CPR parasitic capacitance, IL light emitting element, SWF light emission control signal supply switch, SWI lighting control switch, SWD charge discharge switch, SWR reset switch, SWS selection switch, TRD the driving transistor, _{T F} field period, _{T 1} precharge _{period, T 1A} first precharge _{period, T 1B} second precharge period, _{T 2} data writing period, _{T 3} emission period.

Claims (13)

A light emitting element that emits light with a luminance according to the amount of current;
A storage capacitor to which a data signal from a data line is supplied to one end in a data writing period;
In the data writing period, a current is supplied to the gate electrode through the source electrode and the drain electrode to supply a correction potential that is the potential of the gate electrode to the other end of the storage capacitor. A drive transistor that controls the amount of current flowing from the source electrode to the drain electrode according to the potential difference between the gate electrode and the source electrode according to the potential difference held by the storage capacitor during the light emission period;
A reset switch for conducting the gate electrode and the drain electrode of the driving transistor in the precharge period and the data writing period before the data writing period;
A lighting control switch for conducting the drain electrode of the driving transistor and the light emitting element during the light emission period;
A charge discharge switch for conducting the drain electrode of the drive transistor to a gate control line for controlling the potential of the gate electrode of the drive transistor during the precharge period;
Including
A potential lower than the drain electrode of the driving transistor is applied to the gate control line during the precharge period.
An image display device characterized by that. A power control switch for cutting off conduction between a power supply potential and the source electrode of the drive transistor during the precharge period;
The image display device according to claim 1, further comprising: The lighting control switch makes the drain electrode of the driving transistor and the light emitting element conductive even in the precharge period.
The image display device according to claim 2. The precharge period is
A first precharge period in which the lighting control switch interrupts conduction between the drain electrode of the driving transistor and the light emitting element;
A second precharge period in which the lighting control switch causes the drain electrode of the driving transistor and the light emitting element to conduct after the first precharge period;
The image display device according to claim 3, further comprising: A selection switch for conducting one end of the storage capacitor to the data line during the precharge period and the data writing period;
The image display device according to claim 1, further comprising: The reset switch and the selection switch are transistors having the same polarity,
The gate electrode of the reset switch and the gate electrode of the selection switch are connected to a reset control line that controls the potential of the gate electrode in common.
The image display device according to claim 5, further comprising: A light emission control signal supply switch for electrically connecting one end of the storage capacitor to a light emission control signal line for supplying a light emission control signal during the light emission period;
The driving transistor controls the amount of the current according to a potential difference held by the holding capacitor and a potential of one end of the holding capacitor controlled by the light emission control signal during the light emission period.
The image display device according to claim 6. The reset switch and the light emission control signal supply switch are transistors having opposite polarities,
A gate electrode of the light emission control signal supply switch is connected to the reset control line;
The image display device according to claim 7. The drive transistor, the reset switch, and the selection switch are P-channel transistors,
The gate control line is the reset control line;
The image display apparatus according to claim 8. The gate control line is the light emission control signal line;
The image display device according to claim 7. The power control switch and the charge discharge switch are transistors having opposite polarities,
The gate electrode of the power control switch and the gate electrode of the charge discharge switch are connected to a power switch control line for commonly controlling the potential of the gate electrode.
The image display device according to claim 2. A plurality of light emitting elements;
A plurality of P-channel transistors that respectively control the amount of current flowing through the plurality of light emitting elements;
A gate control line for controlling the potential of the gate electrodes of the plurality of P-channel transistors;
Including
At least one drain electrode of the plurality of P-channel transistors is connected to the gate control line;
An image display device characterized by that. The amount of current that flows from the source electrode to the drain electrode in accordance with the potential difference between the light emitting element that emits light with luminance corresponding to the amount of current, the storage capacitor, and the potential difference between the gate electrode and the source electrode that is stored in the storage capacitor. A drive transistor for controlling the image display device, comprising:
A data signal from the data line is supplied to one end of the storage capacitor, and a current is supplied to the gate electrode through the source electrode and the drain electrode of the driving transistor, so that a correction potential which is the potential of the gate electrode is supplied to the storage capacitor. A data writing step for supplying to the other end;
After the data writing step, a light emitting step for conducting the drain electrode of the driving transistor and the light emitting element;
Before the data writing step, the gate electrode and the drain electrode of the driving transistor are made conductive, and the drain electrode of the driving transistor is a gate control line to which a potential lower than the drain electrode is applied, and the driving transistor A precharge step for conducting to a gate control line for controlling the potential of the gate electrode;
A method for driving an image display device, comprising:

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