JP2012127911A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of reducing time for IDDQ test and the like.SOLUTION: In a semiconductor integrated circuit 1 in which a CMOS logic circuit 10 is integrated, an output logic value control circuit 20 is provided between a plurality of output stage CMOS devices 12 of the CMOS logic circuit 10 and a plurality of output terminals 32 for outputting a signal to the outside. The output logic value control circuit 20 is composed of a plurality of logical operators 21 of two-input one-output that is provided corresponding to the plurality of output stage CMOS devices 12, respectively. While a logical value output by the output stage CMOS device 12 is input into one input port, a control signal 22 is input into the other input port. The logical operator 21 can fix the logical value of an output port at either High or Low when the control signal 22 is fixed at either High or Low.

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit in which a CMOS logic circuit to be subjected to an IDDQ test or the like is integrated.

  As a method for inspecting a CMOS (complementary metal oxide semiconductor) logic circuit integrated in a semiconductor integrated circuit (IC), an IDDQ test called a static power supply current observation test is known. This IDDQ test is useful as a test means for improving the reliability of a semiconductor integrated circuit because it can detect a circuit abnormality such as a short circuit between wirings or a transistor leak, which is difficult to detect by a scan test or a function test.

  This IDDQ test is a normal state CMOS device that does not have a failure or defect, but only a small amount of current (called a quiescent current) flows when the operation is not performed, but there is a failure or defect. The CMOS device in the state uses a characteristic that a current several times as large as that in the normal state flows even when the operation is stationary, and the quiescent power supply current (Idddq) of the CMOS logic circuit is measured to obtain a predetermined reference. This is a test method for judging whether or not there is an abnormality in a CMOS device by comparing with a current value.

  In a well-known function test, a CMOS device in a CMOS logic circuit is operated, and a logic value obtained by the operation is propagated to a signal output point (output terminal of a semiconductor integrated circuit) of the CMOS logic circuit. While the logic value of the output point must be observed, in the IDDQ test, it is only necessary to operate the CMOS device inside the CMOS logic circuit and observe the static power supply current of the CMOS logic circuit. For this reason, the IDDQ test is easier and more observable than the function test.

  Also, as illustrated in FIG. 3, a plurality of CMOS devices 111 of about several tens to several hundreds are generally formed inside the CMOS logic circuit 110 integrated in the semiconductor integrated circuit 101. For this reason, in the IDDQ test, an inspection for determining whether or not there is an abnormality is performed for each of the plurality of CMOS devices 111.

  Specifically, in the conventional IDDQ test, a test pattern for changing the inside of the CMOS logic circuit 110 to a logic state suitable for the CMOS device 111 is input from the input terminal 131 for each CMOS device 111 to be inspected. After the logic value of each node (connection point between the CMOS devices 111) in the logic circuit 110 is fixed (the logic value is fixed to either the high logic value “1” or the low logic value “0”), the CMOS The quiescent power supply current of the logic circuit 110 is observed. See, for example, US Pat.

  As described above, in the conventional IDDQ test, the first step of determining the logical value of each node by changing the internal logic state of the CMOS logic circuit 110 and the CMOS logic circuit after determining the logical value of each node. The second step of measuring the quiescent power supply current of 110 is repeated as many times as necessary until the inspection of all the plurality of CMOS devices 111 is completed, so that the presence / absence of abnormality of the CMOS logic circuit 110 can be accurately determined. Deciding.

JP 2005-140759 A

  Usually, the IDDQ test is performed in a state where the chip-like semiconductor integrated circuit 101 on which the CMOS logic circuit 110 is integrated is mounted on an IC package, or in a state where the IC package is mounted on a substrate. Accordingly, among the CMOS devices 111 constituting the CMOS logic circuit 110, the output stage CMOS device 112 directly connected to the output terminal (bonding pad) 132 of the semiconductor integrated circuit 101 has the resistance value, output terminal and package of the bonding wire. It is affected by various external loads such as parasitic capacitance of terminals and circuits connected by mounting on the board.

Since it is affected by such an external load (because the load increases), the output stage CMOS device 112 needs to determine its own logical value after the test pattern is input in the first step described above. The time t becomes relatively longer than that of the CMOS device 111 other than the output stage. Therefore, until the processing of the second process can be started, that is, until all the logical values of the CMOS device 111 and the output stage CMOS device 112 constituting the CMOS logic circuit 110 are determined and the quiescent power supply current is stabilized. The time T is inevitably longer.
FIG. 4 is a diagram comparing the time t and the time T described above for the CMOS device 111 and the output stage CMOS device 112 that constitute the CMOS logic circuit 110.

  For this reason, in the conventional semiconductor integrated circuit 101, the inspection time (the time for completing the first step and the second step) required for one CMOS device forming the CMOS logic circuit 110 becomes long. The length of the inspection time has a more significant effect as the number of CMOS devices to be inspected increases, resulting in a problem that the IDDQ test takes a long time.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor integrated circuit in which the time required for the IDDQ test of the CMOS logic circuit is reduced by controlling the output stage CMOS device so as not to be affected by an external load during the IDDQ test. To provide a circuit.

The present invention is directed to a semiconductor integrated circuit in which CMOS logic circuits are integrated. In order to achieve the above object, the semiconductor integrated circuit of the present invention has a normal mode in which the logical value output from the CMOS logic circuit is output as it is to an output terminal formed in the semiconductor integrated circuit, and the CMOS logic circuit outputs An output logic value control circuit for switching and controlling a test mode for outputting a predetermined fixed logic value regardless of the logic value to be integrated is integrated.
With this configuration, the CMOS logic circuit is connected by mounting the resistance value of the wire bonded to the output terminal, the parasitic capacitance of the package terminal on which the output terminal and the semiconductor integrated circuit are mounted, and the package mounted on the substrate. It is possible to prevent an external load from being received by a circuit or the like.

This output logic value control circuit is preferably provided between the output stage CMOS device that outputs the operation result of the CMOS logic circuit and the output terminal.
If the output logic value control circuit is provided at this position, it is possible to prevent an external load applied to the output stage CMOS device of the CMOS logic circuit, which greatly affects the test time, so that the test time can be expected to be shortened.

Also, typically, the output logic value control circuit is a logic operator (OR, NOR, AND) in which the logic value appearing at the output terminal is fixed if the logic value input to one of the two input terminals is fixed. , NAND, etc.). The logical operator inputs the logical value output from the output stage CMOS device to one input terminal, and switches the logical value of the control signal input to the other input terminal, thereby switching between the normal mode and the test mode. Switch.
With this configuration, it is possible to easily switch between the normal mode and the test mode simply by switching the logical value of the control signal.

  In the test mode, if the control signal is supplied from the CMOS logic circuit to the logical operator, a dedicated input terminal for inputting the control signal becomes unnecessary. This test mode is used when observing the static power supply current of the CMOS logic circuit in the IDDQ test.

  The processing performed by the output logic value control circuit integrated by the semiconductor integrated circuit of the present invention described above can be regarded as an output logic value control method that provides a series of processing procedures. This output logical value control method is provided in the form of a program for causing a computer to execute a series of processing procedures. This program may be introduced into a computer storage device via a computer-readable recording medium, or may be directly executed from the recording medium. This recording medium is a semiconductor memory such as ROM, RAM, or flash memory, a magnetic disk memory such as a flexible disk or a hard disk, an optical disk memory such as a CD-ROM, DVD, or BD, and a memory card. And other communication media.

  As described above, according to the semiconductor integrated circuit of the present invention, during an IDDQ test or the like, the connection between the CMOS logic circuit and the output terminal is switched so that an external load is not applied to the output stage CMOS device. Thereby, the time required for the IDDQ test of the CMOS logic circuit can be shortened.

The figure which shows the structural example of the semiconductor integrated circuit 1 which concerns on one Embodiment of this invention. The figure which shows the relationship between the input logical value in various logic operators 21, and an output logical value 1 is a diagram showing a configuration example of a conventional semiconductor integrated circuit 101 The figure which compared time t and time T about the CMOS device 111 and the output stage CMOS device 112

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram illustrating a configuration example of a semiconductor integrated circuit 1 according to an embodiment of the present invention. In FIG. 1, the semiconductor integrated circuit 1 of the present embodiment integrates a CMOS logic circuit 10, an output logic value control circuit 20, and a plurality of input / output terminals 31 and 32. The semiconductor integrated circuit 1 is specifically an IC chip, which is mounted on a predetermined IC package, and a plurality of input / output terminals 31 and 32 are connected to a plurality of package terminals included in the IC package via bonding wires. Each product is manufactured by electrical connection.

First, the outline of each configuration of the semiconductor integrated circuit 1 of the present invention will be described.
Among the plurality of input / output terminals 31 and 32, a plurality of input terminals 31 (four in the example of FIG. 1) for inputting signals from the outside are connected to corresponding signal input points of the CMOS logic circuit 10, respectively. The CMOS logic circuit 10 is composed of a plurality of CMOS devices 11 and 12 (buffers, inverters, logical operators, etc.), and is obtained by performing a predetermined logical operation on a signal input to each signal input point. The result (logical value) is output from signal output points of a plurality of output stage CMOS devices 12 (five in the example of FIG. 1) provided in the final output stage of the CMOS logic circuit 10.

  The output logic value control circuit 20 includes a plurality of output stage CMOS devices 12 of the CMOS logic circuit 10 and a plurality of output terminals 32 (in the example of FIG. 1) that output signals to the outside among the plurality of input / output terminals 31 and 32. 5). The output logic value control circuit 20 inputs the logic value of the operation result output from the signal output points of the plurality of output stage CMOS devices 12, and according to a predetermined control signal 22, the logic value of the operation result is directly used as a plurality of logic values. A “normal mode” that is output to the output terminal 32 and a “test mode” that outputs a fixed logical value to the plurality of output terminals 32 regardless of the logical value of the operation result are selectively switched.

  A typical output logic value control circuit 20 includes a plurality of 2-input 1-output logic operators 21 corresponding to the plurality of output stage CMOS devices 12. For this logical operator 21, an arithmetic element is used in which the logical value appearing at the output end is fixed if the logical value input to one of the two input ends is fixed. For example, operators such as logical sum (OR), negative logical sum (NOR), logical product (AND), and negative logical product (NAND). In the example of FIG. 1, a configuration in the case of using a logical operator 21 of NOT logical sum is shown.

  The logical value of the operation result output from the corresponding output stage CMOS device 12 is input to one input terminal of each logical operator 21, and the control signal 22 is input to the other input terminal of each logical operator 21. Entered. This control signal 22 gives either High “logical value: 1” or low “logical value: 0” to the other input terminal of the logical operator 21 in the normal mode and test mode described above. Which logical value is given in which mode is determined by the type of the logical operator 21 used in the output logical value control circuit 20 as shown in FIG. FIG. 2 is a diagram illustrating the relationship between the input logical value and the output logical value in various logical operators 21.

Next, the effect obtained in the semiconductor integrated circuit 1 of the present invention by the logical value control of the logical operator 21 using the control signal 22 will be described.
As described in the background art, in the IDDQ test, since each of the plurality of CMOS devices 11 and 12 forming the CMOS logic circuit 10 is inspected, the logic state in the CMOS logic circuit 10 is changed to change the logic of each node. The first step of determining the value and the second step of measuring the quiescent power supply current of the CMOS logic circuit 10 after determining the logical value of each node are repeated a plurality of times. For this reason, if it takes time to determine the logical value of the output stage CMOS device 12 in each first step due to various external loads, the time from the start to completion of the IDDQ test becomes longer.

  Therefore, in the semiconductor integrated circuit 1 of the present invention, when performing the IDDQ test, the control signal 22 is set to the test mode, and the logical value appearing at the output terminal of the logical operator 21 is fixed. For example, in the case of the output logical value control circuit 20 using a NOR logical operator as the logical operator 21 shown in FIG. 1, the control signal 22 is controlled as follows.

First, in the normal mode in which the IDDQ test is not performed, a control signal 22 having a low logical value “0” is given to the other input terminal of the logical operator 21. As a result, the logical value of the operation result from the output stage CMOS device 12 input to one input terminal of the logical operator 21 is inverted and output to the output terminal of the logical operator 21 (see FIG. 2). ).
On the other hand, in the test mode in which the IDDQ test is performed, a control signal 22 having a high logical value “1” is applied to the other input terminal of the logical operator 21. As a result, the low logical value “0” is always set at the output terminal of the logical operator 21 regardless of the logical value of the operation result from the output stage CMOS device 12 input to one input terminal of the logical operator 21. Is output.

  This control signal 22 is generated by a control signal generation circuit (not shown) formed in advance in the CMOS logic circuit 10 and is internally supplied from the CMOS logic circuit 10 to the output logic value control circuit 20 during the IDDQ test. The semiconductor integrated circuit 1 may be provided with a dedicated input terminal 31 and supplied from the outside via the dedicated input terminal 31 during the IDDQ test. Good. In the former case, since the control signal generation circuit must be driven during the IDDQ test, the CMOS device constituting the control signal generation circuit cannot be inspected. Therefore, it is desirable to inspect a CMOS device constituting the control signal generation circuit by a conventional method of observing a quiescent power supply current that does not use the output logic value control circuit 20.

As described above, according to the semiconductor integrated circuit 1 according to the embodiment of the present invention, the output logic value of the output logic value control circuit 20 is fixed in the test mode in which the IDDQ test is performed. Therefore, in the test mode, the output terminal of the output stage CMOS device 12 of the CMOS logic circuit 10 has the resistance value of the wire bonded to the output terminal 32, and the package terminal on which the output terminal 32 and the semiconductor integrated circuit 1 are mounted. It is not affected by various external loads such as parasitic capacitance and circuits connected by mounting the package on the substrate.
As a result, the time required for determining the logical value of the output stage CMOS device 12 in the first step in the IDDQ test is shortened, and the time required from the start to completion of the IDDQ test can be shortened (IDDQ Faster testing).

In the above embodiment, a case has been described in which the logical operators 21 configuring the output logical value control circuit 20 are all the same logical operators (all NOR logical operators in the example of FIG. 1). However, all the logical operators 21 do not have to be the same, and a plurality of types may be mixed as long as the logical operator can fix the output logical value.
For example, if the logical operator 21 is such that an open drain N-channel MOS transistor is connected to the output terminal 32 of the output destination, a NOR logical operator, an AND logical operator, or the like that can fix the output with a low logical value can be used. Is suitable. In addition, if the logical operator 21 is such that an open drain P-channel MOS transistor is connected to the output terminal 32 of the output destination, an OR logical operator, a NAND logical operator, or the like whose output can be fixed at a high logical value is provided. Is suitable. That is, it is desirable to use the optimal logical operator 21 depending on the circuit connected to the output terminal 32.

  In the above-described embodiment, the case where there are a plurality of logical operators 21 constituting the output logical value control circuit 20 has been described. However, when there is one output stage CMOS device 12 included in the CMOS logic circuit 10, The number of logical operators 21 may be one.

  The circuit configuration of the present invention can be used for a semiconductor integrated circuit in which a CMOS logic circuit to be subjected to an IDDQ test or the like is integrated, and is particularly useful when it is desired to shorten the time required for the IDDQ test or the like.

DESCRIPTION OF SYMBOLS 1,101 Semiconductor integrated circuit 10, 110 CMOS logic circuit 11, 111 CMOS device 12, 112 Output stage CMOS device 20 Output logic value control circuit 21 Logical operator 22 Control signal 31, 131 Input terminal 32, 132 Output terminal

Claims (5)

A semiconductor integrated circuit in which CMOS logic circuits are integrated,
A normal mode in which a logical value output from the CMOS logic circuit is output as it is to an output terminal formed in a semiconductor integrated circuit, and a predetermined fixed logical value is output regardless of the logical value output from the CMOS logic circuit. A semiconductor integrated circuit, wherein an output logic value control circuit for switching and controlling a test mode is integrated.   The semiconductor integrated circuit according to claim 1, wherein the output logic value control circuit is provided between an output stage CMOS device that outputs a calculation result of the CMOS logic circuit and the output terminal. The output logical value control circuit includes a logical operator that fixes a logical value appearing at the output terminal if the logical value input to one of the two input terminals is fixed;
The logical operator inputs the logical value output from the output stage CMOS device to one input terminal, and the logical value of a control signal input to the other input terminal is switched, so that the normal mode and the test mode are switched. The semiconductor integrated circuit according to claim 2, wherein:   4. The semiconductor integrated circuit according to claim 3, wherein the control signal is supplied from the CMOS logic circuit to the logic operator in the test mode.   2. The semiconductor integrated circuit according to claim 1, wherein the test mode is used when observing a quiescent power supply current of the CMOS logic circuit in an IDDQ test.

Images