JP2012124244A - Mounting method of semiconductor element and mounting body - Google Patents
Mounting method of semiconductor element and mounting body Download PDFInfo
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- JP2012124244A JP2012124244A JP2010272226A JP2010272226A JP2012124244A JP 2012124244 A JP2012124244 A JP 2012124244A JP 2010272226 A JP2010272226 A JP 2010272226A JP 2010272226 A JP2010272226 A JP 2010272226A JP 2012124244 A JP2012124244 A JP 2012124244A
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- insulating resin
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Abstract
Description
本発明は、半導体素子の実装方法、及び実装体に関する。 The present invention relates to a semiconductor element mounting method and a mounting body.
ＩＣチップ等の半導体素子と、プリント配線板（ＰＣＢ）等の基板とを接続する方法の一つとして、フリップチップ工法がある。このフリップチップ工法では、前記ＩＣチップにおけるバンプを、前記ＰＣＢにおける配線と対向させ、直接接触又は導電性粒子を介して接触させると共に、加熱加圧することにより電気的に接続する。 As one method for connecting a semiconductor element such as an IC chip and a substrate such as a printed wiring board (PCB), there is a flip chip method. In this flip-chip method, bumps in the IC chip are opposed to wirings in the PCB, brought into direct contact or contact through conductive particles, and electrically connected by heating and pressing.
従来、前記導電性粒子を介した接続には、異方導電性フィルム（ＡＣＦ；Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）が用いられている。このＡＣＦとしては、一般に、エポキシ樹脂系の接着剤層中に導電性粒子を分散させたものが使用されており、例えば、前記ＩＣチップと前記基板との間に前記ＡＣＦを配置し、加熱押圧すると、前記導電性粒子が、前記ＩＣチップのバンプと前記基板における電極との間に挟まれて潰されることにより、前記ＩＣチップのバンプと前記電極との電気的接続が実現されている。 Conventionally, an anisotropic conductive film (ACF) is used for the connection through the conductive particles. As this ACF, generally, an epoxy resin adhesive layer in which conductive particles are dispersed is used. For example, the ACF is disposed between the IC chip and the substrate, and heated and pressed. Then, the conductive particles are sandwiched and crushed between the bumps of the IC chip and the electrodes on the substrate, thereby realizing electrical connection between the bumps of the IC chip and the electrodes.
近年、電子機器の小型化及び高機能化に伴う半導体デバイスの高集積化により、ＩＣチップのバンプ間スペースの狭ピッチ化及びバンプ面積の狭小化が加速している。
しかし、前記導電性粒子の粒子径は２μｍ程度が限界であり、異方導電性フィルムによる接着には限界がある。
In recent years, due to the high integration of semiconductor devices accompanying the downsizing and high functionality of electronic equipment, the narrowing of the pitch between bumps and the narrowing of the bump area of the IC chip are accelerating.
However, the limit of the particle diameter of the conductive particles is about 2 μm, and there is a limit to the adhesion by the anisotropic conductive film.
そこで、バンプ間スペースの狭ピッチ化及びバンプ面積の狭小化に対応可能な接続法として、前記ＩＣチップにおけるバンプと前記基板における配線とを非導電性フィルム（ＮＣＦ：Ｎｏｎ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）を介して接着するＮＣＦ接合法が注目を集めている。このＮＣＦ接合法では、前記導電性粒子を用いず、スタッドバンプを前記ＩＣチップのバンプとして使用し、前記ＩＣチップと前記基板との圧着時に、前記スタッドバンプが前記基板と接触し、潰れることにより、前記ＩＣチップと前記基板とが直接接合される。 Therefore, as a connection method that can cope with a narrow pitch between bumps and a narrow bump area, the bumps on the IC chip and the wirings on the substrate are bonded via a non-conductive film (NCF: Non Conductive Film). The NCF bonding method is attracting attention. In this NCF bonding method, without using the conductive particles, stud bumps are used as bumps of the IC chip, and when the IC chip and the substrate are pressure-bonded, the stud bumps come into contact with the substrate and are crushed. The IC chip and the substrate are directly bonded.
前記ＮＣＦ接合法においては、前記ＩＣチップと前記基板とを圧着した後に、又は圧着の際に、加熱することにより、前記ＮＣＦを硬化させ、接着及びＩＣチップと基板との接続を実現している。
しかし、圧着条件を高精度に制御しないと、前記ＩＣチップのバンプが潰れすぎ、隣接するバンプ間での接触が発生し、導通不良、即ちショートが起きてしまうという問題がある。特に、バンプ間スペースの狭ピッチ化が進むとこの問題は顕著となる。
In the NCF bonding method, the NCF is cured by heating after the IC chip and the substrate are pressure-bonded or during the pressure-bonding, thereby realizing adhesion and connection between the IC chip and the substrate. .
However, unless the pressure bonding conditions are controlled with high accuracy, the bumps of the IC chip are too crushed, and contact between adjacent bumps occurs, resulting in a problem of conduction failure, that is, a short circuit. In particular, this problem becomes conspicuous as the pitch between the bumps becomes narrower.
導通を改良する技術として、ＩＣチップの電極にジョイントボールを用い、二層構造のＮＣＦを介して、ＩＣチップと基板とを接合する方法が開示されている（特許文献１参照）。この提案の技術においては、前記ＮＣＦを二層構造にするために、前記ＮＣＦの厚み方向において、単一種のエポキシ樹脂組成物中に、無機質充填剤を含有する層と含有しない層とを形成している。
しかし、この提案の技術は、バンプの潰れすぎを防ぐことはできない点で問題がある。
As a technique for improving conduction, a method is disclosed in which a joint ball is used as an electrode of an IC chip, and the IC chip and the substrate are bonded via a two-layer NCF (see Patent Document 1). In this proposed technique, in order to make the NCF into a two-layer structure, a layer containing an inorganic filler and a layer not containing are formed in a single type of epoxy resin composition in the thickness direction of the NCF. ing.
However, this proposed technique has a problem in that it cannot prevent the bumps from being crushed.
また、可溶性ポリイミドを用い組成の異なる二層構造の接着シートを用いたＮＣＦ接合方法が開示されている（特許文献２参照）。
この提案の技術は、ダイシング時の割れ、欠け、剥がれなどの欠損を低減し、切削粉による汚染を低減することができるものの、バンプの潰れすぎを防ぐことはできない点で問題がある。
Moreover, the NCF joining method using the adhesive sheet of the double layer structure from which a composition differs using soluble polyimide is disclosed (refer patent document 2).
Although this proposed technique can reduce defects such as cracking, chipping, and peeling during dicing and reduce contamination by cutting powder, there is a problem in that bumps cannot be crushed too much.
圧着時のバンプの潰れすぎを防ぐためには、ＮＣＦをある程度硬化させ、ＮＣＦを硬くした状態でバンプを圧着することも考えられるが、このようにした場合には、ＮＣＦの接着性が低下するという問題がある。 In order to prevent the bumps from being crushed too much during crimping, it may be possible to cure the NCF to some extent and to crimp the bumps in a state where the NCF is hardened. However, in this case, the adhesion of the NCF is reduced. There's a problem.
したがって、バンプの潰れすぎによる導通不良を防ぎつつ、接着性が良好な半導体素子の実装方法、及び該半導体素子の実装方法により得られる実装体の提供が求められているのが現状である。 Therefore, the present situation is that there is a demand for a method for mounting a semiconductor element with good adhesion while preventing conduction failure due to excessive crushing of bumps, and a mounting body obtained by the method for mounting the semiconductor element.
本発明は、従来における前記諸問題を解決し、以下の目的を達成することを課題とする。即ち、本発明は、バンプの潰れすぎによる導通不良〔ショート（短絡）〕を防ぎつつ、接着性が良好な半導体素子の実装方法、及び該半導体素子の実装方法により得られる実装体を提供することを目的とする。 An object of the present invention is to solve the above-described problems and achieve the following objects. That is, the present invention provides a method for mounting a semiconductor element with good adhesion while preventing conduction failure [short (short circuit)] due to excessive crushing of bumps, and a mounting body obtained by the method for mounting the semiconductor element. With the goal.
前記課題を解決するための手段としては、以下の通りである。即ち、
＜１＞ バンプが形成された半導体素子の前記バンプを有する面上に、硬化した第一の絶縁性樹脂層と、未硬化の第二の絶縁性樹脂層とをこの順に積層した積層物を作製する積層物作製工程と、
電極を有する基板上に、前記基板の前記電極を有する面が前記第二の絶縁性樹脂層に対向するように前記積層物を配置する配置工程と、
前記半導体素子を加熱及び押圧し、前記第二の絶縁性樹脂層を硬化させるとともに、前記バンプと前記基板の前記電極とを電気的に接続する接続工程と、を含むことを特徴とする半導体素子の実装方法である。
＜２＞ 第二の絶縁性樹脂層の硬化温度（Ｔ２）と第一の絶縁性樹脂層の硬化温度（Ｔ１）との差（Ｔ２−Ｔ１）が、２０℃以上である前記＜１＞に記載の半導体素子の実装方法である。
＜３＞ 積層物作製工程において、未硬化の第二の絶縁性樹脂層が、硬化した第一の絶縁性樹脂層上に積層される前記＜１＞から＜２＞のいずれかに記載の半導体素子の実装方法である。
＜４＞ バンプが、ハンダボールである前記＜１＞から＜３＞のいずれかに記載の半導体素子の実装方法である。
＜５＞ 前記＜１＞から＜４＞のいずれかに記載の半導体素子の実装方法により得られることを特徴とする実装体である。
Means for solving the problems are as follows. That is,
<1> A laminate in which a cured first insulating resin layer and an uncured second insulating resin layer are laminated in this order on the surface of the semiconductor element on which the bump is formed having the bump is manufactured. A laminate manufacturing process,
An arrangement step of arranging the laminate on a substrate having an electrode so that a surface of the substrate having the electrode faces the second insulating resin layer;
A step of heating and pressing the semiconductor element to cure the second insulating resin layer and electrically connecting the bump and the electrode of the substrate. This is the implementation method.
<2> The difference (T 2 −T 1 ) between the curing temperature (T 2 ) of the second insulating resin layer and the curing temperature (T 1 ) of the first insulating resin layer is 20 ° C. or more. <1> A method for mounting a semiconductor element according to <1>.
<3> The semiconductor according to any one of <1> to <2>, wherein the uncured second insulating resin layer is laminated on the cured first insulating resin layer in the laminate manufacturing step. This is an element mounting method.
<4> The method for mounting a semiconductor element according to any one of <1> to <3>, wherein the bump is a solder ball.
<5> A mounting body obtained by the method for mounting a semiconductor element according to any one of <1> to <4>.
本発明によれば、従来における前記諸問題を解決し、前記目的を達成することができ、バンプの潰れすぎによる導通不良〔ショート（短絡）〕を防ぎつつ、接着性が良好な半導体素子の実装方法、及び該半導体素子の実装方法により得られる実装体を提供することができる。 According to the present invention, it is possible to solve the above-mentioned problems and achieve the above-mentioned object, and to mount a semiconductor element with good adhesion while preventing a conduction failure (short circuit) due to excessive crushing of bumps. A mounting body obtained by the method and the mounting method of the semiconductor element can be provided.
（半導体素子の実装方法、及び実装体）
本発明の半導体素子の実装方法は、積層物作製工程と、配置工程と、接続工程とを少なくとも含み、更に必要に応じて、その他の工程を含む。
本発明の実装体は、本発明の前記半導体素子の実装方法により得られる。
(Semiconductor element mounting method and mounting body)
The semiconductor element mounting method of the present invention includes at least a laminate manufacturing process, an arrangement process, and a connection process, and further includes other processes as necessary.
The mounting body of the present invention is obtained by the semiconductor element mounting method of the present invention.
＜積層物作製工程＞
前記積層物作製工程としては、バンプが形成された半導体素子の前記バンプを有する面上に、硬化した第一の絶縁性樹脂層と、未硬化の第二の絶縁性樹脂層とをこの順に積層した積層物を作製する工程であれば、特に制限はなく、目的に応じて適宜選択することができる。
前記積層物作製工程としては、例えば、前記半導体素子の前記バンプを有する面上に、未硬化の第一の絶縁性樹脂層を形成した後に、その未硬化の第一の絶縁性樹脂層上に、未硬化の第二の絶縁性樹脂層を積層し、更に前記未硬化の第一の絶縁性樹脂層を硬化させる工程が挙げられる。なお、この際に、前記未硬化の第二の絶縁性樹脂層は硬化させない。
また、例えば、前記半導体素子の前記バンプを有する面上に、未硬化の第一の絶縁性樹脂層を形成した後に、前記未硬化の第一の絶縁性樹脂層を硬化させ、その硬化した第一の絶縁性樹脂層上に、未硬化の第二の絶縁性樹脂層を積層する工程が挙げられる。
<Laminate production process>
As the laminate manufacturing step, a cured first insulating resin layer and an uncured second insulating resin layer are laminated in this order on the surface of the semiconductor element on which the bump is formed having the bump. If it is the process of producing the laminated body which did, there will be no restriction | limiting in particular, According to the objective, it can select suitably.
As the laminate manufacturing step, for example, after forming an uncured first insulating resin layer on the surface of the semiconductor element having the bumps, on the uncured first insulating resin layer, And a step of laminating an uncured second insulating resin layer and further curing the uncured first insulating resin layer. At this time, the uncured second insulating resin layer is not cured.
Further, for example, after forming an uncured first insulating resin layer on the surface of the semiconductor element having the bumps, the uncured first insulating resin layer is cured, and the cured first A step of laminating an uncured second insulating resin layer on one insulating resin layer may be mentioned.
−半導体素子−
前記半導体素子としては、前記バンプが形成された半導体素子であれば、特に制限はなく、目的に応じて適宜選択することができ、例えば、バンプが形成された、集積回路（ＩＣ）、大規模集積回路（ＬＳＩ）、トランジスタ、サイリスタ、ダイオードなどが挙げられる。また、前記半導体素子は、ダイシングにより個片化される前の各半導体素子の集合体、即ち、各半導体素子が形成された半導体ウェハーであってもよい。
-Semiconductor element-
The semiconductor element is not particularly limited as long as it is a semiconductor element on which the bumps are formed, and can be appropriately selected according to the purpose. For example, an integrated circuit (IC) on which a bump is formed, a large scale An integrated circuit (LSI), a transistor, a thyristor, a diode, and the like can be given. The semiconductor element may be an aggregate of semiconductor elements before being singulated by dicing, that is, a semiconductor wafer on which each semiconductor element is formed.
前記バンプとしては、特に制限はなく、目的に応じて適宜選択することができ、例えば、スタッドバンプ、ハンダボールなどが挙げられる。前記スタッドバンプは、例えば、金属ワイヤを用いて形成することができる。前記ハンダボールは、例えば、半導体素子の電極に超音波を併用しながら加熱及び加圧して固定することにより形成することができる。これらの中でも、前記バンプとしては、ハンダボールが好ましい。
前記バンプの平均高さとしては、特に制限はなく、目的に応じて適宜選択することができ、例えば、１０μｍ〜７０μｍが挙げられる。ここで、前記バンプの高さとは、言い換えれば、バンプとなる突起の前記半導体素子面からの最大高さをいう。前記バンプの平均高さは、前記バンプの高さを任意で５０点測定した際の平均値である。
There is no restriction | limiting in particular as said bump, According to the objective, it can select suitably, For example, a stud bump, a solder ball, etc. are mentioned. The stud bump can be formed using, for example, a metal wire. The solder ball can be formed, for example, by fixing it by heating and pressurizing an electrode of a semiconductor element together with ultrasonic waves. Among these, a solder ball is preferable as the bump.
There is no restriction | limiting in particular as average height of the said bump, According to the objective, it can select suitably, For example, 10 micrometers-70 micrometers are mentioned. Here, the height of the bump means, in other words, the maximum height of the protrusion serving as the bump from the semiconductor element surface. The average height of the bump is an average value when the height of the bump is arbitrarily measured at 50 points.
前記バンプの平均ピッチ（バンプ間距離）としては、特に制限はなく、目的に応じて適宜選択することができ、例えば、５０μｍ〜１５０μｍが挙げられる。
前記バンプの平均ピッチは、前記バンプのピッチを任意で２０点測定した際の平均値である。
ここで、前記バンプの高さ、及び前記バンプのピッチについて図を用いて説明する。図１は、バンプ２が形成された半導体素子１の概略断面図である。図１において、前記バンプ２の高さ（Ｈ）は、バンプとなる突起の最大高さである。また、前記バンプ２のピッチ（Ｌ）は、隣接する前記バンプの中心間距離である。
前記半導体素子の実装方法においては、前記バンプが必要以上に潰れることを防止できることから、上記のごとくバンプ間距離が短い、いわゆる狭ピッチにおいても、ショートを起こすことなく、半導体素子を基板上に実装することができる。
There is no restriction | limiting in particular as an average pitch (bump distance) of the said bump, According to the objective, it can select suitably, For example, 50 micrometers-150 micrometers are mentioned.
The average pitch of the bumps is an average value when the bump pitch is arbitrarily measured at 20 points.
Here, the height of the bump and the pitch of the bump will be described with reference to the drawings. FIG. 1 is a schematic cross-sectional view of a
In the semiconductor element mounting method, since the bumps can be prevented from being crushed more than necessary, the semiconductor elements can be mounted on the substrate without causing a short-circuit even when the distance between the bumps is short as described above, so-called narrow pitch. can do.
−第一の絶縁性樹脂層、及び第二の絶縁性樹脂層−
前記第一の絶縁性樹脂層及び前記第二の絶縁性樹脂層の材質としては、特に制限はなく、目的に応じて適宜選択することができ、例えば、硬化性樹脂と、硬化剤と、無機充填剤とを少なくとも含有し、更に必要に応じて、その他の成分を含有する絶縁性の材質が挙げられる。
-First insulating resin layer and second insulating resin layer-
There is no restriction | limiting in particular as a material of said 1st insulating resin layer and said 2nd insulating resin layer, According to the objective, it can select suitably, For example, curable resin, a hardening | curing agent, inorganic An insulating material containing at least a filler and, if necessary, other components may be used.
−−硬化性樹脂−−
前記硬化性樹脂としては、特に制限はなく、目的に応じて適宜選択することができ、例えば、エポキシ樹脂、フェノキシ樹脂などが挙げられる。
前記エポキシ樹脂としては、例えば、ビスフェノールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ樹脂、フェノールノボラック型エポキシ樹脂などが挙げられる。
前記絶縁性樹脂層における前記硬化性樹脂の含有量としては、特に制限はなく、目的に応じて適宜選択することができるが、２０質量％〜４０質量％が好ましい。
前記含有量が、２０質量％未満であると、接着層としての性能が低下することがあり、４０質量％を超えると、接続信頼性に悪影響を及ぼすことがある。
--Curable resin--
There is no restriction | limiting in particular as said curable resin, According to the objective, it can select suitably, For example, an epoxy resin, a phenoxy resin, etc. are mentioned.
Examples of the epoxy resin include bisphenol A type epoxy resin, bisphenol F type epoxy resin, and phenol novolac type epoxy resin.
There is no restriction | limiting in particular as content of the said curable resin in the said insulating resin layer, Although it can select suitably according to the objective, 20 mass%-40 mass% are preferable.
When the content is less than 20% by mass, the performance as an adhesive layer may be deteriorated. When the content exceeds 40% by mass, connection reliability may be adversely affected.
−−硬化剤−−
前記硬化剤としては、特に制限はなく、目的に応じて適宜選択することができ、例えば、イミダゾール系硬化剤、酸無水物系硬化剤、ポリアミド系硬化剤、フェノール系硬化剤、ポリメルカプタン系硬化剤、有機過酸化物系硬化剤、アニオン系硬化剤、カチオン系硬化剤などが挙げられる。これらは、１種単独で使用してもよいし、２種以上を併用してもよい。
前記イミダゾール系硬化剤としては、例えば、２−メチルイミダゾール、２−フェニルイミダゾールなどが挙げられる。
前記酸無水物系硬化剤としては、例えば、無水フタル酸、無水マレイン酸などが挙げられる。
前記フェノール系硬化剤としては、例えば、フェノールノボラックなどが挙げられる。
前記有機過酸化物系硬化剤としては、例えば、ロイルパーオキサイド、ブチルパーオキサイド、ベンジルパーオキサイド、ジラウロイルパーオキサイド、ジブチルパーオキサイド、ベンジルパーオキサイド、パーオキシジカーボネート、ベンゾイルパーオキサイドなどが挙げられる。
前記アニオン系硬化剤としては、例えば、有機アミン類などが挙げられる。
前記カチオン系硬化剤としては、例えば、スルホニウム塩、オニウム塩、アルミニウムキレート剤などが挙げられる。
前記絶縁性樹脂層における前記硬化剤の含有量としては、特に制限はなく、目的に応じて適宜選択することができるが、１質量％〜２０質量％が好ましい。
--Curing agent--
The curing agent is not particularly limited and may be appropriately selected depending on the intended purpose. For example, an imidazole curing agent, an acid anhydride curing agent, a polyamide curing agent, a phenol curing agent, or a polymercaptan curing. Agents, organic peroxide curing agents, anionic curing agents, cationic curing agents and the like. These may be used individually by 1 type and may use 2 or more types together.
Examples of the imidazole curing agent include 2-methylimidazole and 2-phenylimidazole.
Examples of the acid anhydride curing agent include phthalic anhydride and maleic anhydride.
As said phenol type hardening | curing agent, a phenol novolak etc. are mentioned, for example.
Examples of the organic peroxide-based curing agent include royl peroxide, butyl peroxide, benzyl peroxide, dilauroyl peroxide, dibutyl peroxide, benzyl peroxide, peroxydicarbonate, benzoyl peroxide, and the like. .
Examples of the anionic curing agent include organic amines.
Examples of the cationic curing agent include a sulfonium salt, an onium salt, and an aluminum chelating agent.
There is no restriction | limiting in particular as content of the said hardening | curing agent in the said insulating resin layer, Although it can select suitably according to the objective, 1 mass%-20 mass% are preferable.
−−無機充填剤−−
前記無機充填剤としては、特に制限はなく、目的に応じて適宜選択することができ、例えば、水酸化アルミニウム、水酸化マグネシウム、炭酸カルシウム、炭酸マグネシウム、珪酸カルシウム、珪酸マグネシウム、酸化カルシウム、酸化マグネシウム、アルミナ粉末、シリカ、窒化アルミニウム、窒化ホウ素粉末、ホウ酸アルミウイスカなどが挙げられる。これらは、１種単独で使用してもよいし、２種以上を併用してもよい。
前記絶縁性樹脂層における前記無機充填剤の含有量としては、特に制限はなく、目的に応じて適宜選択することができるが、３０質量％〜７０質量％が好ましい。
前記含有量が、３０質量％未満であると、寸法安定性が低下することがあり、７０質量％を超えると、フィルム状態の維持が困難になることがある。
--Inorganic filler--
The inorganic filler is not particularly limited and may be appropriately selected depending on the intended purpose. For example, aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide , Alumina powder, silica, aluminum nitride, boron nitride powder, aluminum borate whisker and the like. These may be used individually by 1 type and may use 2 or more types together.
There is no restriction | limiting in particular as content of the said inorganic filler in the said insulating resin layer, Although it can select suitably according to the objective, 30 mass%-70 mass% are preferable.
When the content is less than 30% by mass, the dimensional stability may be lowered, and when it exceeds 70% by mass, it may be difficult to maintain the film state.
−−その他の成分−−
前記その他の成分としては、特に制限はなく、目的に応じて適宜選択することができ、例えば、応力緩和剤、軟化剤、促進剤、老化防止剤、着色剤（顔料、染料）、イオンキャッチャー剤などが挙げられる。
-Other ingredients-
There is no restriction | limiting in particular as said other component, According to the objective, it can select suitably, For example, a stress relaxation agent, a softening agent, an accelerator, anti-aging agent, a coloring agent (pigment, dye), an ion catcher agent Etc.
−−−応力緩和剤−−−
前記応力緩和剤としては、例えば、ＰＢ（ポリブタジエンゴム）、アクリルゴム、アクリロニトリルゴム、ＥＶＡ、ゴム変性エポキシ樹脂などが挙げられる。これらは、１種単独で使用してもよいし、２種以上を併用してもよい。
前記絶縁性樹脂層における前記応力緩和剤の含有量としては、特に制限はなく、目的に応じて適宜選択することができるが、５質量％〜３０質量％が好ましい。
---- Stress relaxation agent ---
Examples of the stress relaxation agent include PB (polybutadiene rubber), acrylic rubber, acrylonitrile rubber, EVA, rubber-modified epoxy resin, and the like. These may be used individually by 1 type and may use 2 or more types together.
There is no restriction | limiting in particular as content of the said stress relaxation agent in the said insulating resin layer, Although it can select suitably according to the objective, 5 mass%-30 mass% are preferable.
前記第一の絶縁性樹脂層、及び前記第二の絶縁性樹脂層の形成方法としては、特に制限はなく、目的に応じて適宜選択することができ、例えば、前記硬化性樹脂、前記硬化剤、前記無機充填剤、及び溶剤などを含有する絶縁層用組成物を塗布して形成する方法が挙げられる。
前記塗布方法としては、例えば、スピンコート法、キャスティング法、マイクログラビアコート法、グラビアコート法、ナイフコート法、バーコート法、ロールコート法、ワイヤーバーコート法、ディップコート法、スプレーコート法などが挙げられる。
また、離型性のあるＰＥＴ（ポリエチレンテレフタレート）フィルムなどの離型フィルムに前記絶縁性用組成物を塗布して絶縁性樹脂フィルムを形成した後に、該絶縁性樹脂フィルムを前記半導体素子に貼り付けることにより形成する方法が挙げられる。
There is no restriction | limiting in particular as a formation method of said 1st insulating resin layer and said 2nd insulating resin layer, According to the objective, it can select suitably, For example, said curable resin, said hardening | curing agent And a method of applying and forming a composition for an insulating layer containing the inorganic filler and a solvent.
Examples of the coating method include spin coating, casting, micro gravure coating, gravure coating, knife coating, bar coating, roll coating, wire bar coating, dip coating, and spray coating. Can be mentioned.
In addition, after the insulating composition is applied to a release film such as a releasable PET (polyethylene terephthalate) film to form an insulating resin film, the insulating resin film is attached to the semiconductor element. The method of forming by this is mentioned.
前記第一の絶縁性樹脂層の平均厚みとしては、特に制限はなく、目的に応じて適宜選択することができるが、５μｍ以上が好ましい。前記平均厚みが、５μｍ未満であると、接着力が低下することがあり好ましくない。 There is no restriction | limiting in particular as average thickness of said 1st insulating resin layer, Although it can select suitably according to the objective, 5 micrometers or more are preferable. If the average thickness is less than 5 μm, the adhesive strength may be lowered, which is not preferable.
また、前記第一の絶縁性樹脂層の平均厚みとしては、前記バンプの平均高さの１／２倍よりも大きいことが好ましく、３／５倍よりも大きいことがより好ましい。前記平均厚みが、１／２倍以下であると、バンプの潰れ過ぎによるショート（導通不良）が生じることがある。 The average thickness of the first insulating resin layer is preferably larger than ½ times the average height of the bumps, and more preferably larger than 3/5 times. If the average thickness is 1/2 times or less, a short circuit (conducting failure) may occur due to excessive crushing of bumps.
前記第二の絶縁性樹脂層の平均厚みとしては、特に制限はなく、目的に応じて適宜選択することができるが、５μｍ以上が好ましい。前記平均厚みが、５μｍ未満であると、接着力が低下することがあり好ましくない。 There is no restriction | limiting in particular as average thickness of said 2nd insulating resin layer, Although it can select suitably according to the objective, 5 micrometers or more are preferable. If the average thickness is less than 5 μm, the adhesive strength may be lowered, which is not preferable.
また、前記第二の絶縁性樹脂層の平均厚みとしては、前記バンプの平均高さの１／２倍よりも小さいことが好ましく、２／５倍よりも小さいことがより好ましい。前記平均厚みが、１／２倍以上であると、圧着時のバンプの潰れを制御できないことがある。 The average thickness of the second insulating resin layer is preferably smaller than ½ times the average height of the bumps, and more preferably smaller than 2/5 times. When the average thickness is ½ times or more, it may be impossible to control the crushing of the bumps during pressure bonding.
前記積層物作製工程において、前記第一の絶縁性樹脂は硬化するが、本発明において「硬化」とは、硬化率が５０％を超える状態をいう。
また、前記積層物作製工程において、前記第二の絶縁性樹脂層は未硬化であるが、本発明において「未硬化」とは、硬化率が５０％以下の状態をいう。
In the laminate manufacturing step, the first insulating resin is cured. In the present invention, “curing” refers to a state where the curing rate exceeds 50%.
In the laminate manufacturing step, the second insulating resin layer is uncured. In the present invention, “uncured” refers to a state where the curing rate is 50% or less.
前記硬化率は、以下の方法により求めることができる。
測定対象の絶縁性樹脂層について、示差走査熱量計により示差走査熱量測定を行い、発熱量（Ｊ１）を測定する。また、前記測定対象の絶縁性樹脂層と同じ組成であり、かつ熱履歴が硬化温度未満である（硬化温度以上の熱にさらされたことがない）絶縁性樹脂層について、示差走査熱量計により示差走査熱量測定を行い、発熱量（Ｊ０）を測定する。そして、次式：硬化率（％）＝〔（Ｊ０−Ｊ１）／Ｊ０〕×１００〕により硬化率（％）を求めることができる。
ここで、示差走査熱量測定における測定条件としては、例えば、測定試料の質量が１０ｍｇ、昇温速度が１０℃／分、測定温度が２５℃〜２００℃であることが挙げられる。
The curing rate can be determined by the following method.
The insulating resin layer to be measured is subjected to differential scanning calorimetry with a differential scanning calorimeter, and the calorific value (J 1 ) is measured. Further, with respect to the insulating resin layer having the same composition as the insulating resin layer to be measured and having a thermal history lower than the curing temperature (has not been exposed to heat higher than the curing temperature), a differential scanning calorimeter is used. Differential scanning calorimetry is performed, and the calorific value (J 0 ) is measured. Then, the following formula: hardening rate (%) = [(J 0 -J 1) / J 0 ] hardening rate by × 100] (%) can be obtained.
Here, as measurement conditions in differential scanning calorimetry, for example, the mass of the measurement sample is 10 mg, the temperature increase rate is 10 ° C./min, and the measurement temperature is 25 ° C. to 200 ° C.
前記第二の絶縁性樹脂層の硬化温度（Ｔ２）と前記第一の絶縁性樹脂層の硬化温度（Ｔ１）との差（Ｔ２−Ｔ１）としては、特に制限はなく、目的に応じて適宜選択することができるが、２０℃以上であることが好ましい。前記差（Ｔ２−Ｔ１）が、２０℃未満であると、第一の絶縁性樹脂層が十分に支柱として機能せず、圧着時にショート（導通不良）が発生する原因となることがある。 The difference (T 2 −T 1 ) between the curing temperature (T 2 ) of the second insulating resin layer and the curing temperature (T 1 ) of the first insulating resin layer is not particularly limited, Although it can select suitably according to, it is preferable that it is 20 degreeC or more. If the difference (T 2 −T 1 ) is less than 20 ° C., the first insulating resin layer does not sufficiently function as a support column, which may cause a short circuit (conducting failure) during crimping. .
ここで、前記硬化温度とは、未硬化の絶縁性樹脂をレオメーター法で測定した際に、最低溶融粘度を示す温度をいう。前記硬化温度とは、硬化開始温度ともいうことができる。
前記レオメーター法による測定は、例えば、レオメーター（ＡＲＥＳ、ＴＡインスツルメンツ社）を使用し、昇温速度５℃／ｍｉｎ、周波数１ｒａｄ／ｓｅｃの条件にて行うことができる。
Here, the curing temperature refers to a temperature showing a minimum melt viscosity when an uncured insulating resin is measured by a rheometer method. The curing temperature can also be referred to as a curing start temperature.
The measurement by the rheometer method can be performed, for example, using a rheometer (ARES, TA Instruments) under conditions of a temperature rising rate of 5 ° C./min and a frequency of 1 rad / sec.
前記積層物作製工程は、各半導体素子が形成された半導体ウェハーとしての前記半導体素子の前記バンプを有する面上に、硬化した第一の絶縁性樹脂層と、未硬化の第二の絶縁性樹脂層とをこの順に積層した積層物を作製する工程であってもよい。この場合、前記積層物作製工程の後に、ダイシング工程を行うことにより、個片化された前記半導体素子上に、硬化した第一の絶縁性樹脂層と、未硬化の第二の絶縁性樹脂層とをこの順に積層した積層物を得ることができる。 In the laminate manufacturing step, a cured first insulating resin layer and an uncured second insulating resin are formed on the surface of the semiconductor element having the bumps of the semiconductor element as a semiconductor wafer on which each semiconductor element is formed. It may be a step of producing a laminate in which layers are laminated in this order. In this case, a hardened first insulating resin layer and an uncured second insulating resin layer are formed on the semiconductor element separated by performing a dicing process after the laminate manufacturing process. Can be obtained in this order.
＜配置工程＞
前記配置工程としては、電極を有する基板上に、前記基板の前記電極を有する面が前記第二の絶縁性樹脂層に対向するように前記積層物を配置する工程であれば、特に制限はなく、目的に応じて適宜選択することができる。
<Arrangement process>
The placement step is not particularly limited as long as it is a step of placing the laminate on the substrate having electrodes so that the surface of the substrate having the electrodes faces the second insulating resin layer. Can be appropriately selected according to the purpose.
−基板−
前記基板としては、電極を有する基板であれば、特に制限はなく、目的に応じて適宜選択することができ、例えば、ガラスエポキシ基板、リジッド基板、フレキシブル配線板などが挙げられる。
-Board-
The substrate is not particularly limited as long as it is a substrate having electrodes, and can be appropriately selected according to the purpose. Examples thereof include a glass epoxy substrate, a rigid substrate, and a flexible wiring board.
＜接続工程＞
前記接続工程としては、前記半導体素子を加熱及び押圧し、前記第二の絶縁性樹脂層を硬化させるとともに、前記バンプと前記基板の前記電極とを電気的に接続する工程であれば、特に制限はなく、目的に応じて適宜選択することができる。
前記加熱及び押圧の方法としては、特に制限はなく、目的に応じて適宜選択することができ、例えば、加熱機構を備えた押圧部材により行う方法が挙げられる。前記加熱機構を備えた押圧部材としては、例えば、加熱ボンダーが挙げられる。
前記押圧部材の先端形状としては、特に制限はなく、目的に応じて適宜選択することができ、例えば、平面状、曲面状などが挙げられる。なお、前記先端形状が曲面状である場合、前記曲面状に沿って押圧してもよい。
前記加熱の温度としては、前記第二の絶縁性樹脂層が硬化する温度であれば、特に制限はなく、目的に応じて適宜選択することができるが、１００℃〜３００℃が好ましい。
前記押圧の圧力としては、特に制限はなく、目的に応じて適宜選択することができる。
前記加熱及び押圧の時間としては、特に制限はなく、目的に応じて適宜選択することができ、例えば、１秒間〜３００秒間が挙げられる。
<Connection process>
The connecting step is not particularly limited as long as it is a step of heating and pressing the semiconductor element to cure the second insulating resin layer and electrically connecting the bump and the electrode of the substrate. It can be appropriately selected depending on the purpose.
There is no restriction | limiting in particular as the method of the said heating and press, According to the objective, it can select suitably, For example, the method performed with the press member provided with the heating mechanism is mentioned. Examples of the pressing member provided with the heating mechanism include a heating bonder.
There is no restriction | limiting in particular as a front-end | tip shape of the said press member, According to the objective, it can select suitably, For example, planar shape, curved surface shape, etc. are mentioned. In addition, when the said front-end | tip shape is a curved surface shape, you may press along the said curved surface shape.
The heating temperature is not particularly limited as long as it is a temperature at which the second insulating resin layer is cured, and can be appropriately selected according to the purpose, but is preferably 100 ° C to 300 ° C.
There is no restriction | limiting in particular as the pressure of the said press, According to the objective, it can select suitably.
There is no restriction | limiting in particular as time of the said heating and press, According to the objective, it can select suitably, For example, 1 second-300 seconds are mentioned.
前記加熱により、前記第二の絶縁性樹脂層が硬化して、前記半導体素子と前記基板とが接着されるとともに、前記押圧により、前記半導体素子の前記バンプと、前記基板の前記電極とが接触し電気的な接続が行われる。前記加熱及び押圧の際に、前記第一の絶縁性樹脂層は既に硬化していることから、この硬化した前記第一の絶縁性樹脂層により、押圧による前記バンプの潰れすぎを防ぐことができる。また、このことにより、隣接する前記バンプ間の接触による導通不良を防ぐことができる。 The second insulating resin layer is cured by the heating to bond the semiconductor element and the substrate, and the bump contacts the semiconductor element and the electrode of the substrate by the pressing. Electrical connection is made. Since the first insulating resin layer is already cured during the heating and pressing, the cured first insulating resin layer can prevent the bumps from being crushed by the pressing. . In addition, this can prevent conduction failure due to contact between adjacent bumps.
ここで、図を用いて前記半導体素子の実装方法の一例を説明する。
図２Ａから図２Ｅに、前記積層物作製工程として、前記半導体素子の前記バンプを有する面上に、未硬化の第一の絶縁性樹脂層を形成した後に、その未硬化の第一の絶縁性樹脂層上に、未硬化の第二の絶縁性樹脂層を積層し、前記未硬化の第一の絶縁性樹脂層を硬化させる工程を用いた前記半導体素子の実装方法を示す。
図２Ａは、バンプ２が形成された半導体素子１の概略断面図である。まず、前記半導体素子１の前記バンプ２を有する面上に、未硬化の第一の絶縁性樹脂層３ａ、及び未硬化の第二の絶縁性樹脂層４ａを順次積層する（図２Ｂ）。続いて、前記未硬化の第一の絶縁性樹脂層３ａが硬化し、かつ前記未硬化の第二の絶縁性樹脂層４ａが硬化しない加熱温度でこれらを加熱し、前記未硬化の第一の絶縁性樹脂層３ａを硬化させ、硬化した第一の絶縁性樹脂層３ｂにし、積層物を得る（図２Ｃ）。続いて、電極６を有する基板５上に、前記基板５の前記電極６を有する面が前記未硬化の第二の絶縁性樹脂層４ａに対向するように前記積層物を配置する（図２Ｄ）。なお、この配置の際には、前記未硬化の第二の絶縁性樹脂層４ａと前記基板５は接していてもよい。続いて、前記半導体素子１を加熱装置を備えた押圧部材７により加熱及び押圧し、前記未硬化の第二の絶縁性樹脂層４ａを硬化させ、硬化した第二の絶縁性樹脂層４ｂにするとともに、前記バンプ２と前記電極６とを電気的に接続する（図２Ｅ）。以上により接合体が得られる。
Here, an example of the mounting method of the semiconductor element will be described with reference to the drawings.
In FIG. 2A to FIG. 2E, after forming the uncured first insulating resin layer on the surface of the semiconductor element having the bumps as the laminate manufacturing step, the uncured first insulating property is formed. The mounting method of the said semiconductor element using the process of laminating | stacking an uncured 2nd insulating resin layer on a resin layer and hardening | curing the said uncured 1st insulating resin layer is shown.
FIG. 2A is a schematic cross-sectional view of the
また、図３Ａから図３Ｆに、前記積層物作製工程として、前記半導体素子の前記バンプを有する面上に、未硬化の第一の絶縁性樹脂層を形成した後に、前記未硬化の第一の絶縁性樹脂層を硬化させ、その硬化した第一の絶縁性樹脂層上に、未硬化の第二の絶縁性樹脂層を積層する工程を用いた前記半導体素子の実装方法を示す。
図３Ａは、バンプ２が形成された半導体素子１の概略断面図である。まず、前記半導体素子１の前記バンプ２を有する面上に、未硬化の第一の絶縁性樹脂層３ａを形成する（図３Ｂ）。続いて、これらを加熱して、前記未硬化の第一の絶縁性樹脂層を硬化させ、硬化した第一の絶縁性樹脂層３ｂにし、積層物を得る（図３Ｃ）。続いて、前記硬化した第一の絶縁性樹脂層３ｂ上に、未硬化の第二の絶縁性樹脂層４ａを形成し、積層物を得る（図３Ｄ）。続いて、電極６を有する基板５上に、前記基板５の前記電極６を有する面が前記未硬化の第二の絶縁性樹脂層４ａに対向するように前記積層物を配置する（図３Ｅ）。なお、この配置の際には、前記未硬化の第二の絶縁性樹脂層４ａと前記基板５は接していてもよい。続いて、前記半導体素子１を加熱装置を備えた押圧部材７により加熱及び押圧し、前記未硬化の第二の絶縁性樹脂層４ａを硬化させ、硬化した第二の絶縁性樹脂層４ｂにするとともに、前記バンプ２と前記基板５の前記電極６とを電気的に接続する（図３Ｆ）。以上により接合体が得られる。
3A to 3F, as the laminate manufacturing process, after forming an uncured first insulating resin layer on the surface of the semiconductor element having the bumps, the uncured first A method of mounting the semiconductor element using a step of curing an insulating resin layer and laminating an uncured second insulating resin layer on the cured first insulating resin layer is shown.
FIG. 3A is a schematic cross-sectional view of the
以下、本発明の実施例を説明するが、本発明は、これらの実施例に何ら限定されるものではない。なお、「部」は質量部を示す。 Examples of the present invention will be described below, but the present invention is not limited to these examples. “Part” means part by mass.
（製造例１）
＜絶縁性樹脂フィルムの作製＞
以下の表１に示す配合を含有する絶縁性樹脂用組成物を調製し、該絶縁性樹脂用組成物を離型フィルム上にバーコーターにより塗布し、その後７０℃のオーブンにて有機溶媒を除去することにより、所定の厚みを有する絶縁性樹脂フィルムを作製した。
(Production Example 1)
<Preparation of insulating resin film>
An insulating resin composition containing the composition shown in Table 1 below was prepared, the insulating resin composition was applied onto a release film with a bar coater, and then the organic solvent was removed in an oven at 70 ° C. Thus, an insulating resin film having a predetermined thickness was produced.
表１中、ビスフェノールＡ型エポキシ樹脂は、ＪＲ−８２８（三菱化学社製）である。カチオン系硬化剤は、サンエイドＳＩ−６０Ｌ（三新化学社製、芳香族スルホニウム塩）である。アニオン系硬化剤は、アミキュアＰＮ−２３（味の素ファインテクノ社製）である。フェノール系硬化剤は、ＰＨＥＮＯＬＩＴＥ ＴＤ２１３１（ＤＩＣ社製）である。アクリルゴムは、ＳＧ−Ｐ−３（ナガセケムテック社製）である。シリカは、ＥＸＶ−４（龍森社製）である。
表１中の「硬化温度」は、得られた絶縁性樹脂フィルムの硬化温度である。この硬化温度とは、レオメーター法で測定した際の、最低溶融粘度を示す温度である。前記レオメーター法による測定は、レオメーター（ＡＲＥＳ、ＴＡインスツルメンツ社）を使用し、昇温速度５℃／ｍｉｎ、周波数１ｒａｄ／ｓｅｃ、２５℃〜２５０℃の条件にて行った。
In Table 1, the bisphenol A type epoxy resin is JR-828 (manufactured by Mitsubishi Chemical Corporation). The cationic curing agent is Sun-Aid SI-60L (manufactured by Sanshin Chemical Co., Ltd., aromatic sulfonium salt). The anionic curing agent is Amicure PN-23 (manufactured by Ajinomoto Fine Techno Co.). The phenolic curing agent is PHENOLITE TD2131 (manufactured by DIC). The acrylic rubber is SG-P-3 (manufactured by Nagase Chemtech). Silica is EXV-4 (manufactured by Tatsumori).
“Curing temperature” in Table 1 is the curing temperature of the obtained insulating resin film. The curing temperature is a temperature showing the lowest melt viscosity when measured by the rheometer method. The measurement by the rheometer method was performed using a rheometer (ARES, TA Instruments) under the conditions of a temperature rising rate of 5 ° C./min, a frequency of 1 rad / sec, and 25 ° C. to 250 ° C.
（実施例１）
＜半導体素子の実装＞
−半導体素子の準備−
評価用ＩＣチップ（ソニーケミカル＆インフォメーションデバイス株式会社製、大きさ６．３ｍｍ×６．３ｍｍ、厚み０．２ｍｍ、ハンダバンプ、バンプ平均高さ３５μｍ、バンプ平均ピッチ８５μｍ）を用意した。
−積層物作製工程−
前記評価用ＩＣチップのバンプを有する面上に、配合１の絶縁性樹脂フィルム（厚み２５μｍ）を貼り付け、未硬化の第一の絶縁性樹脂層を形成した。続いて、前記未硬化の第一の絶縁性樹脂層上に、配合４の絶縁性樹脂フィルム（厚み１０μｍ）を貼り付け、未硬化の第二の絶縁性樹脂層を形成した。そして、１００℃で３０分間加熱することにより、前記第一の絶縁性樹脂層を硬化させ、積層物を得た。前記加熱後の、前記第一の絶縁性樹脂層の硬化率は、１００％（硬化状態）であり、前記第二の絶縁性樹脂層の硬化率は、４０％（未硬化状態）であった。
−配置工程−
続いて、電極を有する基板（ガラスエポキシ基板）上に、前記基板の前記電極を有する面が前記未硬化の第二の絶縁性樹脂層に対向するように前記積層物を配置した。
−接続工程−
続いて、前記評価用ＩＣチップをフリップチップボンダー（ＦＣＢ３、パナソニックファクトリーソリューションズ社製、加熱装置を備えた押圧部材）により３０秒間、２５０℃で加熱及び５０Ｎ／ＩＣで押圧し、前記未硬化の第二の絶縁性樹脂層を硬化させ、硬化した第二の絶縁性樹脂層にするとともに、前記バンプと前記電極とを電気的に接続させた。
Example 1
<Mounting of semiconductor elements>
-Preparation of semiconductor elements-
An IC chip for evaluation (manufactured by Sony Chemical & Information Device Co., Ltd., size 6.3 mm × 6.3 mm, thickness 0.2 mm, solder bump, bump average height 35 μm, bump average pitch 85 μm) was prepared.
-Laminate production process-
On the surface of the evaluation IC chip having the bumps, an insulating resin film (thickness 25 μm) of
-Placement process-
Subsequently, the laminate was disposed on a substrate having an electrode (glass epoxy substrate) such that a surface of the substrate having the electrode opposed to the uncured second insulating resin layer.
-Connection process-
Subsequently, the IC chip for evaluation was heated at 250 ° C. and pressed at 50 N / IC for 30 seconds by a flip chip bonder (FCB3, manufactured by Panasonic Factory Solutions, a pressing member equipped with a heating device), and the uncured second IC chip was pressed. The two insulating resin layers were cured to form a cured second insulating resin layer, and the bumps and the electrodes were electrically connected.
＜測定＞
−硬化率−
硬化率は、以下の方法により求めた。
測定対象の絶縁性樹脂層について、示差走査熱量計（ＤＳＣ ９１００、ＴＡインスツルメンツ社製）により示差走査熱量測定を行い、発熱量（Ｊ１）を測定した。また、前記測定対象の絶縁性樹脂層と同じ組成であり、かつ熱履歴が硬化温度未満である（硬化温度以上の熱にさらされたことがない）絶縁性樹脂層について、示差走査熱量計により示差走査熱量測定を行い、発熱量（Ｊ０）を測定した。そして、次式：硬化率（％）＝〔（Ｊ０−Ｊ１）／Ｊ０〕×１００〕により硬化率（％）を求めた。
ここで、示差走査熱量測定における測定条件は、測定試料の質量が１０ｍｇ、昇温速度が１０℃／分、測定温度が２５℃〜２００℃であった。
<Measurement>
-Curing rate-
The curing rate was determined by the following method.
The insulating resin layer to be measured was subjected to differential scanning calorimetry using a differential scanning calorimeter (DSC 9100, manufactured by TA Instruments), and the calorific value (J 1 ) was measured. Further, with respect to the insulating resin layer having the same composition as the insulating resin layer to be measured and having a thermal history lower than the curing temperature (has not been exposed to heat higher than the curing temperature), a differential scanning calorimeter is used. Differential scanning calorimetry was performed and the calorific value (J 0 ) was measured. Then, the following formula: was obtained hardening rate (%) Curing rate (%) = [(J 0 -J 1) / J 0 ] × 100].
Here, the measurement conditions in differential scanning calorimetry were as follows: the mass of the measurement sample was 10 mg, the heating rate was 10 ° C./min, and the measurement temperature was 25 ° C. to 200 ° C.
＜評価＞
−バンプ評価−
ＳＥＭ（Ｓ−３０００Ｎ、日立製作所社製）によりバンプの潰れ率を測定し、更に隣接するバンプの導通を測定し、下記評価基準にて評価した。結果を表２−１に示す。
○：バンプ潰れ率が５０％以下、かつ導通ＯＫ
△：バンプ潰れ率が５０％を超えるが導通はＯＫ
×：バンプ潰れ率が５０％を超える、又は導通不良
ここで、バンプ潰れ率とは、次式：
バンプ潰れ率（％）＝［〔（実装前のバンプ平均高さ）−（実装後のバンプ平均高さ）〕／（実装前のバンプ平均高さ）］×１００
で求められる値である。
ここで、導通ＯＫとは、隣接するバンプ同士に接触が無く、導通がないことを指す。導通不良とは、隣接するバンプ同士に接触があり、導通があることを指す。ここで、４端子法で測定した際に、０．１Ω以上０．２Ω以下であると導通は良好であり、０．１Ω未満であるとショート（短絡）が発生している、０．２Ωを超えるであると接続が十分でない、と判断する。
<Evaluation>
-Bump evaluation-
The bump crush rate was measured by SEM (S-3000N, manufactured by Hitachi, Ltd.), and the continuity of adjacent bumps was measured and evaluated according to the following evaluation criteria. The results are shown in Table 2-1.
○: Bump crushing rate is 50% or less and conduction is OK
Δ: Bump crushing rate exceeds 50%, but conduction is OK
X: Bump crushing rate exceeds 50% or poor conduction Here, the bump crushing rate is the following formula:
Bump crushing rate (%) = [[(average bump height before mounting) − (average bump height after mounting)] / (average bump height before mounting)] × 100
This is the value obtained by.
Here, “conduction OK” means that there is no contact between adjacent bumps and there is no conduction. The conduction failure means that there is contact between adjacent bumps and there is conduction. Here, when measured by the four-terminal method, if it is 0.1Ω or more and 0.2Ω or less, conduction is good, and if it is less than 0.1Ω, a short circuit occurs. If it exceeds, it is determined that the connection is not sufficient.
−接着性−
目視により圧着時の接合体を下記基準により評価した。評価結果を表２−１に示す。
○：圧着時に基板と接合できた
×：圧着時に基板と接合できない
-Adhesiveness-
The joined body at the time of pressure bonding was visually evaluated according to the following criteria. The evaluation results are shown in Table 2-1.
○: Can be joined to the substrate during crimping ×: Cannot be joined to the substrate during crimping
−接続信頼性−
デジタルマルチメーター（Ｆｌｕｋｅ社製、Ｆｌｕｋｅ−１１５）により抵抗値を測定し、下記評価基準により評価した。結果を表２−１に示す。
○：０．１Ω〜０．２Ω
×：０．１Ω未満、又は０．２Ωより大
-Connection reliability-
The resistance value was measured with a digital multimeter (Fluke-115, manufactured by Fluke), and evaluated according to the following evaluation criteria. The results are shown in Table 2-1.
○: 0.1Ω to 0.2Ω
X: Less than 0.1Ω or greater than 0.2Ω
（実施例２〜１３、比較例１〜２３）
実施例１において、第一の絶縁性樹脂層、及び第二の絶縁性樹脂層の配合、及び厚み、並びに積層物作製工程における加熱温度を、表２−１〜表２−３に示したものに代えた以外は、実施例１と同様にして、半導体素子の実装を行い、測定、及び評価を行った。結果を表２−１〜表２−３に示す。
(Examples 2 to 13, Comparative Examples 1 to 23)
In Example 1, the composition and thickness of the first insulating resin layer and the second insulating resin layer, and the heating temperature in the laminate manufacturing process are shown in Tables 2-1 to 2-3. A semiconductor element was mounted, measured, and evaluated in the same manner as in Example 1 except that it was replaced with. The results are shown in Tables 2-1 to 2-3.
（実施例１４）
＜半導体素子の実装＞
−半導体素子の準備−
評価用ＩＣチップ（ソニーケミカル＆インフォメーションデバイス株式会社製、大きさ６．３ｍｍ×６．３ｍｍ、厚み０．２ｍｍ、ハンダバンプ、バンプ平均高さ３５μｍ、バンプ平均ピッチ８５μｍ）を用意した。
−積層物作製工程−
前記評価用ＩＣチップのバンプを有する面上に、配合２の絶縁性樹脂フィルム（厚み２５μｍ）を貼り付け、未硬化の第一の絶縁性樹脂層を形成した。続いて、これらを１５０℃で３０分間加熱することにより、前記第一の絶縁性樹脂層を硬化させた。続いて、前記硬化した第一の絶縁性樹脂層上に、配合３の絶縁性樹脂フィルム（厚み１０μｍ）を貼り付け、未硬化の第二の絶縁性樹脂層を形成し積層物を得た。得られた積層物における、前記第一の絶縁性樹脂層の硬化率は、１００％（硬化状態）であった。前記第二の絶縁性樹脂層の硬化率は、０％（未硬化状態）であった。
−配置工程−
続いて、電極を有する基板（ガラスエポキシ基板）上に、前記基板の前記電極を有する面が前記未硬化の第二の絶縁性樹脂層に対向するように前記積層物を配置した。
−接続工程−
続いて、前記評価用ＩＣチップをフリップチップボンダー（ＦＣＢ３、パナソニックファクトリーソリューションズ社製）により３０秒間、２５０℃で加熱及び５０Ｎ／ＩＣで押圧し、前記未硬化の第二の絶縁性樹脂層を硬化させ、硬化した第二の絶縁性樹脂層にするとともに、前記バンプと前記電極とを電気的に接続させた。
(Example 14)
<Mounting of semiconductor elements>
-Preparation of semiconductor elements-
An IC chip for evaluation (manufactured by Sony Chemical & Information Device Co., Ltd., size 6.3 mm × 6.3 mm, thickness 0.2 mm, solder bump, bump average height 35 μm, bump average pitch 85 μm) was prepared.
-Laminate production process-
An insulating resin film (thickness 25 μm) of
-Placement process-
Subsequently, the laminate was disposed on a substrate having an electrode (glass epoxy substrate) such that a surface of the substrate having the electrode opposed to the uncured second insulating resin layer.
-Connection process-
Subsequently, the IC chip for evaluation is heated by a flip chip bonder (FCB3, manufactured by Panasonic Factory Solutions) for 30 seconds at 250 ° C. and pressed with 50 N / IC to cure the uncured second insulating resin layer. The cured second insulating resin layer was formed, and the bump and the electrode were electrically connected.
実施例１と同様にして、測定、及び評価を行った。結果を表２−４に示す。 Measurement and evaluation were performed in the same manner as in Example 1. The results are shown in Table 2-4.
（実施例１５、及び１６）
実施例１４において、第一の絶縁性樹脂層、及び第二の絶縁性樹脂層の配合を、表２−４に示したものに代えた以外は、実施例１４と同様にして、半導体素子の実装を行い、測定、及び評価を行った。結果を表２−４に示す。
(Examples 15 and 16)
In Example 14, except that the combination of the first insulating resin layer and the second insulating resin layer was changed to that shown in Table 2-4, Mounting, measurement, and evaluation were performed. The results are shown in Table 2-4.
実施例１〜１３、及び比較例１〜２３のバンプ評価の結果について、硬化温度との関係を表３にまとめた。 The results of bump evaluation of Examples 1 to 13 and Comparative Examples 1 to 23 are summarized in Table 3 with respect to the curing temperature.
表２−１〜表２−３及び表３の結果から、実施例１〜１３の、本発明の半導体素子の製造方法により得られた実装体は、接続時に第一の絶縁性樹脂層が硬化していることから、バンプのつぶれによる導通不良（ショート）を防ぐことができた。また、接着性、接続信頼性も良好であった。特に、第二の絶縁性樹脂層の硬化温度（Ｔ２）と第一の絶縁性樹脂層の硬化温度（Ｔ１）との差（Ｔ２−Ｔ１）が２０℃以上である実施例１〜３、７〜９、１１、１２、及び１４においては、バンプ潰れ率が５０％以下であり、かつ導通不良（ショート）もなく、非常に良好であった。
また、表２−４の結果から、実施例１４〜１６の、本発明の半導体素子の製造方法により得られた実装体は、第一の絶縁性樹脂層を硬化した上に第二の絶縁性樹脂層を積層しているため、硬化温度が近くても、バンプ潰れ率が５０％以下であり、かつ導通不良（ショート）もなく、非常に良好であった。
From the results of Tables 2-1 to 2-3 and Table 3, in the mounting bodies obtained by the semiconductor element manufacturing method of Examples 1 to 13 of the present invention, the first insulating resin layer was cured at the time of connection. Therefore, it was possible to prevent a conduction failure (short circuit) due to the collapse of the bumps. Also, the adhesiveness and connection reliability were good. In particular, Examples 1 to 3 and 7 where the difference (T2−T1) between the curing temperature (T2) of the second insulating resin layer and the curing temperature (T1) of the first insulating resin layer is 20 ° C. or more. In 9, 9, 12, and 14, the bump crush rate was 50% or less, and there was no conduction failure (short circuit), which was very good.
In addition, from the results of Table 2-4, the mounting bodies obtained by the method for manufacturing a semiconductor element of Examples 14 to 16 were cured with the first insulating resin layer and then the second insulating property. Since the resin layers were laminated, even when the curing temperature was close, the bump crushing rate was 50% or less, and there was no conduction failure (short circuit), which was very good.
一方、比較例１〜２３の半導体素子の製造方法により得られた実装体は、バンプ評価、接着性、及び接続信頼性のいずれもが、本発明の半導体素子の製造方法により得られた実装体よりも劣っていた。 On the other hand, the mounting body obtained by the semiconductor element manufacturing method of Comparative Examples 1 to 23 has a bump evaluation, adhesiveness, and connection reliability that are all obtained by the semiconductor element manufacturing method of the present invention. Was inferior.
本発明の半導体素子の実装方法は、バンプの潰れすぎによる導通不良〔ショート（短絡）〕を防ぎつつ、接着性が良好なため、バンプのピッチが狭ピッチの半導体素子の実装に好適に使用できる。 The method for mounting a semiconductor element according to the present invention can be suitably used for mounting a semiconductor element having a narrow pitch of bumps because it has good adhesiveness while preventing conduction failure (short circuit) due to excessive crushing of bumps. .
１ 半導体素子
２ バンプ
３ａ 未硬化の第一の絶縁性樹脂層
３ｂ 硬化した第一の絶縁性樹脂層
４ａ 未硬化の第二の絶縁性樹脂層
４ｂ 硬化した第二の絶縁性樹脂層
５ 基板
６ 電極
７ 押圧部材
DESCRIPTION OF
Claims (5)
電極を有する基板上に、前記基板の前記電極を有する面が前記第二の絶縁性樹脂層に対向するように前記積層物を配置する配置工程と、
前記半導体素子を加熱及び押圧し、前記第二の絶縁性樹脂層を硬化させるとともに、前記バンプと前記基板の前記電極とを電気的に接続する接続工程と、を含むことを特徴とする半導体素子の実装方法。 A laminate for producing a laminate in which a cured first insulating resin layer and an uncured second insulating resin layer are laminated in this order on the surface of the semiconductor element on which the bump is formed having the bump. Production process;
An arrangement step of arranging the laminate on a substrate having an electrode so that a surface of the substrate having the electrode faces the second insulating resin layer;
A step of heating and pressing the semiconductor element to cure the second insulating resin layer and electrically connecting the bump and the electrode of the substrate. How to implement
A mounting body obtained by the method for mounting a semiconductor element according to claim 1.
Priority Applications (3)
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| JP2010272226A JP2012124244A (en) | 2010-12-07 | 2010-12-07 | Mounting method of semiconductor element and mounting body |
| PCT/JP2011/075677 WO2012077447A1 (en) | 2010-12-07 | 2011-11-08 | Method for mounting semiconductor elements, and mounted body |
| TW100143300A TW201227855A (en) | 2010-12-07 | 2011-11-25 | Method for mounting semiconductor element, and mounted product |
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| JP2010272226A JP2012124244A (en) | 2010-12-07 | 2010-12-07 | Mounting method of semiconductor element and mounting body |
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| WO2015037632A1 (en) * | 2013-09-11 | 2015-03-19 | デクセリアルズ株式会社 | Underfill material and method for manufacturing semiconductor device using same |
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Also Published As
| Publication number | Publication date |
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| WO2012077447A1 (en) | 2012-06-14 |
| TW201227855A (en) | 2012-07-01 |
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