JP2012080110A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device obtained by applying a gettering method that is suitable for silicon on insulator (SOI).SOLUTION: A semiconductor device having an SOI structure including an embedded oxide film and a surface silicon layer on the embedded oxide film comprises a transistor including the surface silicon layer as an active layer on the embedded oxide film, and an element isolation insulating film. A capacitor is formed on the element isolation insulating film and a rare gas element or a metal element is included in the element isolation insulating film.

Description

  In particular, the present invention relates to a semiconductor device obtained by applying a gettering method for removing contaminants such as heavy metals from an active region of an element formed in SOI (silicon on insulator) and a method for manufacturing the same.

  A large scale integrated circuit (LSI) using a silicon single crystal substrate has been improved in various ways by increasing the operation speed. However, it is considered indispensable to reduce the parasitic capacitance in order to achieve further speedup. It has been. In order to reduce the parasitic capacitance, SOI that forms a silicon single crystal layer on an insulating layer is considered as one solution.

  As SOI, SIMOX (Separation by Implanted Oxygen), in which oxygen is ion-implanted into a silicon single crystal substrate to form a buried oxide film to form an SOI structure, bonded SOI, and the like are known.

  In SIMOX, oxygen ions are implanted into a silicon single crystal substrate by ion implantation, and then heat-treated at 1200 ° C. or higher to form a buried oxide film, thereby forming an SOI structure. Bonded SOI is a structure in which two silicon single crystal substrates are directly bonded to each other without using an adhesive.

  In element formation using SOI, mesa-type element isolation by simply etching the SOI layer and various methods for arranging contacts in the body region have been proposed as isolation methods between elements. From the viewpoint of consistency and reliability, a LOCOS (Local Oxidation of Silicon) method is often used.

Bonded SOI is an SOI structure in which two silicon single crystal substrates are directly bonded together without an adhesive. A first silicon single crystal substrate having an oxide film formed on the surface with a predetermined thickness is bonded to a non-oxidized second silicon single crystal substrate.
In order to obtain a sufficiently high adhesive strength, heat treatment in an oxygen atmosphere is required at 800 ° C. or higher, preferably 1100 ° C. for 2 hours. Then, the SOI structure is obtained by polishing the first silicon single crystal substrate to a predetermined thickness. Although the manufacturing method is slightly different, there is also a method in which hydrogen injection or a porous silicon layer is formed in a predetermined depth region of the first silicon substrate without polishing, and this is used as a release layer. On the other hand, SIMOX is an SOI structure in which oxygen is ion-implanted into a silicon single crystal substrate to form a buried oxide film. At this time, it is necessary to form the buried oxide film at a controlled depth with a thickness and quality that sufficiently satisfy the insulation isolation characteristics without destroying the crystal of the surface silicon layer.

  Also in SOI, the importance of gettering technology for removing contaminants such as heavy metals that reduce device yield is recognized. For example, in order to form SIMOX, a long ion implantation process or a heat treatment exceeding 1200 ° C. is required, and thus impurities such as iron, nickel, copper, and aluminum may diffuse into the surface silicon layer during the manufacturing process. It is a problem. In addition, the bonding SOI requires high-temperature heat treatment in order to bond by hydrogen bonding. There is a possibility that contaminants are taken in from the outside world during the manufacturing process and contaminate the active region of the device.

  Gettering technology forms strain and lattice defects outside the element formation region of a silicon single crystal substrate, and traps or fixes heavy metal and other impurities there by heat treatment, reducing element deterioration or characteristic defects due to contamination. It has been actively introduced as a means to do this. Gettering is an extrinsic effect that provides a gettering effect by applying physical or chemical action from the outside of the silicon single crystal substrate, and distortion of lattice defects involving oxygen generated inside the silicon single crystal substrate. It is roughly divided into intrinsic gettering using the venue.

  In the case of SOI, the presence of an oxide film under the silicon layer is a significant difference from a silicon single crystal substrate, and heavy metal impurities cannot be captured or fixed to the gettering site through the oxide film, or There is a concern that a sufficient gettering effect cannot be obtained.

  In general, the diffusion coefficient of heavy metal is much smaller in the oxide film than in the silicon single crystal. In SOI, since an oxide film exists between the element formation region and the substrate bulk or the back surface of the substrate, diffusion of contamination impurities is remarkably suppressed. Therefore, in SOI, a situation where it is extremely difficult to apply gettering technology occurs. An object of the present invention is to provide a semiconductor device obtained by applying a gettering method suitable for SOI and a manufacturing method thereof.

  In order to solve the above problems, the present invention is directed to injecting a rare gas element into a selected region of a surface silicon layer of a substrate having an SOI structure, and performing a heat treatment on the metal contained in the surface silicon layer in the selected region. It is characterized by gettering such contaminants.

As rare gas elements, helium (He), argon (Ar), neon (Ne)
, One or more selected from krypton (Kr) and xenon (Xe) are used. An ion implantation method or an ion doping method (referring to a method of implanting ions without mass separation) is adopted, and the dose is set to 1 × 10 ^{14 to} 5 × 10 ¹⁶ / cm ² to destroy the crystal structure of the implantation region. . One of the effects of injecting a rare gas element into the surface silicon layer is to form a dangling bond by the injection to distort the semiconductor film, and to inject the ions between the lattices of the semiconductor film. As a result of the lattice distortion, a strain field is formed and a gettering site is obtained. In particular, the latter effect is remarkably obtained when an element having a larger atomic radius than silicon, such as argon (Ar), krypton (Kr), and xenon (Xe) is used.

The temperature of the heat treatment is 450 to 1000 ° C., preferably 700 to 900 ° C. in an inert gas atmosphere. The rare gas element implanted into the silicon at a concentration of 1 × 10 ¹⁹ to 1 × 10 ²² / cm ² remains in the implanted region without being re-emitted to the outside even in this heat treatment temperature range, thereby inhibiting recrystallization. is doing. The metal impurity contained in the surface silicon layer moves to the rare gas injection region where the strain is accumulated, and high gettering efficiency is obtained.

Thereafter, when heat treatment is performed at 800 to 1150 ° C. in an oxidizing atmosphere, a silicon oxide film can be formed on the surface silicon layer. In the region where the rare gas is injected, the crystal structure is destroyed, oxygen is diffused quickly, and is easily oxidized. Oxidation in a water vapor atmosphere of 1 × 10 ⁶ to 1 × 10 ⁷ Pa (high-pressure oxidation) further promotes oxidation, and an oxidation reaction at a sufficient rate is obtained even at about 700 ° C.

  In order to form an element isolation structure by LOCOS, a silicon oxide film and a silicon nitride film are stacked on the surface silicon layer, and a rare gas element is injected in accordance with the opening. Thereafter, gettering and formation of a field oxide film may be performed by performing heat treatment at 800 to 1150 ° C. in an oxidizing atmosphere or heat treatment at 450 to 1000 ° C. in an inert gas atmosphere and 800 to 1150 ° C. in an oxidizing atmosphere. it can.

  Since the region where the rare gas element remains is formed in the formed field oxide film, the strain remains, and the metal element is concentrated in the region. It does not diffuse again into the surface silicon layer by the subsequent heat treatment.

  The rare gas element is formed by ion implantation or ion doping. This method has a difference in whether ionized elements are mass-separated or implanted without mass-separation, but in any case, there is no substitute for a method in which ions are accelerated by an electric field and implanted into the silicon layer. Although the depth at which the rare gas element is implanted is controlled by the acceleration voltage, the rare gas element may be distributed near the surface of the surface silicon layer, inside the surface silicon layer, and even in the buried oxide film.

  As described above, in the semiconductor device of the present invention, the rare gas element is injected into the element isolation region of the SOI, and the characteristics of the element are improved by concentrating the metal element therein. The depth to which the rare gas element is implanted can be gettered by injecting the surface silicon layer, or the surface silicon layer and the buried oxide film, or the thin film silicon layer, the buried oxide film, and the semiconductor under the buried silicon film. The same effect can be obtained even if a field oxide film is formed in this element isolation region and a LOCOS structure is formed.

As the rare gas element implanted by the ion implantation method or the ion doping method, one or more selected from helium, neon, argon, krypton, and xenon can be used. The concentration of the rare gas element to be injected is 10 ¹⁹ to 1 × 10 ²² / cm ³ .

  The rare gas element to be injected is intended to getter metal elements such as iron, nickel, copper, and aluminum that may exist in the element isolation region of the surface silicon layer. The SOI formed by the SIMOX method or the bonding method may be mixed with the metal element in the manufacturing process, but the intrinsic getter and the extrinsic getter in the prior art are effective because there is a buried oxide film. Does not work. On the other hand, the method of injecting a rare gas element into the element isolation region as in the present invention and gettering does not involve a buried oxide film, and can perform gettering very effectively.

  In order to perform such gettering, a method for manufacturing a semiconductor device of the present invention is characterized in that a rare gas element is injected into an element isolation region of SOI and a metal element is concentrated in the element isolation region by heat treatment. Yes. The depth at which the rare gas element is implanted is controlled by increasing or decreasing the acceleration voltage in the ion implantation method or the ion doping method, but the surface silicon layer, or the surface silicon layer and the buried oxide film, or the thin film silicon layer, and the buried Implanted into the oxide film and the underlying semiconductor.

  The temperature of the heat treatment for gettering can obtain a gettering effect at 400 to 800 ° C. because the thin film silicon layer into which the rare gas element is implanted becomes amorphous and strain is accumulated. The region into which the rare gas element is implanted is an element isolation region. When a LOCOS structure is formed, a field oxide film is formed, but the concentrated metal element is not re-diffused by the oxidation.

  By using the present invention, contaminants such as metals contained in SOI can be easily gettered. Although the gettering site remains in the element isolation insulating film, the metal elements concentrated there are not re-emitted, and the reliability of the manufactured element is not impaired. The gettering method of the present invention can be applied to the manufacturing process of either fully depleted or partially depleted MOS transistors.

8A and 8B illustrate a method for manufacturing a semiconductor device using the gettering method of the present invention. 10 is a cross-sectional view illustrating a manufacturing process of a MOSFET using a substrate having an SOI structure. FIG. 10 is a cross-sectional view illustrating a manufacturing process of a MOSFET using a substrate having an SOI structure. FIG. The top view of MOSFET. Sectional drawing explaining the manufacturing process of MOSFET by the salicide using the board | substrate of SOI structure. The figure explaining the structure of the heat processing apparatus for performing high pressure steam oxidation. 9 is a cross-sectional view illustrating a structure of a liquid crystal display device using a semiconductor substrate having an SOI structure. FIG. 6 illustrates a circuit diagram of a pixel provided with an SRAM. The figure explaining the structure of a three-plate projector. The figure explaining the form of the gettering site formed by inject | pouring a rare gas element. FIG. 11 illustrates an example of a semiconductor device.

  The SOI applied to the present invention is not particularly limited in its manufacturing method and structure. Typically, SIMOX, ELTRAN (registered trademark of Canon Inc.), UNIBOND (registered trademark of SIO Tech Silicon On Insulator Technologies, Inc.) and the like can be used.

FIG. 1A is a cross-sectional structure diagram of a substrate having an SOI structure including a thin film silicon layer 101, a buried oxide film 102, and a semiconductor 103. A silicon oxide film 104 and a silicon nitride film 105 are stacked on the thin film silicon layer 101, and a rare gas element is added to the element isolation region 106 formed in the opening by an ion implantation method or an ion doping method. The concentration of the rare gas element to be injected is 1 × 10 ¹⁹ to 1 × 10 ²² / cm ³ .

In the region of the surface silicon layer where the rare gas element is implanted, the crystal structure is disturbed by inserting the rare gas between the lattices of silicon, and strain accumulates accordingly. Then, metal elements such as iron, nickel, copper, and magnesium can be gettered by heat treatment at 400 to 800 ° C. in a nitrogen atmosphere.
That is, the region into which the rare gas element is implanted becomes a gettering site, and the metal element can be removed from the element formation region of the surface silicon layer.

  The position of the gettering site can be determined by the depth at which the rare gas element is implanted, and the gettering site may be formed only in the surface layer portion of the surface silicon layer 101 as shown in FIG. Alternatively, a rare gas element may be implanted into the surface silicon layer 101 and the buried oxide film 102 as shown in FIG. Further, as shown in FIG. 10C, a rare gas element may be implanted into the surface silicon layer 101, the buried oxide film 102, and the semiconductor substrate 103.

  Further, as shown in FIG. 1B, a LOCOS structure can be obtained by forming an element isolation insulating film (field oxide film) 107 by dry oxidation or steam oxidation. A rare gas element and a concentrated metal element remain in the element isolation insulating film 107, but they do not diffuse into the element formation region.

  A MOS transistor can be formed using the LOCOS structure thus formed. Since the gettering method of the present invention is not affected by the thickness of the surface silicon layer and the thickness of the buried oxide film, it can be applied to the manufacturing process of either a fully depleted or partially depleted MOS transistor. Further, as shown in FIGS. 1 and 10, since the gettering site formed by implanting a rare gas element remains in the element isolation region, the gettering may be performed at an arbitrary stage of the MOS transistor manufacturing process. it can.

  Embodiments of the present invention will be described below with reference to the drawings.

  In this embodiment, an example of a process for manufacturing a MOS transistor in an SOI using the present invention will be described with reference to FIGS. In FIG. 3A, first, an SOI structure substrate including a semiconductor substrate 303, a buried oxide film 302, and a surface silicon layer 301 is prepared. The SOI structure may be either a SIMOX method or a bonded SOI method. Here, a CMOS process based on a fully depleted SOI will be mainly described.

  On the surface silicon layer, a 50 nm silicon oxide film 304 is formed by a CVD method, and then a 150 nm silicon nitride film 305 is formed. Next, a photoresist mask 306 is formed by a light exposure process. The opening of the mask 306 is provided corresponding to the element isolation region, and the silicon nitride film and silicon oxide film in that portion are removed by dry etching.

Thereafter, as shown in FIG. 3B, argon is implanted as a rare gas element into the element isolation region with an acceleration voltage of 100 keV to an average concentration of 1 × 10 ²¹ / cm ³ by ion implantation or ion doping. Then, a rare gas addition region 307 is formed. Then, using a furnace annealing furnace, heat treatment is performed at 600 ° C. in a nitrogen atmosphere, and impurities such as metal elements are concentrated on the surface silicon layer in the rare gas addition region.

  As other heat treatment methods, an RTA method using a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, a high pressure mercury lamp, or the like is employed. When the RTA method is used, the lamp light source for heating is turned on for 1 to 60 seconds, preferably 30 to 60 seconds, and this is repeated 1 to 10 times, preferably 2 to 6 times. The emission intensity of the lamp light source is arbitrary, but the semiconductor film is instantaneously heated to 600 to 1000 ° C., preferably about 650 to 800 ° C.

  After removing the mask 306, as shown in FIG. 3C, oxidation is performed in saturated water vapor at 1000 ° C. to form an element isolation insulating film (field oxide film) 308, whereby a LOCOS structure can be obtained. A rare gas element and a concentrated metal element remain in the element isolation insulating film 107, but they do not diffuse into the element formation region.

  Next, as shown in FIG. 3D, after forming a mask 309, boron is added as an acceptor to a region where an n-channel MOS transistor is to be formed, so that a p-type semiconductor region 310 is formed.

  Thereafter, in order to control the threshold voltages of the PMOS and NMOS, an acceptor or a donor may be implanted into the surface silicon layer by an ion implantation method.

Then, a silicon oxide film 311 to be a gate insulating film is formed with a thickness of 7 nm by a thermal oxidation method. Subsequently, a polycrystalline silicon film for gate is formed with a thickness of 100 to 300 nm by a CVD method. The polycrystalline silicon film for the gate may be doped with phosphorus (P) at a concentration of about 10 ²¹ / cm ³ in advance in order to reduce the resistance, or may be concentrated after the polycrystalline silicon film is formed. An n-type impurity may be diffused. Here, in order to further reduce the resistance, a silicide film is formed with a thickness of 50 to 300 nm on the polycrystalline silicon film. As the silicide material, molybdenum silicide (MoSix), tungsten silicide (WSix), tantalum silicide (TaSix), titanium silicide (TiSix), or the like can be used. The silicide material may be formed according to a known method. Then, a resist pattern corresponding to the gate electrode is formed, and the gate electrode is formed by dry etching. As shown in FIG. 2E, a polycide gate made of polycrystalline silicon (312, 313) and silicide (314, 315) is formed as the gate electrode.

After forming the gate, an impurity region for forming the LDD is formed. Phosphorus (P) is ion-implanted into the element region for forming the NMOS, and boron (B) is ion-implanted into the region for forming the PMOS. The dose amount is 1 × 10 ¹³ / cm ² . As shown in FIG. 2E, a mask 316 is provided in the P-type MOSFET formation region and ion implantation is performed using the gate as a mask, whereby phosphorus (P) is added to the region where the n-type MOS is formed. Region 316 is formed. Further, after providing a mask 317 as shown in FIG. 3A, boron (B) is added to the p-type MOSFET region to form a p-type impurity region 318.

Thereafter, an insulating film such as a silicon oxide film or a silicon nitride film is formed on the entire surface by CVD, and this film is uniformly etched on the entire surface by anisotropic dry etching. As a result, as shown in FIG. 3B, the insulating film remains on the side wall of the gate, and sidewall spacers 319 and 320 are formed. Using this sidewall spacer as a mask, arsenic as a donor is ion-implanted into the n-type MOSFET region at a dose of 5 × 10 ¹⁵ / cm ² to form an n-type impurity region (source or drain region) 322. Further, as shown in FIG. 3C, boron (B) serving as an acceptor is ion-implanted into the p-type MOSFET region to form a p-type impurity region (source or drain region) 324.

  Then, the silicon oxide film remaining on the n-type impurity region (source or drain region) 320 and the p-type impurity region (source or drain region) 324 is removed by etching to form an interlayer insulating film 325 over the entire surface. The interlayer insulating film 325 is formed with a thickness of 100 to 200 nm using a silicon oxide film, a silicon oxynitride film, or the like.

  Thereafter, heat treatment is performed for activating the ion-implanted impurity element and restoring crystallinity. This heat treatment is performed by a furnace annealing furnace or rapid thermal annealing. The conditions for the heat treatment are arbitrary, but it is preferable to perform the annealing by 800 ° C. annealing using a furnace annealing furnace and 1000 ° C. instantaneous thermal annealing. The hydrogenation treatment is a treatment necessary for improving the characteristics, and can be performed by a method of performing a heat treatment in a hydrogen atmosphere or a method of performing a plasma treatment. By forming the interlayer insulating film with a silicon nitride film and performing heat treatment at 350 to 500 ° C., hydrogen in the silicon nitride film 320 is released. This hydrogen can be diffused into the semiconductor to be hydrogenated to compensate for defects.

Then, contact holes reaching the n-type impurity region (source or drain region) 320 and the p-type impurity region (source or drain region) 324 are formed in the first interlayer insulating film 325, and wirings 326 and 327 are formed. There is no limitation on the material used for wiring, but aluminum (Al), which is often used as a low-resistance material
It is good to use. Alternatively, a stacked structure of Al and titanium (Ti) may be used.

  The second interlayer insulating film 329 is formed with a silicon oxide film having a thickness of 1 to 2 μm by a CVD method, and then the surface is flattened by CMP (chemical mechanical polishing). After forming a contact hole in the second interlayer insulating film, a W plug electrode is formed, and a second electrode having a laminated structure of titanium nitride and aluminum is formed. FIG. 4 shows a top view of such an arrangement of n-type and p-type MOSFETs.

  In this way, the n-channel MOS transistor 331 and the p-channel MOS transistor 330 are completed. The structure of the transistor described in this embodiment is just an embodiment, and is not necessarily limited to the manufacturing process and structure illustrated in FIGS. A CMOS circuit, an NMOS circuit, or a PMOS circuit can be formed using these transistors. Various circuits such as a shift register, a buffer, sampling, a D / A converter, and a latch can be formed, and a semiconductor device such as a memory, a CPU, a gate array, and a RISC can be manufactured. Such a circuit can be operated at high speed by being composed of MOS, and can reduce power consumption by setting the drive voltage to 3 to 5V.

  In this embodiment, an embodiment of a MOS transistor manufacturing process using salicide technology will be described.

  In FIG. 5A, gate electrodes and sidewall spacers are formed in the same manner as in the first embodiment. The gate electrode is formed of polycrystalline silicon having a thickness of 200 nm, and n-type and p-type impurities are simultaneously added when forming the source and drain regions of the n-type and p-type MOSFETs to form a dual gate.

  After that, heat treatment for impurity diffusion, activation, and crystallinity recovery is performed. The heat treatment is performed by furnace annealing at 800 ° C. and instantaneous thermal annealing at 1000 ° C.

Next, salicide is formed using titanium silicide (TiSi ₂ ). A 20 nm titanium (Ti) film 340 is deposited, and the first RTA treatment is performed at 600 to 650 ° C. Thereafter, unreacted titanium is removed, and TiSi ₂ salicide films 343 to 346 are obtained by the _second RTA treatment at 850 ° C. The surface resistance of the salicide layer on the surface silicon layer is 10Ω / sq.

  The subsequent steps are performed in the same manner as in Example 1, and a p-type MOSFET and an n-type MOSFET can be manufactured.

The high-pressure steam heat treatment has a strong oxidizing power and can form an oxide film having a low defect density and a low fixed charge density even at a low temperature. When high-pressure steam oxidation is used for the oxidation treatment for forming the element isolation insulating film, the film becomes denser and an oxide film with low stress can be formed with a rare gas element remaining in the oxide film.
When silicon mixed with a rare gas element is oxidized, the rare gas element naturally remains in the oxide film, and an oxide film having many defects is formed in the oxide film. However, by heating in a steam atmosphere of 1 × 10 6 to 5 × 10 6 Pa, oxidation is promoted and an oxide film with few defects can be formed.

  FIG. 6 is a diagram illustrating the configuration of an apparatus for performing high-pressure steam oxidation. A heater 203 and a quartz reaction tube 202 are provided inside a pressure vessel 201 made of metal. The substrate 205 is placed in a quartz substrate cassette 204. The water vapor is supplied into the pressure vessel 201 by the pure water supply means 207, and the water vapor is supplied into the reaction tube by the evaporation means 206. The water vapor pressure increases until the saturated vapor pressure is reached in the reaction tube.

  The high-pressure steam heat treatment can be suitably used for forming an oxide film, but it is particularly preferable in the present invention to oxidize a surface silicon layer into which a rare gas element is ion-implanted.

A structure of a display device will be described with reference to FIG. 7 as an example of application using a semiconductor substrate having an SOI structure. FIG. 7 shows an example of a liquid crystal display device. A p-type MOSFET 402, an n-type MOSFET 403 of the drive circuit 400, and an n-type MOSFET 404 of the pixel portion 401 are manufactured in the same manner as in the first embodiment. The pixel electrode 408 forming the pixel is formed on the second interlayer insulating film 407 that has been subjected to planarization processing.
Reference numeral 409 denotes a metal layer formed at the same time as the pixel electrode, which is provided on the driving circuit 400 and serves as a light shielding layer. An auxiliary capacitor provided auxiliary to hold a voltage applied to the liquid crystal is formed by the electrode 406, the pixel electrode 408, and the second interlayer insulating film 407 formed on the element isolation insulating film.

  The opposite substrate 410 is formed of glass or quartz material, and the transparent electrode 411 is formed in the pixel portion. The alignment films 412 and 413 are formed and subjected to a rubbing process, and the opposite substrate 410 and the semiconductor substrate on which the MOSFET is formed are bonded together using a sealant. As the liquid crystal 414, a TN liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used.

  Although only the switching n-type MOSFET 404 is shown in the pixel portion 401, a p-type MOSFET may be formed in addition thereto, and a memory circuit (memory) may be formed in each pixel. FIG. 8 is a circuit diagram showing the configuration of a pixel provided with such a memory.

  FIG. 8 shows a circuit configuration for one pixel, which includes a liquid crystal switching element 705, a static memory (SRAM) 707, and a liquid crystal element 708. The switching element 705 and the SRAM 707 are formed of p-type and n-type MOSFETs.

The gate of the switching element 705 is connected to the scanning line 709. One of the source and drain regions of the switching element 705 is connected to the data line, and the other is connected to the input side of the SRAM 707. The SRAM 707 is composed of n-type and p-type MOSFETs, and the source side of the p-type MOSFET is a high potential power supply line (V _DD ).
Connected and V _DD is applied. The source side of the n-type MOSFET is connected to a low potential power supply line (V _SS ). A pair of p-type MOSFET and n-type MOSFET have their gates and drains connected to each other. The drains of one p-type and n-type MOSFET pair are kept at the same potential as the gates of the other p-type and n-type MOSFET pair. The output side of the SRAM is connected to the pixel electrode of the liquid crystal cell.

  The SRAM is designed to hold the input voltage Vin and output Vout that is an inverted signal thereof. The switching element 705 is turned on by the selection signal of the gate line, and the digital video signal of the data line is input to the SRAM. The digital video signal input to the SRAM is held until the next digital video is input. Then, the output signal of the SRAM is input to the pixel electrode of the liquid crystal cell. Thus, the liquid crystal is driven. By performing this for each pixel, an image can be displayed on the pixel portion. Thus, by providing the SRAM in the pixel, it becomes possible to store a digital video signal for each pixel and display an image with it. Since the digital video signal is stored for each pixel, for example, when displaying a still image, it is not necessary to repeat writing constantly, and power consumption can be reduced.

  Thus, a reflective liquid crystal display device can be formed using a semiconductor substrate having an SOI structure. The MOSFET process using a semiconductor substrate is advantageous for increasing the density of pixels because the LSI production technology can be applied as it is. Therefore, as an example of a suitable application, it can be used to form a light valve of a projector.

  FIG. 9 shows an example in which a reflective display device is applied to a three-plate projection device. In FIG. 9, light emitted from a light source 901 formed of a metal halide lamp, a halogen lamp, or the like is reflected by a polarization beam splitter 902 and proceeds to a cross dichroic mirror 903. The polarization beam splitter is an optical filter having a function of reflecting or transmitting light depending on the polarization direction of light. In this case, the light from the light source 901 is polarized so as to be reflected by the polarization beam splitter 902.

  The cross dichroic mirror 903 reflects red (R) component light in the direction of the liquid crystal display device 904 corresponding to red (R), and blue (B) component light in the direction of the liquid crystal display device 906 corresponding to blue (B). Is reflected. The green (G) component light is transmitted through the cross dichroic mirror 903 and is incident on the liquid crystal display device 905 corresponding to green (G). The liquid crystal display devices 904 to 906 corresponding to the respective colors align liquid crystal molecules so as to reflect the light without changing the polarization direction of the incident light when the pixel is in the off state. Further, when the pixel is in the on state, the alignment state of the liquid crystal layer is changed, and the polarization direction of incident light is changed accordingly.

  The light reflected by these liquid crystal display devices 904 to 906 is reflected again by the cross dichroic mirror 903 (green (G) component light is transmitted) and synthesized, and is incident on the polarization beam splitter 902 again. At this time, the light reflected by the pixel region in the on state is transmitted through the polarization beam splitter 902 because the polarization direction changes. On the other hand, the light reflected by the pixel region in the off state is reflected by the polarization beam splitter 902 because the polarization direction does not change. As described above, the pixel region arranged in a matrix in the pixel portion is turned on / off by the plurality of transistors, so that only the light reflected by the specific pixel region can be transmitted through the polarization beam splitter 902. This operation is common to the liquid crystal display devices 904 to 906.

  The light including the image information transmitted through the polarization beam splitter 902 as described above is displayed on the screen 908 by the optical system lens 907 configured by a projection lens or the like. Although a basic configuration is shown here, a projection type electro-optical device can be realized by applying such a principle.

  The configuration of the projector shown in FIG. 9 is an example and is not limited to the configuration of the optical system shown in FIG. Although the case where the present invention is applied to a liquid crystal display device is shown here, the present invention can be applied to any other integrated circuit such as a microprocessor, a memory, and an LSI using a gate array.

  Various semiconductor devices can be manufactured by using the present invention. Examples of such a semiconductor device include a goggle type display device (head mounted display), a portable information terminal (such as a mobile computer, a mobile phone, a portable game machine, or an electronic book). Specific examples of these semiconductor devices are shown in FIGS.

  FIG. 11A illustrates a mobile phone, which includes a main body 3401, an audio output portion 3402, an audio input portion 3403, a display portion 3404, operation switches 3405, and an antenna 3406. By using the present invention, the display portion 3404 and other integrated circuits can be manufactured.

  FIG. 11B shows a part (right side) of a head-mounted EL display, which includes a main body 3321, a signal cable 3322, a head fixing band 3323, a projection unit 3324, an optical system 3325, a display unit 3326, and the like. By using the present invention, the display portion 3326 and other integrated circuits can be manufactured.

  FIG. 11C illustrates a goggle type display device (head mounted display), which includes a main body 3341, a display portion 3342, and an arm portion 3343. By using the present invention, the display portion 3342 and other integrated circuits can be manufactured.

  As described above, the applicable range of the present invention is so wide that the present invention can be applied to various electronic devices. Further, the electronic apparatus of the present embodiment can be realized by using a configuration including any combination of the first to fourth embodiments.

Claims (7)

A semiconductor device having an SOI structure having a buried oxide film and a surface silicon layer on the buried oxide film,
A transistor having the surface silicon layer as an active layer on the buried oxide film, and an element isolation insulating film;
A first insulating film on the transistor and the element isolation insulating film;
On the first insulating film, there is provided a first conductive layer electrically connected to the transistor, and a second conductive layer overlapping the element isolation insulating film via the first insulating film. And
A second insulating film on the second conductive layer;
A third conductive layer electrically connected to the first conductive layer on the second insulating film;
The third conductive layer overlaps with the second conductive layer through the second insulating film,
A capacitor is formed by the second conductive layer, the second insulating film, and the third conductive layer.   2. The semiconductor device according to claim 1, wherein the element isolation insulating film contains a rare gas element or a metal element.   3. The semiconductor device according to claim 2, wherein the rare gas element is one or more selected from helium, neon, argon, krypton, and xenon. The semiconductor device according to claim 2, wherein the concentration of the rare gas element is 1 × 10 ¹⁹ to 1 × 10 ²² / cm ³ .   3. The semiconductor device according to claim 2, wherein the metal element includes one selected from iron, nickel, copper, and aluminum. In any one of Claims 1 thru | or 5,
A semiconductor device comprising a liquid crystal on the third conductive layer with an alignment film interposed therebetween. In any one of Claims 1 thru | or 5,
The semiconductor device is used for a display unit or an integrated circuit of a mobile phone or a head mounted EL display.

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