JP2012064754A - Nonvolatile semiconductor storage device manufacturing method and nonvolatile semiconductor storage device - Google Patents

Abstract

A method of manufacturing a nonvolatile semiconductor memory device capable of forming a sufficient amount of silicide while suppressing defects caused by a silicide process is provided.
A method of manufacturing a nonvolatile semiconductor memory device includes forming a memory cell transistor having a floating gate electrode, a first interelectrode insulating film on the floating gate electrode, and a control gate electrode on the first interelectrode insulating film. A field effect transistor having a lower gate electrode, a second interelectrode insulating film, and an upper gate electrode on the second interelectrode insulating film is formed. An interlayer insulating film is formed so that the upper surfaces of the control gate electrode and the upper gate electrode are exposed. Etchback is performed so that the upper surfaces of the control gate electrode and the upper gate electrode are lower than the upper surface of the interlayer insulating film. A first conductive film is formed on the entire surface of the control gate electrode, the upper gate electrode, and the interlayer insulating film. The first interlayer insulating film is etched back. A metal is deposited on the control gate electrode, the upper gate electrode, and the first conductive film to be silicided.
[Selection] Figure 28

Description

  Embodiments described herein relate to a method for manufacturing a nonvolatile semiconductor memory device and a nonvolatile semiconductor memory device.

  A NAND flash memory is known as a nonvolatile semiconductor memory device (EEPROM) that can be electrically rewritten and can be highly integrated. In a NAND flash memory, a plurality of memory cells are connected in series so that adjacent memory cells share a source / drain region to constitute a NAND cell unit. Both ends of the NAND cell unit are connected to a bit line and a source line via a select gate transistor, respectively. With such a NAND cell unit configuration, the unit cell area is smaller than that of the NOR type and large capacity storage is possible.

  A peripheral circuit for controlling the operation of the NAND flash memory is provided around the memory cell area for storing information. The field effect transistor formed in the peripheral circuit region is formed by the same process as that of the memory cell transistor and the select gate transistor. In order to improve the performance of the memory cell transistor and the field effect transistor in the peripheral circuit region, a structure in which the gate electrode is silicided is known.

  In the silicide process performed in the memory cell region and the peripheral circuit region of the nonvolatile semiconductor memory device, when a sufficient amount of silicide is formed in the polysilicon, the gate electrode expands. For example, when polysilicon is converted into mono-nickel silicide (NiSi), the volume expands about 1.2 times. In particular, when silicide expands in the memory cell region, the distance between adjacent gate electrodes becomes narrow, and the performance of the memory cell transistor may deteriorate, such as an increase in leakage current between the gate electrodes and deterioration in breakdown voltage. Further, when the supply amount of the metal film is reduced in order to prevent the polysilicon from expanding due to the silicide process, a sufficient amount of silicide is not formed in the memory cell region and the peripheral circuit region, and the resistance of the wiring may not be lowered. Therefore, in the silicide process of the nonvolatile semiconductor memory device, it is required to form a sufficient amount of silicide while ensuring a space between adjacent gate electrodes.

JP 2009-302502 A

  An object of the present invention is to provide a method for manufacturing a nonvolatile semiconductor memory device and a nonvolatile semiconductor memory device capable of forming a sufficient amount of silicide while suppressing problems caused by the silicide process.

  A method of manufacturing a nonvolatile semiconductor memory device according to one embodiment includes a floating gate electrode in a memory cell region on a semiconductor substrate, a first interelectrode insulating film on the floating gate electrode, and a first interelectrode insulating film A memory cell transistor having a control gate electrode, a lower gate electrode in the peripheral circuit region on the semiconductor substrate, a second interelectrode insulating film including an opening, and an upper gate on the second interelectrode insulating film A field effect transistor having an electrode is formed. An interlayer insulating film is formed on the semiconductor substrate so that the upper surfaces of the control gate electrode and the upper gate electrode are exposed. Etchback is performed so that the upper surfaces of the control gate electrode and the upper gate electrode are lower than the upper surface of the interlayer insulating film. A first conductive film is formed on the entire surface of the control gate electrode, the upper gate electrode, and the interlayer insulating film. The first interlayer insulating film is etched back so that the first conductive film remains on the sidewalls of the interlayer insulating film on the control gate electrode and the upper gate electrode. A metal is deposited on the control gate electrode, the upper gate electrode, and the first conductive film to be silicided.

1 is a diagram showing a memory cell region and a peripheral circuit region of a nonvolatile semiconductor memory device according to a first embodiment. 1 is an equivalent circuit diagram showing a memory cell array of a nonvolatile semiconductor memory device according to a first embodiment. 1 is a layout diagram of a memory cell array of a nonvolatile semiconductor memory device according to a first embodiment. 3 is a layout diagram of a part of a peripheral circuit region of the nonvolatile semiconductor memory device according to the first embodiment. FIG. 1 is a cross-sectional view of a memory cell array of a nonvolatile semiconductor memory device according to a first embodiment. 1 is a cross-sectional view of a memory cell array of a nonvolatile semiconductor memory device according to a first embodiment. 1 is a partial cross-sectional view of a peripheral circuit region of a nonvolatile semiconductor memory device according to a first embodiment. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device of a comparative example. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device of a comparative example. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device of a comparative example. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 3rd Embodiment. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 3rd Embodiment. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 3rd Embodiment. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 3rd Embodiment. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device based on the other example of 3rd Embodiment. It is sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device based on the other example of 3rd Embodiment. It is sectional drawing which shows the manufacturing method of a non-volatile semiconductor memory device. It is sectional drawing which shows the manufacturing method of a non-volatile semiconductor memory device. It is sectional drawing which shows the manufacturing method of a non-volatile semiconductor memory device.

  Next, embodiments of the present invention will be described in detail with reference to the drawings. In the embodiment, a NAND flash memory will be described as an example. However, the present invention is not limited to this, and can be applied to other semiconductor memory devices having a so-called floating gate structure. In the description of the drawings in the following embodiments, portions having the same configuration are denoted by the same reference numerals and description thereof is omitted. The drawings are schematic, and the relationship between the thickness of each film and the planar dimensions, the ratio of the thickness of each layer, and the like are different from those of an actual nonvolatile semiconductor memory device.

(First embodiment)
[Configuration of Nonvolatile Semiconductor Memory Device According to First Embodiment]
Hereinafter, the configuration of the nonvolatile semiconductor memory device according to the first embodiment of the present invention will be described with reference to FIGS. First, the configuration of the NAND flash memory according to the present embodiment will be described.

  FIG. 1 is a block diagram showing the entire nonvolatile semiconductor memory device. As shown in FIG. 1, the nonvolatile semiconductor memory device is used for controlling a memory cell region 100 used for storing information and each operation of writing, erasing, and reading information on the memory cell region 100. Peripheral circuit region 200 to be provided. A memory cell array described later is formed in the memory cell region 100. In the peripheral circuit region 200, a row decoder, a column decoder, a voltage generation circuit, an interface for transmitting and receiving various commands, addresses, and data are formed.

  FIG. 2A is an equivalent circuit diagram showing a part of the memory cell array formed in the memory cell region 100 of the NAND flash memory. The NAND cell unit 1 of the NAND flash memory includes two select gate transistors ST1, ST2 and a plurality of memory cell transistors Mn (n is an integer from 0 to 15) connected in series between the select gate transistors ST1, ST2. The same shall apply hereinafter. In the NAND cell unit 1, a plurality of memory cell transistors Mn are formed by sharing adjacent source / drain regions. The memory cell array is configured by providing NAND cell units 1 in a matrix.

  The control gate electrodes of the memory cell transistors Mn arranged in the X direction (corresponding to the gate width direction) in FIG. 2A are commonly connected by a word line WLn. Further, the gate electrodes of the selection gate transistors ST1 arranged in the X direction in FIG. 2A are commonly connected by a selection gate line S1, and the gate electrodes of the selection gate transistors ST2 are commonly connected by a selection gate line S2. A bit line contact BLC is connected to the drain region of the select gate transistor ST1. This bit line contact BLC is connected to a bit line BL extending in the Y direction (corresponding to the gate length direction) orthogonal to the X direction in FIG. 2A. The select gate transistor ST2 is connected to a source line SL extending in the X direction in FIG. 2A via a source region.

  The memory cell transistor Mn has an n-type source / drain region formed in a p-type well of a silicon substrate, and has a stacked gate structure having a floating gate electrode as a charge storage layer and a control gate electrode. The NAND flash memory stores 1-bit or multi-bit data by changing the threshold voltage of the memory cell transistor Mn by changing the charge amount held in the floating gate electrode by the write operation and the erase operation. . In the NAND flash memory, a set of a plurality of NAND cell units 1 sharing a word line WL constitutes a block. Data erasure in the NAND flash memory is executed in units of blocks.

  FIG. 2B is a layout diagram of a part of the memory cell array formed in the memory cell region 100 of the NAND flash memory. FIG. 3 is a layout diagram of a field effect transistor formed in the peripheral circuit region 200 of the NAND flash memory.

  As shown in FIG. 2B, a plurality of element isolation regions 4 having an STI (Shallow Trench Isolation) structure extending along the Y direction in FIG. 2B are formed on the silicon substrate (semiconductor substrate) at predetermined intervals in the X direction. . Thereby, the element region 5 is formed separately in the X direction in FIG. 2B. Further, the word lines WLn of the memory cell transistors Mn extending along the X direction in FIG. 2B are formed at a predetermined interval in the Y direction. On the element region 5 intersecting the word line WLn, the word line WLn becomes a part of the gate electrode MGn of the memory cell transistor Mn. Further, the selection gate line S1 of the selection gate transistor ST1 is formed so as to extend along the X direction in FIG. 2B. On the element region 5 intersecting with the selection gate line S1, the selection gate line S1 becomes a part of the gate electrode SG1 of the selection gate transistor ST1. Bit line contacts BLC are respectively formed in the element regions 5 between the adjacent select gate lines S1. This bit line contact BLC is connected to a bit line BL (not shown) extending in the Y direction in FIG. 2B. Further, the selection gate line S2 of the selection gate transistor ST2 is formed so as to extend along the X direction in FIG. 2B. On the element region 5 intersecting with the selection gate line S2, the selection gate line S2 becomes a part of the gate electrode SG2 of the selection gate transistor ST2. Source line contacts SLC are respectively formed in the element regions 5 between the adjacent select gate lines S2. This source line contact SLC is connected to a source line SL (not shown) extending in the X direction in FIG. 2B.

  Next, the structure of the field effect transistor Tr formed in the peripheral circuit region 200 will be described. As shown in FIG. 3, the field effect transistor Tr formed in the peripheral circuit region 200 is provided on the element region 6 left on the silicon substrate (semiconductor substrate) in a rectangular shape. An element isolation region 4 is formed so as to surround the element region 6. In each element region 6, a gate electrode 7 is formed across the element region 6, and source / drain regions 8 formed by diffusing impurities are provided on both sides thereof. Contact plugs 9 are formed in the source / drain regions 8.

  4 to 6 are cross-sectional views taken along lines A-A ', B-B', and C-C 'shown in FIGS. 2B and 3, respectively. FIG. 4 is a cross-sectional view of a part of the memory cell array of the NAND flash memory along the X direction of FIG. 2B. FIG. 5 is a cross-sectional view of a part of the memory cell array of the NAND flash memory along the Y direction of FIG. 2B. FIG. 6 is a cross-sectional view of the field effect transistor Tr formed in the peripheral circuit region 200 of the NAND flash memory. Note that the length of the polycrystalline silicon film 13 of the memory cell transistor Mn in the BB ′ line direction is the gate length of the memory cell transistor, and the length of the polycrystalline silicon 13 of the field effect transistor Tr in the CC ′ line direction is. This is referred to as the gate length of the field effect transistor.

  As shown in FIG. 4, a p-type well 3 is formed in the memory cell region 100 on the silicon substrate S. Trenches T are formed in the p-type well 3 at equal intervals, and element isolation insulating films 11 are embedded in the trenches T. The region where the element isolation insulating film 11 is embedded becomes the element isolation region 4 described above. A memory cell transistor Mn is formed on the p-type well 3 sandwiched between the element isolation insulating films 11. That is, the p-type well 3 sandwiched between the element isolation insulating films 11 functions as an element region 5 in which the memory cell transistor Mn, the select gate transistor ST1, and the like are formed.

As shown in FIGS. 4 and 5, a tunnel insulating film 12 is formed on the p-type well 3. Through the tunnel insulating film 12, the gate electrode MGn of the memory cell transistor Mn and the gate electrode SG1 of the selection gate transistor ST1 are formed. The gate electrodes MGn and SG1 have a structure in which a polycrystalline silicon film 13 functioning as a floating gate electrode, an interelectrode insulating film 14, and polycrystalline silicon films 15A and 15B functioning as control gate electrodes are sequentially stacked. . The polycrystalline silicon films 15A and 15B extend with the direction perpendicular to the plane of FIG. 5 as the longitudinal direction to form the word line WL. On the other hand, the polycrystalline silicon film 13 is insulated and isolated for each memory cell transistor Mn. As the interelectrode insulating film 14, an ONO structure composed of a silicon oxide film-silicon nitride film-silicon oxide film, a NONON structure in which the silicon nitride film is further sandwiched, or the like is used. Furthermore, in order to increase the coupling ratio of the memory cell transistor Mn, a high dielectric constant material such as aluminum oxide (Al ₂ O ₃ ) or hafnium silicate (HfSiO) can be included.

  As shown in FIG. 5, an opening 17 is formed in the interelectrode insulating film 14 of the gate electrode SG1 of the selection gate transistor ST1, and a polycrystalline silicon film 15B is embedded in the opening 17. The polycrystalline silicon film 13 and the polycrystalline silicon films 15A and 15B are electrically connected through the opening 17. Impurity diffusion regions 18 serving as source / drain regions are formed in the surface layer (surface) of the p-type well 3 between the gate electrodes MGn and between the gate electrodes MG15-SG1. Impurity diffusion region 18 is formed such that adjacent memory cell transistors Mn share a source / drain region. A high concentration impurity diffusion region 19 is formed in the surface layer of the silicon substrate S between the gate electrodes SG1 to SG1. The source / drain region between the gate electrodes SG1 to SG1 may have an LDD (Lightly Doped Drain) structure including not only the high concentration impurity diffusion region 19 but also a low concentration and shallow impurity diffusion region.

  A silicon oxide film 21 that functions as an interlayer insulating film is formed between each gate electrode MGn and between the gate electrode MG15 and the gate electrode SG1, for example, by LP-CVD (Low Pressure Chemical Vapor Deposition). These silicon oxide films 21 are formed on the silicon substrate S via the tunnel insulating film 12, and the upper surfaces thereof are planarized by using, for example, CMP (Chemical Mechanical Polishing).

  A contact hole 27 reaching the surface of the silicon substrate S is formed in the silicon oxide film 21 between the gate electrodes SG1 to SG1, as shown in FIG. The contact hole 27 is formed so as to penetrate the silicon oxide film 21 and the tunnel insulating film 12 and expose the surface of the impurity diffusion region 19. A contact plug 28 embedded with a conductor is formed in the contact hole 27 and is electrically connected to the impurity diffusion region 19. The contact plug 28 functions as the bit line contact BLC shown in FIG. 2B. A bit line BL made of, for example, copper (Cu) or aluminum (Al) is formed on the contact plug 28. Although only the contact portion on the bit line side is shown in FIG. 5, the contact portion on the source line side is also connected to the source line SL in the same configuration. A silicon oxide film 22 that functions as a passivation film is deposited on the bit line BL.

  As shown in FIG. 6, a gate insulating film 29 is formed on the p-type well 3 in the peripheral circuit region 200. A gate electrode PG of the field effect transistor Tr is formed through the gate insulating film 29. The thickness of the gate insulating film 29 is larger than the thickness of the tunnel insulating film 12 formed in the memory cell region 100. The gate electrode PG has a structure in which a polycrystalline silicon film 13, functioning as a lower gate electrode, an interelectrode insulating film 14, and polycrystalline silicon films 15A, 15B functioning as upper gate electrodes are sequentially stacked. As the interelectrode insulating film 14, an ONO structure composed of a silicon oxide film-silicon nitride film-silicon oxide film, a NONON structure in which the silicon nitride film is further sandwiched, or the like is used.

  An opening 17 is also formed in the interelectrode insulating film 14 of the gate electrode PG of the field effect transistor Tr, and the polycrystalline silicon film 15B is embedded in the opening 17. The polycrystalline silicon film 13 and the polycrystalline silicon films 15A and 15B are electrically connected through the opening 17. On the surface layer (surface) of the p-type well 3 on both sides of the gate electrode PG, impurity diffusion regions 30 to be the source / drain regions 8 are formed. The impurity diffusion region 30 may have an LDD structure. A silicon oxide film 21 functioning as an interlayer insulating film is formed so as to embed the gate electrode PG, and the upper surface thereof is planarized using, for example, CMP (Chemical Mechanical Polishing).

  A contact hole 27 reaching the surface of the p-type well 3 is formed on the impurity diffusion region 30 as shown in FIG. The contact hole 27 is formed so as to penetrate the silicon oxide film 21 and the gate insulating film 29 and expose the surface of the impurity diffusion region 30. A contact plug 28 embedded with a conductor is formed inside the contact hole 27 and is electrically connected to the impurity diffusion region 30. The contact plug 28 functions as the contact plug 9 shown in FIG. A connection wiring 31 made of, for example, copper (Cu) or aluminum (Al) is formed on the contact plug 28. A silicon oxide film 22 that functions as a passivation film is deposited on the connection wiring 31.

  In the nonvolatile semiconductor memory device of the above-described embodiment, the polysilicon films 15A and 15B in the memory cell region 100 and the peripheral circuit region 200 are partly silicided. Metals such as nickel (Ni), tungsten (W), titanium (Ti), cobalt (Co), and molybdenum (Mo) are used for silicidation of the polycrystalline silicon films 15A and 15B. As shown in FIGS. 4 to 6, in the nonvolatile semiconductor memory device of this embodiment, a sufficient amount of silicide is formed in the gate electrodes MG and PG in the memory cell region 100 and the peripheral circuit region 200. . On the other hand, in the memory cell region 100 and the peripheral circuit region 200, the gate electrodes MG and PG are formed in a desired shape without expanding. In the following method for manufacturing a nonvolatile semiconductor memory device, a method for forming such a silicide will be described.

[Method of Manufacturing Nonvolatile Semiconductor Memory Device According to First Embodiment]
Next, a method for manufacturing the nonvolatile semiconductor memory device of this embodiment will be described with reference to FIGS. 7 to 17 are cross-sectional views of manufacturing steps of the memory cell transistor Mn formed in the memory cell region 100 and the field effect transistor Tr formed in the peripheral circuit region 200. 7 to 17 show the cross section taken along the line BB ′ shown in FIG. 2B and the cross section taken along the line CC ′ shown in FIG. 3. In order to simplify the description, in the cross-sectional view taken along the line BB ′, the selection gate transistor ST1 is omitted and only the portion of the memory cell Mn is shown.

As shown in FIG. 7, a stacked structure of gate electrodes MGn, SG, and PG is formed. First, ion implantation for forming the p-type well 3 is performed on the silicon substrate S. Thereafter, a tunnel insulating film 12 is formed on the p-type well 3 in the memory cell region 100 as shown in the cross section along the line BB ′. Further, as shown in the CC ′ line cross section, the gate insulating film 29 is formed on the p-type well 3 in the peripheral circuit region 200. Next, a polycrystalline silicon film 13 to be a floating gate electrode of the memory cell transistor Mn or a lower gate electrode of the field effect transistor Tr is deposited through a subsequent process. Thereafter, the element isolation region 4 is formed using a known manufacturing method. Next, an ONO film (a laminated film of silicon oxide film-silicon nitride film-silicon oxide film) is formed as the interelectrode insulating film 14. Instead of the ONO film, a NONON film in which silicon nitride films are further added on both sides of the ONO film, or an insulating film containing aluminum oxide (Al ₂ O ₃ ), hafnium silicate (HfSiO), or the like, which is a high dielectric constant material, is used. You can also. Next, a polycrystalline silicon film 15A that becomes a part of the control gate electrode of the memory cell transistor Mn or the upper gate electrode of the field effect transistor Tr is formed through a subsequent process. Then, in the peripheral circuit region 200, an opening 17 is formed so as to penetrate the polycrystalline silicon film 15 </ b> A and the interelectrode insulating film 14 and reach the polycrystalline silicon film 13. Although not shown in the cross section along the line BB ′, the openings 17 of the select gate transistors ST1 and ST2 in the memory cell region 100 are also formed at the same time.

  Next, as shown in FIG. 8, a polycrystalline silicon film 15B is formed on the polycrystalline silicon film 15A so as to fill the opening 17. In the following description of the embodiment, the polycrystalline silicon films 15A and 15B will be described as the polycrystalline silicon film 15 together. In the field effect transistor Tr in the peripheral circuit region 200, the polycrystalline silicon film 15 that forms the upper gate electrode and the polycrystalline silicon film 13 that forms the lower gate electrode are electrically connected through the opening 17. . This polycrystalline silicon film 15 becomes the control gate electrode of the memory cell transistor Mn or the upper gate electrode of the field effect transistor Tr through the steps described later. Thereafter, a silicon nitride film 10 serving as an etching mask and a stopper for the planarization process is formed on the polycrystalline silicon film 15. Thereafter, patterning is performed using a photolithography method, and a resist R is formed on the silicon nitride film 10.

Next, as shown in FIG. 9, the silicon nitride film 10, the polycrystalline silicon film 15, the interelectrode insulating film 14, and the polycrystalline silicon in the memory cell region 100 and the peripheral circuit region 200 are formed by the RIE method using the resist R as a mask material. The film 13 is etched in order. Then, the impurity diffusion region 18 and the impurity diffusion region 30 are formed by ion implantation, and the memory cell transistor Mn and the field effect transistor Tr are formed. When the field effect transistor Tr is an NMOS transistor, for example, arsenic (As) or phosphorus (P) is ion-implanted, and when it is a PMOS transistor, for example, boron (B) or boron fluoride (BF ₂ ) is ion-implanted. A diffusion region 30 is formed.

  Next, as shown in FIG. 10, the silicon oxide film 21 is embedded between the patterned gate electrodes MGn of the memory cell region 100 and the gate electrodes PG of the peripheral circuit region 200. All of the gate electrodes MGn and PG are once buried by the silicon oxide film 21. Thereafter, planarization is performed by CMP using the silicon nitride film 10 on the gate electrodes MGn and PG as a stopper.

  Next, as shown in FIG. 11, etch back is performed by RIE to remove the silicon nitride film 10 on the gate electrodes MGn and PG. It is difficult to obtain a selection ratio between the silicon nitride film 10 used as a mask material at the time of patterning and the silicon oxide film 21. Therefore, the polysilicon film 15 and the silicon oxide film 21 after the silicon nitride film 10 is removed are etched back almost flatly.

  Next, as shown in FIG. 12, etch back is performed under conditions such that the polycrystalline silicon film 15 has a high selectivity with respect to the silicon oxide film 21. At this time, the polycrystalline silicon film 15 is formed so that the upper surface thereof is lower than the upper surface of the silicon oxide film 21. That is, the silicon oxide film 21 and the polycrystalline silicon film 15 are processed so as to have a concave shape.

  Next, as shown in FIG. 13, a metal film 20 is deposited so as to cover the polycrystalline silicon film 15 by sputtering or CVD. This metal film 20 is used for diffusing metal into the polycrystalline silicon film 15 in the next silicide process. As shown in the B-B ′ line cross section and the C-C ′ line cross section, the metal film 20 is provided in contact with the upper surface of the polycrystalline silicon film 15.

  Next, as shown in FIG. 14, the polycrystalline silicon film 15 is silicided by annealing. Here, in the memory cell region 100 and the peripheral circuit region 200, the polycrystalline silicon film 15 expands with silicidation. However, since the silicon oxide film 21 is formed beside the polycrystalline silicon film 15, it is possible to prevent the polycrystalline silicon film 15 from expanding in the gate length direction (the lateral direction in the drawing). Thereafter, hydrofluoric acid treatment is performed, and the metal film 20 is peeled off. In the above-described silicide process, the metal film 20 is formed only on the upper surface of the polycrystalline silicon film 15. In this state, the ratio of metal to the polycrystalline silicon film 15 is small, and it is difficult for the polycrystalline silicon film 15 to obtain a sufficient amount of silicide formation. Therefore, in the method for manufacturing the nonvolatile semiconductor memory device according to the present embodiment, the following steps are further performed.

  As shown in FIG. 15, a polycrystalline silicon film 16 is formed so as to cover the entire surfaces of the polycrystalline silicon film 15 and the silicon oxide film 21. The polycrystalline silicon film 16 becomes a part of the control gate electrode of the memory cell transistor Mn or the upper gate electrode of the field effect transistor Tr through a subsequent process.

  Next, as shown in FIG. 16, etch back is performed under conditions such that the polycrystalline silicon film 16 has a high selectivity with respect to the silicon oxide film 21. The upper surface of the polycrystalline silicon film 16 is formed to be lower than the upper surface of the silicon oxide film 21. That is, the silicon oxide film 21 and the polycrystalline silicon film 16 are processed so as to have a concave shape. At this time, in the peripheral circuit region 200, the polycrystalline silicon film 16 remains only on the sidewall of the silicon oxide film 21, and the upper surface of the central portion of the polycrystalline silicon film 15 is exposed.

  Next, as shown in FIG. 17, a metal film is deposited so as to cover the polycrystalline silicon film 16 by sputtering or CVD, and the polycrystalline silicon film 16 is silicided by annealing. Here, in the memory cell region 100 and the peripheral circuit region 200, the polycrystalline silicon film 16 expands with silicidation. However, since the silicon oxide film 21 is formed beside the polycrystalline silicon film 16, it is possible to prevent the polycrystalline silicon film 16 from expanding in the gate length direction (the lateral direction in the drawing). Thereafter, hydrofluoric acid treatment is performed, and the metal film 20 is peeled off.

  Here, in the memory cell region 100, although a part of the polycrystalline silicon film 16 is silicided, the silicide process is completed without reaching the polycrystalline silicon film 15. Therefore, in the gate electrode MG in the memory cell region 100, a polycrystalline silicon film and a silicide are alternately stacked in the control gate electrode. On the other hand, in the gate electrode PG in the peripheral circuit region 200, the polycrystalline silicon film 16 is completely silicided and integrated with the silicide portion of the polycrystalline silicon film 15. The silicide process may be performed so that the polysilicon film 16 is completely silicided by adjusting the film thickness of the metal film 20 and the polysilicon film 16, conditions for annealing, and the like. In this case, also in the memory cell region 100, the polycrystalline silicon film 16 is integrated with the silicide portion of the polycrystalline silicon film 15.

  Thereafter, the semiconductor device is manufactured by a known non-volatile semiconductor memory device manufacturing process. The memory cell region 100 and the peripheral circuit region 200 are embedded with the silicon oxide film 21. Then, the contact plug 27 is formed by opening the contact hole 27 and filling it with a conductor. An upper layer wiring is formed so as to connect to the contact plug 28, and a passivation film is deposited. Thereby, the nonvolatile semiconductor memory device of the present embodiment shown in FIGS. 4 to 6 can be manufactured.

[Effect of Manufacturing Method of Nonvolatile Semiconductor Memory Device According to First Embodiment]
The effects of the manufacturing method of the NAND flash memory according to the present embodiment will be described in comparison with the manufacturing method of the comparative example. 18 to 20 are diagrams for explaining a method of manufacturing a nonvolatile semiconductor memory device of a comparative example. In the method for manufacturing the nonvolatile semiconductor memory device of the comparative example, the same processes as those of the above-described embodiment are performed until the process of removing the silicon nitride film 10 shown in FIG. The manufacturing method of the nonvolatile semiconductor memory device of the comparative example is the first embodiment in that the silicon oxide film 21 is etched back under the condition that the polycrystalline silicon film 15 has a high selection ratio. This is different from the manufacturing method of the nonvolatile semiconductor memory device.

  FIG. 18 is a diagram showing a state in which etch back is performed by the method for manufacturing the nonvolatile semiconductor memory device of the comparative example. As shown in FIG. 18, in the manufacturing method of the nonvolatile semiconductor memory device of the comparative example, the upper surface of the silicon oxide film 21 is formed to be lower than the upper surface of the polycrystalline silicon film 15. That is, it differs from FIG. 12 in that the silicon oxide film 21 and the polycrystalline silicon film 15 are processed so as to have a convex shape.

  Next, as shown in FIG. 19, a metal film 20 is deposited so as to cover the polycrystalline silicon film 15 by sputtering or CVD. This metal film 20 is used for diffusing metal into the polycrystalline silicon film 15 in the next silicide process. As shown in the B-B ′ line cross section and the C-C ′ line cross section, the metal film 20 in the memory cell region 100 is provided in contact with the upper surface and part of the side surface of the polycrystalline silicon film 15.

  Next, as shown in FIG. 20, the polycrystalline silicon film 15 is silicided by annealing. Thereafter, hydrofluoric acid treatment is performed, and the metal film 20 is peeled off. Here, in the memory cell region 100 and the peripheral circuit region 200, the metal film 20 is in contact with the upper surface and the side surface of the polycrystalline silicon film 15, and metal atoms diffuse from the respective surfaces. Since there is a large proportion of metal in contact with the polycrystalline silicon film 15, the amount of silicide extending to the polycrystalline silicon film 15 is large, and silicide is sufficiently formed in the polycrystalline silicon film 15.

  However, in the memory cell region 100 and the peripheral circuit region 200, the polycrystalline silicon film 15 expands with silicidation. In the case of the manufacturing method of the comparative example, the silicon oxide film 21 is not formed beside the polycrystalline silicon film 15. Therefore, the polycrystalline silicon film 15 expands in the gate length direction (lateral direction in the drawing). In particular, in the memory cell region 100, when the gate electrode MG expands, the distance between adjacent gate electrodes is narrowed, leading to a decrease in the performance of the memory cell transistor, such as a deterioration in inter-gate breakdown voltage. As described above, in the silicide process of the nonvolatile semiconductor memory device of the comparative example, even if sufficient silicide can be formed by increasing the contact area between the metal film 20 and the polycrystalline silicon film 15, the silicidation proceeds excessively. The gate electrode expands.

  In contrast, in the manufacturing method of the present embodiment, the silicide process is performed in a state where the upper surface of the polycrystalline silicon film 15 is lower than the upper surface of the silicon oxide film 21. The silicon oxide film 21 does not expand even if the polycrystalline silicon film 15 is silicided, and the polycrystalline silicon film 15 having a desired shape can be maintained. In the silicide process of the manufacturing method of the present embodiment, in addition to the polycrystalline silicon film 15, a polycrystalline silicon film 16 is deposited to perform silicidation. By the silicidation twice, silicide is sufficiently formed in the gate electrodes MG and PG in the memory cell region 100 and the peripheral circuit region 200, and the resistance is reduced. By using the method for manufacturing the nonvolatile semiconductor memory device of this embodiment, a sufficient amount of silicide can be formed while suppressing the expansion of the gate electrodes MG and PG, and the memory cell transistor Mn and the field effect transistor can be formed. The operating characteristics of Tr can be improved.

(Second Embodiment)
[Method of Manufacturing Nonvolatile Semiconductor Memory Device According to Second Embodiment]
Next, a method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment of the present invention will be described with reference to FIGS. In the nonvolatile semiconductor memory device of the second embodiment, the shape of the polycrystalline silicon film 16 further deposited on the polycrystalline silicon film 15 is different from that of the first embodiment. Other configurations in the memory cell region 100 and the peripheral circuit region 200 of the nonvolatile semiconductor memory device according to the second embodiment are the same as those in the first embodiment shown in FIGS. The portions corresponding to those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  In the subsequent drawings, FIGS. 21 to 25 are cross-sectional views of the manufacturing process of the memory cell transistor Mn formed in the memory cell region 100 and the field effect transistor Tr formed in the peripheral circuit region 200. FIGS. 21 to 25 show the cross section taken along line B-B ′ shown in FIG. 2B and the cross section taken along line C-C ′ shown in FIG. 3. In order to simplify the description, the selection gate transistor ST1 is omitted in the cross-sectional view taken along the line B-B ′, and only the memory cell Mn portion is shown.

  The manufacturing method of this embodiment is the same as that of the first embodiment until the step of siliciding the polycrystalline silicon film 15 shown in FIG. Next, as shown in FIG. 21, a polycrystalline silicon film 16 is formed so as to cover the entire surfaces of the polycrystalline silicon film 15 and the silicon oxide film 21. The polycrystalline silicon film 16 becomes a part of the control gate electrode of the memory cell transistor Mn or the upper gate electrode of the field effect transistor Tr through a subsequent process. In the manufacturing method of the present embodiment, the polycrystalline silicon film 16 is deposited so as to completely fill the concave shapes of the polycrystalline silicon film 15 and the silicon oxide film 21. That is, the polycrystalline silicon film 16 is formed to be higher than the upper surface of the silicon oxide film 21 even at the lowest position on the upper surface.

  Next, as shown in FIG. 22, CMP is performed using the silicon oxide film 21 as a stopper, and the excess polycrystalline silicon film 16 is removed. As a result, the upper surfaces of the polycrystalline silicon film 16 and the silicon oxide film 21 become flat.

  Next, as shown in FIG. 23, etch back is performed under conditions such that the polycrystalline silicon film 16 has a high selection ratio with respect to the silicon oxide film 21. The upper surface of the polycrystalline silicon film 16 is formed to be lower than the upper surface of the silicon oxide film 21. That is, the silicon oxide film 21 and the polycrystalline silicon film 16 are processed so as to have a concave shape. Here, in the peripheral circuit region 200, the polycrystalline silicon film 16 is provided on the entire surface of the polycrystalline silicon film 15, and there is no step.

  Next, as shown in FIG. 24, a metal film 20 is deposited so as to cover the polycrystalline silicon film 16 by sputtering or CVD. The metal film 20 is used for diffusing metal into the polycrystalline silicon film 16 in the next silicide process. As shown in the B-B ′ line cross section and the C-C ′ line cross section, the metal film 20 is provided in contact with the upper surface of the polycrystalline silicon film 16.

  Next, as shown in FIG. 25, the polycrystalline silicon film 16 is silicided by annealing. Here, in the memory cell region 100 and the peripheral circuit region 200, the polycrystalline silicon film 16 expands with silicidation. However, since the silicon oxide film 21 is formed beside the polycrystalline silicon film 16, it is possible to prevent the polycrystalline silicon film 16 from expanding in the gate length direction (the lateral direction in the drawing). Thereafter, hydrofluoric acid treatment is performed, and the metal film 20 is peeled off. By adjusting the film thickness of the metal film 20 and the polycrystalline silicon film 16 and the annealing conditions, the polycrystalline silicon film 16 is completely silicided and integrated with the silicide portion of the polycrystalline silicon film 15. it can.

  Thereafter, the semiconductor device is manufactured by a known non-volatile semiconductor memory device manufacturing process. The memory cell region 100 and the peripheral circuit region 200 are embedded with the silicon oxide film 21. Then, the contact plug 27 is formed by opening the contact hole 27 and filling it with a conductor. An upper layer wiring is formed so as to connect to the contact plug 28, and a passivation film is deposited. Thereby, the nonvolatile semiconductor memory device of the present embodiment shown in FIGS. 4 to 6 can be manufactured.

[Effect of Manufacturing Method of Nonvolatile Semiconductor Memory Device According to Second Embodiment]
In the manufacturing method of the present embodiment, the polycrystalline silicon film 16 formed in the peripheral circuit region 200 is provided on the entire surface of the polycrystalline silicon film 15 and has no step. Therefore, the upper surface of the gate electrode PG in the peripheral circuit region after silicidation also remains flat. On the other hand, the gate electrode PG of the first embodiment shown in FIGS. 16 and 17 has a step due to the polycrystalline silicon film 16. According to the manufacturing method of the present embodiment, the upper surface of the silicided gate electrode can be formed flat, and the operating characteristics of the gate electrode can be improved.

  In the manufacturing method of the present embodiment, the polycrystalline silicon film 15 does not expand even if the polycrystalline silicon film 15 is silicided, and the polycrystalline silicon film 15 having a desired shape can be maintained. Then, silicidation is performed twice on the polycrystalline silicon film 15 and the polycrystalline silicon film 16. By the silicidation twice, silicide is sufficiently formed in the gate electrodes MG and PG in the memory cell region 100 and the peripheral circuit region 200, and the resistance is reduced. By using the method for manufacturing the nonvolatile semiconductor memory device of this embodiment, a sufficient amount of silicide can be formed while suppressing the expansion of the gate electrodes MG and PG, and the memory cell transistor Mn and the field effect transistor can be formed. The operating characteristics of Tr can be improved.

(Third embodiment)
[Method of Manufacturing Nonvolatile Semiconductor Memory Device According to Third Embodiment]
Next, a method for manufacturing the nonvolatile semiconductor memory device according to the third embodiment of the present invention will be described with reference to FIGS. The manufacturing method according to the third embodiment is different from the first and second embodiments in that the silicide process is performed only once. Other configurations in the memory cell region 100 and the peripheral circuit region 200 of the nonvolatile semiconductor memory device according to the third embodiment are the same as those in the first embodiment shown in FIGS. The portions corresponding to those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  In the subsequent drawings, FIGS. 26 to 29 are cross-sectional views of the manufacturing process of the memory cell transistor Mn formed in the memory cell region 100 and the field effect transistor Tr formed in the peripheral circuit region 200. 26 to 29 show a cross section taken along line B-B ′ shown in FIG. 2B and a cross section taken along line C-C ′ shown in FIG. 3. In order to simplify the description, the selection gate transistor ST1 is omitted in the cross-sectional view taken along the line B-B ′, and only the memory cell Mn portion is shown.

  The manufacturing method of this embodiment is the same as that of the first embodiment until the step of forming the polycrystalline silicon film 15 shown in FIG. At this time, the upper surface of the polycrystalline silicon film 15 is lower than the upper surface of the silicon oxide film 21, and the silicon oxide film 21 and the polycrystalline silicon film 15 have a concave shape.

  Next, as shown in FIG. 26, a polycrystalline silicon film 23 is formed so as to cover the entire surfaces of the polycrystalline silicon film 15 and the silicon oxide film 21. The polycrystalline silicon film 23 becomes a part of the control gate electrode of the memory cell transistor Mn or the upper gate electrode of the field effect transistor Tr through a subsequent process. In the manufacturing method of the present embodiment, the polycrystalline silicon film 23 is deposited in a thin film shape that does not bury the concave shape of the polycrystalline silicon film 15 and the silicon oxide film 21 formed in the memory cell region 100. That is, even if the polycrystalline silicon film 23 is deposited, the space between the silicon oxide films 21 is not buried, and the polycrystalline silicon film 23 is formed so that the recessed shapes of the polycrystalline silicon films 15 and 23 and the silicon oxide film 21 remain. To do.

  Next, as shown in FIG. 27, etch back is performed under conditions such that the polycrystalline silicon film 23 has a high selectivity with respect to the silicon oxide film 21. Here, the polycrystalline silicon film 23 on the upper surface of the polycrystalline silicon film 15 is removed, and the polycrystalline silicon film 15 is exposed. The polycrystalline silicon film 23 is provided so as to remain only on the side wall of the silicon oxide film 21.

  Next, as shown in FIG. 28, a metal film 20 is deposited so as to cover the polycrystalline silicon films 15 and 23 by sputtering or CVD. This metal film 20 is used for diffusing metal into the polycrystalline silicon films 15 and 23 in the next silicide process. As shown in the B-B ′ line cross section, the metal film 20 is provided in the memory cell region 100 so as to bury the concave-shaped polycrystalline silicon film 23.

  Next, as shown in FIG. 29, the polycrystalline silicon films 15 and 23 are silicided by annealing. Thereafter, hydrofluoric acid treatment is performed, and the metal film 20 is peeled off. Here, in the memory cell region 100 and the peripheral circuit region 200, the metal film 20 is in contact with the upper surface of the polycrystalline silicon film 15 and the side surface of the polycrystalline silicon film 23, and metal atoms diffuse from the respective surfaces. Since the ratio of the metal to the polycrystalline silicon films 15 and 23 is large, the amount of silicide extending to the polycrystalline silicon films 15 and 23 is large, and the silicide is sufficiently formed in the polycrystalline silicon films 15 and 23. Even if the concave shaped space is not buried when the metal film 20 is deposited by sputtering or CVD, the silicide expands inward of the concave shape when the silicide is formed, so that it can be filled after the silicide is formed.

  In the memory cell region 100 and the peripheral circuit region 200, the polycrystalline silicon films 15 and 23 expand with silicidation. Thus, the silicided polycrystalline silicon film 23 fills the space between the silicon oxide films 21 in the memory cell region 100. On the other hand, since the silicon oxide film 21 is formed, the polycrystalline silicon film 16 can be prevented from expanding in the gate length direction (the lateral direction in the drawing). By adjusting the thickness of the metal film 20 and the polycrystalline silicon film 23, the annealing conditions, etc., the silicided polycrystalline silicon film 23 completely embeds the silicon oxide film 21, and the silicide of the polycrystalline silicon film 15 is obtained. Can be integral with the part. As shown in FIG. 29, the thicknesses of the metal film 20 and the polycrystalline silicon film 23, the annealing conditions, etc. are set so that the upper surface of the silicided polycrystalline silicon film 15 is aligned with the upper surface of the silicon oxide film 21. Can be adjusted.

  Thereafter, the semiconductor device is manufactured by a known non-volatile semiconductor memory device manufacturing process. The memory cell region 100 and the peripheral circuit region 200 are embedded with the silicon oxide film 21. Then, the contact plug 27 is formed by opening the contact hole 27 and filling it with a conductor. An upper layer wiring is formed so as to connect to the contact plug 28, and a passivation film is deposited. Thereby, the nonvolatile semiconductor memory device of the present embodiment shown in FIGS. 4 to 6 can be manufactured.

[Effect of Manufacturing Method of Nonvolatile Semiconductor Memory Device According to Third Embodiment]
In the manufacturing method of the present embodiment, the step of siliciding the polycrystalline silicon films 15 and 23 is performed once. However, as shown in FIG. 28, the metal film 20 is in contact with the upper surface of the polycrystalline silicon film 15 and the side surface of the polycrystalline silicon film 23, and metal atoms diffuse from the respective surfaces. Even in one silicidation process, the gate electrodes MG and PG in the memory cell region 100 and the peripheral circuit region 200 are sufficiently silicided by controlling the etch back amount of the polycrystalline silicon film 15 in FIG. Is formed and the resistance is reduced.

  In the manufacturing method of the present embodiment, the polycrystalline silicon film 15 does not expand even if the polycrystalline silicon film 15 is silicided, and the polycrystalline silicon film 15 having a desired shape can be maintained. By using the method for manufacturing the nonvolatile semiconductor memory device of this embodiment, a sufficient amount of silicide can be formed while suppressing the expansion of the gate electrodes MG and PG, and the memory cell transistor Mn and the field effect transistor can be formed. The operating characteristics of Tr can be improved.

[Another Example of Nonvolatile Semiconductor Memory Device According to Third Embodiment]
In the manufacturing method of the third embodiment described above, the gate electrode PG in the peripheral circuit region 200 has a step due to the polycrystalline silicon film 16, as shown in FIG. That is, the silicided region of the polycrystalline silicon film 15 is formed such that the upper surface of the central portion is lower than the upper surface of the peripheral portion. On the other hand, as shown in FIG. 30, after the silicidation is performed, the polycrystalline silicon film 24 can be formed so as to cover the entire surfaces of the polycrystalline silicon film 15 and the silicon oxide film 21. The polycrystalline silicon film 24 also becomes a part of the control gate electrode of the memory cell transistor Mn or the upper gate electrode of the field effect transistor Tr through a subsequent process. In the manufacturing method of the present embodiment, the polycrystalline silicon film 24 is deposited so as to completely fill the concave shapes of the polycrystalline silicon film 15 and the silicon oxide film 21. That is, the polycrystalline silicon film 24 is formed to be higher than the upper surface of the silicon oxide film 21 even at the lowest position on the upper surface.

  Next, as shown in FIG. 31, CMP is performed using the silicon oxide film 21 as a stopper, and the excess polycrystalline silicon film 16 is removed. As a result, the upper surfaces of the polycrystalline silicon film 16 and the silicon oxide film 21 become flat.

  Thereafter, the semiconductor device is manufactured by a known non-volatile semiconductor memory device manufacturing process. The memory cell region 100 and the peripheral circuit region 200 are embedded with the silicon oxide film 21. Then, the contact plug 27 is formed by opening the contact hole 27 and filling it with a conductor. An upper layer wiring is formed so as to connect to the contact plug 28, and a passivation film is deposited. Thereby, the nonvolatile semiconductor memory device of the present embodiment shown in FIGS. 4 to 6 can be manufactured.

  According to the manufacturing method of this example, the upper surface of the silicided gate electrode can be formed flat, and the operating characteristics of the gate electrode can be improved. In addition, although the silicidation performed on the polycrystalline silicon films 15 and 23 is performed once, as described above, sufficient silicidation is formed in the gate electrodes MG and PG even if the silicidation is performed once. Resisted. By using the manufacturing method of the nonvolatile semiconductor memory device of this example, a sufficient amount of silicide can be formed while suppressing the expansion of the gate electrodes MG and PG, and the memory cell transistor Mn and the field effect transistor Tr can be formed. The operating characteristics can be improved.

  In the present embodiment, the polycrystalline silicon film 23 is formed so that the concave shapes of the polycrystalline silicon films 15 and 23 and the silicon oxide film 21 remain. At this time, the thickness of the polycrystalline silicon film 23 is adjusted as follows. 32 to 34 are views for explaining conditions for depositing the polycrystalline silicon film 23 in the memory cell region 100. FIG. As shown in FIG. 32, before the polycrystalline silicon film 23 is formed, the polycrystalline silicon film 15 and the silicon oxide film 21 have a concave shape. Here, the width X and the height Y of the concave shape are used. In this case, in order to leave the deposited polycrystalline silicon film 23 to have a concave shape, the thickness t of the polycrystalline silicon film 23 is smaller than half the length of the control gate electrode in the gate length direction (t <X / 2) Must be set (see FIG. 33). If the thickness t of the polycrystalline silicon film 23 is set in this way, a concave shape as indicated by the width s remains in the deposited polycrystalline silicon films 15 and 23 and the silicon oxide film 21. As shown in the first and second embodiments, when the polycrystalline silicon film 16 embeds a concave shape, the thickness t of the polycrystalline silicon film 16 may be set to t> X / 2. (See FIG. 34).

  In the third embodiment, the height Y can be adjusted when the polycrystalline silicon film 15 is etched back in order to form a desired silicide amount in one silicide process. If the height Y is set large, the contact area between the polycrystalline silicon film 23 and the metal film 20 formed on the side wall thereafter increases, and the amount of silicide formed increases. On the other hand, if the height Y is set small, the contact area between the polycrystalline silicon film 23 and the metal film 20 is reduced, and the amount of silicide formed is reduced.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to these, A various change, addition, a combination, etc. are possible in the range which does not deviate from the meaning of invention. For example, the number of memory cell transistors Mn connected in series between the select transistors ST1 and ST2 only needs to be plural, and the number is not limited to sixteen.

  DESCRIPTION OF SYMBOLS 1 ... NAND cell unit, 3 ... p-type well, 4 ... Element isolation region, 5, 6 ... Element region, 7 ... Gate electrode, 8 ... Source / drain region, 9 ...... Contact plug, 10 ... silicon nitride film, 11 ... element isolation insulating film, 12 ... tunnel insulating film, 13 ... polycrystalline silicon film, 14 ... interelectrode insulating film, 15 , 16 ... polycrystalline silicon film, 17 ... opening, 18, 19 ... impurity diffusion region, 20 ... metal film, 21, 22 ... silicon oxide film, 23, 24 ... many Crystal silicon film, 27 ... Contact hole, 28 ... Contact plug, 29 ... Gate insulating film, 30 ... Impurity diffusion region, 31 ... Connection wiring, Mn ... Memory cell transistor, ST・ ・Select gate transistors, WL ··· word lines, BL ··· bit line, SL ··· source line.

Claims (5)

Forming a memory cell transistor having a floating gate electrode in a memory cell region on a semiconductor substrate, a first interelectrode insulating film on the floating gate electrode, and a control gate electrode on the first interelectrode insulating film; Forming a field effect transistor having a lower gate electrode in a peripheral circuit region on the substrate, a second interelectrode insulating film including an opening, and an upper gate electrode on the second interelectrode insulating film;
Forming an interlayer insulating film on the semiconductor substrate such that the upper surfaces of the control gate electrode and the upper gate electrode are exposed;
Etching back so that the upper surfaces of the control gate electrode and the upper gate electrode are lower than the upper surface of the interlayer insulating film;
Forming a first conductive film on the entire surface of the control gate electrode, the upper gate electrode, and the interlayer insulating film;
Etching back the first interlayer insulating film such that the first conductive film remains on the sidewalls of the interlayer insulating film on the control gate electrode and the upper gate electrode;
A method of manufacturing a nonvolatile semiconductor memory device, comprising: depositing a metal on the control gate electrode, the upper gate electrode, and the first conductive film to form a silicide.   2. The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, further comprising a step of forming a second conductive film on the upper gate electrode after silicidation.   3. The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the film thickness of the first conductive film is smaller than a half of a length of the control gate electrode in a gate length direction. A semiconductor substrate;
A floating gate electrode formed on the semiconductor substrate via a first gate insulating film, a first inter-electrode insulating film disposed on the floating gate electrode, and the first inter-electrode insulating film A memory cell transistor having a control gate electrode disposed and formed in the memory cell region;
A lower gate electrode formed on the semiconductor substrate via a second gate insulating film; a second interelectrode insulating film disposed on the lower gate electrode and having an opening; and the second gate electrode A field effect transistor disposed on the interelectrode insulating film, having an upper gate electrode electrically connected to the lower gate electrode through the opening, and formed in a peripheral circuit region;
The control gate electrode and the upper gate electrode are partly silicided,
The non-volatile semiconductor memory device, wherein the silicided region of the upper gate electrode is formed such that the upper surface of the central portion is lower than the upper surface of the peripheral portion. Forming a memory cell transistor having a floating gate electrode in a memory cell region on a semiconductor substrate, a first interelectrode insulating film on the floating gate electrode, and a control gate electrode on the first interelectrode insulating film; Forming a field effect transistor having a lower gate electrode in a peripheral circuit region on the substrate, a second interelectrode insulating film including an opening, and an upper gate electrode on the second interelectrode insulating film;
Forming an interlayer insulating film on the semiconductor substrate such that the upper surfaces of the control gate electrode and the upper gate electrode are exposed;
Etching back so that the upper surfaces of the control gate electrode and the upper gate electrode are lower than the upper surface of the interlayer insulating film;
Depositing metal on the control gate electrode and the upper gate electrode for silicidation;
Forming a first conductive film on the entire surface of the control gate electrode, the upper gate electrode, and the interlayer insulating film;
Etching back the first conductive film such that the upper surface of the first conductive film is lower than the upper surface of the interlayer insulating film;
A method of manufacturing a nonvolatile semiconductor memory device, comprising: depositing a metal on the control gate electrode, the upper gate electrode, and the first conductive film to form a silicide.

Images