JP2012049911A - Photoelectric conversion device and imaging system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve high-speed reading while suppressing an increase in power consumption and a decrease in image quality with a conventional technique.
A signal processing unit including at least a plurality of A / D conversion units that are provided corresponding to columns of a pixel array and converts a signal output from a pixel into a digital signal, and two or more first outputs A first output section including a first output block provided corresponding to each of the first output terminals, one or more second output terminals, and a second output terminal A second output block provided corresponding to each of the first output terminals, wherein the number of the first output terminals is larger than the number of the second output terminals, and a plurality of columns adjacent to each other or every other column. The first output block outputs signals output from a plurality of signal processing units belonging to the same block, and the second output block includes a plurality of signal processing units belonging to different blocks. The signal output from is output.
[Selection] Figure 1

Description

  The present invention relates to a photoelectric conversion device, and more particularly to a photoelectric conversion device that outputs a digital signal.

  Various functions are required for photoelectric conversion devices used in digital cameras and the like.

  Patent Document 1 describes that the number of channels is changed according to an operation mode. Among these, it is described that the number of channels between the image processing unit including the sensor unit which is a semiconductor device and the image processing unit is changed. From the sensor unit, a certain number of channels are used regardless of the operation mode. A signal is output. Each channel is associated with every other pixel column. Pixels for one row of the sensor unit are selected at the same time, and thereafter, signals from a plurality of columns of pixels adjacent to each other are simultaneously transmitted to the subsequent stage via the predetermined number of channels.

  In Patent Document 2, the pixel unit is divided into a plurality of regions in units of a plurality of adjacent columns, and an output port is provided for each of the divided regions, thereby realizing high-speed reading, and only a part of the pixel unit. In the case of reading out signals from the above-mentioned area, a configuration is disclosed in which all signals are read out from a single output port.

JP 2008-283331 A JP 2003-179816 A

  However, in the configuration disclosed in Patent Document 1, since each channel of the sensor unit is associated with every other pixel column, a signal line extending over the entire area of the sensor unit is required. For this reason, the parasitic capacitance and the wiring resistance associated with the signal line are increased, and the power consumption is increased to drive this large load. Furthermore, if the load on the signal line is increased, the signal settling time becomes longer, making it difficult to cope with higher speeds.

  In the configuration disclosed in Patent Document 2, an analog signal is transmitted to each output port. The analog signal is attenuated by the capacity of the signal line. For this reason, in the configuration of Patent Document 2, if there is a variation in the capacity of the signal line between the divided regions, the signal level of the signal obtained from the output port also varies, and the image quality of the obtained image decreases.

  Furthermore, in the configuration disclosed in Patent Document 2, since signals are obtained from a single output port during random access, it is difficult to cope with high speed.

  In view of the above problems, an object of the present invention is to provide a photoelectric conversion device capable of increasing the reading speed while suppressing an increase in power consumption and a decrease in image quality.

  In order to achieve the above object, according to the present invention, a pixel array in which a plurality of pixels are arranged in a matrix and a signal output from the pixel provided corresponding to a column of the pixel array are converted into a digital signal. A plurality of first output blocks each having a signal processing unit including at least a plurality of A / D conversion units and two or more first output terminals provided corresponding to each of the first output terminals A first output section including one or more second output terminals, one or more second output blocks provided corresponding to each of the second output terminals, and the signal processing section And an output selection unit that selectively transmits a signal output from the first or second output unit, wherein the number of the first output terminals is larger than the number of the second output terminals. The signal processing units adjacent to each other or every other column are defined as blocks. The first output block outputs signals output from a plurality of the signal processing units belonging to the same block, and the second output block includes a plurality of the signal processing units belonging to different blocks. The photoelectric conversion device is characterized in that it outputs a signal output from.

  According to the present invention, it is possible to realize a photoelectric conversion device capable of increasing the reading speed while suppressing an increase in power consumption and a decrease in image quality.

1 is a block diagram illustrating a configuration example of a photoelectric conversion apparatus according to a first embodiment. FIG. 6 is a block diagram illustrating a configuration example of a photoelectric conversion apparatus according to the second embodiment. Timing chart showing state of output signal according to embodiment 2 FIG. 7 is a block diagram illustrating a configuration example of a photoelectric conversion apparatus according to the third embodiment. FIG. 6 is a block diagram illustrating a configuration example of a photoelectric conversion apparatus according to a fourth embodiment. Timing chart showing state of output signal according to embodiment 4 Another timing chart showing the state of the output signal according to the fourth embodiment FIG. 10 is a diagram illustrating a configuration example of a photoelectric conversion apparatus according to the fifth embodiment. FIG. 10 is a diagram illustrating another configuration example of the photoelectric conversion apparatus according to the fifth embodiment. FIG. 6 is a diagram illustrating an imaging surface according to a sixth embodiment. The figure which shows the mode of operation | movement of the photoelectric conversion apparatus which concerns on Example 7. FIG. The figure which shows the mode of operation | movement of the photoelectric conversion apparatus which concerns on Example 8. FIG. FIG. 9 is a block diagram illustrating a configuration example of a photoelectric conversion apparatus according to the ninth embodiment. FIG. 10 is a block diagram illustrating a configuration example of an imaging system according to the tenth embodiment.

Example 1
An embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram illustrating a configuration example of the imaging apparatus according to the present embodiment, which is formed on the same semiconductor substrate, for example.

  The photoelectric conversion device 1 includes a pixel array PA in which pixels 101 are arranged in a matrix. Here, pixels of N rows and M columns are provided. Pixels in the same column in the pixel array PA are connected to the signal processing unit 102 via a common signal line 104. The signal processing unit 102 includes at least an A / D conversion unit and outputs a digital signal. The row selection unit 103 supplies a signal for selecting a row of pixels that output signals to the signal line 104, so that the pixels 101 in the same row simultaneously output signals to the corresponding signal lines 104. The output selection unit 105 includes a switching unit 106 and transmits the digital signal output from the signal processing unit 102 to the first output unit 107 or the second output unit 109. The switching unit 106 is controlled by a signal input from a control unit (not shown). The first output unit 107 includes a plurality of first output blocks, and each output block is associated with three columns of signal processing units 102 adjacent to each other. Digital signals input from the signal processing unit 102 are sequentially output from the first output terminal 108. The second output unit 109 includes a plurality of second output blocks, and each output block is associated with six columns of signal processing units 102 adjacent to each other. Digital signals input from the signal processing unit 102 are sequentially output from the second output terminal 110. That is, with the signal processing units 102 of a plurality of columns as blocks, the first output unit outputs signals from the signal processing units 102 belonging to the same block from two or more output terminals 108, and the second output unit The signals from the signal processing units 102 belonging to different blocks are output from one or more output terminals 110. When the relationship between the first output unit 107 and the second output unit 109 is generalized, the first output unit 107 uses the signal processing unit 102 of S (S ≧ 2) columns as one block, and M / S units. A signal is output from the output terminal. On the other hand, the second output unit 109 outputs a signal from M / T output terminals, with the signal processing units 102 of T (T> 2) columns more than the first output unit 107 as one block. FIG. 1 shows a case where S = 3 and T = M / 2.

  The elements constituting the photoelectric conversion device 1 will be described in more detail. The pixel 101 photoelectrically converts incident light and outputs an electrical signal corresponding to the amount of incident light. The pixel 101 may be an amplifying pixel including an amplifying element such as a source follower circuit in the pixel, or may be a passive pixel that outputs charges generated by photoelectric conversion.

  In addition to the A / D conversion unit, the signal processing unit 102 may further include a correlated double sampling (CDS) circuit as a noise reduction circuit for reducing a noise component included in the signal output from the pixel 101. By performing A / D conversion on a signal with reduced noise, accuracy can be increased. Moreover, you may further provide the memory part which hold | maintains the digital data obtained by the A / D conversion part temporarily. The memory unit can be composed of, for example, an SRAM (Static Random Access Memory). In FIG. 1, in order to simplify the drawing, the output from the signal processing unit 102 is shown by a single line, but in actuality, n-bit digital data is output in parallel.

  The output selection unit 105 selectively transmits the digital signal output from the signal processing unit 102 to the first or second output unit. In FIG. 1, each signal processing unit 102 is provided with changeover switches 106-1 and 106-2, and either one is made conductive to transmit to one of the output units.

  Each of the first output blocks 107-1, 107-2,... Of the first output unit 107 has a parallel-serial conversion unit (hereinafter referred to as a P / S conversion unit). The n-bit parallel data input in this way is converted into serial data and output from the output terminal 108. The output terminal 108 may be a system that outputs voltage from a single terminal, or may be an LVDS (Low Voltage Differential Signaling) system that has two differential terminals. In addition, a column selection unit is provided to select which column of the three columns input in parallel is to be transmitted to the output terminal 108. The column selection unit can use a decoder or a shift register. As described above, the signal processing unit outputs the parallel data as a high speed, and the first output unit converts the serial data into the serial data, thereby suppressing an increase in the number of output terminals. Since the photoelectric conversion device formed over the semiconductor substrate is required to have a small area, it is effective to suppress an increase in the number of output terminals.

  When signals are output from the first output unit 107, a number of signals corresponding to the number of output blocks can be output in parallel. That is, taking the configuration of FIG. 1 as an example, signals in the first column of the signal processing units 102 associated with each output block are simultaneously output from the respective output terminals 108, and in each output block at the next timing. The signals in the second column are simultaneously output from the output terminal 108. In other words, when the entire pixel array is viewed, the signals in the columns 1, 2, 7,... Are output after the signals in the columns 2, 5, 8,. Is obtained. Therefore, a processing circuit (not shown) performs processing for rearranging the signal arrangement.

  Similar to the first output unit 107, each of the output blocks 109-1 and 109-2 of the second output unit 109 has a P / S conversion unit, and is input via the output selection unit 105. A configuration in which bit parallel data is converted into serial data and then output from the output terminal 110 can be taken. Similarly to the first output unit 107, a column selection unit is provided to select which column of the six columns input in parallel is to be transmitted to the output terminal 110. The column selection unit can use a decoder or a shift register.

  Even when a signal is output from the second output unit 109, the output terminal 110 outputs simultaneously the first, (M / 2) + 1st column, 2, (M / 2) + 2th column,... Therefore, the signal arrangement is rearranged in a processing circuit (not shown).

  The photoelectric conversion device 1 can operate by switching between a first mode in which a signal is output from the output terminal 108 and a second mode in which a signal is output from the output terminal 110. In each mode, an output unit that does not output a signal stops power supply or stops operation of some circuits to reduce power consumption.

  In the second mode, signals are output simultaneously from M / T output terminals, whereas in the first mode, signals are output simultaneously from M / S output terminals (S <T). Thus, it is possible to read out a signal at a higher speed, and it is effective for an application in which a reading speed is required, for example, when shooting a moving image. However, since the number of output blocks that operate in the first mode is large, power consumption increases. On the other hand, in the second mode, since a smaller number of output blocks operate than in the first mode, the reading speed is reduced, but the power consumption can be reduced. The second mode is effective when there is a margin in the readout speed, for example, when shooting a still image.

  A digital signal processing unit that can execute addition, subtraction, gain adjustment, and the like may be further added between the output selection unit and each output unit. For example, the sensitivity can be increased by adding signals from a plurality of signal processing units 102 and treating the signals as one signal. In addition, digital gain can be applied digitally by bit-shifting the digital data. By providing these functions in the photoelectric conversion device, it is possible to reduce the load on the subsequent processing circuit. The subsequent processing circuit may be formed, for example, on a semiconductor substrate different from the photoelectric conversion device 1.

  As shown in the present embodiment, it can be output from either the first output unit 107 or the second output unit 10. By adopting the configuration, it is possible to cope with high-speed reading while suppressing an increase in power consumption.

(Example 2)
Another embodiment of the present invention will be described with reference to the drawings.

  FIG. 2 is a block diagram illustrating a configuration example of the photoelectric conversion device according to the present embodiment, which is formed on the same semiconductor substrate, for example. Below, it demonstrates centering on difference with the photoelectric conversion apparatus 1 shown in FIG.

  A significant difference from the photoelectric conversion device 1 is that a synchronization signal generation unit 701, a synchronization code addition unit 702, and a drive signal generation unit 703 are added.

  The synchronization signal generation unit 701 includes, for example, a PLL (Phase Locked Loop) circuit. The periodic signal supplied to the PLL circuit may be generated by providing an oscillator inside the photoelectric conversion device, or may be given from the outside of the photoelectric conversion device. The PLL circuit may further include means for multiplying the input periodic signal, and the frequency of the synchronization signal may be variable. In the PLL circuit, the synchronization signals supplied to the first and second output units may have different frequencies.

  The synchronization code adding unit 702 adds a synchronization code for determining the head of each data to the head of the digital signal output from each output block in synchronization with the synchronization signal output from the synchronization signal generating unit 701. Is. More specifically, a synchronization code is output at a predetermined timing prior to the start of transmission of a digital signal from the output selection unit 105 to each output block. As the predetermined timing, for example, a timing set by external communication (not shown) or a timing stored in advance in a memory device (not shown) can be considered.

  The amount of data read out per line differs depending on the read mode, such as when reading signals from all the pixels of the pixel array, when cutting out and reading out from a specific area, or when thinning out and reading. For this reason, the synchronization code is read once in the horizontal direction, that is, added to each row, so that the head of one row can be easily identified by the processing circuit in the subsequent stage, and errors during data capture are reduced. be able to.

  The drive signal generation unit 703 supplies the synchronization signal output control signal 704 to the synchronization signal generation unit 701 and the synchronization code addition control signal 705 to the synchronization code addition unit 702 to control the operation timing and the timing for adding the synchronization code. .

  FIG. 3 is a timing diagram showing the state of the synchronization signal and the synchronization code when a digital signal is output from the first or second output unit. In the figure, “synchronization signal” indicates a synchronization signal output from the synchronization signal generation unit 701, and “digital output” indicates a digital signal output from the output terminal 108 or 110.

  In synchronization with the synchronization signal becoming high level, a digital signal is output from the output terminal bit by bit. Prior to pixel output in the first row (digital signal supplied from the signal processing unit 102), a synchronization code is output from the output terminal. After the pixel output of the first row is completed, the synchronization code is output from the output terminal again before the pixel output of the second row. Here, 16-bit data “1111000011110000” is added as a synchronization code. Since the processing circuit at the subsequent stage can identify that the transfer of the data of the line, which is to receive the synchronization code, is started, the error at the time of fetching can be reduced. In particular, by adding a synchronization code to the output of each output block, the head of data can be identified even if an error occurs in the timing of signal output between the output blocks.

  Although the example in which the synchronization signal generation unit 701 and the synchronization code addition unit 702 are provided in common for the first and second output blocks has been shown, a configuration in which the synchronization signal generation unit 701 and the synchronization code addition unit 702 are provided separately for the first and second output blocks But it ’s okay.

(Example 3)
FIG. 4 is a block diagram showing a configuration example of another embodiment according to the present invention. Here, the previous configuration is extracted from the output selection unit 105.

  In the second embodiment, the synchronization signal generation unit and the synchronization code addition unit are provided on one side of the first output unit. However, according to this configuration, all output blocks of the first output unit 107 are connected with a common wiring. In particular, when the number of columns of the pixel array is large, signal delay may occur. On the other hand, in the configuration shown in FIG. 4, the synchronization signal generation units 901 and 902 and the synchronization code addition units 903 and 904 are provided on both sides of the first output unit, thereby increasing the ability to drive the wiring and reducing the delay. To do.

  The synchronization signal generation unit and the synchronization code addition unit are controlled by the drive signal generation unit 905, but in order to maintain the synchronization of the operations of the synchronization signal generation units provided apart from each other and the synchronization code addition unit. In addition, the drive signal generation unit 905 is connected by a wire having an equal length. That is, the signal delay is made equal between the synchronization signal generation units and the synchronization code addition unit.

  Although FIG. 4 shows a configuration in which two synchronization signal generation units and two synchronization code addition units are provided, they may be distributed to three or more.

  According to the present embodiment described above, the head data can be identified by adding the synchronization code, and the influence of the wiring delay between the output blocks can be reduced. More specifically, it is possible to reduce the influence of the data fetch error in the block due to the delay of the sync signal and sync code supplied to each output block and the variation in the data fetch timing for each row. .

Example 4
FIG. 5 is a block diagram showing a configuration example of another embodiment according to the present invention. Here, the previous configuration is extracted from the output selection unit 105.

  In this embodiment, a synchronization signal generating unit 1002 and a synchronization code adding unit 1003 are included in each output block of the first output unit 107. For each output block of the second output unit 109, a common synchronization signal generation unit 1006 and a synchronization code addition unit 1007 are provided. The synchronization signal generation unit 1002 and the synchronization code addition unit 1003 and the synchronization signal generation unit 1006 and the synchronization code addition unit 1007 provided in each output block of the first output unit 107 are controlled by a common drive signal generation unit 1001. The

  Also in this embodiment, a synchronization code is added to the head of the pixel output of each row (digital signal supplied from the signal processing unit 102) as in the second embodiment.

  FIG. 6 is a timing chart showing the relationship between the pixel output of a certain row and the synchronization signal. In the figure, reference numeral 1004 denotes a synchronization signal output control signal output from the drive signal generation unit 1001, and 1005 denotes a synchronization code addition control signal output from the drive signal generation unit 1001. The “synchronization signal” is a synchronization signal generated by the synchronization signal generation unit 1002, and the “transfer signal” is a digital signal output from the signal processing unit 102 by the switch unit 106 of the output selection unit 105 to the first output unit 107. It is a signal to start that. “Digital output” represents a signal output from the output terminal 108.

  In FIG. 6, when the synchronization signal output control signal 1004 becomes high level, a synchronization signal is output. Thereafter, in synchronization with the second cycle pulse from the generation of the synchronization signal, the synchronization code addition control signal becomes high level, and the synchronization code is output. Here, “1010” is added as the synchronization code. The transfer signal goes high in synchronization with the sync signal that goes high immediately after the last bit of the sync code is output. As a result, the digital signal output from the signal processing unit 102 is converted into serial data and sequentially output.

  Further, the synchronization code may not only indicate the beginning of the line but may also give other information. FIG. 7 shows an example in which information indicating the position of the output block and information indicating the number of bits of the pixel output are added as a synchronization code in addition to the head of the row. In the first 4 bits of the synchronization code, a code “1010” for identifying the head of the row is added, and subsequently, a code “00110” for identifying the output block is added. Further, a code “01010” indicating the number of bits of the pixel output is added.

  In the configuration shown in this embodiment, since the phase relationship is completed in each output block, it is not necessary to manage the phase between the output blocks, and the addition in the processing circuit in the subsequent stage can be reduced.

(Example 5)
Another embodiment of the present invention will be described with reference to the drawings.

  In the present embodiment, the description will be given focusing on the configuration of the output selection unit. In the configuration shown in FIG. 1, when a signal is output from the second output unit 109, the signal processing unit 102 provided in each column drives the signal line and transmits the signal to the second output unit 109. Take the configuration to do.

  However, while the wiring driven by the signal processing unit 102 close to the second output unit 109 is short, the wiring driven by the signal processing unit 102 far from the second output unit 109 becomes long. For this reason, the transmission speed of the signal output from the signal processing unit 102 far from the second output unit 109 may be reduced.

  In this embodiment, the signal processing unit 102 that outputs a signal from the same second output unit 109 is connected to the second output unit 109 via a common transmission line. As shown in FIG. 8, reducing the load driven by each signal processing unit 102 by connecting a plurality of columns as one block, connecting the blocks with a connection unit 501, and disconnecting unnecessary transmission lines. And a decrease in transmission speed can be suppressed.

  The connection unit 501 may be configured to include a buffer in addition to the switch as illustrated in FIG. When the connection unit 501 includes a buffer, the buffer is configured to have a synchronization function, and when the signal is transmitted to the next buffer in synchronization with a clock signal (not shown), the continuity of the signal between the blocks is maintained. Can do.

  Another configuration example is shown in FIG. As a configuration in which one transmission line is used for the entire pixel array, it is possible to suppress a decrease in signal transmission speed by connecting blocks with a buffer. In addition, since there is one second output unit 109, power consumption in the second mode can be further reduced.

  In particular, when a single transmission line is used, since signals from the first column are sequentially output from the output terminal 110 of the second output unit, it is necessary to rearrange the signals in a subsequent processing circuit. There is an advantage of disappearing.

(Example 6)
Another embodiment of the present invention will be described with reference to the drawings.

  In some cases, the photoelectric conversion device may require a cutout reading mode in which only a part of the imaging surface is cut out. FIG. 10 is a diagram schematically illustrating the pixel array PA that is the imaging surface and the signal processing unit 102. Consider a case where an area 201 is cut out and read out in the figure.

  When only the region 201 is read out, only the signal processing unit 102 in the column corresponding to this region needs to operate, so that the power supply to the signal processing unit in the column not involved in the reading is stopped to save power. By setting, the power consumption of the photoelectric conversion device can be reduced. As a specific example, it is conceivable to interrupt the current that drives the comparator of the A / D converter. A power saving mechanism may be provided for each signal processing unit 102, but one power saving mechanism may be provided for each block illustrated in FIG. If a power saving mechanism is provided for each block, there is a possibility that the signal processing unit 102 in a column that does not need to read out signals may be in an operating state, but power consumption can be reduced with a simpler configuration than providing a power saving mechanism in each column. realizable.

  Furthermore, by setting the output blocks not involved in reading to the power saving state, it is possible to further reduce power consumption.

  According to the present embodiment described above, it is possible to suppress an increase in power consumption while realizing high-speed reading.

(Example 7)
Still another embodiment according to the present invention will be described with reference to the drawings.

  In the photoelectric conversion device, a thinning readout mode in which signals are read out with an interval between pixels to be read out on the imaging surface may be required. FIG. 11 is a diagram schematically showing the pixel array PA and the signal processing unit 102 when signals are read from every other column of pixels, and only from the pixels in the column corresponding to the signal processing unit 102 indicated by hatching. It is assumed that the signal is read out.

  Also in this embodiment, the power consumption can be reduced by setting only the signal processing unit 102 of the column from which the signal is read out to the operating state and setting the other columns to the power saving state.

  The signal output from the signal processing unit 102 may be output from either the first output unit or the second output unit, and may be selected according to the application.

  In order to simplify the description, the case of reading signals from all the pixels in the column from which the signals are read has been considered. However, for example, the row selection unit 103 may be driven so as to read signals from every other row of pixels. .

(Example 8)
Still another embodiment according to the present invention will be described with reference to the drawings.

  Here, a photoelectric conversion device provided with a color filter corresponding to each pixel 101 is considered. As shown in FIG. 12, a pixel row in which red (R) pixels and green (G) pixels are alternately repeated, and a pixel row in which green (G) pixels and blue (B) pixels are alternately repeated. In the case of using a Bayer array in which rows are alternately arranged, when a signal is read out from pixels in every other column or every other row, a color for which no signal can be obtained is generated. Therefore, as shown in FIG. 12, it is conceivable to read out signals by selecting pixels every two columns and every two rows. Thereby, signals can be acquired for all colors.

  Also in the present embodiment, as in the seventh embodiment, the power consumption can be reduced by setting only the signal processing unit 102 of the column from which the signal is read and setting the other columns to the power saving state. . Further, the signal output from the signal processing unit 102 may be output from either the first or second output unit, and may be selected according to the application.

Example 9
Still another embodiment according to the present invention will be described with reference to the drawings.

  FIG. 13 is a block diagram illustrating the configuration of the photoelectric conversion apparatus 1 ″ according to the present embodiment. Unlike the photoelectric conversion device 1 shown in FIG. 1, two signal processing units 102 every other column are formed as one block instead of adjacent columns.

  A signal processing unit 102, an output selection unit 105, a first output unit 107, and a second output unit 109 are provided so as to sandwich the pixel array PA. In the pixel array PA, signals from the pixels in the odd-numbered columns from the left are output from the output section on the lower side in the figure, and signals from the pixels in the even-numbered columns from the left are output from the output section in the upper side in the figure.

  Considering in general terms, a plurality of columns (4 in FIG. 13) adjacent to each other is regarded as one block, and the block is further divided into a plurality of (2 in FIG. 13) sub-blocks (107A and 107B in FIG. 13). is doing. Each sub-block corresponds to a plurality of pixels every other column of the pixel array PA. Since the first and second output units are provided corresponding to each sub-block, signals can be read at a higher speed than when not divided into sub-blocks.

  As described above, the advantage of the configuration in which a plurality of signal processing units are selected every other column to form sub-blocks is that when a Bayer array color filter is provided, only R and G are output from one sub-block. Alternatively, since only G and B signals are obtained, the processing of a processing circuit (not shown) provided at the subsequent stage of the output unit is simplified.

(Example 10)
Next, an outline of the imaging system according to the present embodiment will be described with reference to FIG.

  The imaging system 800 includes, for example, an optical unit 810, a photoelectric conversion apparatus 1000, a video signal processing unit 830, a recording / communication unit 840, a timing control circuit unit 850, a system control circuit unit 860, and a reproduction / display unit 870. As the photoelectric conversion device 1000, the photoelectric conversion device described in each of the above-described embodiments is used. Here, a case where the timing generation unit 40 illustrated in FIG. 1 is included in the timing control circuit unit 850 instead of the photoelectric conversion device is illustrated.

  An optical unit 810 that is an optical system such as a lens forms an image of a subject by forming light from the subject on a pixel array in which a plurality of pixels are two-dimensionally arranged in the photoelectric conversion apparatus 1000. The photoelectric conversion device 1000 outputs a signal corresponding to the light imaged on the pixel unit at a timing based on the signal from the timing control circuit unit 850.

  The signal output from the photoelectric conversion apparatus 1000 is input to a video signal processing unit 830 serving as a processing circuit, and the video signal processing unit 830 performs processing such as signal rearrangement according to a method determined by a program or the like. A signal obtained by processing in the video signal processing circuit unit is sent to the recording / communication unit 840 as image data. The recording / communication unit 840 sends a signal for forming an image to the reproduction / display unit 870 and causes the reproduction / display unit 870 to reproduce / display a moving image or a still image. The recording communication unit also receives the signal from the video signal processing unit 830 and communicates with the system control circuit unit 860, and also performs an operation of recording a signal for forming an image on a recording medium (not shown). .

  The system control circuit unit 860 controls the operation of the imaging system in an integrated manner, and controls the driving of the optical unit 810, the timing control circuit unit 850, the recording / communication unit 840, and the reproduction / display unit 870. In addition, the system control circuit unit 860 includes a storage device (not shown) that is a recording medium, for example, and a program necessary for controlling the operation of the imaging system is recorded therein. In addition, the system control circuit unit 860 supplies a signal for switching the drive mode in accordance with, for example, a user operation in the imaging system. Specific examples include a change in a line to be read out and a line to be reset, a change in an angle of view associated with electronic zoom, and a shift in angle of view associated with electronic image stabilization.

  The timing control circuit unit 850 controls the drive timing of the photoelectric conversion apparatus 1000 and the video signal processing unit 830 based on control by the system control circuit unit 860 which is a control unit.

  Each embodiment described above is an example for carrying out the present invention, and can be variously changed or combined without departing from the technical idea of the present invention.

PA pixel array 101 pixel 102 signal processing unit 103 row selection unit 104 signal line 105 output selection unit 106 switching unit 107 first output unit 107-1, 2, ... first output block 108 output terminal 109 second Output unit 109-1, 2, ... Second output block 110 Output terminal

Claims (15)

A pixel array in which a plurality of pixels are arranged in a matrix;
A signal processing unit including at least a plurality of A / D conversion units which are provided corresponding to the columns of the pixel array and convert signals output from the pixels into digital signals;
A first output unit having two or more first output terminals and including a plurality of first output blocks provided corresponding to each of the first output terminals;
One or more second output blocks, each having one or more second output terminals, provided corresponding to each of the second output terminals;
An output selection unit that selectively transmits the signal output from the signal processing unit to the first or second output unit;
The number of the first output terminals is greater than the number of the second output terminals,
The signal processing units of a plurality of columns adjacent to each other as a block,
The first output block outputs signals output from a plurality of the signal processing units belonging to the same block,
The second output block outputs signals output from a plurality of the signal processing units belonging to different blocks. A pixel array in which a plurality of pixels are arranged in a matrix;
A signal processing unit including at least a plurality of A / D conversion units which are provided corresponding to the columns of the pixel array and convert signals output from the pixels into digital signals;
A first output unit having two or more first output terminals and including a plurality of first output blocks provided corresponding to each of the first output terminals;
One or more second output blocks, each having one or more second output terminals, provided corresponding to each of the second output terminals;
An output selection unit that selectively transmits the signal output from the signal processing unit to the first or second output unit;
The number of the first output terminals is greater than the number of the second output terminals,
As a block, the signal processing unit of a plurality of columns every other column,
The first output block outputs signals output from a plurality of the signal processing units belonging to the same block,
The second output block outputs signals output from a plurality of the signal processing units belonging to different blocks. The output selection unit transmits the signal output from the signal processing unit in the first mode to the first output unit,
3. The photoelectric conversion device according to claim 1, wherein a signal output from the signal processing unit in the second mode is transmitted to the second output unit. 4. When reading signals from all the pixels of the pixel array, execute the first mode,
The photoelectric conversion apparatus according to claim 3, wherein the second mode is executed when a signal is read from a part of the pixels of the pixel array. A synchronization signal generator for outputting a synchronization signal;
5. A synchronization code adding unit that adds a synchronization code to signals output from the first and second output units in synchronization with the synchronization signal. The photoelectric conversion apparatus in any one.   The photoelectric conversion apparatus according to claim 5, wherein the synchronization signal generation unit includes a PLL circuit, and a signal output from the PLL circuit is used as the synchronization signal.   The photoelectric conversion device according to claim 5, wherein the synchronization code adding unit adds the synchronization code corresponding to a row of the pixel array. The photoelectric conversion device according to claim 5, wherein the synchronization signal generation unit and the synchronization code addition unit are provided in common to the first and second output units. . 9. The photoelectric conversion device according to claim 5, wherein the synchronization signal generation unit and the synchronization code addition unit are individually provided for the first and second output units. . The signal processing unit outputs the digital signal as parallel data,
10. The photoelectric device according to claim 1, wherein the first and second output blocks convert the parallel data into serial data and output the serial data from the first and second output terminals. 11. Conversion device.   The photoelectric processing apparatus according to claim 1, wherein the signal processing unit includes a noise reduction circuit that reduces noise from a signal output from the pixel and transmits the reduced noise to the A / D conversion unit. Conversion device.   The photoelectric conversion device according to claim 1, wherein the signal processing unit includes a memory unit that stores the digital signal.   13. The photoelectric device according to claim 1, wherein the output selection unit includes a common transmission line that connects the plurality of signal processing units belonging to different blocks to the second output unit. Conversion device.   The photoelectric conversion apparatus according to claim 13, wherein the transmission line includes a buffer provided corresponding to the block. The photoelectric conversion device according to any one of claims 1 to 14,
An optical system for forming an image on a pixel portion of the photoelectric conversion device;
An imaging system comprising: a video signal processing unit that processes a signal output from the photoelectric conversion device to generate image data.

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