JP2012049196A - Printed wiring board and method of manufacturing the same - Google Patents

Abstract

The present invention provides a printed wiring board capable of reducing the cutting time when forming a cavity and a method for manufacturing the same.
A printed wiring board manufacturing method first provides a substrate having an opening, a first wiring layer, and a second wiring layer. The opening penetrates the substrate. The substrate has a first surface and a second surface facing the first surface, and the first wiring layer and the second wiring layer are disposed on the first surface and the second surface, respectively. Then, a release layer is formed in the opening. A first buildup wiring structure is formed on the first surface and the release layer. A second buildup wiring structure is formed on the second surface and the release layer. Subsequently, the first buildup wiring structure is cut along the periphery of the release layer. Thereafter, the first build-up wiring structure in the already cut portion on the release layer and the release layer is removed to form a cavity.
[Selection] Figure 1I

Description

  The present invention relates to a printed wiring board and a manufacturing method thereof, and more particularly to a printed wiring board having a cavity and a manufacturing method thereof.

  In recent years, along with the advancement of electronic technology, the electronic industry of high science and technology has been sent to the world one after another. As a result, more and more electronic products with better functions have been developed one after another. Developed towards. In these electronic goods, a printed wiring board for attaching an electronic member to the upper part is usually arranged. In order to reduce the total thickness of the printed wiring board and the electronic parts attached to the upper part to meet the demand for thinning, in addition to reducing the thickness of the electronic parts, some or all of the electronic parts on the printed wiring board Forming a cavity or opening that accommodates is a thinning means commonly used today. In patent document 1, the manufacturing method of the printed wiring board with a cavity is disclosed.

Japanese Patent Laid-Open No. 10-022645

  The present invention can solve the problem of a long cutting time when forming a cavity or opening for accommodating an electronic member.

  An object of this invention is to provide the manufacturing method of the printed wiring board for manufacturing the printed wiring board which has a cavity.

  Another object of the present invention is to provide a printed wiring board having a cavity for accommodating an electronic member.

  The present invention provides a method for manufacturing a printed wiring board. This method first provides a substrate having an opening, a first wiring layer, and a second wiring layer. The opening penetrates the substrate. The substrate has a first surface and a second surface facing the first surface, and the first wiring layer and the second wiring layer are disposed on the first surface and the second surface, respectively. Then, a release layer is formed in the opening. A first buildup wiring structure is formed on the first surface and the release layer. A second buildup wiring structure is formed on the second surface and the release layer. Subsequently, the first buildup wiring structure is cut along the periphery of the release layer. Thereafter, the first build-up wiring structure in the already cut portion on the release layer and the release layer is removed to form a cavity.

  The present invention provides a printed wiring board. The printed wiring board includes a substrate, a first wiring layer, a second wiring layer, a first buildup wiring structure, and a second buildup wiring structure. The substrate has an opening that passes through the substrate. The substrate has a first surface and a second surface facing the first surface. The first wiring layer is disposed on the first surface, and the second wiring layer is disposed on the second surface. The first buildup wiring structure is disposed on the first surface and exposes an opening adjacent to one end of the first surface. The second buildup wiring structure is disposed on the second surface and seals an opening adjacent to one end of the second surface to form a cavity together with the substrate and the first buildup wiring structure.

  As described above, according to the present invention, before forming the first and second buildup wiring structures on the two sides of the substrate using the buildup method, first, the release layer is formed in the opening of the substrate. After forming the cutting process to cut the first build-up wiring structure, the release layer can quickly remove the already cut portion of the first build-up wiring structure above the release layer. it can.

  In order to make the above and other objects, features and advantages of the present invention more comprehensible, several embodiments accompanied with figures are described below.

It is sectional drawing of the manufacturing method of the printed wiring board which concerns on embodiment of this invention. It is sectional drawing of the manufacturing method of the printed wiring board which concerns on embodiment of this invention. It is sectional drawing of the manufacturing method of the printed wiring board which concerns on embodiment of this invention. It is sectional drawing of the manufacturing method of the printed wiring board which concerns on embodiment of this invention. It is sectional drawing of the manufacturing method of the printed wiring board which concerns on embodiment of this invention. It is sectional drawing of the manufacturing method of the printed wiring board which concerns on embodiment of this invention. It is sectional drawing of the manufacturing method of the printed wiring board which concerns on embodiment of this invention. It is sectional drawing of the manufacturing method of the printed wiring board which concerns on embodiment of this invention. It is sectional drawing of the manufacturing method of the printed wiring board which concerns on embodiment of this invention. It is sectional drawing when the mold release layer concerning another embodiment of this invention and the already cut | disconnected part above it are removed.

  1A to 1I are cross-sectional views of a method for manufacturing a printed wiring board according to an embodiment of the present invention. First, referring to FIG. 1A, a substrate 100 and two wiring material layers 102 are provided. The substrate 100 is, for example, a dielectric core. The substrate 100 has a first surface 100a and a second surface 100b facing each other. These wiring material layers 102 are respectively disposed on the first surface 100a and the second surface 100b, and the material of these wiring material layers 102 is, for example, a metal. Thereafter, an opening 104 and at least one through-hole 106 penetrating the substrate 100 are formed in the substrate 100 and these wiring material layers 102. A method of forming the opening 104 and the through hole 106 is, for example, laser excavation or mechanical excavation.

  Next, referring to FIG. 1B, an electroplating process is performed to form a metal layer 108 on the sidewalls of the opening 104 and the through-hole 106, and these wiring material layers 102 are connected. Thereafter, a plug hole process is performed to fill the through hole 106 with a plug hole material 109.

  Subsequently, referring to FIG. 1C, a patterning process is performed to remove a portion of the metal layer 108 and the wiring material layer 102 on the sidewall of the opening 104, and to form the first wiring layer 102a on the first surface 100a. At the same time, the second wiring layer 102b is formed on the second surface 100b.

  Then, referring to FIG. 1D, a release layer 200 is formed in the opening 104. A method for forming the release layer 200 is, for example, to embed a release material in the opening 104 by performing an embedding process. The material of the release layer 200 is a material that can be easily separated from a dielectric material such as polytetrafluoroethylene (PTFE) or metal.

  Subsequently, referring to FIG. 1E, a build-up dielectric layer 112a and a wiring material layer 114 are formed on the first surface 100a by using a build-up method, and the second surface 100b is formed. Build-up dielectric layer 122a and wiring material layer 124 are formed. The material of the wiring material layers 114 and 124 is, for example, a metal such as copper. Thereafter, at least one blind hole 116 is formed in the build-up dielectric layer 112a and the wiring material layer 114, and at least one blind hole 126 is formed in the build-up dielectric layer 122a and the wiring material layer 124. The blind hole 116 exposes a part of the first wiring layer 102a, and the blind hole 126 exposes a part of the second wiring layer 102b. The method for forming the bride holes 116 and 126 is, for example, laser excavation.

  Next, referring to FIG. 1F, an electroplating process is performed to form a conductive hole 118a in the blind hole 116, and the wiring material layer 114 and the first wiring layer 102a are electrically connected. A conductive hole 128a is formed therein to electrically connect the wiring material layer 124 and the second wiring layer 102b. Thereafter, a patterning process is performed on the wiring material layer 114 and the wiring material layer 124 to form the buildup wiring layer 114a and the buildup wiring layer 124a.

  Then, referring to FIG. 1G, the steps described in FIG. 1E and FIG. 1F are repeated twice to build up the buildup dielectric layer 112b, the buildup wiring layer 114b on the buildup dielectric layer 112a and the buildup wiring layer 114a. Build-up dielectric layer 112c and build-up wiring layer 114c are formed, and build-up dielectric layer 122b, build-up wiring layer 124b, build-up dielectric layer 122c, and build-up dielectric layer 122c are formed on build-up dielectric layer 122a and build-up wiring layer 124a. Build-up wiring layer 124c is formed. The buildup wiring layer 114b is electrically connected to the buildup wiring layer 114a through a conductive hole 118b that penetrates the buildup dielectric layer 112b. The buildup wiring layer 114c is electrically connected to the buildup wiring layer 114b through a conductive hole 118c that penetrates the buildup dielectric layer 112c. The build-up wiring layer 124b is electrically connected to the build-up wiring layer 124a through a conductive hole 128b that penetrates the build-up dielectric layer 122b. The buildup wiring layer 124c is electrically connected to the buildup wiring layer 124b through a conductive hole 128c that penetrates the buildup dielectric layer 122c.

  In this embodiment, the buildup dielectric layer 112a, the buildup wiring layer 114a, the conductive hole 118a, the buildup dielectric layer 112b, the buildup wiring layer 114b, the conductive hole 118b, the buildup dielectric layer 112c, and the buildup wiring layer 114c. The conductive hole 118c constitutes the first build-up wiring structure 110. Also, the buildup dielectric layer 122a, the buildup wiring layer 124a, the conductive hole 128a, the buildup dielectric layer 122b, the buildup wiring layer 124b, the conductive hole 128b, the buildup dielectric layer 122c, the buildup wiring layer 124c, and the conductive hole. The path 128c constitutes the second buildup wiring structure 120.

  Briefly, in the present embodiment, the first build-up wiring structure 110 and the second build-up wiring structure 120 each have three build-up dielectric layers and build-up wiring layers. Of course, in other embodiments, the steps described in FIGS. 1E and 1F may be repeated as many times as necessary in accordance with actual demand. That is, the first buildup wiring structure 110 and the second buildup wiring structure 120 each have one or more buildup dielectric layers and buildup wiring layers.

  1H, a first solder resist layer 150 and a second solder resist layer 152 may be selectively formed on the first buildup wiring structure 110 and the second buildup wiring structure 120, respectively. . In the present embodiment, the first and second solder resist layers 150 and 152 cover the outermost buildup wiring layers (that is, the buildup wiring layer 114c and the buildup wiring layer 124c), respectively.

  1H, the first buildup wiring structure 110 is cut along the periphery of the release layer 200. The step of cutting the first buildup wiring structure 110 is, for example, performing laser cutting. In particular, in this embodiment, the opening 104 is formed in the substrate 100 in advance, and the release layer 200 is formed in the opening 104 in advance. In this case, it is only necessary to cut the first buildup wiring structure 110, and it is not necessary to cut the substrate 100. Therefore, the cutting time can be effectively shortened.

  Then, referring to FIG. 1I, the release layer 200 and the part of the first build-up wiring structure 110 that has already been cut on the release layer 200 are removed to form the cavity 220, and the print of this embodiment is performed. The production of the wiring board 10 is completed. The cavity 220 is used to accommodate a chip or other electronic member. The material of the release layer 200 is selected from a material that can be easily separated from the dielectric material, such as polytetrafluoroethylene or metal. Therefore, in this step, the release layer 200 is easily peeled directly from the opening 104. be able to.

  In another embodiment, the release layer 200 may protrude from the opening 104 using a lift pin.

  FIG. 2 is a cross-sectional view of the release layer according to another embodiment of the present invention and the already cut portion above the release layer. Referring to FIG. 2, in this embodiment, first, a lift pin hole 300 that exposes the bottom of the release layer 200 is formed in the second buildup wiring structure 120. Then, the lift pins 302 are passed through the lift pin holes 300 to protrude the release layer 200 and the already cut first buildup wiring structure 110 thereon, thereby forming the cavity 220.

  Hereinafter, the printed wiring board of this embodiment will be described with reference to FIG. 1I as an example.

  Referring to FIG. 1I, the printed wiring board 10 includes a substrate 100, a first wiring layer 102 a, a second wiring layer 102 b, a first buildup wiring structure 110, a second buildup wiring structure 120, A solder resist layer 150 and a second solder resist layer 152 are provided.

  The substrate 100 has an opening 104, and the opening 104 penetrates the substrate 100. The substrate 100 has a first surface 100a and a second surface 100b facing each other. The first wiring layer 102a is disposed on the first surface 100a, and the second wiring layer 102b is disposed on the second surface 100b. The first buildup wiring structure 100 is disposed on the first surface 100a and exposes the opening 104 adjacent to one end of the first surface 100a. The second buildup wiring structure 120 is disposed on the second surface 100b, blocks the opening 104 adjacent to one end of the second surface 100b, and forms the cavity 220 together with the substrate 100 and the first buildup wiring structure 110. To do.

  In the present embodiment, the first build-up wiring structure 110 includes a build-up dielectric layer 112a, a build-up wiring layer 114a, a conductive hole path 118a, a build-up dielectric layer 112b, a build-up wiring layer 114b, and a conductive hole. A path 118b, a build-up dielectric layer 112c, a build-up wiring layer 114c, and a conductive hole path 118c are included. The second buildup wiring structure 120 includes a buildup dielectric layer 122a, a buildup wiring layer 124a, a conductive hole 128a, a buildup dielectric layer 122b, a buildup wiring layer 124b, a conductive hole 128b, and a build. An up dielectric layer 122c, a build-up wiring layer 124c, and a conductive hole 128c are provided.

  Briefly, in the present embodiment, the first build-up wiring structure 110 and the second build-up wiring structure 120 each have three build-up dielectric layers and build-up wiring layers. However, in other embodiments, the first build-up wiring structure 110 and the second build-up wiring structure 120 may include one or more build-up dielectric layers and build-up wiring layers, respectively, depending on actual demand. You may have.

  The first solder resist layer 150 and the second solder resist layer 152 are selectively disposed on the build-up dielectric layers 112c and 122c, respectively, and the outermost build-up wiring layer (that is, the build-up wiring layer). 114c and buildup wiring layer 124c) are covered to protect buildup wiring layer 114c and buildup wiring layer 124c. Further, a metal layer 108 is further disposed in the substrate 100, and the first wiring layer 102a and the second wiring layer 102b on the two sides of the substrate 100 are electrically connected to each other.

  Further, in another embodiment, taking FIG. 2 as an example, the lift pin 302 is used to project the release layer 200 and the first cut-up wiring structure 110 of the already cut portion above the release layer 200. The buildup wiring structure 120 may further include a lift pin hole 300. Since the lift pin hole 300 penetrates the second buildup wiring structure 120 and reaches the cavity 220, it is convenient for the lift pin 302 to pass through the lift pin hole 300 and push out the release layer 200.

  As described above, according to the present invention, before forming the first buildup wiring structure and the second buildup wiring structure on the two sides of the substrate using the buildup method, first, in the opening of the substrate. In order to form a release layer, a cutting process is performed to cut the first build-up wiring structure, and then the release layer quickly causes the first build-up wiring structure in the already cut portion above the release layer to be formed. Can be removed.

  In addition, before forming the first buildup wiring structure and the second buildup wiring structure, the substrate is formed with an opening in advance, so that after the first buildup wiring structure is cut, the substrate is cut again and the cavity depth is increased. Since it is not necessary to increase the length, the cutting time can be shortened effectively.

  In addition, since the substrate is formed with an opening in advance before forming the first buildup wiring structure and the second buildup wiring structure, the second buildup wiring is formed so as not to waste the wiring area of the buildup wiring layer described above. There is no need to construct the laser shielding area by build-up wiring layers adjacent to several substrates of the structure.

  As described above, the present invention has been disclosed by the embodiments. However, the present invention is not intended to limit the present invention, and is within the scope of the technical idea of the present invention so that those skilled in the art can easily understand. Therefore, the scope of patent protection should be defined based on the scope of claims and the equivalent area.

DESCRIPTION OF SYMBOLS 10 Printed wiring board 100 Board | substrate 100a 1st surface 100b 2nd surface 102,114,124 Wiring material layer 102a 1st wiring layer 102b 2nd wiring layer 104 Opening 106 Through-hole 108 Metal layer 109 Perforated material 110 1st buildup wiring structure 112a, 112b, 112c, 122a, 122b, 122c Build-up dielectric layer 114a, 114b, 114c, 124a, 124b, 124c Build-up wiring layer 116, 126 Blind hole 118a, 118b, 118c, 128a, 128b, 128c Conductive hole 120 Second buildup wiring structure 150 First solder resist layer 152 Second solder resist layer 200 Release layer 220 Cavity 300 Lift pin hole 302 Lift pin

Claims (10)

A substrate having an opening therethrough and having a first surface and a second surface facing the first surface, a first wiring layer disposed on the first surface, and a second disposed on the second surface Providing a wiring layer;
Forming a release layer in the opening;
Forming a first build-up wiring structure on the first surface and the release layer;
Forming a second build-up wiring structure on the second surface and the release layer;
Cutting the first buildup wiring structure along the periphery of the release layer;
Removing the first build-up wiring structure in the part that has already been cut above the release layer and forming a cavity.   The method for manufacturing a printed wiring board according to claim 1, wherein the material of the release layer includes polytetrafluoroethylene or a metal.   The method for manufacturing a printed wiring board according to claim 1, wherein the step of forming the release layer includes embedding a release material in the opening.   The step of removing the first build-up wiring structure on the release layer and the portion above the release layer may be directly peeled off or passed through the second build-up wiring structure using a lift pin, and The method for manufacturing a printed wiring board according to claim 1, further comprising protruding the first build-up wiring structure in a portion above the mold layer and the release layer.   The method of manufacturing a printed wiring board according to claim 1, wherein the step of cutting the first buildup wiring structure includes performing laser cutting. Forming a first solder resist layer on the first buildup wiring structure;
The method of manufacturing a printed wiring board according to claim 1, further comprising: forming a second solder resist layer on the second buildup wiring structure. A substrate having an opening therethrough and having a first surface and a second surface facing the first surface;
A first wiring layer disposed on the first surface;
A second wiring layer disposed on the second surface;
A first build-up wiring structure disposed on the first surface and exposing the opening adjacent to one end of the first surface;
A second build-up wiring structure disposed on the second surface and sealing the opening adjacent to one end of the second surface and forming a cavity together with the substrate and the first build-up wiring structure , Printed wiring board.   The printed wiring board according to claim 7, wherein the substrate is a dielectric core. A first solder resist layer disposed on the first buildup wiring structure;
The printed wiring board according to claim 7, further comprising a second solder resist layer disposed on the second buildup wiring structure.   The printed wiring board according to claim 7, wherein the second buildup wiring structure has a lift pin hole, and the lift pin hole penetrates the second buildup wiring structure and reaches the cavity.

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