JP2012038397A - Resistance change memory and forming method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a resistance change memory and a forming method thereof, capable of enhancing reliability of a memory cell.SOLUTION: A resistance change memory in an embodiment comprises: a memory cell having a variable resistance element and a rectification element which are series connected; first wiring electrically connected to a cathode side of the rectification element; second wiring electrically connected to an anode side of the rectification element; a voltage generating circuit which generates a voltage applied to the first wiring and the second wiring; and a state machine which controls the voltage generating circuit such that a first forming voltage is applied to the first wiring and a ground potential is applied to the second wiring during a first forming operation.

Description

  Embodiments described herein relate generally to a resistance change memory that stores data according to a change in resistance value of a variable resistance element and a forming method thereof.

  In recent years, a resistance change memory (ReRAM; Resistance Random Access Memory) that stores a change in resistance value (high resistance state or low resistance state) of an electrically rewritable variable resistance in a nonvolatile manner has been developed.

  In this resistance change memory, after forming the memory cell structure, in order to make it usable as a memory cell, that is, in a state in which it can transition between a high resistance state and a low resistance state, It is necessary to perform a forming operation in which a large voltage is applied.

JP 2005-522045 A JP 2008-227267 A

  The present invention provides a resistance change memory capable of improving the reliability of a memory cell and a forming method thereof.

According to this embodiment, the resistance change memory includes a variable resistance element and a rectifying element, and is electrically connected to a memory cell in which the variable resistance element and the rectifying element are connected in series, and a cathode side of the rectifying element. The first wiring made,
A second wiring electrically connected to the anode side of the rectifying element, a voltage generation circuit that generates a voltage to be applied to the first wiring and the second wiring, and a first forming operation, And a state machine that controls the voltage generation circuit to apply a first forming voltage to the first wiring and to apply a ground potential to the second wiring.

  According to this embodiment, the resistance change memory forming method is a resistance change memory forming method including a variable resistance element and a rectifying element, and having a memory cell in which the variable resistance element and the rectifying element are connected in series. (A) applying a first forming voltage to the first wiring connected to the cathode side of the rectifying element and applying a ground potential to the second wiring connected to the anode side of the rectifying element; It is characterized by providing.

The block diagram which shows the resistance change memory of this embodiment. FIG. 3 is a perspective view showing a part of the memory cell array according to the embodiment. FIG. 3 is a cross-sectional view of one memory cell portion extracted from the II cross section of FIG. 2. The circuit diagram which shows the determination circuit of this embodiment. The flowchart figure which shows the 1st forming process in the forming method of this embodiment. The flowchart figure which shows the determination process in the forming method of this embodiment. The flowchart figure which shows the 2nd forming process in the forming method in this embodiment.

(Embodiment)
Next, the present embodiment will be described with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings. Further, the dimensional ratios in the drawings are not limited to the illustrated ratios.

[Configuration of resistance change memory]
The configuration of the resistance change memory according to this embodiment will be described with reference to FIGS.

  As shown in the block diagram of FIG. 1, the resistance change memory 100 includes a memory cell array 10, a column control circuit 11 connected to the memory cell array 10, a row control circuit 12 connected to the memory cell array 10, a data input / output buffer 13, An address register 14, a command interface circuit (command I / F in the figure) 15, a state machine 16 that controls the entire resistance change memory 100, a voltage generation circuit 17 connected to the column control circuit 11 and the row control circuit 12 are provided. .

<Memory cell array>
In the memory cell array 10, a plurality of bit lines (also referred to as first wirings) BL0 to BL2 are spaced apart in a first direction above a semiconductor substrate (not shown) as shown in the perspective view of FIG. A plurality of word lines (also referred to as second wirings) WL0 to WL2 are arranged in parallel spaced apart from each other in a second direction orthogonal to the first direction.

  When viewed from above, the memory cells M are disposed between the wiring lines at the intersections between the bit lines BL0 to BL2 and the word lines WL0 to WL2.

  Here, the bit line BL and the word line WL are preferably made of a material that is resistant to heat and has a low resistance value. For example, W, WSi, NiSi, CoSi or the like is used.

  Here, the memory cell M has a structure in which a variable resistance element (a substance whose resistance value can be changed by applying a voltage, for example, using NiO or HfO) VR and a diode DI are connected in series.

  For example, when a PIN diode DI is used as the diode DI, as shown in the cross-sectional view of FIG. 3, the PIN diode DI includes a p + type layer D1, an n− type layer D2, and an n + type layer from the word line WLj side. D3 has a stacked structure. The symbols “+” and “−” indicate the impurity concentration.

  As shown in FIG. 3, an electrode EL1 is disposed between the word line WLj and the variable resistance element VR, an electrode EL2 is disposed between the variable resistance element VR and the PIN diode DI, and the PIN diode DI and the bit line BL1. The electrode EL3 is disposed between the two. Here, as materials for the electrodes EL1 to EL3, Pt, Au, Ag, TiAlN, SrRuO, Ru, RuN, Ir, Co, Ti, TiN, TaN, LaNiO, Al, PtIrOx, PtRhOx, Rh / TaAlN, W, and the like. Used.

  Note that the positions of the variable resistance element VR and the diode DI may be interchanged, and a metal that makes the orientation uniform may be formed on the electrodes EL1 to EL3.

<Column control circuit>
The column control circuit 11 decodes the column address input from the address register 14 and controls the bit line BL of the memory cell array 10. For example, a forming voltage (which means a voltage necessary for forming) is supplied to the bit line BL selected by the column control circuit 11 using a voltage generation circuit 17 described later.

  Further, the column control circuit 11 includes a determination circuit 20 shown in FIG. The determination circuit 20 compares the reference current Ist and the cell current Icell of the memory cell M to determine whether or not forming is sufficient. This reference current Ist is a current when a sufficient filament path is formed in the variable resistance element of the memory cell M. The reference current Ist data is stored in, for example, a ROM in the state machine 16 described later. The reference current Ist data may be stored in an external host device.

  The determination circuit 20 includes current mirror circuits 21 to 24, a differential amplifier 25, and a reference current generation circuit 26.

  The current mirror circuit 21 has a function of supplying a cell current Icell flowing through the memory cell M to the current mirror circuits 22 to 24. The current mirror circuits 22 to 24 have N-channel MOS transistors (hereinafter referred to as NMOS transistors) 31 and 32, P-channel transistors (hereinafter referred to as PMOS transistors) 41 to 43, and NMOS transistors 51 and 52, respectively. Mirror connection.

  The reference current generation circuit 26 has a function of generating a reference current Ist and generating a voltage CVG corresponding to the reference current Ist at the node X. The differential amplifier 25 differentially amplifies the voltage generated at the node Y based on the current Icell and the voltage at the node X, and outputs an output signal OUT. Based on this output signal OUT, the reference current Ist and the cell current Icell are compared.

<Row control circuit>
The row control circuit 12 decodes the row address input from the address register 14 and selects a predetermined word line WL in the memory cell array 10. A voltage necessary for data writing or reading is supplied to the word line WL selected by the row control circuit 12 using a voltage generation circuit 17 described later.

<Data input / output buffer>
The data input / output buffer 13 is connected to an external host device 18 via an I / O line (external I / O), and inputs / outputs write data, address data, and command data.

  For example, when write data is input from the host device 18 to the data input / output buffer 13, the data input / output buffer 13 outputs the write data to the column control circuit 11.

  When address data is input to the data input / output buffer 13, the data input / output buffer 13 outputs this address data to the address register 14.

  Further, when command data is input to the data input / output buffer 13, the data input / output buffer 13 inputs the command data to the command interface circuit 15.

<Command interface circuit>
An external control signal is input from the host device 18 to the command interface circuit 15. Using this external control signal, the command interface circuit 15 determines whether the data input from the data input / output buffer 13 is command data, and if it is command data, inputs it to the state machine 16 as a command signal.

<State machine>
The state machine 16 performs sequence control such as forming operation, data writing, or data reading by an internal control signal based on a command signal input according to the operation mode. Further, the state machine 16 is configured such that after the first forming operation, the memory cell that has not been sufficiently formed based on the output signal OUT of the reference current generation circuit 26 (for convenience of description, if the forming is sufficiently performed, This portion is also referred to as a memory cell that has not been formed until it is determined that the forming has been sufficiently performed.) Control is performed using an internal control signal so that the second forming is performed.

<Voltage generation circuit>
The voltage generation circuit 17 is a circuit that generates a voltage boosted by a charge pump circuit (not shown). The voltage generation circuit 17 supplies a voltage boosted using a clock to an arbitrary wiring selected by the column control circuit 11 and the row control circuit 12. The voltage generation circuit 17 is controlled by an internal control signal output from the state machine 16 described above.

[Formation method of resistance change memory]
Next, the forming method of the resistance change memory according to this embodiment will be described with reference to the flowcharts of FIGS.

<First forming process>
The first forming process is a process for forming all the memory cell structures in the memory cell array 10 collectively. Specific steps are as follows as shown in FIG.

  First, in step S1, the state machine 16 controls the column control circuit 11 and the row control circuit 12 with an internal control signal, and selects all bit lines and all word lines.

  In step S2, the voltage generation circuit 17 applies a positive forming voltage (for example, 5V) to each bit line BL connected to the cathode side of the diode DI in the memory cell before forming through the column control circuit 11 and the row control circuit 12. ) Is applied. On the other hand, the voltage generation circuit 17 applies a ground voltage to each word line WL connected to the anode side of the diode DI.

<Judgment process>
Next, the determination process performed after the first forming process will be described with reference to FIG. The determination step is a step of determining one by one whether or not the forming has been sufficiently performed after the first forming step.

  First, in step S1, the state machine 16 controls the column control circuit 11 and the row control circuit 12 with an internal control signal, and selects one of the memory cells after the first forming process. The determination circuit 20 in the column control circuit 11 is connected to the memory cell after the first forming process. For example, the memory cell after the first forming process and the determination circuit 20 are connected by switching with a switching transistor.

  In step S2, the state machine 16 applies a test voltage CVG (a voltage smaller than the forming voltage) to the word line WL connected to the anode side of the diode DI of the memory cell after the first forming process using the voltage generation circuit 17. Apply. On the other hand, a ground potential is applied to the bit line BL connected to the cathode side using the voltage generation circuit 17.

  At this time, the determination circuit 20 compares the cell current Icell flowing through the memory cell after the first forming process with the reference current Ist, and determines whether or not the current Icell exceeds the reference current Ist. This determination result is output by the output signal OUT of FIG.

  When the cell current Icell exceeds the reference current Ist (step S2, Yes), the state machine 16 determines the selected memory cell as a memory cell that has been formed (step S3). On the other hand, if the determination result indicates that the cell current Icell does not exceed the reference current Ist (step S2, No), the selected memory cell is determined as a memory cell that has not been formed (step S4).

  Next, in step S5, the state machine 16 determines the result data (for example, 1-bit (binary) data) determined as the memory cell in which the forming is completed in step S3 or the memory cell in which the forming is not completed in step S4. ) Is stored in a ROM in the state machine 16, for example. The result data is not limited to being stored in the ROM in the state machine 16 and may be stored in the external host device 18 via the data input / output buffer 13.

  The above-described steps S1 to S5 are similarly performed on all the memory cells after the first forming process.

<Second forming process>
Next, the second forming process performed after the determination process will be described with reference to FIG. The second forming process is a process in which all the memory cells that have not been formed in the first forming process are collectively formed again.

  First, in step S1, the state machine 16 reads the result data stored in the ROM in the state machine 16 to, for example, a temporary storage device in the state machine 16, and the memory cell in which the forming has not been completed and the memory in which the forming has been completed. Identifies the cell.

  When the result data is stored in the external host device 18, the state machine 16 reads the result data stored in the host device 18 to the temporary storage device of the host device 18, and the forming is completed. A memory cell that has not been formed and a memory cell that has been formed are identified.

  In step S2, the state machine 16 controls the column control circuit 11 and the row control circuit 12 with an internal control signal, and selects all bit lines and all word lines.

  In step S3, the state machine 16 controls the voltage generation circuit 17 to apply a higher voltage to the bit line BL connected to the memory cell in which the forming is not completed than the forming voltage (first forming voltage) in the first forming process. A positive positive forming voltage (second forming voltage) is applied, and a ground potential is applied to the word line WL.

  On the other hand, a voltage (for example, 3.5 V) between the ground potential and the second forming voltage is applied to the bit line BL connected to the memory cell that has completed forming, and the second forming voltage is applied to the word line WL. Is applied.

  After the step S3, the above-described determination process is performed again, and the process is repeated until all the memory cells that have not been formed become memory cells that have been formed.

(Modification 1)
In the present embodiment, the second forming voltage is stepped up with respect to the first forming voltage. However, in the first modification, the second forming voltage may be equal to the first forming voltage.

  When the second forming process is performed a plurality of times, the forming voltage used in the second forming process up to the m-th (m> 1) is made equal to the first forming voltage, and the second forming after the (m + 1) th is performed. The forming voltage used in the process may be stepped up.

[Effect of the embodiment]
As described above, it is possible to provide a resistance change memory capable of improving the reliability of the memory cell and a forming method thereof. This will be specifically described below.

  In the resistance change memory forming method of this embodiment, a forming voltage is applied in the reverse direction to the diode of the resistance change memory. That is, the forming voltage is applied to the wiring connected to the cathode side of the diode, and the ground voltage is applied to the wiring connected to the anode side of the diode.

  In general, when a forming voltage is applied in the forward direction to a diode of a resistance change memory to perform forming, once a filament is formed, a transient current tends to flow through the variable resistance element. As a result, the filament formed in the variable resistance element becomes thick, and the resistance state of the variable resistance element may not be switched.

  However, in this embodiment, once the filament is formed, it is difficult for a transient current to flow through the variable resistance element. Therefore, it is possible to provide a resistance change memory in which the filament formed in the variable resistance element is not easily thickened, the resistance state of the variable resistance element can be switched more accurately, and the reliability of the memory cell can be improved.

  In the resistance change memory forming method of the present embodiment, in the second forming process, the bit line BL connected to the memory cell is supplied with a ground voltage and a forming voltage higher than the forming voltage in the first forming process. Apply a voltage between.

  As a result, the voltage load applied to the memory cell in the re-forming process is reduced compared to the voltage load when the forming voltage is applied in the forward direction to the diode. As a result, the transient current flowing through the variable resistance element can be reduced, and the filament formed on the variable resistance element is unlikely to become thick.

  Therefore, the resistance state of the variable resistance element can be switched with higher accuracy, and a resistance change memory with improved reliability of the memory cell can be provided.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be extracted as an invention.

DESCRIPTION OF SYMBOLS 10 ... Memory cell array 11 ... Column control circuit 12 ... Row control circuit 13 ... Data input / output buffer 14 ... Address register 15 ... Command interface circuit 16 ... State machine 17 ... Voltage generation circuit 18 ... Host apparatus 20 ... Determination circuit 21 22 23 24 ... Current mirror circuit 25 ... Differential amplifier 31 32 41 42 43 51 52 ... Transistor 100 ... Resistance change memory

Claims (5)

A memory cell having a variable resistance element and a rectifying element, wherein the variable resistance element and the rectifying element are connected in series;
A first wiring electrically connected to the cathode side of the rectifying element;
A second wiring electrically connected to the anode side of the rectifying element;
A voltage generation circuit for generating a voltage to be applied to the first wiring and the second wiring;
And a state machine that controls the voltage generation circuit to apply a first forming voltage to the first wiring and to apply a ground potential to the second wiring during the first forming operation. Resistance change memory. The resistance change memory according to claim 1, further comprising a determination circuit that determines the magnitude of a cell current and a reference current flowing in the memory cell after the first forming operation,
The state machine applies a second forming voltage to the first wiring connected to the memory cell determined to have a cell current flowing through the memory cell after the first forming operation not exceeding the reference current, A resistance change memory, wherein the voltage generation circuit is controlled to apply the ground potential to a second wiring. The state machine is
A voltage between the ground potential and the second forming voltage applied to the first wiring connected to the memory cell determined that the cell current flowing through the memory cell after the first forming operation does not exceed the reference current. The resistance change memory according to claim 1, wherein the second forming voltage is applied to the second wiring. A resistance change memory forming method including a variable resistance element and a rectifying element, and having a memory cell in which the variable resistance element and the rectifying element are connected in series,
(A) applying a first forming voltage to a first wiring connected to the cathode side of the rectifying element, and applying a ground potential to a second wiring connected to the anode side of the rectifying element. A forming method for a resistance change memory. The resistance change memory forming method according to claim 4,
(A) a step of determining the magnitude of a cell current and a reference current flowing in the memory cell after the step (A);
(B) In the step (a), a forming voltage is applied to the first wiring connected to the memory cell that is determined that the reference current is larger than the cell current flowing in the memory cell after the step (A). And applying a ground potential to the second wiring, and forming a resistance change memory.

Images